TWI533451B - Silicon power device and power conversion equipment provided with the same - Google Patents

Description

Semiconductor device and power conversion device using same

The present invention relates to a semiconductor device and a power conversion device using the same, and more particularly to a semiconductor device suitable for an insulated gate bipolar transistor (hereinafter, slightly IGBT) having an insulating gate structure and power using the same Conversion device.

The IGBT is a switching element that applies a voltage to the gate electrode to control the current flowing between the collector and the emitter. Because the IGBT can control the power and the wide range from tens of watts to hundreds of thousands of watts, the switching frequency is also widely exceeded tens of hertz to hundreds of kilohertz, so it is used in small electric machines such as air conditioners and even railways and steel. Large power machines such as factories. In terms of such power equipment, in order to increase the efficiency and miniaturization of the system, the conduction loss of the IGBT and the switching loss are strongly required to be reduced.

The decrease in the voltage drop (on-voltage) when the conduction loss is ON is effective, and the higher the concentration of the minority carrier accumulated in the drift layer, the lower it can be. In addition, the lower the concentration of the minority carriers accumulated by the shutdown loss, the smaller the smaller, There is a relationship between the turn-on voltage and the turn-off loss. In order to improve the resistance, although the effect of improving the IE (Electronic Injection Promotion) is effective, the characteristics of the IGBT are approaching the limit, and further improvement in characteristics is in a difficult state.

In order to further improve the characteristics, a four-terminal IGBT structure as shown in FIG. 15 is disclosed in Patent Document 1 (Japanese Laid-Open Patent Publication No. Hei-3-268363). In this structure, a high-concentration p-type emitter layer 7 and a high-concentration n+ layer 25 are adjacent to the collector side, and individual electrodes are connected to the respective regions. With such a configuration, since a small amount of carriers are injected from the high-concentration p-type emitter layer 7 at a high level during ON, the average carrier concentration can be increased and the on-voltage can be lowered. In addition, the turn-off loss can be reduced by turning on the high-concentration n+ layer 25 to reduce the accumulation of minority carriers and to reduce the tail current. In other words, since it operates as an IGBT at the time of ON and operates as a MOSFET having a fast switching speed at the time of turning off, it is possible to improve the resistance between the on-voltage and the turn-off loss.

[Previous Technical Literature] [Patent Document]

[Patent Document 1] Japanese Patent Laid-Open Publication No. Hei-3-268363

However, in the IGBT structure shown in FIG. 15, since it operates as a MOSFET during OFF, there is a rebound between the emitters. The problem of pressing down. Further, since there is no hole injection during the operation of the high-concentration n+ layer 25, there is a problem that the conduction loss immediately before the turn-off is increased.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device and a power conversion device using the same, which can suppress an increase in a bounce voltage and can improve a resistance between a turn-on voltage and a turn-off loss.

In order to solve the above problems, the semiconductor device according to the present invention includes a second conductivity type high concentration emitter layer and a second conductivity type low concentration emitter layer which are provided separately from each other in order to inject a carrier into the semiconductor device. Each of the main electrodes of the second conductivity type high concentration emitter layer and the second conductivity type low concentration emitter layer is electrically connected to each other.

According to the present invention, since the amount of carriers accumulated in the semiconductor device can be suppressed during the operation of the semiconductor device, it is possible to improve the resistance between the on-voltage and the turn-off loss while suppressing an increase in the buckling voltage. Further, as long as the semiconductor device according to the present invention is used in a power conversion device, the reliability of the power conversion device can be improved while power loss can be reduced.

1‧‧‧n-substrate

2‧‧‧p-type base layer

3‧‧‧n source layer

4‧‧ ‧ emitter electrode

5‧‧‧Oxide film

6‧‧‧Gate electrode

7‧‧‧p type high concentration emitter layer

8‧‧‧p type low concentration emitter layer

9‧‧‧ Collector electrode connected to p-type high concentration emitter layer

10‧‧‧ Collector electrode connected to p-type low concentration emitter layer

11‧‧‧External switching elements

12‧‧‧ Buffer layer

13‧‧‧High concentration n+ layer

14‧‧‧Insulation

15‧‧‧ hole barrier

16‧‧‧External MOSFET

17‧‧‧2nd gate oxide film

18‧‧‧2nd gate electrode

19‧‧‧p type inversion layer

20‧‧‧ Collector electrode

21‧‧‧ cathode side n+ layer

22‧‧‧Cathode electrode

23‧‧‧Anode electrode connected to a high concentration p-type emitter layer

24‧‧‧Anode electrode connected to a low concentration p-type emitter layer

25‧‧‧High concentration n+ layer

101, 102‧‧‧ DC terminals

103, 104, 105‧‧‧ AC terminals

106‧‧‧ gate drive circuit

107‧‧‧IGBT

108‧‧‧ diode

201‧‧‧IGBT

202‧‧‧External MOSFET

203‧‧‧Drive IC

204‧‧‧MOS transistor built into the emitter side

205‧‧‧drift resistance

206, 207‧‧‧ pn diodes built into the collector

208‧‧‧Power terminal

209‧‧‧Output terminal

210‧‧‧ shot extremes

211‧‧‧gate electrode

212‧‧‧gate electrode

Fig. 1 is a view showing an IGBT according to a first embodiment of the present invention.

FIG. 2 is an example of a circuit using the IGBT of the first embodiment.

FIG. 3 shows a driving sequence of the embodiment 1 of the embodiment.

FIG. 4 is a diagram showing the relationship between the on-voltage and the turn-off loss of the first embodiment.

Fig. 5 is a view showing an IGBT according to a second embodiment of the present invention.

Fig. 6 is a view showing an IGBT according to a third embodiment of the present invention.

Fig. 7 is a view showing an IGBT according to a variation of Embodiment 3 of the embodiment.

Fig. 8 is a view showing an IGBT according to a fourth embodiment of the present invention.

Fig. 9 is a view showing an IGBT according to a variation of Embodiment 4 of the embodiment.

Fig. 10 is a view showing an IGBT according to a fifth embodiment of the present invention.

Fig. 11 is a view showing an IGBT according to a sixth embodiment of the present invention.

Fig. 12 is a view showing an IGBT according to a variation of Embodiment 6 of the embodiment.

Fig. 13 is a view showing an IGBT of a seventh embodiment of the present invention.

Fig. 14 is a diagram showing a power conversion device according to a ninth embodiment of the present invention.

FIG. 15 shows an IGBT disclosed in Patent Document 1.

Fig. 16 is a view showing a diode of the eighth aspect of the present invention.

Hereinafter, a semiconductor device of the present invention will be described in detail based on the illustrated embodiments. In the entire drawings, the same components are denoted by the same reference numerals, and the repeated description thereof will be omitted. In addition, in the figure, p-, p, p+, etc. indicate that the semiconductor layer is p Type, and in this order, the impurity concentration is relatively high. Further, the marks n-, n, n+ indicate that the semiconductor layer is n-type, and in this order, the impurity concentration is relatively high.

(Form 1)

Fig. 1 is a cross-sectional view showing an IGBT of a first embodiment of the present invention.

In the IGBT of the first aspect of the present invention, the n-substrate 1, the p-type base layer 2 selectively formed on the surface of the n-substrate 1, and the n+-type source formed on the surface of the p-type base layer are provided. a layer 3 and an emitter electrode 4 electrically connected to the p-type base layer 2 and the n + -type source layer 3 and formed on the surface of the n + -type source layer 3, and being n-substrate 1 and n+ type source The gate electrode 6 is provided on the surface of the p-type base layer 2 sandwiched by the layer 3 via the gate oxide film 5. Further, in the IGBT of the first embodiment of the present embodiment, the p + -type high-concentration emitter layer 7 and the p-type low-concentration emitter layer 8 are interposed by a part of the n-layer 1 on the other surface of the n-substrate 1 . They are separated from each other into individual p-type conductivity type semiconductor layers. Further, the respective electrodes 9 and 10 are electrically connected to the p + -type high-concentration emitter layer 7 and the p-type low-concentration emitter layer 8 , respectively. That is, this IGBT becomes a 4-terminal element.

2 is an example of a circuit using the IGBT of FIG. 1. The collector terminal c1 corresponds to a terminal connected to the p+ type high concentration emitter layer 7 of FIG. 1, and the terminal c2 corresponds to a p-type low concentration emitter layer. 8 terminal. In this example, the collector terminal c2 of the IGBT 201 is connected to the output terminal 209 (C) via the MOSFET 202 operating as a switch, and the other side The set terminal c1 of the face is directly connected to the output terminal 209 (C). However, the collector terminal c1 can be connected to the output terminal 209 (C) via a switching element different from the MOSFET 202, and the switching element is preferably an insulating gate type element such as a MOSFET or an IGBT. Further, instead of the MOSFET 202, another insulating gate control type element such as an IGBT may be used.

When the IGBT 201 is turned on, a voltage (for example, 15 V) is applied to the gate electrode 6 (terminal G1), and a voltage (for example, 0 V) at which the MOSFET 202 is turned off is input to the terminal G2 so that current flows through the collector terminal c1 and the emitter terminal 210. between. Thereby, since a small number of carriers (holes) are injected into the n-substrate 1 from the p+ type high-concentration emitter layer 7 connected to the terminal c1, the conductivity is modulated and the on-voltage is reduced. An electric signal is input to the terminal G2 from the number μs at which the terminal G1 (IGBT 201) is turned off, and the current mainly flows between the collector terminal c2 and the emitter terminal 210. Although the collector terminals c1 and c2 are commonly connected to the output terminal 209 (C), since the built-in voltage of the p-type low-concentration emitter layer 8 having a low impurity concentration is low, the electron current easily flows into the p-type low. Concentration emitter layer 8 (terminal c2). For this reason, since the minority carriers injected from the collector are reduced, the charge accumulated in the n-substrate 1 is reduced, so that the turn-off loss can be reduced. Further, since OFF operates as a low-injection IGBT, it is possible to suppress the generation of the tail current and increase the rebound voltage between the collector and the emitter.

3 is a driving sequence of the gate electrode 6 (terminal G1) and the gate electrode 212 (terminal G2) of the MOSFET 202. During the period 1 when a minority carrier is injected with a high amount, the MOS transistor 204 is input to the terminal G1. The voltage of ON is input to the terminal G2 and the voltage at which the MOSFET 202 is turned off. During this period, since a small number of carriers are injected at a high amount, the on-voltage is small compared with other periods. During the period 2, when a minority carrier is injected with a low amount, an ON signal is input to the terminal G2 from 0.1 to 10 μs before the terminal G1 is turned OFF. Since the injection of a small number of carriers is low, the charge accumulated in the n-substrate is reduced, and the loss when the terminal G1 is switched from ON to OFF is reduced. Incidentally, in the period 2, although the minority carriers accumulated in the n-substrate 1 are reduced, the on-voltage is increased, but since the period during which the terminals G1 and G2 are turned on (the lag time) is short, the total loss is almost Do not increase. During the period in which the IGBT 201 is turned off, the voltage at which the IGBT 201 is turned off is input to the terminal G1, and the voltage at which the MOSFET 202 is turned on is input to the terminal G2. The terminal G2 inputs an OFF signal in the period 3 during which the OFF signal is input to the terminal G1, and thereafter only the terminal G1 is switched from OFF to ON, and the process shifts to the period 4. The period 4 is the same period as the period 1, and thereafter, the sequence from the period 1 to 3 is repeated. In this embodiment, the resistance between the turn-on voltage and the turn-off loss can be improved by such a driving sequence.

FIG. 4 illustrates an example of the relationship between the on-voltage and the turn-off loss, and the bounce voltage is the same size. The comparative example corresponding to FIG. 15 and the first aspect of the present embodiment are shown in the drawing. In the case of comparison with the same on-voltage, the turn-off loss of the embodiment of the present embodiment was reduced by 57% in comparison with the comparative example, and the characteristics were greatly improved.

As described above, in the IGBT of the present embodiment, by forming the p + -type high-concentration emitter layer 7 and the p-type low-concentration emitter layer 8 on the collector side, and providing individual electrodes, it is possible to suppress the set. Polar-emitter The rebound voltage is increased to improve the resistance between the turn-on voltage and the turn-off loss.

(Form 2)

Fig. 5 is a cross-sectional structural view of an IGBT according to a second embodiment of the present invention. In the IGBT shown in the second aspect, the impurity concentration ratio is set between the n-substrate 1 and the p+ type high concentration emitter layer 7, and between the n-substrate 1 and the p-type low concentration emitter layer 8. The n-buffer layer 12 having a high n-substrate 1 and a lower impurity concentration than the p+-type high-concentration emitter layer 7. Since the thickness of the n-substrate 1 supplied with the desired breakdown voltage can be reduced by the n buffer layer 12, the resistance between the on-voltage and the breakdown voltage can be improved.

(Form 3)

Fig. 6 is a cross-sectional view showing the structure of an IGBT according to a third embodiment of the present invention. In the IGBT shown in the third aspect, the impurity concentration of 1×10 ¹⁸ to 1×10 ²¹ cm ^-3 is set between the p + -type high-concentration emitter layer 7 and the p-type low-concentration emitter layer 8 . Concentration n+ layer 13.

With such a structure, the action of the parasitic pnp bipolar transistor composed of the p+ type high concentration emitter layer 7 and the n-substrate 1 (or n buffer layer 12) and the p-type low concentration emitter layer 8 can be suppressed. . When the parasitic pnp transistor operates, the adjustment of the minority carrier injection using the external switching element 11 (switching of the p+ type high concentration emitter layer 7 and the p-type low concentration emitter layer 8) becomes difficult, affecting the conduction. The exchange of voltage and turn-off loss. For example, if the parasitic transistor operates when the external switching element 11 is turned on, a minority carrier is injected from the p+ type high concentration emitter layer 7 at a high amount, so that the n-substrate 1 is charged. The cumulative amount of holes increases and the turn-off loss increases.

In the embodiment of Fig. 6, all of the regions sandwiched by the p+ type high-concentration emitter layer 7 and the p-type low-concentration emitter layer 8 are high-concentration n+ layers 13, but are p+-type high-concentration emitter layers. The structure in which a portion sandwiched by the p-type low-concentration emitter layer 8 is a high-concentration n+ layer 13 can also suppress the operation of the parasitic transistor. Further, the depth of the high-concentration n+ layer 13 may be made shallower than the p+-type high-concentration emitter layer 7 and the p-type low-concentration emitter layer 8. However, if the high-concentration n+ layer 13 is made deeper than the p-type high-concentration emitter layer 7 and the p-type low-concentration emitter layer 8 as shown in FIG. 7, the operation of the parasitic pnp bipolar transistor can be suppressed.

(Form 4)

Fig. 8 is a cross-sectional view showing the IGBT of the fourth embodiment of the present invention. In the IGBT shown in the fourth aspect, the insulating layer 14 is provided between the p+ type high concentration emitter layer 7 and the p-type low concentration emitter layer 8.

By adopting such a structure, the operation of the parasitic transistor can be suppressed more than the form 3 of the embodiment. In the second embodiment, the high-concentration n+ layer 13 is provided to suppress the operation of the parasitic transistor. However, in the fourth embodiment, a part of the n layers of the parasitic pnp transistor is made an insulating layer to suppress the operation of the parasitic transistor. In Fig. 8, the entire region sandwiched by the p+ type high-concentration emitter layer 7 and the p-type low-concentration emitter layer 8 is the insulating layer 14, but the p+ type high-concentration emitter layer 7 and the p-type are used. The region in which the low-concentration emitter layer 8 is sandwiched may be a structure of the insulating layer 14, and the depth of the insulating layer 14 may be shallower than that of the p+-type high-concentration emitter layer 7 and the p-type low-concentration emitter layer 8. this Further, when the insulating layer 14 is deeper than the p + -type high-concentration emitter layer 7 and the p-type low-concentration emitter layer 8 as shown in FIG. 9, the operation of the parasitic pnp bipolar transistor can be suppressed.

(Form 5)

Fig. 10 is a cross-sectional structural view of an IGBT according to a fifth embodiment of the present invention. In the IGBT shown in the fifth aspect, the distance ln between the p + -type high-concentration emitter layer 7 and the p-type low-concentration emitter layer 8 is longer than the diffusion distance Lp (ln > Lp) of the hole.

With such a configuration, the parasitic pnp bipolar transistor can be suppressed without providing a high concentration n+ layer and an insulating layer or the like between the p+ type high concentration emitter layer 7 and the p-type low concentration emitter layer 8. The action. The diffusion distance Lp of the hole is obtained from the square root of the product of the diffusion coefficient Dp of the cavity and the lifetime τp. When Lp is longer than the width ln of the base region, the parasitic transistor operates. The reason is that the hole injected from the emitter region (for example, the p-type low-concentration emitter layer 8) is not recombined in the base region (n buffer layer 12 or n-substrate 1) and is diffused to reach the collector region. (for example, p+ type high concentration emitter layer 7). Therefore, since Lp is shortened or ln is increased to cause the holes to be combined and eliminated before reaching the collector region, the operation of the parasitic transistor can be suppressed. In the case where the impurity concentration of the n layer (n-substrate 1 in FIG. 10) between the p + -type high-concentration emitter layer 7 and the p-type low-concentration emitter layer 8 is 1 × 10 ¹⁷ cm ^-3 or less, It is most preferable that ln is 5 μm or more.

The diffusion distance Lp can be shortened by shortening the lifetime τp, and can be controlled by introducing the life decay element into the collector side. For recombining the holes The life-attenuating element utilizes a heavy metal such as gold or platinum or an irradiation damage due to radiation such as an electron beam; thereby, the operation of the parasitic transistor can be suppressed by shortening the ln to a level of 1 μm.

(Form 6)

11 and 12 respectively show cross-sectional structures of an IGBT according to a sixth embodiment of the present invention and a modified example thereof. In the case of such IGBTs, an n+ type hole barrier layer 15 is provided between the p+ type high concentration emitter layer 7 and the n buffer layer 12 (or n-substrate 1).

With such a structure, the hole current flowing from the p-type low-concentration emitter layer 8 to the p+-type high-concentration emitter layer 7 can be suppressed, and the operation of the parasitic pnp bipolar transistor can be suppressed.

(Form 7)

Fig. 13 is a cross-sectional view showing the IGBT of the embodiment of the present invention.

The IGBT of the seventh embodiment of the present invention includes an n-substrate 1, a p-type base layer 2 selectively formed on the surface of the n-substrate 1, and an n+-type source layer 3 formed on the surface of the p-type base layer. The emitter electrode 4 electrically connected to the p-type base layer 2 and the n + -type source layer 3 and formed on the surface of the n + -type source layer 3, and sandwiched by the n-substrate 1 and the n + -type source layer 3 The gate electrode 6 is provided on the surface of the p-type base layer 2 via the gate oxide film 5. Further, in the present embodiment, the p + -type high-concentration emitter layer 7 and the p-type low-concentration emitter layer 8 are formed on the opposite surface of the n-substrate 1 in the same manner as in the first embodiment. Formed in a state of being separated from each other, the collector electrode 20 is connected to the p + -type high-concentration emitter layer 7 , and the n-substrate 1 is sandwiched between the p-type high-concentration emitter layer 7 and the p-type low-concentration emitter layer 8 The second gate electrode 18 is formed on the surface via the second gate oxide film 17. The p + -type high-concentration emitter layer 7 and the p-type low-concentration emitter layer 8 are electrically connected to each other through the p-type inversion layer 19 formed by inputting a negative voltage to the second gate electrode.

With such a configuration, as in the case where the external switching element is provided, the resistance between the ON voltage and the turn-off loss can be improved. In Fig. 13, although the region between the p + -type high-concentration emitter layer 7 and the p-type low-concentration emitter layer 8 is the n-substrate 1, it is formed as an n-type well layer having an impurity concentration higher than that of the n-substrate (not The structure shown in the figure) is also possible.

(Form 8)

Fig. 16 is a cross-sectional view showing a diode of a form 8 of the embodiment of the present invention.

In the aspect of the diode of the eighth aspect of the present invention, the n-substrate 1 and the cathode-side n+ layer 21 formed on the surface of the n-substrate 1 are provided, and the cathode electrode 22 is provided on the surface of the n+ layer 21. On the other hand, on the other side of the n-substrate 1, the p+ type high concentration emitter layer 7 and the p-type low concentration emitter layer 8 are separated from each other by the n-substrate 1 intervening, and are p+ type. The high-concentration emitter layer 7 and the p-type low-concentration emitter layer 8 are respectively connected to individual electrodes.

Since the amount of minority carriers accumulated in the n-substrate 1 can be adjusted by such a configuration, the forward voltage drop and recovery loss can be improved. Replace.

(Formation 9)

FIG. 14 shows an example of a power conversion device using an IGBT or a diode described in the above embodiments.

The form of the embodiment of Fig. 14 is an inverter. A series circuit in which two IGBTs 107 are connected in series is connected between the DC terminals 101 and 102. The series circuit has a phase number of alternating current, and the series connection points of the series circuits are connected to the alternating current terminals 103, 104, and 105. In the present embodiment, the number of phases of the alternating current is three phases, and three series circuits are provided. Further, the diode 108 is connected in anti-parallel to each of the IGBTs 107.

Each of the IGBTs 107 is driven by ON/OFF by the gate drive circuit 106, and DC power received at the DC terminals 101 and 102 is converted into AC power, and AC power is output from the AC terminals 103, 104, and 105.

As the IGBT 107, the IGBTs of the first to seventh embodiments of the present embodiment described above are used. Further, the diode of the eighth aspect to be implemented may be used as the diode 108. Further, the IGBT 107 may be a conventional IGBT, and the diode of the eighth aspect to be implemented may be used as the diode 108.

By applying the IGBT or the diode described in the above embodiments to the power conversion device, the power loss of the power conversion device can be reduced.

Further, the ninth embodiment of the present embodiment is an inverter device, but may be applied to other power conversion devices such as a converter and a chopper. According to the IGBT and the diode of the present invention, the same effect can be obtained.

The embodiment of the present invention is not limited to the embodiment described above, and it is needless to say that various modifications can be made without departing from the spirit and scope of the invention.

For example, the shape of the gate on the emitter side is not limited to a planar type, and may be a groove type, and the gate may be configured in a stripe shape and a mesh shape.

Further, although the above-described embodiment is a vertical IGBT and a vertical diode, it may be a horizontal IGBT or a lateral diode. In addition, the semiconductor material may be tantalum or tantalum carbide.

1‧‧‧n-substrate

2‧‧‧p-type base layer

3‧‧‧n source layer

4‧‧ ‧ emitter electrode

5‧‧‧Oxide film

6‧‧‧Gate electrode

7‧‧‧p type high concentration emitter layer

8‧‧‧p type low concentration emitter layer

9‧‧‧ Collector electrode connected to p-type high concentration emitter layer

10‧‧‧ Collector electrode connected to p-type low concentration emitter layer

Claims (15)

A semiconductor device comprising: a second conductive type base layer selectively formed on a first main surface of a first conductive type semiconductor substrate; and a first conductive layer formed on a surface of the second conductive type base layer a source layer; a second conductivity type high concentration emitter layer and a second conductivity type low concentration emitter layer which are separated from each other on the second main surface of the first conductivity type semiconductor substrate; and electrically connected to the first a conductive main layer and a first main electrode of the first conductive type source layer; and the second conductive type group sandwiched between the first conductive type semiconductor substrate and the first conductive type source layer a gate electrode provided on a surface of the electrode layer via a gate oxide film; and each of the plurality of electrodes electrically connected to the second conductivity type high concentration emitter layer and the second conductivity type low concentration emitter layer The second main electrode. The semiconductor device according to claim 1, wherein the second conductivity type low concentration emitter layer is electrically connected to the second conductivity type high concentration emitter layer via a switching means. The semiconductor device according to claim 1 or 2, wherein the first conductive type semiconductor substrate has a first region in contact with the second conductive type high-concentration emitter layer and the second conductive type low-concentration emitter layer Conductive buffer layer. The semiconductor device according to claim 1 or 2, wherein the first conductivity type high concentration layer is provided between the second conductivity type high concentration emitter layer and the second conductivity type emitter low concentration emitter layer. The semiconductor device according to claim 4, wherein the first conductive type high concentration layer has a depth from the second main surface deeper than the second conductive type high concentration emitter layer and the second conductive type emitter Floor. The semiconductor device according to claim 1 or 2, wherein an insulating layer is provided between the second conductivity type high concentration emitter layer and the second conductivity type emitter layer. The semiconductor device according to claim 6, wherein the insulating layer is deeper than the second main surface of the second conductive type high-concentration emitter layer and the second conductive type emitter layer. The semiconductor device according to claim 1 or 2, wherein a distance between the second conductivity type high concentration emitter layer and the second conductivity type low concentration emitter layer is longer than a minority of the first conductivity type semiconductor substrate The diffusion distance of the carrier. The semiconductor device according to claim 1 or 2, wherein the second conductivity type high concentration emitter layer and the first conductivity type semiconductor substrate have a first impurity concentration higher than that of the first conductivity type semiconductor substrate Conductive hole barrier layer. The semiconductor device of claim 2, wherein the switching means is an insulating gate. A semiconductor device as claimed in claim 2, wherein the aforementioned The switching means is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The semiconductor device according to claim 2, wherein the switching means switches from OFF to ON before the signal applied to the gate electrode is switched from ON to OFF, and the switching is performed during a signal OFF period of the gate electrode The means switches from ON to OFF. A semiconductor device comprising: a diode having a first conductivity type high concentration cathode side layer formed on a first main surface of a first conductivity type semiconductor substrate; and a first conductivity type semiconductor substrate a second conductivity type high concentration emitter layer and a second conductivity type low concentration emitter layer which are separated from each other by a main surface; and a first main electrode electrically connected to the first conductivity type high concentration cathode side layer; Each of the second main electrode electrically connected to the second conductive type high-concentration emitter layer and the second conductive type low-concentration emitter layer; and the second conductive type low-concentration emitter A switching means for electrically connecting the layer to the second conductivity type high concentration emitter layer. A power conversion device comprising: a pair of DC terminals; a plurality of series connection circuits connected between the input terminals and having a plurality of semiconductor switching elements connected in series; and a plurality of series connection points connected to the plurality of series connection circuits AC terminal, by the above plurality of semiconductor switching The component is turned ON/OFF to perform power conversion, and each of the plurality of semiconductor switching elements is a semiconductor device according to any one of claims 1 to 12. A power conversion device comprising: a pair of DC terminals; a plurality of series connection circuits connected between the input terminals and having a plurality of semiconductor switching elements connected in series; and a plurality of each of the plurality of semiconductor switching elements connected in anti-parallel And a plurality of AC terminals connected to the series connection points of the plurality of series connection circuits, wherein the plurality of semiconductor switching elements are ON/OFF for power conversion, characterized in that: the plurality of diodes Each of them is a semiconductor device as claimed in claim 13.