WO2021014570A1

WO2021014570A1 - Silicon carbide semiconductor device, power conversion device, and method for manufacturing silicon carbide semiconductor device

Info

Publication number: WO2021014570A1
Application number: PCT/JP2019/028858
Authority: WO
Inventors: 祐輔宮田; 英之八田; 梨菜田中; 勝俊菅原; 裕福井
Original assignee: 三菱電機株式会社
Priority date: 2019-07-23
Filing date: 2019-07-23
Publication date: 2021-01-28
Also published as: JPWO2021014570A1; JP6735950B1

Abstract

This silicon carbide semiconductor device includes a trench gate MOSFET and a trench SBD. A gate trench (11) in which a gate electrode (13) of the MOSFET is embedded passes through a source region (5) and a body region (4) and reaches a drift layer (3). An SBD trench (21) in which a Schottky electrode (22) of the SBD is embedded passes through the source region (5) and the body region (4) and reaches the drift layer (3), and the side walls of the SBD trench (21) has a more gradual slope than the side walls of the gate trench (11).

Description

Manufacturing method of silicon carbide semiconductor device, power conversion device and silicon carbide semiconductor device

The present invention relates to a silicon carbide semiconductor device having a trench gate and a power conversion device using the same.

A semiconductor device for power that incorporates a unipolar type switching element such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a unipolar type freewheeling diode such as a Schottky barrier diode (SBD) is known. .. Such a semiconductor device can be realized by arranging a MOSFET cell and an SBD cell in parallel on the same chip, and generally, a Schottky electrode is provided in a specific region in the chip, and that region is designated as an SBD. It can be realized by operating it.

By incorporating a freewheeling diode in the chip of the switching element, the cost can be reduced compared to the case where the freewheeling diode is externally attached to the switching element. In particular, in a MOSFET using silicon carbide (SiC) as a base material, it is one of the merits that the bipolar operation due to the parasitic pn diode can be suppressed by incorporating the SBD. This is because in a silicon carbide semiconductor device, the reliability of the device may be impaired due to the expansion of crystal defects caused by the recombination energy of carriers due to the operation of the parasitic pn diode.

Further, in a trench gate type MOSFET having a structure in which a gate electrode is embedded in a trench formed in a semiconductor layer, a side wall of the trench is compared with a planar type MOSFET having a structure in which a gate electrode is formed on the surface of the semiconductor layer. There is an advantage that the channel width density can be improved and the on-resistance can be reduced because the channel can be formed. However, there is a problem that electric field concentration is likely to occur at the bottom of the trench when a high voltage is applied in the off state of the semiconductor device. In particular, in a trench gate type silicon carbide semiconductor device, since SiC has a high dielectric breakdown strength, gate insulating film fracture due to electric field concentration at the bottom of the trench is likely to occur prior to avalanche fracture in the drift layer. Electric field concentration at the bottom of the trench tends to be a problem.

For example, Patent Document 1 below discloses a technique for alleviating electric field concentration at the bottom of a trench by providing a conductive protective layer different from the drift layer at the bottom of the trench in a trench gate type semiconductor device. .. In this technique, it is generally important to keep the trench spacing small because the effect of electric field relaxation decreases as the trench spacing, that is, the protective layer spacing increases.

Further, for example, in Patent Document 2, in a semiconductor device including a trench gate type MOSFET, an SBD in which a Schottky electrode is embedded in a trench by replacing a part of the gate electrodes with a Schottky electrode (hereinafter, “trench type SBD”” is provided. ) Is formed, and the Schottky electrode is connected to the source electrode of the MOSFET, thereby disclosing a technique of incorporating an SBD as a freewheeling diode into a trench gate type MOSFET. In this technique, since the trench spacing can be kept small, a high unipolar current can be obtained from the built-in SBD while suppressing the electric field applied to the bottom of the trench.

Japanese Unexamined Patent Publication No. 2006-210392 Japanese Unexamined Patent Publication No. 2009-278067

Like the semiconductor devices of

Patent Documents

1 and 2, a trench (SBD trench) in which a Schottky electrode of a trench type SBD is embedded is provided between a trench (gate trench) in which a gate electrode of a trench gate type MOSFET is embedded. In this case, the metal in the SBD trench is generally formed by a physical vapor deposition method such as a sputtering method. However, when the side wall of the SBD trench is close to perpendicular to the wafer surface, that is, when the SBD trench has a non-tapered shape, it is difficult to form electrodes in all of the SBD trench, and thermal reliability due to poor contact or cavity formation. There is concern about deterioration of sex.

On the other hand, the electrodes in the gate trench are generally formed by a chemical deposition method, and the side wall of the gate trench is preferably in a plane orientation having good channel characteristics. Therefore, the side wall of the gate trench is required to be close to perpendicular to the wafer surface.

The present invention has been made to solve the above problems, and in a silicon carbide semiconductor device including a trench gate type MOSFET and a trench type SBD, the good thermal reliability of the SBD and the good channel characteristics of the MOSFET are obtained. The purpose is to achieve both.

The silicon carbide semiconductor device according to the present invention includes a semiconductor layer made of silicon carbide, a first conductive type drift layer formed on the semiconductor layer, and a second conductive type body formed on the surface layer portion of the drift layer. A region, a first conductive type source region formed on the surface layer of the body region, a gate trench that penetrates the source region and the body region and reaches the drift layer, and an inner surface of the gate trench. The gate insulating film, the gate electrode formed on the gate insulating film in the gate trench, the source region and the body region, reach the drift layer, and the side wall is inclined more than the gate trench. It includes a gentle SBD trench and a shotkey electrode formed in the SBD trench and forming a shotkey contact with the drift layer.

According to the present invention, in MOSFET, good channel characteristics can be obtained because the trench gate has a non-tapered shape. Further, in the SBD, since the SBD trench has a tapered shape, the coverage of the Schottky electrode is good and the formation of cavities can be suppressed, so that good thermal reliability can be obtained.

The object, features, aspects, and advantages of the present invention will be made clearer by the following detailed description and accompanying drawings.

It is a vertical sectional view which shows the structure of the semiconductor device which concerns on Embodiment 1. FIG. It is a process drawing for demonstrating the manufacturing method of the semiconductor device which concerns on Embodiment 1. FIG. It is a process drawing for demonstrating the manufacturing method of the semiconductor device which concerns on Embodiment 1. FIG. It is a process drawing for demonstrating the manufacturing method of the semiconductor device which concerns on Embodiment 1. FIG. It is a process drawing for demonstrating the manufacturing method of the semiconductor device which concerns on Embodiment 1. FIG. It is a process drawing for demonstrating the manufacturing method of the semiconductor device which concerns on Embodiment 1. FIG. It is a vertical sectional view which shows the modification of the structure of the semiconductor device which concerns on Embodiment 1. FIG. It is a vertical sectional view which shows the modification of the structure of the semiconductor device which concerns on Embodiment 1. FIG. It is a vertical sectional view which shows the modification of the structure of the semiconductor device which concerns on Embodiment 1. FIG. It is a vertical sectional view which shows the modification of the structure of the semiconductor device which concerns on Embodiment 1. FIG. It is a vertical sectional view which shows the modification of the structure of the semiconductor device which concerns on Embodiment 1. FIG. It is a vertical sectional view which shows the modification of the structure of the semiconductor device which concerns on Embodiment 1. FIG. It is a vertical sectional view which shows the modification of the structure of the semiconductor device which concerns on Embodiment 1. FIG. It is a vertical sectional view which shows the modification of the structure of the semiconductor device which concerns on Embodiment 1. FIG. It is a vertical sectional view which shows the modification of the structure of the semiconductor device which concerns on Embodiment 1. FIG. It is a vertical sectional view which shows the modification of the structure of the semiconductor device which concerns on Embodiment 1. FIG. It is a vertical sectional view which shows the modification of the structure of the semiconductor device which concerns on Embodiment 1. FIG. It is a vertical sectional view which shows the modification of the structure of the semiconductor device which concerns on Embodiment 1. FIG. It is a block diagram which shows the structure of the power conversion system to which the power conversion apparatus which concerns on Embodiment 2 is applied.

<Embodiment 1>
FIG. 1 is a vertical sectional view showing a configuration of a silicon carbide semiconductor device according to a first embodiment of the present invention. The silicon carbide semiconductor device includes a MOSFET region 10 that functions as a MOSFET and an SBD region 20 that functions as a Schottky barrier diode (SBD). In the following description, the "impurity concentration" in each region represents the maximum value of the impurity concentration in that region.

The silicon carbide semiconductor device according to the first embodiment is formed by using the semiconductor substrate 1 which is the first conductive type silicon carbide semiconductor substrate. In the present embodiment, the semiconductor substrate 1 is composed of 4H-SiC belonging to the hexagonal system among the crystal polymorphs of silicon carbide, and has 1 degree or more and 8 degrees or less between the wafer surface and the (11-20) surface. It is assumed that the silicon carbide semiconductor substrate has an off-angle of.

A semiconductor layer 2 which is an epitaxial growth layer of silicon carbide is formed on the semiconductor substrate 1. A body region 4, which is a second conductive type semiconductor region, is formed on the surface layer portion of the semiconductor layer 2. A source region 5, which is a first conductive type semiconductor region, is formed on the surface layer portion of the body region 4. Of the semiconductor layer 2, the first conductive type portion excluding the body region 4 and the source region 5 becomes the drift layer 3.

Here, the impurity concentration of the first conductive type of the drift layer 3 is 1.0 × 10 ¹⁴ cm ^-3 or more and 1.0 × 10 ¹⁷ cm ^-3 or less, and the withstand voltage performance required for the silicon carbide semiconductor device and the like. It is set according to. The impurity concentration of the second conductive type in the body region 4 is 1.0 × 10 ¹⁴ cm ^-3 or more and 1.0 × 10 ¹⁸ cm ^-3 or less. The concentration of impurities in the first conductive type in the source region 5 is 1.0 × 10 ¹⁸ cm ^-3 or more and 1.0 × 10 ²¹ cm ^-3 or less.

In the MOSFET region 10, a gate trench 11 is formed in the semiconductor layer 2 through the source region 5 and the body region 4 to reach the drift layer 3. As shown in FIG. 1, the gate trench 11 has a non-tapered shape in which the side wall has a steep inclination angle with respect to the surface of the semiconductor layer 2. Specifically, the angle formed by the side wall of the gate trench 11 and the surface of the semiconductor layer 2 is 80 degrees or more and 90 degrees or less.

A gate insulating film 12 is formed on the inner surface (bottom surface and side surface) of the gate trench 11. Further, a gate electrode 13 is formed on the gate insulating film 12 in the gate trench 11 so as to be embedded in the gate trench 11.

The gate trench 11 is formed in a striped shape extending in the <11-20> direction of the semiconductor substrate 1 in a plan view of the semiconductor layer 2. That is, a plurality of gate trenches 11 are formed at equal intervals in the semiconductor layer 2. In the present embodiment, since the surface of the semiconductor substrate 1 has an off angle with respect to the (11-20) plane, the <11-20> direction corresponds to the direction of the step flow in the epitaxial growth of the semiconductor layer 2.

When the longitudinal direction of the gate trench 11 is parallel to the direction of the step flow, the surface orientations of the left and right side walls of the gate trench 11 can be matched, so that the variation in characteristics between the left and right side walls is suppressed, and the gate The reliability of the insulating film 12 is improved. Further, when the longitudinal direction of the gate trench 11 is perpendicular to the direction of the step flow, the side wall of the gate trench 11 on which the channel is formed can be a surface having high channel mobility.

An interlayer insulating film 14 is formed on the upper surface of the semiconductor layer 2 of the MOSFET region 10 so as to cover the gate electrode 13 embedded in the gate trench 11. A contact hole reaching the source region 5 is formed in the interlayer insulating film 14, and a source contact electrode 15 is formed on the source region 5 exposed to the contact hole. The source contact electrode 15 is a silicide formed by reacting a metal such as Ni or Ti with a silicon carbide semiconductor in the source region 5, and forms ohmic contact with the source region 5.

Although omitted in FIG. 1, a second conductive type well contact region having a higher impurity concentration than the body region 4 is further provided on the surface layer portion of the body region 4, and the source contact electrode 15 is provided with the source region 5 and the source region 5. Ohmic contacts may be made with both well contact areas. The concentration of impurities in the second conductive type in the well contact region shall be 1.0 × 10 ¹⁸ cm ^-3 or more and 1.0 × 10 ²¹ cm ^-3 or less.

A source electrode 16 is formed on the interlayer insulating film 14. The source electrode 16 is electrically connected to the source contact electrode 15 through a contact hole formed in the interlayer insulating film 14. As a result, the source electrode 16 is electrically connected to the source region 5 via the source contact electrode 15. In the example of FIG. 1, a metal film which is a part of the Schottky electrode 22 described later is interposed between the source electrode 16 and the source contact electrode 15. Further, a drain electrode 17 is formed on the back surface of the semiconductor substrate 1 (the surface opposite to the semiconductor layer 2).

In the SBD region 20, an SBD trench 21 that penetrates the source region 5 and the body region 4 and reaches the drift layer 3 is formed in the semiconductor layer 2. As shown in FIG. 1, the SBD trench 21 has a tapered shape in which the side surface is gently inclined as compared with the gate trench. That is, the width of the SBD trench 21 becomes narrower at the deeper position. Specifically, the angle formed by the side wall of the SBD trench 21 and the surface of the semiconductor layer 2 is 45 degrees or more and 85 degrees or less. The SBD trench 21 is formed in a striped shape extending in the <11-20> direction of the semiconductor substrate 1 in the plan view of the semiconductor layer 2, similarly to the gate trench 11. That is, a plurality of SBD trenches 21 are formed at equal intervals in the semiconductor layer 2, and the gate trench 11 and the SBD trench 21 are parallel to each other.

A Schottky electrode 22 is embedded in the SBD trench 21. The Schottky electrode 22 is in contact with the inner surface (bottom surface and side surface) of the SBD trench 21. The Schottky electrode 22 is a metal film or metal silicide containing Ti or Mo, and forms a Schottky contact with the drift layer 3.

In the present embodiment, the Schottky electrode 22 is formed along the inner surface of the SBD trench 21, and a part of the source electrode 16 is formed on the Schottky electrode 22 in the SBD trench 21. That is, a part of the source electrode 16 is embedded in the SBD trench 21 together with the Schottky electrode 22.

As described above, the silicon carbide semiconductor device of the first embodiment includes a trench gate type MOSFET formed in the MOSFET region 10 and a trench type SBD formed in the SBD region 20, and the gate trench 11 of the MOSFET is The SBD trench 21 of the non-tapered shape and SBD has a tapered shape.

Here, the operation of the silicon carbide semiconductor device of FIG. 1 will be briefly described. First, the operation of the MOSFET region 10 will be described. In the MOSFET region 10, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 13, a channel in which the conductive type is inverted, that is, a first conductive type channel is formed in a portion adjacent to the gate trench 11 in the body region 4. .. As a result, a first conductive type current path is formed between the source electrode 16 and the drain electrode 17, and the MOSFET region 10 is turned on.

On the other hand, when the voltage of the gate electrode 13 is equal to or less than the threshold voltage, no channel is formed in the body region 4, so that even if a voltage is applied between the drain electrode 17 and the source electrode 16, the drain electrode 17 can be used. Almost no current flows to the source electrode 16. That is, the MOSFET region 10 is turned off. In this way, the MOSFET region 10 switches between an on state and an off state according to the voltage applied to the gate electrode 13.

Next, the operation of the SBD area 20 will be described. When a forward voltage is applied to the Schottky barrier diode in the SBD region 20 when the MOSFET region 10 is off, a unipolar current flows between the Schottky electrode 22 and the drain electrode 17. At this time, if the forward voltage is increased, the unipolar current increases for a while, but when the potential difference between the source electrode 16 and the drain electrode 17 reaches a certain value or more, the body region 4 and the drain electrode 17 A bipolar current derived from the pn junction between the body region 4 and the drift layer 3 flows between the and.

The unipolar current that can be passed immediately before the bipolar current starts to flow is called the "maximum unipolar current". The magnitude of this maximum unipolar current is affected by the pn junction between the body region 4 and the drift layer 3 and the potential difference generated in the drift layer 3.

Subsequently, the manufacturing method of the silicon carbide semiconductor device according to the first embodiment will be described with reference to the process diagrams of FIGS. 2 to 6.

First, a semiconductor substrate 1 made of a silicon carbide semiconductor having a semiconductor layer 2 formed on its upper surface is prepared. Specifically, the first conductive type semiconductor layer 2 is formed on the first conductive type semiconductor substrate 1 by the epitaxial growth method. Then, the body region 4 and the source region 5 are formed by implanting impurities into the surface layer portion of the semiconductor layer 2 (FIG. 2). At this time, the first conductive type portion of the semiconductor layer 2 in which the body region 4 and the source region 5 are not formed becomes the drift layer 3.

When a well contact region is provided on the surface layer of the body region 4, a well contact region is formed in a desired region by selective ion implantation using a mask.

When forming the first conductive type region such as the source region 5, ion implantation of, for example, N or P is performed as a donor. When forming a second conductive type region such as the body region 4, ion implantation of, for example, Al or B is performed as an acceptor. Further, the order in which each region of the semiconductor layer 2 is formed may be any order. The method for forming each region is not limited to the ion implantation method, and for example, a part or all of the regions may be formed by epitaxial growth.

Next, a non-tapered gate trench 11 that penetrates the source region 5 and the body region 4 and reaches the drift layer 3 is formed in the semiconductor layer 2 of the MOSFET region 10 by reactive ion etching (RIE) or dry etching. .. Similarly, by RIE or dry etching, a tapered SBD trench 21 that penetrates the source region 5 and the body region 4 and reaches the drift layer 3 is formed in the semiconductor layer 2 of the SBD region 20 (FIG. 3). The non-tapered gate trench 11 and the tapered SBD trench 21 are made separately, that is, the inclination angle of the side wall of each trench is adjusted, for example, the amount of active species reaching the bottom of the trench, gas partial pressure, and DC. This can be done by controlling the bias value and the like.

After that, a heat treatment is performed to electrically activate the impurities injected into the semiconductor layer 2. This heat treatment may be performed in an atmosphere of an inert gas such as argon or nitrogen, or in a vacuum at a temperature of 1500 ° C. or higher and 2200 ° C. or lower, and for a time of 0.5 minutes or longer and 60 minutes or shorter. This heat treatment may be performed in a state where the surface of the semiconductor layer 2 is covered with a protective film made of carbon. By doing so, it is possible to suppress the occurrence of etching due to the reaction with the residual water and residual oxygen in the semiconductor layer 2 during the heat treatment, and it is possible to prevent the surface of the semiconductor layer 2 from being roughened.

Next, the gate insulating film 12 is formed on the inner surfaces (bottom surface and side surface) of the gate trench 11 and the SBD trench 21. Further, by embedding, for example, polycrystalline silicon in the gate trench 11 and the SBD trench 21 by a chemical deposition method or the like, the gate electrode 13 is formed in the gate trench 11 and the SBD trench 21 (FIG. 4). However, the gate insulating film 12 and the gate electrode 13 in the SBD trench 21 are removed in a subsequent step.

Subsequently, an interlayer insulating film 14 is formed on the semiconductor layer 2, and a contact that reaches the source region 5 (and a well contact region (not shown)) reaches the interlayer insulating film 14 by selective etching or the like using a resist mask or the like. Form a hole. Then, the source contact electrode 15 is formed on the upper surface of the source region 5 (and the well contact region) exposed in the contact hole (FIG. 5).

As a method for forming the source contact electrode 15, for example, a metal film containing Ni as a main component is formed on the interlayer insulating film 14 including the inside of the contact hole, and the metal film is carbonized by heat treatment at 600 ° C. or higher and 1100 ° C. or lower. There is a method of reacting with a silicon semiconductor to form a silicide film, and then removing the unreacted metal film remaining on the interlayer insulating film 14 by wet etching. After removing the unreacted metal film, the heat treatment may be performed again. In this case, the second heat treatment is performed at a higher temperature than the first heat treatment to form an ohmic contact with a lower contact resistance between the source contact electrode 15 and the source region 5 (and the well contact region). be able to.

After that, the gate electrode 13 and the gate insulating film 12 in the SBD trench 21 are removed by selective etching or the like using a mask (FIG. 6). Subsequently, a Schottky electrode 22 is formed on the upper surface of the semiconductor layer 2 including the inside of the SBD trench 21, and a source electrode 16 is further formed on the Schottky electrode 22. The Schottky electrode 22 may be in contact with at least the source electrode 16 and the drift layer 3, but may also be in contact with the source contact electrode 15, the source region 5, and the body region 4 as shown in FIG. Then, the drain electrode 17 is formed on the back surface of the semiconductor substrate 1. The Schottky electrode 22, the source electrode 16, and the drain electrode 17 can be formed by using a physical vapor deposition method such as a sputtering method.

By the above steps, the silicon carbide semiconductor device having the configuration shown in FIG. 1 is formed.

In the silicon carbide semiconductor device according to the first embodiment, since the Schottky electrode 22 is embedded in the SBD trench 21, the area of the SBD contact can be secured even on the side wall of the SBD trench 21. Therefore, it is possible to obtain an SBD contact having a large area while keeping the lateral dimension of FIG. 1 small. As a result, the chip area required to pass the same unipolar current can be reduced, and the chip cost can be reduced.

Further, since the gate trench 11 has a non-tapered shape, the MOS structure can be formed in a plane orientation having high controllability of the formation rate of the gate insulating film 12, channel characteristics, and reliability of the gate insulating film 12 and the channel. it can. Therefore, good channel characteristics can be obtained in the MOSFET.

Further, since the SBD trench 21 has a tapered shape, the coverage of the Schottky electrode 22 is improved, and the Schottky electrode 22 can be brought into contact with the entire surface of the drift layer 3 on the inner wall of the SBD trench 21. As a result, it is possible to increase the unipolar current due to the increase in the contact area and suppress the local current concentration due to the narrowing of the contact area.

Further, since the SBD trench 21 has a tapered shape, the source electrode 16 can be formed in the SBD trench 21 covered with the Schottky electrode 22 as shown in FIG. The source electrode 16 is formed by depositing Al to which Si is added by a physical vapor deposition method such as a sputtering method, but the tapered shape of the SBD trench 21 suppresses the formation of cavities in the source electrode 16 and flattens the surface. It is effective for. When a cavity is formed in the SBD trench 21, the source electrode 16 is preferably embedded in the SBD trench 21 without a gap because there is a concern of local heat generation due to a decrease in thermal reliability and a narrowing of the current path. .. Further, when the surface shape of the source electrode 16 is rough, the surface flatness of the source electrode 16 is high because there is a concern that the thermal reliability may decrease due to the decrease in the adhesion of the wire bonding and the local heat generation may occur due to the narrowing of the current path. Is desirable.

[Modification example]
Hereinafter, some modifications of the configuration of the silicon carbide semiconductor device according to the first embodiment will be shown.

As shown in FIG. 7, the depth of the SBD trench 21 may be shallower than that of the gate trench 11. In this case, as shown later in FIG. 11, contact between the SBD trench 21 and the second conductive type protective layer 31 provided under the trench 21 can be avoided, and the leakage current when the SBD is off can be reduced. can do. On the contrary, as shown in FIG. 8, the depth of the SBD trench 21 may be deeper than that of the gate trench 11. In this case, the electric field strength applied to the gate insulating film 12 in the gate trench 11 is reduced, and the reliability of the silicon carbide semiconductor device is improved.

As shown in FIG. 9 or 10, a second conductive type protective layer 31 may be formed in the drift layer 3 so as to be in contact with the bottoms of one or both of the gate trench 11 and the SBD trench 21. The protective layer 31 has the effect of relaxing the electric field applied around the bottom of the gate trench 11 or the SBD trench 21.

As shown in FIG. 11, the protective layer 31 provided under the SBD trench 21 may be formed at a position separated from the SBD trench 21. In this case, the leakage current flowing through the protective layer 31 can be reduced when the SBD is in the off state.

As shown in FIG. 12, an ohmic electrode 23 that ohmic-bonds to the protective layer 31 may be formed in the SBD trench 21. That is, the ohmic electrode 23 that makes ohmic contact with the protective layer 31 may be interposed at the boundary portion between the Schottky electrode 22 and the protective layer 31 in the SBD trench 21. As a result, charge transfer due to the depletion behavior around the protective layer 31 at the bottom of the SBD trench 21 becomes smooth, and high-speed switching of the SBD becomes possible.

In FIG. 1, the Schottky electrode 22 is made of a material different from that of the source electrode 16, but as shown in FIG. 13, the source electrode 16 in the SBD trench 21 is brought into contact with the inner surface of the SBD trench 21. A part of the source electrode 16 may be used as the Schottky electrode 22. In other words, the Schottky electrode 22 may be made of the same material as the source electrode 16. In this case, the manufacturing cost can be reduced as compared with the case where the source electrode 16 and the Schottky electrode 22 are made of different materials.

As shown in FIG. 14, a second conductive type connection is connected between the body region 4 and the protective layer 31 so as to be adjacent to one or both side walls of the gate trench 11 and the SBD trench 21 in the drift layer 3. The layer 32 may be formed. In this case, at the time of turn-on or turn-off, the path length when extracting or returning the electric charge from the protective layer 31 is shortened, the potential increase is suppressed, and as a result, the reliability of the gate insulating film 12 is improved.

As shown in FIG. 15, a first conductive type first low resistance layer 41 having a higher impurity concentration than the drift layer 3 may be formed in the drift layer 3 so as to be adjacent to the side wall of the gate trench 11. The impurity concentration of the first low resistance layer 41 is, for example, 1.0 × 10 ¹⁶ cm ^-3 or more and 1.0 × 10 ¹⁹ cm ^-3 or less. As a result, depletion between the body region 4 and the protective layer 31 of the MOSFET region 10 can be suppressed, and the current flowing from the drain electrode 17 to the source electrode 16 can be increased when the MOSFET is in the ON state.

As shown in FIG. 16, a first conductive type second low resistance layer 42 having a lower impurity concentration than the drift layer 3 may be formed in the drift layer 3 so as to be adjacent to the side wall of the SBD trench 21. As a result, depletion between the body region 4 of the SBD region 20 and the protective layer 31 can be suppressed, and the unipolar current flowing from the drain electrode 17 to the source electrode 16 through the SBD can be increased. The impurity concentration of the second low resistance layer 42 is set higher than the impurity concentration of the first conductive type of the drift layer 3 and smaller than the impurity concentration of the first conductive type of the first low resistance layer 41, for example, 1.0. It is set in the range larger than × 10 ^{16 and} smaller than 1.0 × 10 ¹⁹ cm ^-3 .

As shown in FIG. 17, the connection layer 32, the first low resistance layer 41, and the second low resistance layer 42 may coexist in one unit cell. As a result, the reliability of the gate insulating film 12 is improved, the current flowing from the drain electrode 17 to the source electrode 16 when the MOSFET is turned on is increased, and the unipolar current flowing from the drain electrode 17 to the source electrode 16 through the SBD is increased. All the effects of the first low resistance layer 41 and the second low resistance layer 42 can be obtained.

As shown in FIG. 18, when the silicon carbide semiconductor device is provided with a plurality of protective layers 31 formed on the bottoms of one or both of the gate trench 11 and the SBD trench 21, the drift layer 3 is provided between the protective layers 31. The first conductive type third low resistance layer 43 having a lower impurity concentration may be formed. The impurity concentration of the third low resistance layer 43 does not need to be adjusted with the first low resistance layer 41 and the second low resistance layer 42, and is 1.0 × 10 ¹⁶ cm ^-3 or more, 1.0 × 10 ¹⁹ cm ^{−. It} may be set in the range of ³ or less. The third low resistance layer 43 can suppress depletion between the protective layers 31 and increase the current flowing from the drain electrode 17 to the source electrode 16 when the MOSFET is turned on.

<Embodiment 2>
In this embodiment, the semiconductor device according to the first embodiment described above is applied to a power conversion device. The application of the semiconductor device according to the first embodiment is not limited to a specific power conversion device, but hereinafter, as the second embodiment, when the semiconductor device according to the first embodiment is applied to a three-phase inverter. Will be described.

FIG. 19 is a block diagram showing a configuration of a power conversion system to which the power conversion device according to the present embodiment is applied.

The power conversion system shown in FIG. 19 includes a power source 100, a power conversion device 200, and a load 300. The power source 100 is a DC power source, and supplies DC power to the power converter 200. The power supply 100 can be configured by various things, for example, it can be configured by a DC system, a solar cell, a storage battery, or by a rectifier circuit or an AC / DC converter connected to an AC system. May be good. Further, the power supply 100 may be configured by a DC / DC converter that converts the DC power output from the DC system into a predetermined power.

The power conversion device 200 is a three-phase inverter connected between the power supply 100 and the load 300, converts the DC power supplied from the power supply 100 into AC power, and supplies AC power to the load 300. As shown in FIG. 19, the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, and a drive circuit 202 that outputs a drive signal that drives each switching element of the main conversion circuit 201. A control circuit 203 that outputs a control signal for controlling the drive circuit 202 to the drive circuit 202 is provided.

The load 300 is a three-phase electric motor driven by AC power supplied from the power converter 200. The load 300 is not limited to a specific application, and is an electric motor mounted on various electric devices. For example, the load 300 is used as an electric motor for a hybrid vehicle, an electric vehicle, a railroad vehicle, an elevator, or an air conditioner.

The details of the power converter 200 will be described below. The main conversion circuit 201 includes a switching element and a freewheeling diode (not shown), and when the switching element switches, the DC power supplied from the power supply 100 is converted into AC power and supplied to the load 300. There are various specific circuit configurations of the main conversion circuit 201, but the main conversion circuit 201 according to the present embodiment is a two-level three-phase full bridge circuit, and has six switching elements and each switching element. It can consist of six anti-parallel freewheeling diodes. The semiconductor device according to the first embodiment described above is applied to each switching element and freewheeling diode of the main conversion circuit 201. The six switching elements are connected in series for each of the two switching elements to form an upper and lower arm, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full bridge circuit. Then, the output terminals of the upper and lower arms, that is, the three output terminals of the main conversion circuit 201 are connected to the load 300.

The drive circuit 202 generates a drive signal for driving the switching element of the main conversion circuit 201 and supplies it to the control electrode of the switching element of the main conversion circuit 201. Specifically, according to the control signal from the control circuit 203 described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrodes of each switching element. When the switching element is kept in the on state, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when the switching element is kept in the off state, the drive signal is a voltage equal to or lower than the threshold voltage of the switching element. It becomes a signal (off signal).

The control circuit 203 controls the switching element of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, the time (on time) for each switching element of the main conversion circuit 201 to be in the on state is calculated based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the on-time of the switching element according to the voltage to be output. Then, a control command (control signal) is output to the drive circuit 202 so that an on signal is output to the switching element that should be turned on at each time point and an off signal is output to the switching element that should be turned off. The drive circuit 202 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to this control signal.

In the power conversion device according to the present embodiment, the semiconductor device according to the first embodiment is applied as the switching element and the freewheeling diode of the main conversion circuit 201, so that the reliability can be improved.

In the present embodiment, an example of applying the semiconductor device according to the first embodiment to a two-level three-phase inverter has been described, but the application of the semiconductor device according to the first embodiment is not limited to this. It can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is used, but a three-level or multi-level power conversion device may be used, and when power is supplied to a single-phase load, a single-phase inverter is used. The semiconductor device according to 1 may be applied. Further, when supplying electric power to a DC load or the like, it is also possible to apply the semiconductor device according to the first embodiment to a DC / DC converter or an AC / DC converter.

Further, the power conversion device to which the semiconductor device according to the first embodiment is applied is not limited to the case where the above-mentioned load is an electric motor, for example, a discharge machine, a laser machine, an induction heating cooker, or a non-electric machine. It can be used as a power supply device for a contact power supply system, and can also be used as a power conditioner for a photovoltaic power generation system, a power storage system, or the like.

It should be noted that, within the scope of the invention, the present invention can be freely combined with each embodiment, and each embodiment can be appropriately modified or omitted.

Although the present invention has been described in detail, the above description is exemplary in all embodiments and the present invention is not limited thereto. It is understood that a myriad of variations not illustrated can be envisioned without departing from the scope of the invention.

1 semiconductor substrate, 2 semiconductor layer, 3 drift layer, 4 body area, 5 source area, 10 MOSFET area, 11 gate trench, 12 gate insulating film, 13 gate electrode, 14 interlayer insulating film, 15 source contact electrode, 16 source electrode , 17 drain electrode, 20 SBD region, 21 SBD trench, 22 shot key electrode, 23 ohmic electrode, 31 protective layer, 32 connection layer, 41 first low resistance layer, 42 second low resistance layer, 43 third low resistance layer. , 100 power supply, 200 power conversion device, 201 main conversion circuit, 202 drive circuit, 203 control circuit, 300 load.

Claims

A semiconductor layer made of silicon carbide and
The first conductive type drift layer formed on the semiconductor layer and
A second conductive body region formed on the surface layer of the drift layer and
The first conductive type source region formed on the surface layer of the body region and
A gate trench that penetrates the source region and the body region and reaches the drift layer.
The gate insulating film formed on the inner surface of the gate trench and
A gate electrode formed on the gate insulating film in the gate trench and
An SBD trench that penetrates the source region and the body region to reach the drift layer and has a gentler side wall slope than the gate trench.
A Schottky electrode formed in the SBD trench and forming a Schottky contact with the drift layer,
A silicon carbide semiconductor device comprising.
The gate trench has a non-tapered shape.
The gate insulating film has a tapered shape.
The silicon carbide semiconductor device according to claim 1.
The angle formed by the side wall of the gate trench and the surface of the semiconductor layer is in the range of 80 degrees or more and 90 degrees or less.
The angle formed by the side wall of the SBD trench and the surface of the semiconductor layer is in the range of 45 degrees or more and 85 degrees or less.
The silicon carbide semiconductor device according to claim 1.
The depth of the gate trench is deeper than that of the SBD trench.
The silicon carbide semiconductor device according to any one of claims 1 to 3.
The depth of the gate trench is shallower than that of the SBD trench.
The silicon carbide semiconductor device according to any one of claims 1 to 3.
Further comprising a second conductive protective layer formed to contact the bottom of the gate trench and one or both of the SBD trenches.
The silicon carbide semiconductor device according to any one of claims 1 to 5.
The protective layer is separated from the bottom of the SBD trench.
The silicon carbide semiconductor device according to claim 6.
An ohmic electrode formed in the SBD trench and making ohmic contact with the protective layer is further provided.
The silicon carbide semiconductor device according to claim 6 or 7.
A second conductive type connecting layer formed adjacent to the gate trench and one or both side walls of the SBD trench and connecting between the body region and the protective layer is further provided.
The silicon carbide semiconductor device according to any one of claims 6 to 8.
Further comprising a source electrode formed on the semiconductor layer and electrically connected to the source region.
The Schottky electrode is formed along the inner surface of the SBD trench.
A part of the source electrode is formed on the Schottky electrode in the SBD trench.
The silicon carbide semiconductor device according to any one of claims 1 to 9.
The drift layer further includes a first conductive type first low resistance layer having a higher impurity concentration than the drift layer, which is formed so as to be adjacent to the side wall of the gate trench.
The silicon carbide semiconductor device according to any one of claims 1 to 10.
A first conductive type second low resistance layer having a lower impurity concentration than the drift layer, which is formed in the drift layer so as to be adjacent to the side wall of the SBD trench, is further provided.
The silicon carbide semiconductor device according to any one of claims 1 to 11.
Provided with a plurality of the protective layers
A first conductive type third low resistance layer having a lower impurity concentration than the drift layer, which is formed between the protective layers, is further provided.
The silicon carbide semiconductor device according to any one of claims 6 to 9.
The longitudinal direction of the gate trench and the SBD trench is parallel to the direction of the step flow of the semiconductor layer.
The silicon carbide semiconductor device according to any one of claims 1 to 13.
The longitudinal direction of the gate trench and the SBD trench is perpendicular to the direction of the step flow of the semiconductor layer.
The silicon carbide semiconductor device according to any one of claims 1 to 13.
A main conversion circuit having the silicon carbide semiconductor device according to any one of claims 1 to 15 and converting and outputting input power.
A drive circuit that outputs a drive signal for driving the silicon carbide semiconductor device to the silicon carbide semiconductor device,
A control circuit that outputs a control signal for controlling the drive circuit to the drive circuit,
A power converter equipped with.
A process of forming a first conductive type drift layer on a semiconductor layer made of silicon carbide, and
A step of forming a second conductive type body region on the surface layer portion of the drift layer, and
A step of forming a first conductive type source region on the surface layer portion of the body region, and
A step of forming a gate trench that penetrates the source region and the body region and reaches the drift layer.
The process of forming a gate insulating film on the inner surface of the gate trench and
A step of forming a gate electrode on the gate insulating film in the gate trench, and
A step of forming an SBD trench having a side wall slope gentler than that of the gate trench, which penetrates the source region and the body region and reaches the drift layer.
A step of forming a Schottky electrode forming a Schottky contact with the drift layer in the SBD trench, and
A method for manufacturing a silicon carbide semiconductor device.
The gate electrode is formed by a chemical deposition method and is formed.
The Schottky electrode is formed by a physical vapor deposition method.
The method for manufacturing a silicon carbide semiconductor device according to claim 17.