JP7047981B1 - Silicon carbide semiconductor device and power conversion device - Google Patents

Silicon carbide semiconductor device and power conversion device Download PDF

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JP7047981B1
JP7047981B1 JP2021551951A JP2021551951A JP7047981B1 JP 7047981 B1 JP7047981 B1 JP 7047981B1 JP 2021551951 A JP2021551951 A JP 2021551951A JP 2021551951 A JP2021551951 A JP 2021551951A JP 7047981 B1 JP7047981 B1 JP 7047981B1
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裕 福井
英之 八田
梨菜 田中
基 吉田
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Abstract

本開示の炭化珪素半導体装置は、活性領域と終端領域とを有し、第１導電型のドリフト層（２０）と、ドリフト層上の第２導電型のボディ領域（３０）と、活性領域内のボディ領域上に設けられた第１導電型のソース領域（４０）と、ボディ領域およびソース領域を貫通するゲートトレンチ（８１）と、ゲートトレンチ内にゲート絶縁膜（５０）を介して形成されたゲート電極（６０）と、活性領域内のボディ領域を貫通して形成されたショットキトレンチ（８２）と、終端領域内のボディ領域を貫通して互いに平行に形成された複数のＪＢＳトレンチ（８３）と、ソース領域と接続され、ショットキトレンチ内およびＪＢＳトレンチ内にドリフト層とショットキ接続されるソース電極（７０）とを備える。本開示の炭化珪素半導体装置によれば、信頼性の高い炭化珪素半導体装置を得ることができる。The silicon carbide semiconductor device of the present disclosure has an active region and a terminal region, and has a first conductive type drift layer (20), a second conductive type body region (30) on the drift layer, and an active region. A first conductive type source region (40) provided on the body region of the above, a gate trench (81) penetrating the body region and the source region, and a gate insulating film (50) formed in the gate trench. The gate electrode (60), the Schottki trench (82) formed through the body region in the active region, and the plurality of JBS trenches (83) formed in parallel with each other through the body region in the terminal region. ), And a source electrode (70) connected to the source region and connected to the drift layer in the Schottky trench and the JBS trench. According to the silicon carbide semiconductor device of the present disclosure, a highly reliable silicon carbide semiconductor device can be obtained.

Description

本開示は、トレンチゲートを有する炭化珪素半導体装置および炭化珪素半導体装置を用いた電力変換装置に関するものである。 The present disclosure relates to a silicon carbide semiconductor device having a trench gate and a power conversion device using the silicon carbide semiconductor device.

ＭＯＳＦＥＴ（Ｍｅｔａｌ－Ｏｘｉｄｅ－Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｆｉｅｌｄ－Ｅｆｆｅｃｔ－Ｔｒａｎｓｉｓｔｏｒ：絶縁ゲート型電界効果トランジスタ）等のユニポーラ型のスイッチング素子と、ショットキバリアダイオード（ＳＢＤ：Ｓｃｈｏｔｔｋｙ Ｂａｒｒｉｅｒ Ｄｉｏｄｅ）等のユニポーラ型の還流ダイオードとを内蔵する電力用の半導体装置が知られている。そのような半導体装置は、同一のチップにＭＯＳＦＥＴセルとＳＢＤセルとを並列に配置することで実現でき、一般的には、チップ内の特定の領域にショットキ電極を設け、その領域をＳＢＤとして動作させることで実現できる。 It incorporates a unipolar type switching element such as a MOSFET (Metal-Oxide-Semiconductor Field-Effective-Transistor: isolated gate type field effect transistor) and a unipolar type recirculation diode such as a Schottky barrier diode (SBD). Semiconductor devices for electric power are known. Such a semiconductor device can be realized by arranging a MOSFET cell and an SBD cell in parallel on the same chip, and generally, a Schottky electrode is provided in a specific region in the chip and the region operates as an SBD. It can be realized by letting it.

スイッチング素子のチップに還流ダイオードを内蔵させることで、スイッチング素子に還流ダイオードを外付けする場合に比べてコストを低減できる。特に、炭化珪素（ＳｉＣ）を母材として用いたＭＯＳＦＥＴでは、ＳＢＤを内蔵させることにより寄生ｐｎダイオードによるバイポーラ動作を抑制できることもメリットの一つとなる。なぜなら、炭化珪素半導体装置では、寄生ｐｎダイオード動作によるキャリアの再結合エネルギーに起因する結晶欠陥の拡張により、素子の信頼性が損なわれる場合があるからである。 By incorporating a freewheeling diode in the chip of the switching element, the cost can be reduced as compared with the case where the freewheeling diode is externally attached to the switching element. In particular, in a MOSFET using silicon carbide (SiC) as a base material, it is one of the merits that the bipolar operation due to the parasitic pn diode can be suppressed by incorporating the SBD. This is because, in a silicon carbide semiconductor device, the reliability of the device may be impaired due to the expansion of crystal defects caused by the recombination energy of carriers due to the operation of the parasitic pn diode.

また、半導体層に形成されたトレンチ内にゲート電極が埋め込まれた構造を有するトレンチゲート型ＭＯＳＦＥＴでは、半導体層の表面上にゲート電極が形成された構造を有するプレーナー型ＭＯＳＦＥＴに比べ、トレンチの側壁にチャネルを形成できる分、チャネル長を小さくでき、オン抵抗を低減できることが知られていた（例えば特許文献１）。 Further, in the trench gate type MOSFET having a structure in which the gate electrode is embedded in the trench formed in the semiconductor layer, the side wall of the trench is compared with the planar type MOSFET having the structure in which the gate electrode is formed on the surface of the semiconductor layer. It has been known that the channel length can be reduced and the on-resistance can be reduced by the amount that the channel can be formed (for example, Patent Document 1).

さらに、ＳＢＤ内蔵のＭＯＳＦＥＴにおいて、終端構造部分においてＳＢＤを高密度に配置する方法として、終端ボディ領域内にＪＢＳ（Ｊｕｎｃｔｉｏｎ Ｂａｒｒｉｅｒ Ｓｃｈｏｔｔｋｙ）を配置する構造が知られていた（例えば特許文献２）。 Further, in a MOSFET having a built-in SBD, a structure in which a JBS (Junction Barrier Schottky) is arranged in a terminal body region has been known as a method of arranging an SBD at a high density in a terminal structure portion (for example, Patent Document 2).

特開２０１９－２１６２２３号（図１等）JP-A-2019-216223 (Fig. 1 etc.) 国際公開ＷＯ２０１４／１６２９６９号（図２１等）International release WO2014 / 162969 (Fig. 21 etc.)

しかしながら、ＳＢＤ内蔵のトレンチ型ＭＯＳＦＥＴの終端領域としてｐ型ボディ領域をトレンチ底部に形成した場合、耐圧を保持するためにより高密度のユニポーラ電流が必要になる場合があった。
また、特許文献２のような半導体層の表面に形成するＪＢＳと特許文献１のようなトレンチ側壁にショットキ面を形成する構造とを同一チップ内に形成すると、製造工程が多くなり、製造コストが高くなる場合があった。However, when a p-type body region is formed at the bottom of the trench as the terminal region of the trench-type MOSFET with a built-in SBD, a higher density unipolar current may be required to maintain the withstand voltage.
Further, if the JBS formed on the surface of the semiconductor layer as in Patent Document 2 and the structure for forming the Schottky surface on the trench side wall as in Patent Document 1 are formed in the same chip, the number of manufacturing steps increases and the manufacturing cost increases. It could be expensive.

本開示は、上記のような課題を解決するためになされたものであり、ＳＢＤを内蔵させたトレンチ型のＳｉＣＭＯＳＦＥＴにおいて、終端構造に高密度のユニポーラ電流を流すことが可能な構造を提供することを目的とする。 The present disclosure has been made to solve the above-mentioned problems, and to provide a structure capable of passing a high-density unipolar current through a terminal structure in a trench-type SiC MOSFET with a built-in SBD. With the goal.

本開示の炭化珪素半導体装置は、活性領域と終端領域とを有し、第１導電型のドリフト層と、ドリフト層上に設けられた第２導電型のボディ領域と、活性領域内のボディ領域上に設けられた第１導電型のソース領域と、ボディ領域およびソース領域をドリフト層の厚さ方向に貫通するゲートトレンチと、ゲートトレンチ内にゲート絶縁膜を介してボディ領域と対向して形成されたゲート電極と、活性領域内のボディ領域をドリフト層の厚さ方向に貫通しゲートトレンチに平面視で平行に形成されたショットキトレンチと、終端領域内のボディ領域をドリフト層の厚さ方向に貫通して互いに平面視で平行に形成された複数のＪＢＳトレンチと、ゲートトレンチの底の前記ドリフト層内に形成された第１保護領域と、ショットキトレンチの底の前記ドリフト層内に形成された第２保護領域と、ＪＢＳトレンチの底の前記ドリフト層内に形成された第３保護領域と、ソース領域と接続されショットキトレンチ内およびＪＢＳトレンチ内にドリフト層とショットキ接続されて形成されるソース電極とを備えたものである。


The silicon carbide semiconductor device of the present disclosure has an active region and a terminal region, a first conductive type drift layer, a second conductive type body region provided on the drift layer, and a body region within the active region. A first conductive type source region provided above, a gate trench penetrating the body region and the source region in the thickness direction of the drift layer, and a gate trench formed in the gate trench facing the body region via a gate insulating film. The gate electrode is formed, the Schottky trench is formed parallel to the gate trench in a plan view by penetrating the body region in the active region in the thickness direction of the drift layer, and the body region in the termination region is formed in the thickness direction of the drift layer. A plurality of JBS trenches formed in parallel to each other in a plan view, a first protective region formed in the drift layer at the bottom of the gate trench, and a drift layer formed in the drift layer at the bottom of the Schottky trench. A second protected region, a third protected region formed in the drift layer at the bottom of the JBS trench, and a source formed by being connected to the source region and connected to the drift layer in the Schottky trench and in the JBS trench. It is equipped with an electrode.

本発明にかかる炭化珪素半導体装置によれば、終端構造に高密度のユニポーラ電流を流すことができ、信頼性の高い炭化珪素半導体装置を低い製造コストで得ることができる。 According to the silicon carbide semiconductor device according to the present invention, a high-density unipolar current can be passed through the terminal structure, and a highly reliable silicon carbide semiconductor device can be obtained at a low manufacturing cost.

実施の形態１に係る炭化珪素半導体装置の断面図である。It is sectional drawing of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. 実施の形態１に係る炭化珪素半導体装置の平面図である。It is a top view of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. 実施の形態１に係る別形態の炭化珪素半導体装置の断面図である。It is sectional drawing of the silicon carbide semiconductor device of another embodiment which concerns on Embodiment 1. FIG. 実施の形態１に係る別形態の炭化珪素半導体装置の断面図である。It is sectional drawing of the silicon carbide semiconductor device of another embodiment which concerns on Embodiment 1. FIG. 実施の形態１に係る別形態の炭化珪素半導体装置の断面図である。It is sectional drawing of the silicon carbide semiconductor device of another embodiment which concerns on Embodiment 1. FIG. 実施の形態１に係る別形態の炭化珪素半導体装置の断面図である。It is sectional drawing of the silicon carbide semiconductor device of another embodiment which concerns on Embodiment 1. FIG. 実施の形態１に係る別形態の炭化珪素半導体装置の断面図である。It is sectional drawing of the silicon carbide semiconductor device of another embodiment which concerns on Embodiment 1. FIG. 実施の形態２に係る炭化珪素半導体装置の断面図である。It is sectional drawing of the silicon carbide semiconductor device which concerns on Embodiment 2. FIG. 実施の形態２に係る別形態の炭化珪素半導体装置の断面図である。It is sectional drawing of the silicon carbide semiconductor device of another embodiment which concerns on Embodiment 2. FIG. 実施の形態２に係る別形態の炭化珪素半導体装置の断面図である。It is sectional drawing of the silicon carbide semiconductor device of another embodiment which concerns on Embodiment 2. FIG. 実施の形態３に係る炭化珪素半導体装置の断面図である。It is sectional drawing of the silicon carbide semiconductor device which concerns on Embodiment 3. FIG. 実施の形態３に係る別形態の炭化珪素半導体装置の断面図である。It is sectional drawing of the silicon carbide semiconductor device of another embodiment which concerns on Embodiment 3. FIG. 実施の形態４に係る炭化珪素半導体装置の平面図である。It is a top view of the silicon carbide semiconductor device which concerns on Embodiment 4. FIG. 実施の形態５に係る電力変換装置の構成を示す模式図である。It is a schematic diagram which shows the structure of the power conversion apparatus which concerns on Embodiment 5.

以下、添付の図面を参照しながら実施の形態について説明する。なお、図面は模式的に示されるものであり、異なる図面にそれぞれ示されている画像のサイズ及び位置の相互関係は、必ずしも正確に記載されるものではなく、適宜変更され得る。また、以下の説明では、同様の構成要素には同じ符号を付して図示し、それらの名称及び機能も同様のものとする。よって、それらについての詳細な説明を省略する場合がある。 Hereinafter, embodiments will be described with reference to the accompanying drawings. It should be noted that the drawings are schematically shown, and the interrelationship between the sizes and positions of the images shown in different drawings is not always accurately described and may be changed as appropriate. Further, in the following description, similar components are illustrated with the same reference numerals, and their names and functions are also the same. Therefore, detailed description about them may be omitted.

実施の形態１．
図１は、実施の形態１にかかる炭化珪素半導体装置であるショットキバリアダイオード内蔵トレンチ型炭化珪素ＭＯＳＦＥＴ（ＳＢＤ内蔵ＳｉＣトレンチＭＯＳＦＥＴ）の活性領域から終端領域にかけての一部分の断面図である。また、図２は、図１に示すＳＢＤ内蔵ＳｉＣトレンチＭＯＳＦＥＴに対応する平面図であり、トレンチだけを記載したものである。Embodiment 1.
FIG. 1 is a cross-sectional view of a part of a trench-type silicon carbide MOSFET with a built-in Schottky barrier diode (SiC trench MOSFET with a built-in SBD), which is a silicon carbide semiconductor device according to the first embodiment, from an active region to a terminal region. Further, FIG. 2 is a plan view corresponding to the SiC trench MOSFET with built-in SBD shown in FIG. 1, and only the trench is shown.

図１に示すように、ｎ型で低抵抗の炭化珪素で構成される半導体基板１０の表面上に、ｎ型の炭化珪素で構成されるドリフト層２０が形成されている。ドリフト層２０上にはｐ型の炭化珪素で構成されるボディ領域３０が設けられている。
活性領域においては、ボディ領域３０が形成されたドリフト層２０にゲートトレンチ８１とショットキトレンチ８２とが交互に、かつ、平行に配置されている。ゲートトレンチ８１とショットキトレンチ８２とに隣接するボディ領域３０上には、ｎ型の炭化珪素で構成されるソース領域４０が設けられている。ゲートトレンチ８１とショットキトレンチ８２との間のボディ領域３０の表層部には、低抵抗ｐ型のコンタクト領域９０が形成されている。As shown in FIG. 1, a drift layer 20 made of n-type silicon carbide is formed on the surface of a semiconductor substrate 10 made of n-type low resistance silicon carbide. A body region 30 made of p-type silicon carbide is provided on the drift layer 20.
In the active region, the gate trench 81 and the Schottky trench 82 are arranged alternately and in parallel in the drift layer 20 in which the body region 30 is formed. A source region 40 made of n-type silicon carbide is provided on the body region 30 adjacent to the gate trench 81 and the Schottky trench 82. A low resistance p-type contact region 90 is formed on the surface layer portion of the body region 30 between the gate trench 81 and the Schottky trench 82.

ゲートトレンチ８１は、ソース領域４０の表面からソース領域４０およびボディ領域３０を貫通してドリフト層２０に達するように形成されている。ショットキトレンチ８２は、ソース領域４０の表面からソース領域４０およびボディ領域３０を貫通してドリフト層２０に達するように形成されている。ゲートトレンチ８１内には酸化珪素からなるゲート絶縁膜５０を介してゲート電極６０が形成されている。ゲート電極６０は、不純物濃度が高い低抵抗多結晶珪素で構成されている。ゲート電極６０上には酸化珪素からなる層間絶縁膜５５が形成されている。ショットキトレンチ８２内にはソース電極７０が形成されており、ソース電極７０はドリフト層２０とショットキ接続する。ゲートトレンチ８１の底のドリフト層２０内には、ｐ型の第１保護領域３１が形成されている。ショットキトレンチ８２の底のドリフト層２０内には、ｐ型の第２保護領域３２が形成されている。第１保護領域３１と第２保護領域３２とは、同じ深さで同じ不純物濃度である。 The gate trench 81 is formed so as to reach the drift layer 20 from the surface of the source region 40 through the source region 40 and the body region 30. The Schottki trench 82 is formed so as to reach the drift layer 20 from the surface of the source region 40 through the source region 40 and the body region 30. A gate electrode 60 is formed in the gate trench 81 via a gate insulating film 50 made of silicon oxide. The gate electrode 60 is made of low resistance polycrystalline silicon having a high impurity concentration. An interlayer insulating film 55 made of silicon oxide is formed on the gate electrode 60. A source electrode 70 is formed in the Schottky trench 82, and the source electrode 70 is connected to the drift layer 20 in a Schottky connection. A p-shaped first protected region 31 is formed in the drift layer 20 at the bottom of the gate trench 81. A p-shaped second protected region 32 is formed in the drift layer 20 at the bottom of the Schottky trench 82. The first protected area 31 and the second protected area 32 have the same depth and the same impurity concentration.

図２に示すように、活性領域の平面視上の外側に位置し、活性領域を囲んで形成された終端領域においては、活性領域に近い位置に第１外周トレンチ８４が形成され、活性領域から遠いチップ外周端に近い箇所にはチップ端にまでの第２外周トレンチ８５が形成されている。ここで、第２外周トレンチ８５がチップ端まで達している場合について説明するが、第２外周トレンチ８５はチップ端まで達していなくてもよく、チップ端より内側までに形成されていてもよい。第２外周トレンチ８５がチップ端まで達している場合にはトレンチ形状にはならないが、ここではトレンチがチップ端まで達していようがいまいがトレンチと呼ぶことにする。第１外周トレンチ８４と第２外周トレンチ８５との間には、複数のＪＢＳトレンチ８３が形成されている。ＪＢＳトレンチ８３と第１外周トレンチ８４と第２外周トレンチ８５とは、部分的に分断されている。
活性領域のゲートトレンチ８１とショットキトレンチ８２と、および、終端領域のＪＢＳトレンチ８３、第１外周トレンチ８４と第２外周トレンチ８５とは、同じ深さで形成されている。As shown in FIG. 2, in the terminal region located outside the active region in a plan view and surrounding the active region, the first outer peripheral trench 84 is formed at a position close to the active region, and the first outer peripheral trench 84 is formed from the active region. A second outer peripheral trench 85 up to the tip end is formed at a position near the distant outer peripheral end of the chip. Here, the case where the second outer peripheral trench 85 reaches the tip end will be described, but the second outer peripheral trench 85 may not reach the tip end and may be formed inward from the tip end. When the second outer peripheral trench 85 reaches the tip end, the trench shape is not formed, but here, whether or not the trench reaches the tip end, it is called a trench. A plurality of JBS trenches 83 are formed between the first outer peripheral trench 84 and the second outer peripheral trench 85. The JBS trench 83, the first outer peripheral trench 84, and the second outer peripheral trench 85 are partially separated.
The gate trench 81 and the Schottky trench 82 in the active region, and the JBS trench 83, the first outer peripheral trench 84 and the second outer peripheral trench 85 in the terminal region are formed at the same depth.

終端領域の断面構造について説明する。図１に示すように、終端領域においては、活性領域に近い位置に、その幅がショットキトレンチ８１の幅より大きい第１外周トレンチ８４が形成されている。第１外周トレンチ８４の外周側には、複数のＪＢＳトレンチ８３が形成されている。複数のＪＢＳトレンチ８３の外周側には、第１外周トレンチ８４の幅より幅が大きい第２外周トレンチ８５が形成されている。
ここで、チップのコーナー部以外では、第１外周トレンチ８４、複数のＪＢＳトレンチ８３、第２外周トレンチ８５は互いに平行に形成されている。The cross-sectional structure of the terminal region will be described. As shown in FIG. 1, in the terminal region, a first outer peripheral trench 84 whose width is larger than the width of the Schottki trench 81 is formed at a position close to the active region. A plurality of JBS trenches 83 are formed on the outer peripheral side of the first outer peripheral trench 84. A second outer peripheral trench 85 having a width larger than the width of the first outer peripheral trench 84 is formed on the outer peripheral side of the plurality of JBS trenches 83.
Here, except for the corner portion of the chip, the first outer peripheral trench 84, the plurality of JBS trenches 83, and the second outer peripheral trench 85 are formed in parallel with each other.

第１外周トレンチ８４の底に接するドリフト層２０内には、ｐ型の第３保護領域３３が形成されている。また、第２外周トレンチ８５の底に接するドリフト層２０内の活性領域に近い箇所にはｐ型の第４保護領域３４が形成されている。さらに、第２外周トレンチ８５の底に接するドリフト層２０内の第４保護領域３４の外周側には、第４保護領域３４より不純物濃度が低いＪＴＥ（Ｊｕｎｃｔｉｏｎ Ｔｅｒｍｉｎａｔｉｏｎ Ｅｘｔｅｎｔｉｏｎ）領域３６が形成されている。
また、ＪＢＳトレンチ８３の底に接するドリフト層２０内にはｐ型の第５保護領域３５が形成されている。
ここで、第３保護領域３３、第４保護領域３４、および、第５保護領域３５は、活性領域の第１保護領域３１と第２保護領域３２と同じ深さで同じ不純物濃度である。A p-shaped third protected region 33 is formed in the drift layer 20 in contact with the bottom of the first outer peripheral trench 84. Further, a p-type fourth protected region 34 is formed in a portion of the drift layer 20 in contact with the bottom of the second outer peripheral trench 85 near the active region. Further, a JTE (Junction Tangent Extension) region 36 having a lower impurity concentration than the fourth protected region 34 is formed on the outer peripheral side of the fourth protected region 34 in the drift layer 20 in contact with the bottom of the second outer peripheral trench 85. ..
Further, a p-type fifth protected region 35 is formed in the drift layer 20 in contact with the bottom of the JBS trench 83.
Here, the third protected region 33, the fourth protected region 34, and the fifth protected region 35 have the same impurity concentration at the same depth as the first protected region 31 and the second protected region 32 of the active region.

第１外周トレンチ８４と第２外周トレンチ８５との間のドリフト層２０の表層部には、活性領域のボディ領域３０と同じ深さで同じ不純物濃度のｐ型のボディ領域３０が形成されている。さらに、ボディ領域３０の表層部には、低抵抗でｐ型の高濃度ｐ型領域９１が形成されている。ＪＢＳトレンチ８３の中にはショットキトレンチ８２の中と同様にソース電極７０が形成されており、ソース電極７０とドリフト層２０とはショットキ接続されている。ＪＢＳトレンチ８３上およびボディ領域３０と高濃度ｐ型領域９１上にはソース電極７０が形成されており、ボディ領域３０とソース電極７０とはオーミック接続されている。
複数のＪＢＳトレンチ８３内のソース電極７０とドリフト層２０とのそれぞれのショットキ界面、複数のＪＢＳトレンチ８３の間のボディ領域３０と高濃度ｐ型領域９１、および、第５保護領域３５でＪＢＳを構成する。A p-type body region 30 having the same depth and the same impurity concentration as the body region 30 of the active region is formed on the surface layer portion of the drift layer 20 between the first outer peripheral trench 84 and the second outer peripheral trench 85. .. Further, a p-type high-concentration p-type region 91 with low resistance is formed on the surface layer portion of the body region 30. A source electrode 70 is formed in the JBS trench 83 as in the Schottky trench 82, and the source electrode 70 and the drift layer 20 are connected to the Schottky. A source electrode 70 is formed on the JBS trench 83, the body region 30, and the high-concentration p-type region 91, and the body region 30 and the source electrode 70 are ohmic-connected.
JBS is provided at the respective Schottky interfaces between the source electrode 70 and the drift layer 20 in the plurality of JBS trenches 83, the body region 30 and the high-concentration p-type region 91 between the plurality of JBS trenches 83, and the fifth protected region 35. Configure.

第１外周トレンチ８４の活性領域側の側壁に隣接するドリフト層２０の表層部には、高濃度低抵抗のコンタクト領域９０が形成されており、第１外周トレンチ８４内部の一部のボディ領域３０に面する領域には、ゲート絶縁膜５０を介してゲート電極６０が形成されている。また、第１外周トレンチ８４内部のゲート電極６０が形成されていない領域には、層間絶縁膜５５が形成されており、第１外周トレンチ８４内の層間絶縁膜５５を貫通して形成されたコンタクトホールの底の第３保護領域３３には、低抵抗でｎ型の低抵抗ｎ型領域４１が形成されている。コンタクトホール内のソース電極７０と低抵抗ｎ型領域４１とはオーミック接続されており、第４保護領域３４とソース電極７０とはオーミック接続されていない。 A contact region 90 having a high concentration and low resistance is formed on the surface layer portion of the drift layer 20 adjacent to the side wall of the first outer peripheral trench 84 on the active region side, and a part of the body region 30 inside the first outer peripheral trench 84 is formed. A gate electrode 60 is formed in the region facing the gate via the gate insulating film 50. Further, an interlayer insulating film 55 is formed in a region where the gate electrode 60 inside the first outer peripheral trench 84 is not formed, and a contact formed through the interlayer insulating film 55 in the first outer peripheral trench 84. A low-resistance, n-type low-resistance n-type region 41 is formed in the third protected region 33 at the bottom of the hole. The source electrode 70 in the contact hole and the low resistance n-type region 41 are ohmic connected, and the fourth protected region 34 and the source electrode 70 are not ohmic connected.

第２外周トレンチ８５内部の第４保護領域３４上には、ゲート絶縁膜５０を介してゲート電極６０が形成されている。また、第２外周トレンチ８５内部のゲート電極６０が形成されていない領域およびゲート電極６０上には、層間絶縁膜５５が形成されており、第２外周トレンチ８５内の層間絶縁膜５５を貫通して形成されたコンタクトホールの底の第４保護領域３４には、低抵抗でｎ型の低抵抗ｎ型領域４１が形成されている。コンタクトホール内のソース電極７０と低抵抗ｎ型領域４１とはオーミック接続されており、第３保護領域３３とソース電極７０とはオーミック接続されていない。第２外周トレンチ８５内のゲート電極６０は、ゲート電極６０上の層間絶縁膜５５に形成されたコンタクトホールを介してゲートパッド７１と接続されている。 A gate electrode 60 is formed on the fourth protective region 34 inside the second outer peripheral trench 85 via the gate insulating film 50. Further, an interlayer insulating film 55 is formed in the region where the gate electrode 60 is not formed inside the second outer peripheral trench 85 and on the gate electrode 60, and penetrates the interlayer insulating film 55 in the second outer peripheral trench 85. A low-resistance, n-type low-resistance n-type region 41 is formed in the fourth protected region 34 at the bottom of the contact hole formed. The source electrode 70 in the contact hole and the low resistance n-type region 41 are ohmic connected, and the third protected region 33 and the source electrode 70 are not ohmic connected. The gate electrode 60 in the second outer peripheral trench 85 is connected to the gate pad 71 via a contact hole formed in the interlayer insulating film 55 on the gate electrode 60.

ここで、複数のＪＢＳトレンチ８３は、その間隔が等しく形成されており、活性領域のゲートトレンチ８１とショットキトレンチ８２との間の間隔と同じ間隔で形成されている。また、最も内側のＪＢＳトレンチ８３と第１外周トレンチ８４との間隔および最外周のＪＢＳトレンチ８３と第２外周トレンチ８５との間隔も、複数のＪＢＳトレンチ８３間の間隔と同じになるように形成されている。 Here, the plurality of JBS trenches 83 are formed at equal intervals, and are formed at the same intervals as the intervals between the gate trench 81 and the Schottky trench 82 in the active region. Further, the distance between the innermost JBS trench 83 and the first outer peripheral trench 84 and the distance between the outermost JBS trench 83 and the second outer peripheral trench 85 are also formed to be the same as the distance between the plurality of JBS trenches 83. Has been done.

次に、本実施の形態にかかる炭化珪素半導体装置であるＳＢＤ内蔵ＳｉＣトレンチＭＯＳＦＥＴの製造方法について説明する。
まず、第１主面の面方位が有する（０００１）面から＜１１－２０＞方向に１°以上４°以下傾斜した４Ｈのポリタイプを有する、ｎ型で低抵抗の炭化珪素からなる半導体基板１０の上に、化学気相堆積法（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ：ＣＶＤ法）により、１×１０１５ｃｍ－３以上、１×１０１７ｃｍ－３以下の不純物濃度でｎ型、５μｍ以上、５０μｍ以下の厚さの炭化珪素からなるドリフト層２０をエピタキシャル成長させる。ドリフト層２０の主面も（０００１）面から＜１１－２０＞方向に１°以上４°以下傾斜する。Next, a method of manufacturing a SiC trench MOSFET with a built-in SBD, which is a silicon carbide semiconductor device according to the present embodiment, will be described.
First, an n-type low-resistance silicon carbide semiconductor substrate having a 4H polytype inclined by 1 ° or more and 4 ° or less in the <11-20> direction from the (0001) plane of the plane orientation of the first main surface. On top of 10, by chemical vapor deposition (CVD method), n-type, 5 μm or more, 50 μm or less with an impurity concentration of 1 × 10 15 cm -3 or more and 1 × 10 17 cm -3 or less. The drift layer 20 made of silicon carbide having a thickness is epitaxially grown. The main surface of the drift layer 20 is also inclined by 1 ° or more and 4 ° or less in the <11-20> direction from the (0001) plane.

つづいて、ドリフト層２０の表面にｐ型の不純物であるＡｌ（アルミニウム）をイオン注入する。このとき、Ａｌのイオン注入の深さはドリフト層２０の厚さを超えない０．５μｍ以上、３μｍ以下程度とする。また、イオン注入されたＡｌの不純物濃度は、１×１０１７ｃｍ－３以上、１×１０１９ｃｍ－３以下の範囲でありドリフト層２０の不純物濃度より高くする。本工程によりＡｌイオンが注入された領域がボディ領域３０となる。Subsequently, Al (aluminum), which is a p-type impurity, is ion-implanted on the surface of the drift layer 20. At this time, the depth of ion implantation of Al is set to about 0.5 μm or more and 3 μm or less, which does not exceed the thickness of the drift layer 20. The impurity concentration of the ion-implanted Al is in the range of 1 × 10 17 cm -3 or more and 1 × 10 19 cm -3 or less, which is higher than the impurity concentration of the drift layer 20. The region into which Al ions are injected by this step becomes the body region 30.

次に、ドリフト層２０の表面のボディ領域３０の所定の箇所が開口するようにフォトレジスト等により注入マスクを形成し、ｎ型の不純物であるＮ（窒素）をイオン注入する。Ｎのイオン注入深さはボディ領域３０の厚さより浅いものとする。また、イオン注入したＮの不純物濃度は、１×１０１８ｃｍ－３以上、１×１０２１ｃｍ－３以下の範囲であり、ボディ領域３０のｐ型の不純物濃度を超えるものとする。本工程でＮが注入された領域のうちｎ型を示す領域がソース領域４０となる。その後、注入マスクを除去する。
また、同様の方法により、活性領域のソース領域４０に隣接したボディ領域３０の所定の領域、および、終端領域の第１外周トレンチ８４形成から第２外周トレンチ８５形成領域にかけての領域に、ボディ領域３０の不純物濃度より高い１×１０１９ｃｍ－３以上、１×１０２１ｃｍ－３以下の範囲の不純物濃度になるようにＡｌをイオン注入することにより、コンタクト領域９０と高濃度ｐ型領域９１とを形成する。Next, an injection mask is formed by a photoresist or the like so that a predetermined portion of the body region 30 on the surface of the drift layer 20 is opened, and N (nitrogen), which is an n-type impurity, is ion-implanted. The ion implantation depth of N is shallower than the thickness of the body region 30. The impurity concentration of the ion-implanted N is in the range of 1 × 10 18 cm -3 or more and 1 × 10 21 cm -3 or less, and exceeds the p-type impurity concentration in the body region 30. Of the regions in which N is injected in this step, the region showing n type is the source region 40. Then remove the injection mask.
Further, by the same method, a predetermined region of the body region 30 adjacent to the source region 40 of the active region and a region from the formation of the first outer peripheral trench 84 to the formation of the second outer peripheral trench 85 of the terminal region are formed in the body region. Contact region 90 and high-concentration p-type region 91 by ion-implanting Al so that the impurity concentration is in the range of 1 × 10 19 cm -3 or more and 1 × 10 21 cm -3 or less, which is higher than the impurity concentration of 30. And form.

次に、活性領域のソース領域４０が形成された領域の一部、ソース領域４０が形成されていない領域の一部、および、終端領域のボディ領域３０が形成された領域を開口するレジストマスクを形成し、ドライエッチング法により、ゲートトレンチ８１、ショットキトレンチ８２、ＪＢＳトレンチ８３、第１外周トレンチ８４および、第２外周トレンチ８５を形成する。これらのトレンチ８１～８５は、別工程で形成してもよい。
ここで、活性領域のゲートトレンチ８１とショットキトレンチ８２とは、半導体基板１０のオフ角の方向である＜１１－２０＞方向と平行に形成されている。Next, a resist mask that opens a part of the region where the source region 40 of the active region is formed, a part of the region where the source region 40 is not formed, and the region where the body region 30 of the terminal region is formed is applied. The gate trench 81, the Schottki trench 82, the JBS trench 83, the first outer peripheral trench 84, and the second outer peripheral trench 85 are formed by a dry etching method. These trenches 81 to 85 may be formed in a separate step.
Here, the gate trench 81 and the Schottky trench 82 in the active region are formed in parallel with the <11-20> direction, which is the off-angle direction of the semiconductor substrate 10.

つづいて、各トレンチ８１～８５底部のドリフト層２０に、所定の位置をマスクしたレジストマスクを形成してｐ型不純物をイオン注入し、それぞれ第１保護領域３１、第２保護領域３２、第３保護領域３３、第４保護領域３４、および、第５保護領域３５を形成する。第１～第５保護領域のｐ型不純物濃度は、１×１０１７ｃｍ－３以上、１×１０１９ｃｍ－３以下である。
また、同様の方法により、第１外周トレンチ８４の底部の一部と第２外周トレンチ８５の底部の一部とに低抵抗ｎ型領域４１を形成する。低抵抗ｎ型領域４１のｎ型不純物濃度は、ソース領域４０のｎ型不純物濃度と同程度である。Subsequently, a resist mask masking a predetermined position is formed in the drift layer 20 at the bottom of each trench 81 to 85, and p-type impurities are ion-implanted, and the first protected region 31, the second protected region 32, and the third are respectively. A protected area 33, a fourth protected area 34, and a fifth protected area 35 are formed. The concentration of p-type impurities in the first to fifth protected regions is 1 × 10 17 cm -3 or more and 1 × 10 19 cm -3 or less.
Further, by the same method, a low resistance n-type region 41 is formed in a part of the bottom of the first outer peripheral trench 84 and a part of the bottom of the second outer peripheral trench 85. The concentration of n-type impurities in the low resistance n-type region 41 is about the same as the concentration of n-type impurities in the source region 40.

次に、熱処理装置によって、アルゴン（Ａｒ）ガス等の不活性ガス雰囲気中で、１３００から１９００℃の温度で、３０秒から１時間のアニールを行なう。このアニールにより、イオン注入されたＮ及びＡｌを電気的に活性化させる。 Next, the heat treatment apparatus performs annealing at a temperature of 1300 to 1900 ° C. for 30 seconds to 1 hour in an atmosphere of an inert gas such as argon (Ar) gas. This annealing electrically activates the ion-implanted N and Al.

つづいて、ショットキトレンチ８２とＪＢＳトレンチ８３とを絶縁膜で覆った状態でゲートトレンチ８１、第１外周トレンチ８４と第２外周トレンチ８５内に厚さが１０ｎｍ以上、３００ｎｍ以下の酸化珪素からなるゲート絶縁膜５０と導電性を有する多結晶珪素からなるゲート電極６０とを形成する。ゲート絶縁膜５０は熱酸化法で形成する。ゲート電極６０は減圧ＣＶＤ法により形成する。 Next, a gate made of silicon oxide having a thickness of 10 nm or more and 300 nm or less in the gate trench 81, the first outer peripheral trench 84 and the second outer peripheral trench 85 with the Schottki trench 82 and the JBS trench 83 covered with an insulating film. The insulating film 50 and the gate electrode 60 made of polycrystalline silicon having conductivity are formed. The gate insulating film 50 is formed by a thermal oxidation method. The gate electrode 60 is formed by a reduced pressure CVD method.

次に、厚さが５００ｎｍ以上、３０００ｎｍ以下の酸化珪素からなる層間絶縁膜５５を減圧ＣＶＤ法により形成する。
つづいて、ゲートトレンチ８１上および第１外周トレンチ８４と第２外周トレンチ８５上の一部を残して層間絶縁膜５５をドライエッチングする。
次に、Ｎｉなどの金属を堆積、アニールによるシリサイド化等の工程により、ソース領域４０上およびコンタクト領域９０上に図示しないオーミック電極を形成する。Next, an interlayer insulating film 55 made of silicon oxide having a thickness of 500 nm or more and 3000 nm or less is formed by a reduced pressure CVD method.
Subsequently, the interlayer insulating film 55 is dry-etched, leaving a part on the gate trench 81, the first outer peripheral trench 84, and the second outer peripheral trench 85.
Next, an ohmic electrode (not shown) is formed on the source region 40 and the contact region 90 by a process such as depositing a metal such as Ni and silicidizing by annealing.

つづいて、ショットキトレンチ８２とＪＢＳトレンチ８３とのショットキ界面になるドリフト層２０表面をフッ酸でライトエッチングした後に、ソース電極７０、ゲートパッド７１となるＡｌ／Ｔｉ等の積層金属からなる電極を形成する、最後に半導体基板１０の裏面側にドレイン電極７２を形成することによって、本実施の形態のＳＢＤ内蔵ＳｉＣトレンチＭＯＳＦＥＴを製造することができる。 Subsequently, after light-etching the surface of the drift layer 20 which is the Schottky interface between the Schottky trench 82 and the JBS trench 83 with hydrofluoric acid, an electrode made of laminated metal such as Al / Ti which becomes the source electrode 70 and the gate pad 71 is formed. Finally, by forming the drain electrode 72 on the back surface side of the semiconductor substrate 10, the SBD-embedded SiC trench MOSFET of the present embodiment can be manufactured.

本実施の形態の炭化珪素半導体装置であるＳＢＤ内蔵ＳｉＣトレンチＭＯＳＦＥＴによれば、終端領域に高密度のユニポーラ電流を流すことができ、その結果、終端領域のＳＢＤを形成する領域の面積を低減できる。したがって、より信頼性の高い炭化珪素半導体装置を得ることができる。また、本実施の形態のＳＢＤ内蔵ＳｉＣトレンチＭＯＳＦＥＴは、活性領域のゲートトレンチ、ショットキトレンチと、終端領域のＪＢＳトレンチとを同じエッチング工程で形成することができるので、製造コストを低減できる。 According to the SiC trench MOSFET with built-in SBD, which is the silicon carbide semiconductor device of the present embodiment, a high-density unipolar current can be passed through the terminal region, and as a result, the area of the region forming the SBD in the terminal region can be reduced. .. Therefore, a more reliable silicon carbide semiconductor device can be obtained. Further, in the SiC trench MOSFET with built-in SBD of the present embodiment, the gate trench and the Schottky trench in the active region and the JBS trench in the terminal region can be formed by the same etching process, so that the manufacturing cost can be reduced.

なお、ここまでの実施の形態では、ソース電極７０をそのままショットキトレンチ８２内とＪＢＳトレンチ８３内とに形成する例を説明したが、ショットキトレンチ８２内とＪＢＳトレンチ８３内とに別のショットキ金属７３を形成してもよい。図３に別のショットキ金属７３を使用して形成したＳＢＤ内蔵ＳｉＣトレンチＭＯＳＦＥＴの断面図を示す。 In the embodiments up to this point, an example in which the source electrode 70 is formed as it is in the Schottky trench 82 and the JBS trench 83 has been described, but different Schottky metals 73 are formed in the Shotkit trench 82 and the JBS trench 83. May be formed. FIG. 3 shows a cross-sectional view of a SiC trench MOSFET with a built-in SBD formed by using another Schottky metal 73.

また、ここまでの実施の形態では、ドリフト層２０の不純物濃度が一定であるように説明してきたが、ドリフト層２０の不純物濃度は一定でなくでもよい。例えば、図４にその断面図を示すように、各保護領域３１～３５より上側には、それらより下側のドリフト層２０よりｎ型不純物濃度を高くした高濃度ドリフト層２１を形成してもよい。
ゲートトレンチ８１近傍を各保護領域３１～３５より下側のドリフト層２０より不純物濃度が高い高濃度ドリフト層２１とすることにより、本実施の形態の炭化珪素半導体装置のオン抵抗をより低くすることができる。また、ＪＢＳトレンチ８３間を高濃度ドリフト層２１にすることにより、本実施の形態の炭化珪素半導体装置に、終端領域により大きなユニポーラ電流を流すことができる。Further, in the embodiments so far, the impurity concentration of the drift layer 20 has been described as being constant, but the impurity concentration of the drift layer 20 does not have to be constant. For example, as shown in the cross-sectional view in FIG. 4, a high-concentration drift layer 21 having a higher n-type impurity concentration than the drift layer 20 below them may be formed above each of the protected areas 31 to 35. good.
By forming the vicinity of the gate trench 81 as a high-concentration drift layer 21 having a higher impurity concentration than the drift layer 20 below each of the protected regions 31 to 35, the on-resistance of the silicon carbide semiconductor device of the present embodiment is further lowered. Can be done. Further, by forming the high-concentration drift layer 21 between the JBS trenches 83, a larger unipolar current can be passed through the termination region of the silicon carbide semiconductor device of the present embodiment.

さらに、活性領域のショットキトレンチ８２に接するドリフト層２０の不純物濃度より終端領域のＪＢＳトレンチ８３に接するドリフト層２０の不純物濃度を高くしてもよい。図５は、活性領域のショットキトレンチ８２に接する箇所に、各保護領域３１～３５より下側のドリフト層２０より不純物濃度が高い高濃度ドリフト層２１を形成し、終端領域のＪＢＳトレンチ８３に接する箇所に高濃度ドリフト層２１よりさらに不純物濃度が高い第２高濃度ドリフト層２２を形成した場合の断面模式図である。
このように、活性領域のショットキトレンチ８２に接するドリフト層２０の不純物濃度より終端領域のＪＢＳトレンチ８３に接するドリフト層２０の不純物濃度を高くすることにより、終端領域にさらに大きなユニポーラ電流を流すことができる。Further, the impurity concentration of the drift layer 20 in contact with the JBS trench 83 in the terminal region may be higher than the impurity concentration of the drift layer 20 in contact with the Schottki trench 82 in the active region. In FIG. 5, a high-concentration drift layer 21 having a higher impurity concentration than the drift layer 20 below each of the protected regions 31 to 35 is formed at a position in contact with the Schottki trench 82 in the active region, and is in contact with the JBS trench 83 in the terminal region. It is sectional drawing in the case where the 2nd high-concentration drift layer 22 which has a higher impurity concentration than the high-concentration drift layer 21 is formed in the place.
In this way, by increasing the impurity concentration of the drift layer 20 in contact with the JBS trench 83 in the terminal region to be higher than the impurity concentration of the drift layer 20 in contact with the Schottki trench 82 in the active region, a larger unipolar current can be passed through the terminal region. can.

また、ＪＢＳトレンチ８３底に、活性領域のゲートトレンチ８１、ショットキトレンチ８２の底の第１保護領域３１、第２保護領域３２のｐ型不純物濃度よりｐ型不純物濃度が小さい低濃度保護領域３７を形成してもよい。図６は、ＪＢＳトレンチ８３底に低濃度保護領域３７を形成した場合の断面模式図である。
ＪＢＳトレンチ８３底に低濃度保護領域３７を形成することにより、ＪＢＳトレンチ８３間のドリフト層２０に拡がる空乏層の幅を小さくでき、より大きなユニポーラ電流を流すことができる。Further, at the bottom of the JBS trench 83, a low concentration protected region 37 having a p-type impurity concentration smaller than that of the gate trench 81 in the active region, the first protected region 31 at the bottom of the Schottky trench 82, and the second protected region 32 is provided. It may be formed. FIG. 6 is a schematic cross-sectional view when a low concentration protection region 37 is formed on the bottom of the JBS trench 83.
By forming the low concentration protection region 37 at the bottom of the JBS trench 83, the width of the depletion layer extending to the drift layer 20 between the JBS trench 83 can be reduced, and a larger unipolar current can flow.

なお、本実施の形態の炭化珪素半導体装置中のＪＢＳは、複数の同じ深さのＪＢＳトレンチ８３とＪＢＳトレンチ８３間のドリフト層２０と、ドリフト層２０上層部に形成されたボディ領域３０と、ボディ領域３０上部に形成された高濃度ｐ型領域９１とを備えた構成により、従来のＳＢＤより高密度のユニポーラ電流を流すことができる。ＪＢＳは、ＪＢＳトレンチ８３底のドリフト層内に第５保護領域３５をさらに備えていてもよい。また、両端のＪＢＳトレンチ８３の両方の外側に、ＪＢＳトレンチ８３と同じ深さの第１外周トレンチ８４と第２外周トレンチ８５とを備えていてもよい。また、第１外周トレンチ８４と第２外周トレンチ８５との底に、ｐ型の第３保護領域３３と第４保護領域３４とを備えていてもよい。ＪＢＳトレンチ８３間のドリフト層２０を保護領域３３～３５より下側のドリフト層２０よりｎ型不純物濃度が高い高濃度ドリフト層２１としてもよい。
また、活性領域のゲートトレンチ８１またはショットキトレンチ８２とＪＢＳトレンチ８３との間に第１外周トレンチ８４を形成しなくてもよい。図７は、第１外周トレンチ８４を形成しない場合の断面模式図である。図７の構造においても、終端領域に大きなユニポーラ電流を流すことができる。
本実施の形態の炭化珪素半導体装置中では、活性領域のショットキトレンチ８１が、ソース領域４０と呼んだｎ型の領域を貫通して形成されている図を説明したが、ショットキトレンチ８１に接するソース領域４０は、なくてもよい。The JBS in the silicon carbide semiconductor device of the present embodiment includes a drift layer 20 between a plurality of JBS trenches 83 and JBS trenches 83 having the same depth, a body region 30 formed in an upper layer portion of the drift layer 20, and a body region 30 formed in the upper layer portion of the drift layer 20. Due to the configuration including the high-concentration p-type region 91 formed in the upper part of the body region 30, a unipolar current having a higher density than that of the conventional SBD can be passed. The JBS may further include a fifth protected area 35 in the drift layer at the bottom of the JBS trench 83. Further, the first outer peripheral trench 84 and the second outer peripheral trench 85 having the same depth as the JBS trench 83 may be provided on the outer sides of both of the JBS trenches 83 at both ends. Further, a p-shaped third protected area 33 and a fourth protected area 34 may be provided at the bottom of the first outer peripheral trench 84 and the second outer peripheral trench 85. The drift layer 20 between the JBS trenches 83 may be a high-concentration drift layer 21 having a higher n-type impurity concentration than the drift layer 20 below the protected areas 33 to 35.
Further, it is not necessary to form the first outer peripheral trench 84 between the gate trench 81 or the Schottky trench 82 in the active region and the JBS trench 83. FIG. 7 is a schematic cross-sectional view when the first outer peripheral trench 84 is not formed. Also in the structure of FIG. 7, a large unipolar current can be passed through the terminal region.
In the silicon carbide semiconductor device of the present embodiment, the figure in which the Schottky trench 81 in the active region is formed through the n-type region called the source region 40 has been described, but the source in contact with the Schottky trench 81 has been described. Region 40 may not be present.

実施の形態２．
実施の形態１では、ＳＢＤ内蔵ＳｉＣトレンチＭＯＳＦＥＴの活性領域のゲートトレンチ８１とショットキトレンチ８２との間隔が、終端領域のＪＢＳトレンチ８３間の間隔と同じ例について説明したが、本実施の形態では、終端領域のＪＢＳトレンチ８３間の間隔が活性領域のゲートトレンチ８１とショットキトレンチ８２との間隔より小さい。その他の点については、実施の形態１と同様であるので、詳しい説明は省略する。Embodiment 2.
In the first embodiment, an example in which the distance between the gate trench 81 and the Schottky trench 82 in the active region of the SiC trench MOSFET with built-in SBD is the same as the distance between the JBS trench 83 in the terminal region has been described. The distance between the JBS trenches 83 in the termination region is smaller than the distance between the gate trench 81 and the Schottki trench 82 in the active region. Since other points are the same as those in the first embodiment, detailed description thereof will be omitted.

図８は、実施の形態２にかかる炭化珪素半導体装置であるＳＢＤ内蔵ＳｉＣトレンチＭＯＳＦＥＴの活性領域から終端領域にかけての部分断面図である。図８において、活性領域のゲートトレンチ８１とショットキトレンチ８２との間隔Ｄ１は、終端領域のＪＢＳトレンチ８３間の間隔Ｄ２より大きく形成されている。
本実施の形態のＳＢＤ内蔵ＳｉＣトレンチＭＯＳＦＥＴは、実施の形態１のものと同じ工程で、マスクパターンを変えることによって形成できる。FIG. 8 is a partial cross-sectional view from the active region to the terminal region of the SiC trench MOSFET with built-in SBD, which is the silicon carbide semiconductor device according to the second embodiment. In FIG. 8, the distance D1 between the gate trench 81 and the Schottky trench 82 in the active region is formed to be larger than the distance D2 between the JBS trench 83 in the terminal region.
The SiC trench MOSFET with built-in SBD of the present embodiment can be formed by changing the mask pattern in the same process as that of the first embodiment.

本発明の炭化珪素半導体装置においては、ショットキ界面に接するドリフト層２０の不純物濃度が高いほど、ショットキ界面に流れるユニポーラ電流密度が高くなり、オフ時にショットキ界面にかかる電界強度が大きくなる。したがって、ショットキ界面に流れる電流密度を大きくしたいという要求と、ショットキ界面にかかる電界の強度を小さくしたいという要求は、トレードオフの関係にある。 In the silicon carbide semiconductor device of the present invention, the higher the impurity concentration of the drift layer 20 in contact with the Schottky interface, the higher the unipolar current density flowing through the Schottky interface, and the higher the electric field strength applied to the Schottky interface when off. Therefore, there is a trade-off between the demand for increasing the current density flowing at the Schottky interface and the demand for reducing the strength of the electric field applied to the Schottky interface.

活性領域では、ショットキ界面にかかる電界の強度を所定の値以下にするために、ドリフト層２０の不純物濃度が決められ、この不純物濃度によって、必要なゲートトレンチ８１とショットキトレンチ８２との間隔Ｄ１が決まる。また、この不純物濃度のドリフト層２０をオン電流が流れる。これに対して、終端領域では、ＪＢＳトレンチ８３間にオン電流が流れないので、ＪＢＳトレンチ８３間の間隔Ｄ２を小さくしてもよい。 In the active region, the impurity concentration of the drift layer 20 is determined in order to keep the strength of the electric field applied to the Schottky interface below a predetermined value, and the required distance D1 between the gate trench 81 and the Schottky trench 82 is determined by this impurity concentration. It will be decided. Further, an on-current flows through the drift layer 20 having this impurity concentration. On the other hand, in the terminal region, since the on-current does not flow between the JBS trenches 83, the interval D2 between the JBS trenches 83 may be reduced.

このような構成にすることにより、本実施の形態の炭化珪素半導体装置において、終端領域の幅を小さくすることができたり、同じ幅により多くのＪＢＳトレンチ８３を形成してより多くのユニポーラ電流を流したりすることができる。
さらに、実施の形態１の図５で説明した構成と同様に、ＪＢＳトレンチ８３間のドリフト層２０の不純物濃度を活性領域のゲートトレンチ８１とショットキトレンチ８２との間のドリフト層２０の不純物濃度より高くすることもできる。この構造を採用することにより、終端構造により高密度のユニポーラ電流を流すことができる。With such a configuration, in the silicon carbide semiconductor device of the present embodiment, the width of the terminal region can be reduced, or more JBS trenches 83 can be formed with the same width to generate more unipolar current. It can be shed.
Further, as in the configuration described with reference to FIG. 5 of the first embodiment, the impurity concentration of the drift layer 20 between the JBS trench 83 is adjusted from the impurity concentration of the drift layer 20 between the gate trench 81 and the Schottky trench 82 in the active region. It can also be raised. By adopting this structure, a high-density unipolar current can flow due to the terminal structure.

また、ＪＢＳトレンチ８３の幅を活性領域のゲートトレンチ８１、ショットキトレンチ８２より小さくしてもよい。図９は、ＪＢＳトレンチ８３の幅をゲートトレンチ８１、ショットキトレンチ８２の幅より小さく形成した場合の活性領域から終端領域にかけての部分断面図である。ＪＢＳトレンチ８３にはゲートトレンチ８１のように複数の材料を埋め込む必要が無い。そのため、終端領域のＪＢＳトレンチ８３の幅Ｄ４を活性領域のゲートトレンチ８１、ショットキトレンチ８２の幅Ｄ３より小さくすることができる。この構造を採用することによっても、終端構造により高密度のユニポーラ電流を流すことができる。 Further, the width of the JBS trench 83 may be smaller than that of the gate trench 81 and the shot kit trench 82 in the active region. FIG. 9 is a partial cross-sectional view from an active region to a terminal region when the width of the JBS trench 83 is formed smaller than the width of the gate trench 81 and the Schottky trench 82. Unlike the gate trench 81, it is not necessary to embed a plurality of materials in the JBS trench 83. Therefore, the width D4 of the JBS trench 83 in the terminal region can be made smaller than the width D3 of the gate trench 81 and the Schottky trench 82 in the active region. By adopting this structure as well, a high-density unipolar current can be passed due to the terminal structure.

さらに、ＪＢＳトレンチ８３を活性領域のゲートトレンチ８１、ショットキトレンチ８２より深く形成してもよい。図１０は、ＪＢＳトレンチ８３をゲートトレンチ８１、ショットキトレンチ８２より深く形成した場合の活性領域から終端領域にかけての部分断面図である。ＪＢＳトレンチ８３を深く形成した場合にも、ＪＢＳトレンチ８３のショットキ界面の面積を増大させることができ、終端構造により高密度のユニポーラ電流を流すことができる。したがって、より信頼性の高い炭化珪素半導体装置を得ることができる。 Further, the JBS trench 83 may be formed deeper than the gate trench 81 and the Schottky trench 82 in the active region. FIG. 10 is a partial cross-sectional view from the active region to the terminal region when the JBS trench 83 is formed deeper than the gate trench 81 and the Schottky trench 82. Even when the JBS trench 83 is formed deeply, the area of the Schottky interface of the JBS trench 83 can be increased, and a high-density unipolar current can flow due to the termination structure. Therefore, a more reliable silicon carbide semiconductor device can be obtained.

実施の形態３．
実施の形態１では、ＳＢＤ内蔵ＳｉＣトレンチＭＯＳＦＥＴの活性領域のゲートトレンチ８１とショットキトレンチ８２とが、終端領域のＪＢＳトレンチ８３と同じ深さで形成された構造について主に説明したが、本実施の形態では、終端領域のＪＢＳトレンチ８３が活性領域のゲートトレンチ８１、ショットキトレンチ８２より浅く形成されている。その他の点については、実施の形態１と同様であるので、詳しい説明は省略する。Embodiment 3.
In the first embodiment, the structure in which the gate trench 81 and the Schottky trench 82 in the active region of the SiC trench MOSFET with built-in SBD are formed at the same depth as the JBS trench 83 in the terminal region has been mainly described. In the form, the JBS trench 83 in the terminal region is formed shallower than the gate trench 81 and the Schottki trench 82 in the active region. Since other points are the same as those in the first embodiment, detailed description thereof will be omitted.

図１１は、実施の形態３にかかる炭化珪素半導体装置であるＳＢＤ内蔵ＳｉＣトレンチＭＯＳＦＥＴの活性領域から終端領域にかけての部分断面図である。図１１において、終端領域のＪＢＳトレンチ８３は、活性領域のゲートトレンチ８１とショットキトレンチ８２とより浅く形成されている。
ここで、本実施の形態のＳＢＤ内蔵ＳｉＣトレンチＭＯＳＦＥＴは、実施の形態１のものと同じ工程で形成し、ＪＢＳトレンチ８３のエッチングは、ゲートトレンチ８１とショットキトレンチ８２とのエッチングと別工程で行なってもよいし、同じ工程でＲＩＥ（Ｒｅａｃｔｉｖｅ Ｉｏｎ Ｅｔｃｈｉｎｇ）－ｌａｇを用いて行なってもよい。FIG. 11 is a partial cross-sectional view from the active region to the terminal region of the SiC trench MOSFET with built-in SBD, which is the silicon carbide semiconductor device according to the third embodiment. In FIG. 11, the JBS trench 83 in the terminal region is formed shallower than the gate trench 81 and the Schottky trench 82 in the active region.
Here, the SiC trench MOSFET with built-in SBD of the present embodiment is formed in the same process as that of the first embodiment, and the etching of the JBS trench 83 is performed in a separate process from the etching of the gate trench 81 and the Schottki trench 82. Alternatively, the same step may be performed using RIE (Reactive Ion Etching) -lag.

本発明の炭化珪素半導体装置においては、ゲートトレンチ８１とショットキトレンチ８２とよりＪＢＳトレンチ８３が浅く形成されているため、ＪＢＳトレンチ８３のショットキ界面の電界強度を相対的に小さくすることができる。そのため、ＪＢＳトレンチ８３底に形成する第３保護領域３３を設けなくすることができる。もちろん、第３保護領域３３は設けてもよい。
ＪＢＳトレンチ８３底に形成する第３保護領域３３を設けない構成にすることにより、ＪＢＳトレンチ８３底にもドリフト層２０との間にショットキ界面を形成することができ、ユニポーラ電流密度をより高くすることができる。In the silicon carbide semiconductor device of the present invention, since the JBS trench 83 is formed shallower than the gate trench 81 and the Schottky trench 82, the electric field strength at the Schottky interface of the JBS trench 83 can be relatively reduced. Therefore, it is possible to eliminate the provision of the third protected area 33 formed at the bottom of the JBS trench 83. Of course, the third protected area 33 may be provided.
By not providing the third protective region 33 formed on the bottom of the JBS trench 83, a Schottky interface can be formed on the bottom of the JBS trench 83 with the drift layer 20, and the unipolar current density is further increased. be able to.

また、ＪＢＳトレンチ８３を浅く形成することにより、ＪＢＳトレンチ８３のショットキ界面の電界強度を相対的に小さくすることができ、そのため、ＪＢＳトレンチ８３間のドリフト層２０の不純物濃度を高くすることができる。 図１２は、本実施の形態の別形態の炭化珪素半導体装置であるＳＢＤ内蔵ＳｉＣトレンチＭＯＳＦＥＴの活性領域から終端領域にかけての部分断面図である。図１２において、終端領域のＪＢＳトレンチ８３は、活性領域のゲートトレンチ８１とショットキトレンチ８２とより浅く形成されており、ＪＢＳトレンチ８３間には、第３保護領域３３より下部のドリフト層２０よりｎ型不純物濃度が高い第２高濃度ドリフト層２２が形成されている。
この構造を採用することにより、より高密度のユニポーラ電流を流すことができる。Further, by forming the JBS trench 83 shallowly, the electric field strength at the Schottky interface of the JBS trench 83 can be made relatively small, and therefore the impurity concentration of the drift layer 20 between the JBS trench 83 can be increased. .. FIG. 12 is a partial cross-sectional view from the active region to the terminal region of the SiC trench MOSFET with built-in SBD, which is another embodiment of the silicon carbide semiconductor device of the present embodiment. In FIG. 12, the JBS trench 83 in the terminal region is formed shallower than the gate trench 81 and the Schottky trench 82 in the active region, and between the JBS trench 83, n from the drift layer 20 below the third protected region 33. A second high-concentration drift layer 22 having a high type impurity concentration is formed.
By adopting this structure, a higher density unipolar current can be passed.

本実施の形態のＳＢＤ内蔵ＳｉＣトレンチＭＯＳＦＥＴによれば、終端領域の幅を小さくすることができたり、同じ幅により多くのＪＢＳトレンチ８３を形成してより多くのユニポーラ電流を流したりすることができる。したがって、より信頼性の高い炭化珪素半導体装置を得ることができる。 According to the SBD built-in SiC trench MOSFET of the present embodiment, the width of the termination region can be reduced, or more JBS trenches 83 can be formed with the same width to allow more unipolar current to flow. .. Therefore, a more reliable silicon carbide semiconductor device can be obtained.

実施の形態４．
実施の形態１では、活性領域においてゲートトレンチ８１とショットキトレンチ８２とが一方向に形成され、終端領域のＪＢＳトレンチ８３が活性領域を取り囲むように形成されていたが、本実施の形態の炭化珪素半導体装置では、終端領域のＪＢＳトレンチ８３が、活性領域のゲートトレンチ８１とショットキトレンチ８２と同じ方向に形成されている。その他の点については、実施の形態１と同様であるので、詳しい説明は省略する。Embodiment 4.
In the first embodiment, the gate trench 81 and the Schottky trench 82 are formed in one direction in the active region, and the JBS trench 83 in the terminal region is formed so as to surround the active region. However, the silicon carbide of the present embodiment is formed. In the semiconductor device, the JBS trench 83 in the terminal region is formed in the same direction as the gate trench 81 and the Schottky trench 82 in the active region. Since other points are the same as those in the first embodiment, detailed description thereof will be omitted.

図１３は、実施の形態４にかかる炭化珪素半導体装置であるＳＢＤ内蔵ＳｉＣトレンチＭＯＳＦＥＴのコーナー部近傍の平面図である。図１３において、終端領域のＪＢＳトレンチ８３が、活性領域のゲートトレンチ８１とショットキトレンチ８２と同じ向きに形成されている。
本実施の形態のＳＢＤ内蔵ＳｉＣトレンチＭＯＳＦＥＴは、実施の形態１のものと同じ工程で、マスクパターンを変えることによって形成できる。FIG. 13 is a plan view of the vicinity of the corner portion of the SiC trench MOSFET with built-in SBD, which is the silicon carbide semiconductor device according to the fourth embodiment. In FIG. 13, the JBS trench 83 in the terminal region is formed in the same direction as the gate trench 81 and the Schottky trench 82 in the active region.
The SiC trench MOSFET with built-in SBD of the present embodiment can be formed by changing the mask pattern in the same process as that of the first embodiment.

本実施の形態の炭化珪素半導体装置であるＳＢＤ内蔵ＳｉＣトレンチＭＯＳＦＥＴによれば、終端領域のショットキ界面が形成されるＪＢＳトレンチ８３のトレンチ側壁の結晶面が活性領域のショットキトレンチ８２と同じ結晶面になるので、活性領域のユニポーラ電流と終端領域のユニポーラ電流との大きさの差のばらつきを小さくできる。
特に、半導体基板１０の第１主面の面方位が＜１１－２０＞方向にオフ角を有する（０００１）面とした場合、活性領域のゲートトレンチ８１、ショットキトレンチ８２、および、終端領域のＪＢＳトレンチ８３を全て＜１１－２０＞方向に平行に形成することにより、ショットキトレンチ８２とＪＢＳトレンチ８３との両側のトレンチ側壁が基板のオフ方向の影響を受けなくなるため、ショットキトレンチ８２とＪＢＳトレンチ８３とのショットキ界面のバリア高さのばらつきを低減できる。According to the SiC trench MOSFET with built-in SBD, which is a silicon carbide semiconductor device of the present embodiment, the crystal plane of the trench side wall of the JBS trench 83 in which the Schottky interface of the terminal region is formed becomes the same crystal plane as the Schottky trench 82 of the active region. Therefore, the variation in the magnitude difference between the unipolar current in the active region and the unipolar current in the terminal region can be reduced.
In particular, when the surface orientation of the first main surface of the semiconductor substrate 10 is a (0001) surface having an off angle in the <11-20> direction, the gate trench 81 in the active region, the Schottki trench 82, and the JBS in the terminal region are used. By forming all the trenches 83 in parallel in the <11-20> direction, the trench side walls on both sides of the Schottki trench 82 and the JBS trench 83 are not affected by the off-direction of the substrate, so that the Schottki trench 82 and the JBS trench 83 are not affected. It is possible to reduce the variation in the barrier height at the interface between the two and the shot.

なお、実施の形態１～４においては、ｐ型不純物としてアルミニウム（Ａｌ）を用いたが、ｐ型不純物がホウ素（Ｂ）またはガリウム（Ｇａ）であってもよい。ｎ型不純物は、窒素（Ｎ）で無く燐（Ｐ）であってもよい。実施の形態１～４で説明したＭＯＳＦＥＴにおいては、ゲート絶縁膜は、必ずしもＳｉＯ２などの酸化膜である必要はなく、酸化膜以外の絶縁膜、または、酸化膜以外の絶縁膜と酸化膜とを組み合わせたものであってもよい。また、ゲート絶縁膜５０として炭化珪素を熱酸化した酸化珪素を用いたが、ＣＶＤ法による堆積膜の酸化珪素であってもよい。また、上記実施形態では、結晶構造、主面の面方位、オフ角および各注入条件等、具体的な例を用いて説明したが、これらの数値範囲に適用範囲が限られるものではない。In the first to fourth embodiments, aluminum (Al) is used as the p-type impurity, but the p-type impurity may be boron (B) or gallium (Ga). The n-type impurity may be phosphorus (P) instead of nitrogen (N). In the MOSFETs described in the first to fourth embodiments, the gate insulating film does not necessarily have to be an oxide film such as SiO 2 , and the insulating film other than the oxide film, or the insulating film other than the oxide film and the oxide film It may be a combination of. Further, although silicon oxide obtained by thermally oxidizing silicon carbide is used as the gate insulating film 50, it may be silicon oxide of the deposited film by the CVD method. Further, in the above embodiment, specific examples such as the crystal structure, the plane orientation of the main surface, the off angle, and each injection condition have been described, but the applicable range is not limited to these numerical ranges.

また、炭化珪素半導体装置は、絶縁ゲートバイポーラトランジスタ（ＩＧＢＴ）にＳＢＤを内蔵させたものであってもよい。さらに、スーパージャンクション構造を有するＭＯＳＦＥＴ、ＩＧＢＴにＳＢＤを内蔵させたものにも適用することができる。 Further, the silicon carbide semiconductor device may have an SBD built in an insulated gate bipolar transistor (IGBT). Further, it can be applied to a MOSFET having a super junction structure, an IGBT having an SBD built-in.

実施の形態５．
本実施の形態は、上述した実施の形態１～４にかかる炭化珪素半導体装置の製造方法を電力変換装置の製造に適用したものである。本開示は特定の電力変換装置の製造方法に限定されるものではないが、以下、実施の形態４として、三相のインバータの製造方法に本開示を適用した場合について説明する。Embodiment 5.
In this embodiment, the manufacturing method of the silicon carbide semiconductor device according to the above-described first to fourth embodiments is applied to the manufacturing of the power conversion device. Although the present disclosure is not limited to the method for manufacturing a specific power conversion device, the case where the present disclosure is applied to the method for manufacturing a three-phase inverter will be described below as the fourth embodiment.

図１４は、本実施の形態にかかる電力変換装置を適用した電力変換システムの構成を示すブロック図である。 FIG. 14 is a block diagram showing a configuration of a power conversion system to which the power conversion device according to the present embodiment is applied.

図１４に示す電力変換システムは、電源１００、電力変換装置２００、負荷３００から構成される。電源１００は、直流電源であり、電力変換装置２００に直流電力を供給する。電源１００は種々のもので構成することが可能であり、例えば、直流系統、太陽電池、蓄電池で構成することができるし、交流系統に接続された整流回路やＡＣ／ＤＣコンバータで構成することとしてもよい。また、電源１００を、直流系統から出力される直流電力を所定の電力に変換するＤＣ／ＤＣコンバータによって構成することとしてもよい。 The power conversion system shown in FIG. 14 includes a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply, and supplies DC power to the power conversion device 200. The power supply 100 can be configured with various things, for example, it can be configured with a DC system, a solar cell, a storage battery, or it can be configured with a rectifier circuit or an AC / DC converter connected to an AC system. May be good. Further, the power supply 100 may be configured by a DC / DC converter that converts the DC power output from the DC system into a predetermined power.

電力変換装置２００は、電源１００と負荷３００の間に接続された三相のインバータであり、電源１００から供給された直流電力を交流電力に変換し、負荷３００に交流電力を供給する。電力変換装置２００は、図３０に示すように、直流電力を交流電力に変換して出力する主変換回路２０１と、主変換回路２０１の各スイッチング素子を駆動する駆動信号を出力する駆動回路２０２と、駆動回路２０２を制御する制御信号を駆動回路２０２に出力する制御回路２０３とを備えている。
駆動回路２０２は、ノーマリオフ型の各スイッチング素子を、ゲート電極の電圧とソース電極の電圧とを同電位にすることによってオフ制御している。The power conversion device 200 is a three-phase inverter connected between the power supply 100 and the load 300, converts the DC power supplied from the power supply 100 into AC power, and supplies AC power to the load 300. As shown in FIG. 30, the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, and a drive circuit 202 that outputs a drive signal that drives each switching element of the main conversion circuit 201. A control circuit 203 that outputs a control signal for controlling the drive circuit 202 to the drive circuit 202 is provided.
The drive circuit 202 off-controls each normally-off type switching element by making the voltage of the gate electrode and the voltage of the source electrode the same potential.

負荷３００は、電力変換装置２００から供給された交流電力によって駆動される三相の電動機である。なお、負荷３００は特定の用途に限られるものではなく、各種電気機器に搭載された電動機であり、例えば、ハイブリッド自動車や電気自動車、鉄道車両、エレベーター、もしくは、空調機器向けの電動機として用いられる。 The load 300 is a three-phase electric motor driven by AC power supplied from the power converter 200. The load 300 is not limited to a specific application, and is an electric motor mounted on various electric devices. For example, the load 300 is used as an electric motor for a hybrid vehicle, an electric vehicle, a railroad vehicle, an elevator, or an air conditioner.

以下、電力変換装置２００の詳細を説明する。主変換回路２０１は、スイッチング素子と還流ダイオードを備えており（図示せず。内蔵されたＳＢＤでもよい。）、スイッチング素子がスイッチングすることによって、電源１００から供給される直流電力を交流電力に変換し、負荷３００に供給する。主変換回路２０１の具体的な回路構成は種々のものがあるが、本実施の形態にかかる主変換回路２０１は２レベルの三相フルブリッジ回路であり、６つのスイッチング素子とそれぞれのスイッチング素子に逆並列された６つの還流ダイオードから構成することができる。主変換回路２０１の各スイッチング素子には、上述した実施の形態１～３のいずれかにかかる炭化珪素半導体装置の製造方法で製造された炭化珪素半導体装置を適用する。６つのスイッチング素子は２つのスイッチング素子ごとに直列接続され上下アームを構成し、各上下アームはフルブリッジ回路の各相（Ｕ相、Ｖ相、Ｗ相）を構成する。そして、各上下アームの出力端子、すなわち主変換回路２０１の３つの出力端子は、負荷３００に接続される。 Hereinafter, the details of the power conversion device 200 will be described. The main conversion circuit 201 includes a switching element and a freewheeling diode (not shown. A built-in SBD may be used), and the DC power supplied from the power supply 100 is converted into AC power by switching the switching element. Then, it is supplied to the load 300. There are various specific circuit configurations of the main conversion circuit 201, but the main conversion circuit 201 according to the present embodiment is a two-level three-phase full bridge circuit, and has six switching elements and each switching element. It can consist of six anti-parallel freewheeling diodes. A silicon carbide semiconductor device manufactured by the method for manufacturing a silicon carbide semiconductor device according to any one of the above-described embodiments 1 to 3 is applied to each switching element of the main conversion circuit 201. The six switching elements are connected in series for each of the two switching elements to form an upper and lower arm, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full bridge circuit. Then, the output terminals of each upper and lower arm, that is, the three output terminals of the main conversion circuit 201 are connected to the load 300.

駆動回路２０２は、主変換回路２０１のスイッチング素子を駆動する駆動信号を生成し、主変換回路２０１のスイッチング素子の制御電極に供給する。具体的には、後述する制御回路２０３からの制御信号に従い、スイッチング素子をオン状態にする駆動信号とスイッチング素子をオフ状態にする駆動信号とを各スイッチング素子の制御電極に出力する。スイッチング素子をオン状態に維持する場合、駆動信号はスイッチング素子の閾値電圧以上の電圧信号（オン信号）であり、スイッチング素子をオフ状態に維持する場合、駆動信号はスイッチング素子の閾値電圧以下の電圧信号（オフ信号）となる。 The drive circuit 202 generates a drive signal for driving the switching element of the main conversion circuit 201 and supplies the drive signal to the control electrode of the switching element of the main conversion circuit 201. Specifically, according to the control signal from the control circuit 203 described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element. When the switching element is kept on, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when the switching element is kept off, the drive signal is a voltage equal to or lower than the threshold voltage of the switching element. It becomes a signal (off signal).

制御回路２０３は、負荷３００に所望の電力が供給されるよう主変換回路２０１のスイッチング素子を制御する。具体的には、負荷３００に供給すべき電力に基づいて主変換回路２０１の各スイッチング素子がオン状態となるべき時間（オン時間）を算出する。例えば、出力すべき電圧に応じてスイッチング素子のオン時間を変調するＰＷＭ制御によって主変換回路２０１を制御することができる。そして、各時点においてオン状態となるべきスイッチング素子にはオン信号を、オフ状態となるべきスイッチング素子にはオフ信号が出力されるよう、駆動回路２０２に制御指令（制御信号）を出力する。駆動回路２０２は、この制御信号に従い、各スイッチング素子の制御電極にオン信号又はオフ信号を駆動信号として出力する。
本実施の形態に係る電力変換装置では、主変換回路２０１のスイッチング素子として実施の形態１～４にかかる炭化珪素半導体装置の製造方法で製造された炭化珪素半導体装置を適用するため、低損失、かつ、高速スイッチングの信頼性を高めた電力変換装置を実現することができる。The control circuit 203 controls the switching element of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, the time (on time) in which each switching element of the main conversion circuit 201 should be in the on state is calculated based on the electric power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the on-time of the switching element according to the voltage to be output. Then, a control command (control signal) is output to the drive circuit 202 so that an on signal is output to the switching element that should be turned on at each time point and an off signal is output to the switching element that should be turned off. The drive circuit 202 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to this control signal.
In the power conversion device according to the present embodiment, the silicon carbide semiconductor device manufactured by the method for manufacturing the silicon carbide semiconductor device according to the first to fourth embodiments is applied as the switching element of the main conversion circuit 201, so that the loss is low. Moreover, it is possible to realize a power conversion device with improved reliability of high-speed switching.

本実施の形態では、２レベルの三相インバータに本発明を適用する例を説明したが、本発明は、これに限られるものではなく、種々の電力変換装置に適用することができる。本実施の形態では、２レベルの電力変換装置としたが３レベルやマルチレベルの電力変換装置であっても構わないし、単相負荷に電力を供給する場合には単相のインバータに本発明を適用しても構わない。また、直流負荷等に電力を供給する場合にはＤＣ／ＤＣコンバータやＡＣ／ＤＣコンバータに本発明を適用することも可能である。 In the present embodiment, an example of applying the present invention to a two-level three-phase inverter has been described, but the present invention is not limited to this, and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is used, but a three-level or multi-level power conversion device may be used, and when power is supplied to a single-phase load, the present invention is applied to a single-phase inverter. You may apply it. Further, when supplying electric power to a DC load or the like, the present invention can be applied to a DC / DC converter or an AC / DC converter.

また、本開示を適用した電力変換装置は、上述した負荷が電動機の場合に限定されるものではなく、例えば、放電加工機やレーザー加工機、又は誘導加熱調理器や非接触器給電システムの電源装置として用いることもでき、さらには太陽光発電システムや蓄電システム等のパワーコンディショナーとして用いることも可能である。 Further, the power conversion device to which the present disclosure is applied is not limited to the case where the above-mentioned load is an electric motor, and is, for example, a power source for a discharge machine, a laser machine, an induction heating cooker, or a non-contact power supply system. It can be used as a device, and can also be used as a power conditioner for a photovoltaic power generation system, a power storage system, or the like.

１０ 半導体基板、２０ ドリフト層、２１ 高濃度ドリフト層、２２ 第２高濃度ドリフト層、３０ ボディ領域、３１ 第１保護領域、３２ 第２保護領域、３３ 第３保護領域、３４ 第４保護領域、３５ 第５保護領域、４０ ソース領域、４１ 低抵抗ｎ型領域、５０ ゲート絶縁膜、５５ 層間絶縁膜、６０ ゲート電極、７０ ソース電極、７１ ゲートパッド、７２ ドレイン電極、８１ ゲートトレンチ、８２ ショットキトレンチ、８３ ＪＢＳトレンチ、８４ 第１外周トレンチ、８５ 第２外周トレンチ、９０ コンタクト領域、９１ 高濃度ｐ型領域、１００ 電源、２００、電力変換装置、２０１ 主変換回路、２０２ 駆動回路、２０３ 制御回路、３００ 負荷。 10 semiconductor substrate, 20 drift layer, 21 high concentration drift layer, 22 second high concentration drift layer, 30 body region, 31 first protected region, 32 second protected region, 33 third protected region, 34 fourth protected region, 35 5th protection region, 40 source region, 41 low resistance n-type region, 50 gate insulating film, 55 interlayer insulating film, 60 gate electrode, 70 source electrode, 71 gate pad, 72 drain electrode, 81 gate trench, 82 shotkit trench , 83 JBS trench, 84 1st outer peripheral trench, 85 2nd outer peripheral trench, 90 contact area, 91 high concentration p-type area, 100 power supply, 200, power converter, 201 main conversion circuit, 202 drive circuit, 203 control circuit, 300 load.

Claims (13)

活性領域と前記活性領域を囲んで形成された終端領域とを有し、
第１導電型のドリフト層と、
前記ドリフト層上に設けられた第２導電型のボディ領域と、
前記活性領域内の前記ボディ領域上に設けられた第１導電型のソース領域と、
前記ボディ領域および前記ソース領域を前記ドリフト層の厚さ方向に貫通するゲートトレンチと、
前記ゲートトレンチ内にゲート絶縁膜を介して前記ボディ領域と対向して形成されたゲート電極と、
前記活性領域内の前記ボディ領域を前記ドリフト層の厚さ方向に貫通し、前記ゲートトレンチに平面視で平行に形成されたショットキトレンチと、
前記終端領域内の前記ボディ領域を前記ドリフト層の厚さ方向に貫通して互いに平面視で平行に形成された複数のＪＢＳトレンチと、
前記ソース領域と接続され、前記ショットキトレンチ内および前記ＪＢＳトレンチ内に前記ドリフト層とショットキ接続されて形成されるソース電極と
を備えた炭化珪素半導体装置。 It has an active region and a terminal region formed around the active region.
The first conductive type drift layer and
The second conductive type body region provided on the drift layer and
A first conductive type source region provided on the body region in the active region,
A gate trench that penetrates the body region and the source region in the thickness direction of the drift layer.
A gate electrode formed in the gate trench facing the body region via a gate insulating film, and a gate electrode.
A Schottky trench that penetrates the body region in the active region in the thickness direction of the drift layer and is formed parallel to the gate trench in a plan view.
A plurality of JBS trenches formed parallel to each other in a plan view through the body region in the terminal region in the thickness direction of the drift layer,
A silicon carbide semiconductor device including a source electrode connected to the source region and formed by being connected to the drift layer in the Schottki trench and in the JBS trench. 前記ゲートトレンチの底の前記ドリフト層内に形成された第２導電型の第１保護領域と、
前記ショットキトレンチの底の前記ドリフト層内に形成された第２導電型の第２保護領域と、
前記ＪＢＳトレンチの底の前記ドリフト層内に形成された第２導電型の第３保護領域とを備えた
請求項１に記載の炭化珪素半導体装置。 A second conductive type first protective region formed in the drift layer at the bottom of the gate trench,
A second protective region of the second conductive type formed in the drift layer at the bottom of the shot kit trench, and
The silicon carbide semiconductor device according to claim 1, further comprising a second conductive type third protected region formed in the drift layer at the bottom of the JBS trench. 前記ゲートトレンチと前記ショットキトレンチと前記ＪＢＳトレンチとは、同じ深さで形成されている
請求項１または請求項２に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to claim 1 or 2, wherein the gate trench, the shot kit trench, and the JBS trench are formed at the same depth. 前記複数のＪＢＳトレンチの間隔は、前記ゲートトレンチに隣接する前記ショットキトレンチと前記ゲートトレンチとの間隔と同じである
請求項１から請求項３のいずれか１項に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein the distance between the plurality of JBS trenches is the same as the distance between the Schottky trench adjacent to the gate trench and the gate trench. 前記複数のＪＢＳトレンチの間隔は、前記ゲートトレンチに隣接する前記ショットキトレンチと前記ゲートトレンチとの間隔より小さい
請求項１から請求項３のいずれか１項に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein the distance between the plurality of JBS trenches is smaller than the distance between the Schottky trench adjacent to the gate trench and the gate trench. 前記ＪＢＳトレンチの幅は、前記ショットキトレンチの幅より小さい
請求項１から請求項３のいずれか１項に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein the width of the JBS trench is smaller than the width of the Schottky trench. 前記ＪＢＳトレンチの深さは、前記ゲートトレンチおよび前記ショットキトレンチの深さより小さい
請求項１に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to claim 1, wherein the depth of the JBS trench is smaller than the depth of the gate trench and the Schottky trench. 前記ＪＢＳトレンチの深さは、前記ゲートトレンチおよび前記ショットキトレンチの深さより大きい
請求項１に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to claim 1, wherein the depth of the JBS trench is larger than the depth of the gate trench and the Schottky trench. 複数の前記ＪＢＳトレンチの間の前記ドリフト層の不純物濃度は、前記ショットキトレンチに隣接する前記ドリフト層の不純物濃度より大きい
請求項１から請求項８のいずれか１項に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to any one of claims 1 to 8, wherein the impurity concentration of the drift layer between the plurality of JBS trenches is larger than the impurity concentration of the drift layer adjacent to the Schottky trench. 前記ドリフト層の主面は、（０００１）面から＜１１－２０＞方向に傾斜し、
前記ゲートトレンチと前記ショットキトレンチは、＜１１－２０＞方向に平行に形成された
請求項１から請求項９のいずれか１項に記載の炭化珪素半導体装置。 The main surface of the drift layer is inclined in the <11-20> direction from the (0001) surface.
The silicon carbide semiconductor device according to any one of claims 1 to 9, wherein the gate trench and the shot kit trench are formed in parallel in the <11-20> direction. 前記ＪＢＳトレンチは、前記ゲートトレンチと前記ショットキトレンチと平行に形成された
請求項１０に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to claim 10, wherein the JBS trench is formed in parallel with the gate trench and the Schottky trench. 前記第３保護領域の第２導電型不純物濃度は、前記第１保護領域の第２導電型不純物濃度より小さい
請求項２に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to claim 2 , wherein the concentration of the second conductive impurity in the third protected region is smaller than the concentration of the second conductive impurity in the first protected region. 請求項１～１２のいずれか１項に記載の炭化珪素半導体装置を有し、入力される電力を変換して出力する主変換回路と、
前記炭化珪素半導体装置の前記ゲート電極の電圧を前記ソース電極の電圧と同じにすることによってオフ動作させ、前記炭化珪素半導体装置を駆動する駆動信号を前記炭化珪素半導体装置に出力する駆動回路と、
前記駆動回路を制御する制御信号を前記駆動回路に出力する制御回路と、
を備えた電力変換装置。 A main conversion circuit having the silicon carbide semiconductor device according to any one of claims 1 to 12 and converting and outputting input power.
A drive circuit that turns off the voltage of the gate electrode of the silicon carbide semiconductor device by making it the same as the voltage of the source electrode and outputs a drive signal for driving the silicon carbide semiconductor device to the silicon carbide semiconductor device.
A control circuit that outputs a control signal that controls the drive circuit to the drive circuit, and a control circuit that outputs the control signal to the drive circuit.
Power conversion device equipped with.
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