WO2022097221A1

WO2022097221A1 - Semiconductor device, power conversion device, and method for manufacturing semiconductor device

Info

Publication number: WO2022097221A1
Application number: PCT/JP2020/041300
Authority: WO
Inventors: 梨菜田中; 英之八田; 基吉田; 裕福井
Original assignee: 三菱電機株式会社
Priority date: 2020-11-05
Filing date: 2020-11-05
Publication date: 2022-05-12
Also published as: JPWO2022097221A1; JP7330396B2

Abstract

To provide a semiconductor device with a reduced reverse leak current in a MOSFET including an SBD.　A semiconductor device (101) comprises a drift layer (2) of a first conductivity type, a body region (3) of a second conductivity type provided on the drift layer, a source region (4) of the first conductivity type provided on the body region, a gate insulating film (7) provided in a gate trench (6) passing through the body region and the source region, a gate electrode (8) provided in the gate trench, a Schottky electrode (12) provided in a Schottky trench (11) passing through the body region, and a first bottom-protecting region (15) of the second conductivity type provided to be in contact with the bottom of the gate trench, a part of the sides thereof, and corners between the bottom and the sides thereof. The Schottky trench (11) has a shallower depth than the gate trench (6) in the thickness direction of the drift layer.

Description

Manufacturing method of semiconductor device, power conversion device and semiconductor device

The present disclosure relates to a semiconductor device, a power conversion device to which the semiconductor device is applied, and a method for manufacturing the semiconductor device.

As a power switching element, an insulated gate type semiconductor device such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor / metal oxide semiconductor field effect transistor) is widely used. As an insulated gate type semiconductor device, a trench gate type semiconductor device is being developed.

As such a trench gate type semiconductor device, there is a MOSFET having a gate trench in which a gate electrode is formed and a Schottky trench in which a Schottky electrode is formed, and a built-in SBD (Schottky barrier diode) (for example). See Patent Document 1).

2019-216224 Gazette

However, in such a conventional semiconductor device, there is a problem that a high electric field tends to occur near the bottom of the Schottky trench and a reverse leakage current tends to increase.

The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to obtain a semiconductor device having a reduced reverse leakage current.

The semiconductor device according to the present disclosure includes a first conductive type drift layer, a second conductive type body region provided on the drift layer, a first conductive type source region provided on the body region, and a body. A gate insulating film provided in the gate trench penetrating the region and the source region in the thickness direction of the drift layer, and a gate insulating film provided in the gate trench so as to face the source region via the gate insulating film. Gate electrodes provided, shot key electrodes provided in a shot key trench penetrating the body region in the thickness direction of the drift layer, bottom surface, part of the side surface, and corners between the bottom surface and the side surface of the gate trench. A second conductive type first bottom protection region provided in contact with the portion is provided, and the shot key trench is characterized in that the depth in the thickness direction of the drift layer is formed shallower than that of the gate trench. do.

The semiconductor device according to the present disclosure has an effect that the reverse leakage current can be reduced because the Schottky trench is formed shallower than the gate trench in the MOSFET having the SBD built-in.

It is a plan schematic diagram which shows the whole structure of the semiconductor device of Embodiment 1. FIG. It is a plane schematic diagram which shows the layout of the cell area of the semiconductor device of Embodiment 1. FIG. It is sectional drawing which shows the cell region of the semiconductor device of Embodiment 1. FIG. It is a 1st figure which shows each process of the manufacturing method of the semiconductor device of Embodiment 1. FIG. It is a 2nd figure which shows each process of the manufacturing method of the semiconductor device of Embodiment 1. FIG. It is a 3rd figure which shows each process of the manufacturing method of the semiconductor device of Embodiment 1. FIG. It is a 4th figure which shows each process of the manufacturing method of the semiconductor device of Embodiment 1. FIG. It is a figure which shows each process of another example of the manufacturing method of the semiconductor device of Embodiment 1. FIG. It is a 5th figure which shows each process of the manufacturing method of the semiconductor device of Embodiment 1. FIG. It is a 6th figure which shows each process of the manufacturing method of the semiconductor device of Embodiment 1. FIG. It is a 7th figure which shows each process of the manufacturing method of the semiconductor device of Embodiment 1. FIG. It is a figure 8 which shows each process of the manufacturing method of the semiconductor device of Embodiment 1. FIG. It is sectional drawing which shows the cell region of the semiconductor device of Embodiment 2. It is a 1st figure which shows each process of the manufacturing method of the semiconductor device of Embodiment 2. FIG. It is a figure which shows each process of another example of the manufacturing method of the semiconductor device of Embodiment 2. It is a 2nd figure which shows each process of the manufacturing method of the semiconductor device of Embodiment 2. FIG. It is a 3rd figure which shows each process of the manufacturing method of the semiconductor device of Embodiment 2. FIG. It is a 4th figure which shows each process of the manufacturing method of the semiconductor device of Embodiment 2. FIG. It is a 5th figure which shows each process of the manufacturing method of the semiconductor device of Embodiment 2. FIG. It is a plane schematic diagram which shows the layout of the cell area of the semiconductor device of Embodiment 3. FIG. It is sectional drawing which shows the cell region of the semiconductor device of Embodiment 3. FIG. It is a figure which shows each process of the manufacturing method of the semiconductor device of Embodiment 3. It is a figure which shows each process of the modification of the manufacturing method of the semiconductor device of Embodiment 3. It is a figure which shows each process of the modification of the manufacturing method of the semiconductor device of Embodiment 3. It is a figure which shows each process of the manufacturing method of another example of the semiconductor device of Embodiment 3. It is a figure which shows each process of the manufacturing method of the modification of the semiconductor device of Embodiment 3. It is a figure which shows each process of the manufacturing method of the modification of the semiconductor device of Embodiment 3. It is sectional drawing which shows the cell region of the semiconductor device of Embodiment 4. It is a figure which shows each process of the manufacturing method of the semiconductor device of Embodiment 4. It is a block diagram which shows the structure of the power conversion system to which the power conversion apparatus of Embodiment 5 is applied.

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be noted that the drawings are schematically shown, and the interrelationship between the sizes and positions of the images shown in different drawings is not always accurately described and may be changed as appropriate. Further, in the following drawings, the same or corresponding parts are designated by the same reference numerals, and the description thereof will not be repeated.

Further, in each drawing, a broken line may be shown to indicate a specific area or a boundary between the areas, but these are described for convenience of explanation or for easy understanding of the drawing. However, the content of each embodiment is not limited in any way.

In the following description, terms such as "top", "bottom", "side", "bottom", "front", and "back" may be used to mean a specific position and direction. The term is used for convenience in order to facilitate understanding of the contents of the embodiment, and has nothing to do with the direction in which it is actually implemented.

In the present disclosure, when the mutual relationship of the components is expressed by using terms such as "-upper" and "-lower", it does not prevent the existence of inclusions between the components. For example, when the description "B provided on A" is described, it includes those in which another component C is provided between A and B and those in which the other component C is not provided. Further, in the present disclosure, when expressing using terms such as "-upper" and "-lower", the concept of upper and lower with the laminated structure in mind is also included. For example, when the description is described as "B provided on A covering the groove", B includes the meaning of being present in the direction opposite to the groove surface seen from A, and within the range of the meaning, the lateral direction or Including diagonal direction.

In the following description, regarding the conductive type of impurities, the case where the first conductive type is n-type and the second conductive type is p-type will be described, but the first conductive type is p-type and the second conductive type is n-type. It doesn't matter. Further, the "impurity concentration" indicates the maximum value of impurities in each region. Further, the description of "n ^- type" indicates that the impurity concentration is lower than that of the description of "n-type", and the description of "n ⁺ type" is described as "n-type". It shows that the impurity concentration is higher than that of the above. Similarly, the description of "p ^- type" indicates that the impurity concentration is lower than that of the description of "p-type", and the description of "p ⁺ type" is described as "p-type". It shows that the impurity concentration is higher than that of the one.

In the following description, the current flowing from the drain to the source of the MOSFET is referred to as a forward current, the direction thereof is referred to as a forward current, the current flowing from the source to the drain is referred to as a reflux current, and the direction thereof is referred to as a reverse direction. .. The term "MOS" has long been used for metal / oxide / semiconductor junction structures, and is an acronym for Metal-Oxide-Semiconductor. However, particularly in the field effect transistor having a MOS structure (hereinafter, simply referred to as “MOS transistor”), the material of the gate insulating film and the gate electrode has been improved from the viewpoint of integration and improvement of the manufacturing process in recent years.

For example, in MOS transistors, polycrystalline silicon has been adopted as the material for gate electrodes, mainly from the viewpoint of forming source and drain in a self-aligned manner. Further, from the viewpoint of improving the electrical characteristics, a material having a high dielectric constant is adopted as the material of the gate insulating film, but this material is not necessarily limited to the oxide.

Therefore, the term "MOS" is not necessarily limited to the metal / oxide / semiconductor laminated structure, and the present specification does not presuppose such limitation. That is, in view of common general technical knowledge, "MOS" has a meaning not only as an abbreviation derived from the etymology but also broadly including a laminated structure of a conductor / insulator / semiconductor.

Embodiment 1.
The semiconductor device of the first embodiment will be described with reference to FIGS. 1 to 12.

First, the configuration of the semiconductor device according to the first embodiment will be described with reference to FIGS. 1 to 3. FIG. 1 is a schematic plan view schematically showing a top surface configuration of the entire semiconductor device 101 of the present embodiment. FIG. 2 is an enlarged view of the region X shown in FIG. 1, and is a schematic plan view schematically showing the layout of MOSFET cells in the semiconductor device 101. FIG. 3 is a cross-sectional view taken along the line AA'of FIG. 2, which is a schematic cross-sectional view showing a partial cross section of the active region 40 in the semiconductor device 101 of the present embodiment. Note that FIG. 2 corresponds to a top view of a lateral cross section at a certain depth between the bottom surface of the shot key trench 11 and the body region 3 shown in FIG.

As shown in FIG. 1, the semiconductor device 101 has a square outer shape, and in the central portion thereof, an active region 40 in which a plurality of minimum unit structures (MOSFET cells) of MOSFETs called “unit cells” are arranged. Is provided, and the outside of the active region 40 is surrounded by the terminal region 41. A plurality of gate trenches 6 and a plurality of shot key trenches 11 are provided in parallel in the active region 40 at intervals from each other. The plurality of gate trenches 6 are connected to the gate wiring provided in the active region 40, and the gate wiring is connected to the gate pad, but the illustration and description thereof will be omitted.

As shown in FIG. 2, the gate trench 6 and the shot key trench 11 are formed in a striped shape in a plan view. Further, in a plan view, the extending direction of the gate trench 6 and the extending direction of the shot key trench 11 are formed to be the same direction. In the SBD region 20, the shotkey interface 22 is formed on the side surface of the shotkey trench 11 exposed to the drift layer 2.

1 and 2 show a structure in which two MOS regions 19 sandwich one SBD region 20, but the arrangement of each region is not limited to this. For example, the structure may be such that two MOS regions 19 sandwich two SBD regions 20, two gate trenches 6 in the MOS region 19, two shotkey trenches 11 in the SBD region 20, and a gate trench 6 in the MOS region 19. However, the structure may be such that the arrangement of one shot key trench 11 in the SBD region 20 is repeated, and the structure is not limited to these examples.

In the semiconductor device 101, a plurality of MOSFET cell structures as shown in FIG. 3 are repeatedly and periodically provided in the active region 40. In the following, the characteristic configuration shown in the region X shown in FIG. 1 will be described as each embodiment and its modification, and FIG. 1 is common to each embodiment and its modification.

As shown in FIG. 3, the semiconductor device 101 includes a substrate 1, a drift layer 2, a body region 3, a source region 4, a body contact region 5, a gate trench 6, a gate insulating film 7, a gate electrode 8, and an interlayer insulating film 9. It includes a shot key trench 11, a shot key electrode 12, a source electrode 13, a drain electrode 14, a first bottom protection region 15, and a contact region 17.

The MOS region 19 has a gate trench 6, a gate insulating film 7, a gate electrode 8, and an interlayer insulating film 9. The SBD region 20 has a shot key trench 11 and a shot key electrode 12. Further, the semiconductor layer 21 includes a body region 3, a source region 4, a body contact region 5, and a first bottom protection region 15, which are an impurity region formed above or inside the drift layer 2 and the drift layer 2.

The substrate 1 is an n ⁺ type SiC (silicon carbide) semiconductor substrate, and has, for example, a 4H polytype. The substrate 1 may be a (0001) surface having an off angle θ inclined in the <11-20> axial direction. In this case, the off angle θ may be, for example, 10 ° or less.

An n ^- type drift layer 2 having an n-type impurity concentration lower than that of the substrate 1 is provided on the substrate 1. SiC (silicon carbide) is used as the semiconductor material for the drift layer 2. The drift layer 2 occupies most of the semiconductor layer 21 and constitutes a main part of the semiconductor layer 21. When the main surface of the substrate 1 is a (0001) surface having an off angle θ inclined in the <11-20> axial direction, the main surface of the drift layer 2 is also a (0001) surface having the same off angle θ. That is, the drift layer 2 has a main surface provided with an off angle larger than 0 ° in the <11-20> axial direction.

A p-shaped body region 3 is provided above the drift layer 2. An n ⁺ type source region 4 is selectively provided above the drift layer 2 (body region 3). The source region 4 is a semiconductor region in which the concentration of n-type impurities is higher than that of the drift layer 2. Further, on the upper part of the drift layer 2 (body region 3), a p ⁺ type body contact region 5 is selectively provided adjacent to the source region 4. The body contact region 5 is a semiconductor region in which the concentration of p-type impurities is higher than that of the body region 3.

The MOS region 19 is provided with a gate trench 6 that penetrates the body region 3 in the thickness direction of the drift layer 2. The gate trench 6 is formed so as to penetrate the source region 4 and the body region 3 from the surface of the semiconductor layer 21 and reach the drift layer 2. The bottom of the gate trench 6 typically has a surface, but may have a tapered shape with a tapered tip. Further, the side surfaces of the gate trench 6 are typically substantially parallel, but may have a tapered shape that is inclined with respect to each other.

A gate insulating film 7 is provided on the bottom and side surfaces of the gate trench 6. Further, in the gate trench 6, a gate electrode 8 is provided so as to fill the inside of the gate trench 6 via the gate insulating film 7. The gate electrode 8 is provided so as to face the drift layer 2, the body region 3, and the source region 4 via the gate insulating film 7. An interlayer insulating film 9 is provided on the gate trench 6 so as to cover the gate electrode 8.

The SBD region 20 is provided with a shot key trench 11 that penetrates the body region 3 in the thickness direction of the drift layer 2. The shot key trench 11 is formed so as to penetrate the source region 4 and the body region 3 from the surface of the semiconductor layer 21 and reach the drift layer 2. The shot key trench 11 is formed so that the depth of the drift layer 2 in the thickness direction is shallower than that of the gate trench 6. More specifically, the bottom surface of the shot key trench 11 is formed above the top surface of the first bottom protection region 15. The shot key trench 11 is formed so that the trench width in the direction orthogonal to the thickness direction of the drift layer 2 is the same as that of the gate trench 6. The bottom of the shot key trench 11 typically has a surface, but may have a tapered shape with a tapered tip. Further, the side surfaces of the shot key trench 11 are typically substantially parallel, but may have a tapered shape that is inclined with respect to each other.

The shot key trench 11 is not limited to the one formed so that the trench width in the direction orthogonal to the thickness direction of the drift layer 2 is the same as that of the gate trench 6. The gate trench 6 and the shot key trench 11 may have different trench widths in the direction orthogonal to the thickness direction of the drift layer 2. These trenches may have either a large or narrow trench width, and differ depending on the specifications of each semiconductor device.

A shot key electrode 12 is provided in the shot key trench 11. The shotkey electrode 12 is formed of a metal such as Ti (titanium) or Mo (molybdenum). The shot key electrode 12 is in contact with the drift layer 2, the body region 3, and the source region 4 at the bottom or side surface of the shot key trench 11, and is electrically connected to these.

The Schottky electrode 12 forms a Schottky junction with the drift layer 2 on the side surface of the Schottky trench 11. That is, as shown in FIGS. 2 and 3, the shot key electrode 12 forms a shot key interface 22 (not shown in FIG. 3) with the drift layer 2 on the side surface and the bottom surface of the shot key trench 11. As a result, a parasitic Schottky barrier diode (hereinafter, simply referred to as SBD) between the Schottky electrode 12 and the drift layer 2 is formed on the side surface and the bottom surface of the Schottky trench 11.

Further, a contact region 17 is formed on the source region 4 and the body contact region 5. The contact region 17 is a silicide of a metal such as Ni (nickel) or Ti (titanium) and the semiconductor layer 21, and is in contact with the source region 4 and the body contact region 5 to form ohmic contact with them.

A source electrode 13 is provided on the interlayer insulating film 9, the contact region 17, and the shotkey electrode 12 so as to cover them. The source electrode 13 is an electrode made of a metal whose main component is Al (aluminum). In the MOS region 19, the source electrode 13 functions as a main electrode on the front surface side together with the contact region 17. The source electrode 13 is electrically connected to the source region 4 and the body contact region 5 via the contact region 17. Further, in the SBD region 20, the source electrode 13 is connected to the Schottky electrode 12, and together with the Schottky electrode 12, constitutes the anode electrode of the SBD.

A drain electrode 14 containing a metal such as Ni (nickel) is provided on the surface of the substrate 1 opposite to the surface on which the source electrode 13 is provided. The source electrode 13 is provided on the front surface (first main surface) side of the substrate 1 (semiconductor layer 21), and the drain electrode 14 faces the front surface of the substrate 1 (semiconductor layer 21). It is provided on the back surface (second main surface) side.

Below the gate trench 6 (gate insulating film 7), a p ⁺ -shaped first bottom protection region 15 is provided so as to cover the bottom of the gate trench 6 along the extending direction of the gate trench 6. The first bottom protection area 15 is in contact with the bottom surface of the gate trench 6, a part of the side surface, and the corner portion between the bottom surface and the side surface, and is provided so as to cover the entire bottom portion of the gate trench 6 including the corner portion. Has been done. As a result, the gate trench 6 is provided so as to be embedded in the first bottom protection region 15. The "bottom surface" and "side surface" do not necessarily have to be formed in a flat shape. Further, the "corner portion" may have a rounded shape.

Next, the impurity concentration of each semiconductor region in the semiconductor device 101 of the first embodiment will be described. The concentration of n-type impurities in the drift layer 2 is 1.0 × 10 ¹⁴ to 1.0 × 10 ¹⁷ cm ^-3 , and is set based on the withstand voltage of the semiconductor device and the like. The concentration of p-type impurities in the body region 3 is 1.0 × 10 ¹⁴ to 1.0 × 10 ¹⁸ cm ^-3 . The concentration of n-type impurities in the source region 4 is 1.0 × 10 ¹⁸ to 1.0 × 10 ²¹ cm ^-3 . The concentration of p-type impurities in the body contact region 5 is 1.0 × 10 ¹⁸ to 1.0 × 10 ²¹ cm ^-3 , and in order to reduce the contact resistance with the source electrode 13, it is more p-type than the body region 3. Set the impurity concentration to be high. The concentration of p-type impurities in the first bottom protection region 15 is preferably 1.0 × 10 ¹⁴ or more and 1.0 × 10 ²⁰ cm ^-3 or less, and the concentration profile does not have to be uniform.

Next, the operation of the semiconductor device 101 according to the first embodiment will be briefly described. In the MOS region 19, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 8, the conductive type is inverted in the body region 3, that is, an n-type channel is formed along the side surface of the gate trench 6. Then, the same conductive type (n type in the first embodiment) current path is formed between the source electrode 13 and the drain electrode 14, so that a current flows. The state in which the voltage equal to or higher than the threshold voltage is applied to the gate electrode 8 in this way is the on state of the semiconductor device 101.

On the other hand, when a voltage lower than the threshold voltage is applied to the gate electrode 8, a channel is not formed in the body region 3, so that a current path as in the case of the on state is not formed. Therefore, even if a voltage is applied between the drain electrode 14 and the source electrode 13, almost no current flows from the drain electrode 14 to the source electrode 13. The state in which the voltage of the gate electrode 8 is less than the threshold voltage is the off state of the semiconductor device 101.

Then, the semiconductor device 101 operates by switching between the on state and the off state by controlling the voltage applied to the gate electrode 8. As described above, in the MOS region 19, the semiconductor device 101 has a MOSFET structure composed of a gate electrode 8, a gate insulating film 7, a drift layer 2, a body region 3, a source region 4, a source electrode 13, a drain electrode 14, and the like. Has.

On the other hand, when a forward voltage is applied to the SBD in the SBD region 20 in the off state of the semiconductor device 101, a unipolar current flows between the Schottky electrode 12 and the drain electrode 14. When further biased, a bipolar current begins to flow in the parasitic pn diode formed in the body region 3 and the first bottom protection region 15. The current value obtained by the time the parasitic pn diode starts bipolar operation is the maximum unipolar current of the device.

In addition, in FIGS. 1 and 2, it is desirable that the gate trench 6 and the shot key trench 11 are formed so that their extension directions are parallel to the <11-20> axial direction. This is because the side surfaces of the gate trench 6 and the Schottky trench 11 serve as current paths, so that when the semiconductor layer 21 has an off angle θ inclined in the <11-20> axial direction, both side surfaces facing each other of the trenches are off. This is to avoid a difference in characteristics on both side surfaces due to different crystal planes due to the influence of the angle.

When the semiconductor device 101 is off, the first bottom protected region 15 promotes the depletion of the n-type region of the drift layer 2 by the depletion layer extending from the first bottom protected region 15, and also to the bottom of the gate trench 6. By relaxing the electric field concentration, the electric field applied to the gate insulating film 7 is reduced, and the gate insulating film 7 is prevented from being destroyed.

By electrically connecting the first bottom protection region 15 to the body region 3 of the MOS region 19 and fixing the potential of the first bottom protection region 15, the electric field concentration at the bottom of the gate trench 6 can be further relaxed. Can be planned. For example, a p-shaped connection region (not shown) in contact with the first bottom protection region 15 and the body region 3 may be formed on the side surface of the gate trench 6. The potential of the first bottom protection region 15 is grounded by being electrically connected to the source electrode 13 via the connection region, the body region 3, and the source region 4. This electrical connection is provided, for example, through adjacent cells. The connection region may have, for example, a p-type impurity concentration of 1.0 × 10 ¹⁴ or more and 1.0 × 10 ²⁰ cm ^-3 or less.

Further, when the gate trench 6 is formed in a line shape, the gate trench 6 is formed by extending a low-concentration p-type connection region (p ^--- region) on the side surface of the end portion in the longitudinal direction of the gate trench 6. The first bottom protection region 15 at the bottom of the gate trench 6 and the body region 3 above it can be electrically connected through the p ^- region.

The gate trench 6 may be formed in a grid pattern, and in this case, the first bottom protection region 15 at the bottom of the gate trench 6 and the gate electrode 8 pass through the gate electrode 8 at the intersection of the gate electrodes 8. By providing a contact for connecting the source electrode 13 on the upper layer, the first bottom protection region 15 can be electrically connected to the body region 3 through the contact and the source electrode 13.

By connecting the first bottom protection region 15 to the source potential, the elongation of the depletion layer is promoted from the first bottom protection region 15 toward the drift layer 2 when the semiconductor device 101 is turned off, and the electric field strength of the bottom surface of the gate trench 6 is increased. Can be reduced. Further, during the on / off operation of the semiconductor device 101, a current path for charging / discharging the pn junction formed by the first bottom protection region 15 and the drift layer 2 is secured, and the electric charge is drawn out to the source electrode 13 so that the semiconductor device 101 is depleted. The response of the layer becomes faster, and the switching loss can be reduced.

Next, the method of manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS. 4 to 12. 4 to 12 are diagrams showing each step of the manufacturing method of the semiconductor device 101 of the present embodiment.

As shown in FIG. 4, first, a substrate 1 on which an n ^- type semiconductor layer 21 made of silicon carbide is formed is prepared. More specifically, the n ^- type semiconductor layer 21 may be formed by the epitaxial growth method on the substrate 1 which is an n ⁺ type silicon carbide substrate. Further, the n-type impurity concentration of the semiconductor layer 21 is formed so as to correspond to the n-type impurity concentration of the drift layer 2 described above.

Then, as shown in FIG. 5, a p-type body region 3 is formed by ion implantation in the upper layer portion in the semiconductor layer 21 (drift layer 2), and the upper layer of the body region 3 (semiconductor layer 21 or drift layer 2) is formed. An n ⁺ type source region 4 and a p ⁺ type body contact region 5 are selectively formed in the portion by ion implantation. In ion implantation, ions such as N (nitrogen) and P (phosphorus) are implanted as donors when forming an n-type region, and Al (aluminum) and B are used as acceptors when forming a p-type region. Inject ions such as (boron). The impurity concentration in each region is formed so as to have the above-mentioned value.

The order of forming the body region 3, the source region 4, and the body contact region 5 may be different, and all or some of the regions may be formed by epitaxial growth instead of ion implantation. When the body region 3, the source region 4, and the body contact region 5 are formed by epitaxial growth, each region is laminated on the drift layer 2.

Based on the above, "forming the body region 3 on the upper part of the drift layer 2" means including those formed by any of the above-mentioned ion implantation or epitaxial growth manufacturing methods, and "the body region 3 is the drift layer." "Provided on 2" means that the region occupied by the body region 3 is the drift layer 2 in the finally completed semiconductor device 101 regardless of whether it is formed by the above-mentioned ion implantation or epitaxial growth manufacturing method. It shall mean that it is located on the area occupied by. Similarly, “forming the source region 4 on the upper part of the body region 3” means including those formed by any of the above-mentioned ion implantation or epitaxial growth manufacturing methods, and “the source region 4 is the body”. "Provided on the region 3" means that the region occupied by the source region 4 is located on the region occupied by the body region 3 in the semiconductor device 101. The same applies to other areas.

Next, as shown in FIG. 6, the first mask 51 is used to reach the drift layer 2 from the surface of the semiconductor layer 21 through the source region 4 and the body region 3 by reactive ion etching (RIE). The gate trench 6 and the shot key trench 11 are formed. At this time, the width of the gate trench 6 and the width of the shot key trench 11 may be different from each other. Further, a plurality of masks may be used to form the gate trench 6 in the MOS region 19 and the shot key trench 11 in the SBD region 20 by using individual etching steps.

Then, as shown in FIG. 7, additional etching is performed only on the gate trench 6 using the first mask 51 and the second mask 52. As a result, after forming the gate trench 6 deeper than the shot key trench 11, ion implantation is performed in an oblique direction (for example, an inclination angle of 10 to 50 °) slightly inclined from the vertical direction with respect to the surface of the semiconductor layer 21. conduct. The second mask 52 is a mask provided so as to cover the shot key trench 11 and open only the gate trench 6. In this way, by implanting p-type ions into the bottom of the gate trench 6, a first bottom protection region 15 having a width larger than that of the gate trench 6 is formed. By doing so, the bottom surface of the shot key trench 11 can be formed so as to be located above the upper surface of the first bottom protection region 15.

Alternatively, as shown in FIG. 8, in the first bottom protection region 15 ^, an n− type first drift layer 25 is formed on the substrate 1 by epitaxial growth, and then ions are implanted into the upper layer of the first drift layer 25 in advance. It may be selectively formed or embedded by epitaxial growth. In this case, after the formation of the first bottom protection region 15 ^, the n− type second drift layer 26 is formed on the first drift layer 25 and the first bottom protection region 15 by epitaxial growth, and then each semiconductor region or trench is formed. Will be formed. For example, the body region 3 is formed in the upper layer of the second drift layer 26. The combination of the first drift layer 25 and the second drift layer 26 corresponds to the above drift layer 2.

As shown in FIG. 7, the first bottom protection region 15 formed in this way projects toward the drift layer 2 side (direction orthogonal to the thickness direction of the drift layer 2) with respect to the side surface of the gate trench 6. ..

Next, as shown in FIG. 9, the gate trench 6 is further etched by using the first mask 51 and the second mask 52. By doing so, the bottom surface of the gate trench 6 can be embedded in the first bottom protection area 15. That is, the corner portion of the gate trench 6 is covered with the first bottom protection region 15.

Next, as shown in FIG. 10, the first mask 51 and the second mask 52 are removed by selective etching or the like using a resist mask or the like, and the gate insulating film 7 is entirely formed on the semiconductor layer 21. By forming the gate insulating film 7, the gate insulating film 7 is formed on the bottom and side surfaces in the gate trench 6 and on the bottom and side surfaces in the shot key trench 11. After that, for example, a conductive polycrystalline silicon film is formed on the gate insulating film 7 by a reduced pressure CVD method, and by etching back this, the polycrystalline silicon is formed only inside the gate trench 6 and the shot key trench 11. The film is left and the structure of the cross-sectional view shown in FIG. 10 is obtained. Since the polycrystalline silicon film in the gate trench 6 becomes the gate electrode 8, it is shown as the gate electrode 8 in FIG. 10. It was

After that, as shown in FIG. 11, the polycrystalline silicon film in the shot key trench 11 is removed by a wet etching method using an alkaline etching solution such as an alkaline developer. Further, an interlayer insulating film 9 is formed so as to cover the gate electrode 8. Then, a third mask 53 is formed on the interlayer insulating film 9 that covers the gate trench 6. Using the third mask 53, the gate insulating film 7 is also patterned together with the interlayer insulating film 9 to expose the surface of the semiconductor layer 21. As a result, the contact hole can be opened.

Next, as shown in FIG. 12, the contact region 17 is formed on the surface of the semiconductor layer 21 exposed by the opening of the contact hole (the surface of the source region 4 and the body contact region 5) using a metal such as Ni (nickel). Form. The contact region 17 is a silicide of the metal and the semiconductor layer 21.

After that, the insulating film formed on the bottom and side surfaces in the shot key trench 11 is removed to expose the surface of the semiconductor layer 21. Then, by depositing a metal such as Ti (titanium) or Mo (molybdenum) on the exposed semiconductor layer 21, the shotkey electrode 12 is formed in the shotkey trench 11 in the SBD region 20. In the SBD region 20 and the MOS region 19, the source electrode 13 is formed by depositing a metal such as Al (aluminum) on the shotkey electrode 12, the contact region 17, and the interlayer insulating film 9 so as to cover them. do. Then, the drain electrode 14 is formed so as to cover the back surface of the substrate 1. By the above steps, the semiconductor device 101 shown in FIGS. 1 to 3 can be manufactured.

The gate insulating film 7 and the interlayer insulating film 9 are typically both formed as an oxide film. Therefore, in FIG. 10 and the like, the portion of the gate insulating film 7 that overhangs the gate trench 6 (protrudes onto the surface of the semiconductor layer 21) is described as the same layer as the interlayer insulating film 9. ing.

The features and effects of the semiconductor device 101 according to the first embodiment configured as described above will be described.

The semiconductor device 101 is a switching element for electric power in which an SBD is built in antiparallel in a MOSFET, which is a unipolar type semiconductor device, as a unipolar type freewheeling diode. Therefore, the cost can be reduced as compared with the case where individual diodes are externally used.

Further, since the semiconductor device 101 is a MOSFET in which silicon carbide (SiC) is used as a base material for the substrate 1 and the semiconductor layer 21, the bipolar operation due to the parasitic pn diode can be suppressed by incorporating the SBD. This is because, in a semiconductor device using silicon carbide, the reliability of the device may be impaired due to the expansion of crystal defects caused by the carrier recombination energy due to the operation of the parasitic pn diode.

Further, the semiconductor device 101 is a so-called trench gate type MOSFET having a gate electrode 8 in the gate trench 6 formed in the element. Therefore, as compared with the planar MOSFET having the gate electrode 8 on the surface of the element, the channel width density can be improved and the on-resistance can be reduced by the amount that the channel can be formed on the side wall portion of the gate trench 6.

Further, the semiconductor device 101 is a trench gate type MOSFET, and has a structure in which a Schottky electrode 12 is embedded in the Schottky trench 11 in the SBD region 20 and a Schottky interface 22 is formed on the side surface of the Schottky trench 11. be. Therefore, since both the gate electrode 8 and the shot key electrode 12 are formed inside the gate trench 6 and the shot key trench 11, respectively, the distance between the trenches, that is, the cell pitch of each cell can be kept small, and a high current density can be obtained. can.

The semiconductor device 101 is a trench gate type MOSFET with a built-in SBD having the above characteristics. In the trench type device structure, there is a problem that electric field concentration occurs at the bottom of the trench when a high voltage is applied in the off state of the semiconductor device. In particular, in a trench-type silicon carbide semiconductor device, SiC has a high dielectric breakdown strength. Therefore, in the MOS region, the gate insulating film is broken due to the electric field concentration at the bottom of the trench before the avalanche break in the drift layer. In the SBD region, there is a problem that the reverse leakage current tends to increase due to the high electric field at the Schottky interface on the side surface and the bottom surface of the trench.

On the other hand, the semiconductor device 101 according to the first embodiment forms a first bottom protection region 15 below the gate trench 6 in the MOS region 19. Since a depletion layer is formed around the first bottom protection region 15, the electric field strength of the portion is reduced. Therefore, in the MOS region 19, it is possible to suppress the occurrence of dielectric breakdown of the gate insulating film 7 due to the electric field concentration at the bottom of the gate trench 6. In particular, in the semiconductor device 101, in the MOS region 19, the bottom portion of the gate trench 6 is embedded in the first bottom protection region 15, and the corner portion between the bottom surface and the side surface of the gate trench 6 is the first bottom protection region 15. It is configured to be covered with. Therefore, the semiconductor device 101 has the effect of suppressing the formation of a high electric field at the corners of the gate trench 6 and suppressing the dielectric breakdown of the gate insulating film 7.

On the other hand, as described above, in the SBD region 20, the deeper the Schottky trench 11, the higher the electric field tends to be in the vicinity of the bottom, and the Schottky interface is formed in the vicinity of the bottom, so that the reverse leakage current tends to increase. .. Therefore, it is conceivable that the gate trench 6 and the shot key trench 11 are provided shallowly, but the first bottom protection region 15 is formed in the lower part of the gate trench 6, and both the gate trench 6 and the shot key trench 11 are formed shallowly. Then, the JFET resistance between the body region 3 and the first bottom protection region 15 increases.

Therefore, since the semiconductor device 101 of the present embodiment does not form a bottom protection region under the Schottky trench 11 formed in the SBD region 20, the bottom surface of the Schottky trench 11 also serves as a Schottky interface. Therefore, the Schottky trench 11 can be formed shallowly only at a position where the Schottky interface area for obtaining the required Schottky current density is secured. That is, by forming the shot key trench 11 so that the depth of the drift layer 2 in the thickness direction is shallower than that of the gate trench 6, it is possible to suppress an electric field near the bottom of the shot key trench 11 from becoming a high electric field. By forming the bottom surface of the key trench 11 above the upper surface of the first bottom protection region 15, the electric field near the bottom can be further reduced. Therefore, the semiconductor device 101 has an effect of suppressing an increase in the reverse leakage current in the SBD region 20 and suppressing an increase in the JFET resistance in the MOS region 19.

As described above, in the semiconductor device 101, in the MOS region 19, the bottom of the gate trench 6 is embedded in the first bottom protection region 15 to further suppress the high electric field, so that the gate trench 6 is made deeper. Can be formed. On the other hand, in the SBD region 20, by forming the shot key trench 11 shallowly, it is possible to prevent the bottom portion from becoming a high electric field. With such a configuration, in the semiconductor device 101, it is possible to suppress the dielectric breakdown of the gate insulating film 7 in the MOS region 19 and the increase in the reverse leakage current in the SBD region 20, and the reliability is improved. It has an effect that can be achieved.

Further, in the semiconductor device 101 of the first embodiment, the drift layer 2 has a main surface having an off angle larger than 0 ° in the <11-20> axial direction, and the gate trench 6 and the shot key trench 11 are provided. , <11-20> Since it is provided parallel to the axial direction, it is possible to reduce the variation in characteristics due to the side surface of the trench and to obtain the effect of stabilizing the operation of the semiconductor device 101.

In the first embodiment described above, the gate trench 6 and the shot key trench 11 are formed in a striped shape in a plan view, but the present invention is not limited to this. For example, either the gate trench 6 or the shot key trench 11 may have a grid shape.

Further, in the present embodiment, the case where the bottom surface of the shot key trench 11 is formed on the upper side of the upper surface of the first bottom protection region 15 is described, but the present invention is not limited to this, and the first bottom portion is not limited to this. The upper surface of the protected area 15 and the bottom surface of the shot key trench 11 may be provided at the same position. In such a configuration, in the above-mentioned manufacturing method, it is not necessary to additionally etch the gate trench 6 in the process shown in FIG. 7, so that the manufacturing method becomes simpler.

Embodiment 2.
The semiconductor device of the second embodiment and the manufacturing method of the semiconductor device will be described with reference to FIGS. 13 to 19. FIG. 13 is a schematic cross-sectional view showing a partial cross section of the active region 40 in the semiconductor device 201 of the present embodiment, corresponding to the cross-sectional view taken along the line AA'in FIG. 14 to 19 are diagrams showing each process of the manufacturing method of the semiconductor device 201 of the present embodiment.

As shown in FIG. 13, the semiconductor device 201 of the present embodiment is different from the semiconductor device 101 of the first embodiment in that a second bottom protection region 16 is formed on the bottom surface of the shot key trench 11. Since the other configurations of the semiconductor device 201 of the present embodiment are the same as those of the semiconductor device 101 of the first embodiment, the differences from the semiconductor device 101 will be mainly described below.

In the semiconductor device 201, a p ⁺ -shaped second bottom protection region 16 is provided below the shot key trench 11 (shot key electrode 12) along the stretching direction of the shot key trench 11. The second bottom protection area 16 is in contact with the bottom of the shot key trench 11 and is provided so as to cover the entire bottom of the shot key trench 11. The second bottom protected area 16 is configured so that the width of the second bottom protected area 16 is larger than the width of the shot key trench 11 by covering the entire bottom so as to protrude in the width direction of the shot key trench 11. There is.

The second bottom protection area 16 is not limited to the one provided in contact with the bottom of the shot key trench 11, and may be provided in the drift layer 2 below the bottom of the shot key trench 11.

Further, the second bottom protection area 16 is not limited to covering the entire bottom of the shot key trench 11, and may be provided so as to cover at least a part of the bottom of the shot key trench 11. For example, the second bottom protection region 16 is spaced along the stretching direction of the shot key trench 11 (the direction is defined for each longitudinal direction in a plan view in the case of a stripe shape, and for each shot key trench 11 in the case of a grid shape). It may be arranged periodically with an opening, or it may be provided so as to cover about half of the bottom of the shot key trench 11 in a cross section orthogonal to the stretching direction.

Next, the manufacturing method of the semiconductor device 201 will be described with reference to FIGS. 14 to 19, focusing on the differences from the manufacturing method of the semiconductor device 101 of the first embodiment.

First, the gate trench 6 and the shot key trench 11 are formed as shown in FIG. 6 in the same manner as in the manufacturing method of the semiconductor device 101 described in the first embodiment. Then, as shown in FIG. 14, using the first mask 51, ion implantation is performed in an oblique direction slightly inclined from the vertical direction with respect to the surface of the semiconductor layer 21. In this way, the p-type ion implantation is performed at the bottom of the gate trench 6 to form the p ⁺ type first bottom protection region 15, and the p-type ion implantation is performed at the bottom of the shot key trench 11. A p ⁺ -shaped second bottom protection region 16 is formed.

Alternatively, as shown in FIG. 15, in the first bottom protection region 15 and the second bottom protection region 16 ^, an n− type first drift layer 25 is formed on the substrate 1 by epitaxial growth, and then the first drift layer 25 is formed in advance. It may be selectively formed by ion implantation in the upper layer portion or embedded by epitaxial growth. In this case, after the formation of the first bottom protected area 15 and the second bottom protected area 16, the n ^- type first is placed on the first drift layer 25, the first bottom protected area 15, and the second bottom protected area 16. After the 2 drift layer 26 is formed by epitaxial growth, each semiconductor region or trench is formed. For example, the body region 3 is formed in the upper layer of the second drift layer 26. The combination of the first drift layer 25 and the second drift layer 26 corresponds to the above drift layer 2.

As shown in FIG. 14, the first bottom protection region 15 and the second bottom protection region 16 formed in this way are on the drift layer 2 side (of the drift layer 2) with respect to the side surfaces of the gate trench 6 and the shot key trench 11. Overhangs in the direction orthogonal to the thickness direction).

Next, as shown in FIG. 16, the gate trench 6 is additionally etched by using the first mask 51 and the second mask 52. By doing so, the bottom surface of the gate trench 6 can be embedded in the first bottom protection area 15. That is, the corner portion of the gate trench 6 is covered with the first bottom protection region 15.

Next, as shown in FIG. 17, by forming the gate insulating film 7 entirely on the semiconductor layer 21, gate insulation is provided on the bottom and side surfaces in the gate trench 6 and on the bottom and side surfaces in the shot key trench 11. The film 7 is formed. Then, in the same manner as in the manufacturing method of the semiconductor device 101 described in the first embodiment, for example, polysilicon (Poly-Si) is filled so as to embed the gate trench 6 through the gate insulating film 7, and the gate electrode is used. 8 is formed.

After that, as shown in FIG. 18, the polycrystalline silicon film in the Schottky trench 11 is removed in the same manner as in the manufacturing method of the semiconductor device 101 described in the first embodiment. Further, an interlayer insulating film 9 is formed so as to cover the gate electrode 8. Then, a third mask 53 is formed on the interlayer insulating film 9 that covers the gate trench 6. Using the third mask 53, the gate insulating film 7 is also patterned together with the interlayer insulating film 9 to expose the surface of the semiconductor layer 21 and open a contact hole.

Next, as shown in FIG. 19, the contact region 17 is formed on the surface of the semiconductor layer 21 exposed by the opening of the contact hole (the surface of the source region 4 and the body contact region 5) using a metal such as Ni (nickel). Form.

After that, the shotkey electrode 12 is formed in the shotkey trench 11 in the same manner as in the manufacturing method of the semiconductor device 101 described in the first embodiment, and is placed on the shotkey electrode 12, the contact region 17, and the interlayer insulating film 9. The source electrode 13 is formed in the above. Then, the drain electrode 14 is formed so as to cover the back surface of the substrate 1. By the above steps, the semiconductor device 201 shown in FIG. 13 can be manufactured.

Even the semiconductor device 201 configured in this way has the same effect as the semiconductor device 101 of the first embodiment. Further, in the semiconductor device 201 of the present embodiment, in the SBD region 20, by forming the second bottom protection region 16 below the Schottky trench 11, the shot is made by the depletion layer spreading around the second bottom protection region 16. It has the effect of reducing the electric field at the key interface 22 and further suppressing the increase in the reverse leakage current.

Embodiment 3.
The semiconductor device of the third embodiment and the manufacturing method of the semiconductor device will be described with reference to FIGS. 20 to 28. FIG. 20 is an enlarged view of the region X shown in FIG. 1, and is a schematic plan view schematically showing the layout of MOSFET cells in the semiconductor device 301. FIG. 21 is a cross-sectional view taken along the line BB'of FIG. 20, which is a schematic cross-sectional view showing a partial cross section of the active region 40 in the semiconductor device 301 of the present embodiment. Note that FIG. 20 corresponds to a top view of a lateral cross section at a certain depth between the body region 3 and the first bottom protection region 15 shown in FIG. 21. 22 to 28 are views showing the process of the manufacturing method of the semiconductor device 301 according to the present embodiment.

In the semiconductor device 301 of the present embodiment, as shown in FIGS. 20 and 21, the first low resistance region 31 and the second low resistance region 32 are formed in the MOS region 19 and the SBD region 20, respectively. It is different from the semiconductor device 201 of the second embodiment. Since the other configurations of the semiconductor device 301 of the present embodiment are the same as those of the semiconductor device 201 of the second embodiment, the differences from the semiconductor device 201 will be mainly described below.

The first low resistance region 31 is an n ⁺ type semiconductor region provided along the gate trench 6 in the stretching direction of the gate trench 6 and having an n-type impurity concentration higher than that of the drift layer 2. The first low resistance region 31 is provided on the side of the gate trench 6 as shown in FIGS. 20 and 21. More specifically, as shown in FIG. 20, the first low resistance region 31 is formed so as to be in contact with the entire region of the side surface of the gate trench 6 and cover the side surface of the gate trench 6 in the extending direction of the gate trench 6. .. Further, as shown in FIG. 21, the first low resistance region 31 is formed so as to be in contact with the body region 3 and the first bottom protection region 15.

The second low resistance region 32 is an n ⁺ type semiconductor region provided along the shot key trench 11 in the stretching direction of the shot key trench 11 and having an n-type impurity concentration higher than that of the drift layer 2. The second low resistance region 32 is provided on the side of the shot key trench 11 as shown in FIGS. 20 and 21. More specifically, the second low resistance region 32 is formed so as to be in contact with the entire region of the side surface of the shot key trench 11 and cover the side surface of the shot key trench 11 in the extending direction of the shot key trench 11. Further, as shown in FIG. 21, the second low resistance region 32 is formed so as to be in contact with the body region 3 and the second bottom protection region 16.

Note that FIGS. 20 and 21 show a case where the first low resistance region 31 in the MOS region 19 and the second low resistance region 32 in the SBD region 20 are separated from each other. It may be in contact.

Further, the first low resistance region 31 is not limited to being provided on both side surfaces facing each other of the gate trench 6, and may be formed on only one of the side surfaces. Further, the first low resistance region 31 may not be formed so as to be in contact with the entire region on the side surface of the gate trench 6 in the extending direction of the gate trench 6, or may be partially formed such as only a part of the region. ..

Similarly, the second low resistance region 32 is not limited to being provided on both side surfaces facing each other of the shot key trench 11, and may be formed on only one of the side surfaces. Further, the second low resistance region 32 does not have to be formed so as to be in contact with the entire region on the side surface of the shot key trench 11 in the extending direction of the shot key trench 11, and is partially formed such as only a part of the region. May be good.

The first low resistance region 31 is not limited to the one provided in contact with the side surface of the gate trench 6, and may be provided at a position in the drift layer 2 away from the side surface of the gate trench 6. Similarly, the second low resistance region 32 is not limited to being provided in contact with the side surface of the shot key trench 11, and may be provided at a position in the drift layer 2 away from the side surface of the shot key trench 11.

The first low resistance region 31 is not limited to the one provided in contact with the body region 3 and the first bottom protection region 15, and may be provided at a position away from these regions in the drift layer 2. Similarly, the second low resistance region 32 is not limited to the one provided in contact with the body region 3 and the second bottom protection region 16, and may be provided at a position away from these regions in the drift layer 2. ..

In the present embodiment, the semiconductor device 301 has a first bottom protection region 15 and a first low resistance region 31 on the gate trench 6 side, and a second bottom protection region 16 and a second low on the shotkey trench 11 side. The case where the resistance region 32 is provided will be described, but the present invention is not limited to this, and the semiconductor device 101 according to the first embodiment is further provided with only the first low resistance region 31, that is, the second bottom protection region 16. And the configuration may not have the second low resistance region 32.

Next, the manufacturing method of the semiconductor device 301 will be described with reference to FIGS. 22 to 28, focusing on the differences from the manufacturing method of the semiconductor device 201 of the second embodiment.

First, as shown in FIG. 14, the gate trench 6, the Schottky trench 11, the first bottom protection region 15, and the second bottom protection region 16 are formed in the same manner as in the manufacturing method of the semiconductor device 201 described in the second embodiment. After forming, the gate trench 6 is additionally etched as shown in FIG. Then, after the first mask 51 is formed or the first mask 51 is removed as shown in FIG. 22, N (nitrogen) and P (phosphorus) are formed from the inner walls of the gate trench 6 and the shot key trench 11. The n ⁺ type first low resistance region 31 and the second low resistance region 32 are formed by the gradient ion implantation such as.

Here, the first low resistance region 31 and the second low resistance region 32 are formed so that the concentration of n-type impurities in these regions is lower than the concentration of p-type impurities in the body region 3. By doing so, it is possible to prevent the conductive type of the body region 3 from being inverted to the n type. Further, by forming in this way, the concentration of n-type impurities in the first low resistance region 31 is lower than the concentration of p-type impurities in the first bottom protection region 15. Similarly, the concentration of n-type impurities in the second low resistance region 32 is lower than the concentration of p-type impurities in the second bottom protection region 16. Therefore, the conductive type of the first bottom protection region 15 and the second bottom protection region 16 is not inverted to the n type, and the corner portion of the gate trench 6 remains embedded in the first bottom protection region 15.

When a p-type connection region (not shown) is formed on the side surface of the gate trench 6, the p-type impurity concentration in the connection region is formed to be higher than the n-type impurity concentration in the first low resistance region 31. By doing so, the conductive type of the region originally the first low resistance region 31 can be inverted to the p type to form the connection region. Since the connection region is usually set so that the concentration of p-type impurities is higher than that of the body region 3, the connection region is formed even in the region that was originally the body region 3.

By doing so, the first low resistance region 31 can be formed so as to cover the side surface of the gate trench 6, and the second low resistance region 32 can be formed so as to cover the side surface of the shot key trench 11. Other parts can be manufactured in the same manner as the semiconductor device 201 of the second embodiment.

The first low resistance region 31 and the second low resistance region 32 may be formed as follows. 23 and 24 are diagrams showing a part of the steps of another manufacturing method of the semiconductor device 301 in the third embodiment. First, the body region 3, the source region 4, and the body contact region 5 are formed as shown in FIG. 5 in the same manner as in the manufacturing method of the semiconductor device 101 described in the first embodiment, and then as shown in FIG. 23. A fourth mask 54 having an opening wider than that of the gate trench 6 and the Schottky trench 11 formed in the subsequent process is formed on the semiconductor layer 21. Then, ion implantation is performed in the direction perpendicular to the surface of the semiconductor layer 21, and the first low resistance region 31 and the second low resistance region 32 are formed.

After removing the fourth mask 54, as shown in FIG. 24, the semiconductor layer is a first mask 51 having an opening narrower than that of the fourth mask 54 (first low resistance region 31 and second low resistance region 32). Formed on 21. The opening of the first mask 51 is formed so as to be located on the first low resistance region 31 and the second low resistance region 32. Then, using the first mask 51, the gate trench 6 and the shot key trench 11 reach the drift layer 2 from the surface of the semiconductor layer 21 through the source region 4 and the body region 3 by reactive ion etching (RIE). To form. At this time, as shown in FIG. 24, the gate trench 6 and the shot key trench 11 are formed so that the bottom portion of the trench is shallower than the lower portion of the first low resistance region 31 and the second low resistance region 32.

Further, using the first mask 51, ion implantation is performed in an oblique direction slightly inclined from the vertical direction with respect to the surface of the semiconductor layer 21, and a first bottom protection region 15 is formed at the bottom of the gate trench 6 to make a shot. A second bottom protection region 16 is formed at the bottom of the key trench 11. After that, a mask similar to the second mask 52 described with reference to FIG. 16 is formed, and the gate trench 6 is additionally etched. Other parts can be manufactured in the same manner as the semiconductor device 201 of the second embodiment.

Even the semiconductor device 301 configured in this way has the same effect as the semiconductor device 201 of the second embodiment. Further, in the semiconductor device 301 of the present embodiment, since the first low resistance region 31 having a higher n-type impurity concentration than the drift layer 2 is formed adjacent to the first bottom protection region 15, the first is formed. The resistance around the bottom protection region 15 is reduced, and the on-resistance of the MOSFET can be reduced. Similarly, since the second low resistance region 32 having a higher n-type impurity concentration than the drift layer 2 is formed adjacent to the second bottom protection region 16, the periphery of the second bottom protection region 16 is formed during the operation of the SBD. The resistance is reduced and a high shot key current can be obtained.

Further, since the first low resistance region 31 and the second low resistance region 32 are formed around the first bottom protection region 15 and the second bottom protection region 16, the first bottom protection region 15 and the second bottom protection region 15 are protected. The concentration of n-type impurities around the region 16 is high. That is, the pn junction composed of the first bottom protection region 15 and the first low resistance region 31 and the pn junction composed of the second bottom protection region 16 and the second low resistance region 32 are the drift layer. The potential of the n-type region of the pn junction increases as compared with the case of being composed of 2. As the potential of the n-type region of the pn junction increases, the built-in voltage of the body diode composed of the pn junction also increases, so that it becomes difficult for current to flow through the body diode.

Here, when the body diode made of a pn junction is composed of SiC (silicon carbide), a current usually flows through the body diode at about 3.5 V from the band gap of silicon carbide. However, when the potential of the n-type region of the pn junction is high, the body diode does not turn on unless a bias corresponding to that is applied. Therefore, when a forward bias is applied to the body diode, in the pn junction of the first bottom protection region 15 and the second bottom protection region 16 adjacent to the first low resistance region 31 and the second low resistance region 32, more Bipolar operation is suppressed up to high voltage.

On the other hand, the SBD can be turned on by applying a bias due to the Schottky barrier, and is usually turned on at a voltage lower than that of the body diode made of a pn junction, such as about 1 to 2 V. Therefore, when the forward bias is applied, the Schottky current, which is the unipolar current due to the SBD, begins to flow first, and when the bias becomes higher, the bipolar current due to the body diode starts to flow.

Therefore, by forming the first low resistance region 31 and the second low resistance region 32 having a higher n-type impurity concentration than the drift layer 2 around the first bottom protection region 15 and the second bottom protection region 16. Since the potential of the n-type region of the pn junction can be increased and the operating voltage of the body diode composed of the pn junction can be increased, a higher maximum unipolar current can be obtained in the SBD.

When the configuration does not have the second bottom protection region 16 and the second low resistance region 32, as shown in FIG. 9, the same as the manufacturing method of the semiconductor device 101 described in the first embodiment, The gate trench 6, the Schottky trench 11, and the first bottom protection region 15 are formed, and the gate trench 6 is additionally etched. After that, while the second mask 52 is formed as shown in FIG. 25, the n + type first n ⁺ type first is implanted by implanting inclined ions such as N (nitrogen) and P (phosphorus) from the inner walls of the gate trench 6 and the shot key trench 11. A low resistance region 31 is formed. Other parts can be manufactured in the same manner as the semiconductor device 101 of the first embodiment.

Next, a modified example of the semiconductor device 301 according to the second embodiment will be described. The semiconductor device 302 according to the first modification is different from the semiconductor device 301 in that the low resistance region 33 is formed. The low resistance region 33 is an n-type semiconductor region formed on the first drift layer 27 and having a higher n-type impurity concentration than the first drift layer 27.

Of the low resistance region 33, the portion formed in the MOS region 19 (the portion formed along the side surface of the gate trench 6) corresponds to the first low resistance region 31 and was formed in the SBD region 20. The portion (the portion formed along the side surface of the shot key trench 11) corresponds to the second low resistance region 32. Other configurations are the same as those of the semiconductor device 301 shown in FIGS. 22 and 23.

Next, a method of manufacturing the semiconductor device 302 according to the first modification will be described. 26 and 27 are views showing a part of the process of manufacturing the semiconductor device 302 according to the first modification. In the semiconductor device 302, the low resistance region 33 can be formed by epitaxial growth. That is, as shown in FIG. 26, after the n− type first drift layer 27 is formed on the substrate 1 by epitaxial growth ^, the n ⁺ type low resistance region 33 is formed on the first drift layer 27 by epitaxial growth. .. The combination of the first drift layer 27 and the low resistance region 33 corresponds to the above-mentioned drift layer 2.

Subsequently, in the same manner as in the manufacturing method shown in FIG. 5 of the first embodiment, the body region 3, the source region 4, and the body contact region 5 are set in the low resistance region 33 corresponding to the upper part of the drift layer 2 described above. It is formed by ion implantation in the upper layer. The body region 3, the source region 4, and the body contact region 5 can also be formed by epitaxial growth on the upper portion of the low resistance region 33.

Then, as shown in FIG. 27, the first mask 51 is used to reach the low resistance region 33 from the surface of the semiconductor layer 21 through the source region 4 and the body region 3 by reactive ion etching (RIE). The gate trench 6 and the shot key trench 11 are formed. At this time, the gate trench 6 and the shot key trench 11 are formed so that the bottom surface of the trench is shallower than the lower surface of the low resistance region 33. Further, using the first mask 51, ion implantation is performed in an oblique direction slightly inclined from the vertical direction with respect to the surface of the semiconductor layer 21, and a p ⁺ type first bottom protection region 15 is formed at the bottom of the gate trench 6. It is formed to form a p ⁺ -shaped second bottom protection region 16 at the bottom of the shot key trench 11. At this time, the first bottom protection region 15 and the second bottom protection region 16 are formed so that their lower portions are at the same depth as or deeper than the lower portion of the low resistance region 33.

By doing so, the low resistance region 33 can be formed in the portion of the drift layer 2 located above the lower part of the first bottom protection region 15 and the second bottom protection region 16. Other parts can be manufactured in the same manner as the semiconductor device 301 of the third embodiment.

The semiconductor device 302 according to the first modification can also obtain the same effects as described in the second and third embodiments.

Embodiment 4.
The semiconductor device of the fourth embodiment and the manufacturing method of the semiconductor device will be described with reference to FIGS. 28 and 29. FIG. 28 is a schematic cross-sectional view showing a partial cross section of the active region 40 in the semiconductor device 401 of the present embodiment, corresponding to the cross-sectional view taken along the line AA' in FIG. Further, FIG. 29 is a diagram showing a part of the steps of the manufacturing method of the semiconductor device 401 of the present embodiment.

As shown in FIG. 28, the semiconductor device 401 of the present embodiment is different from the semiconductor device 201 of the second embodiment in that the current diffusion region 34 is formed in the lower part of the body region 3. Since the other configurations of the semiconductor device of the present embodiment are the same as those of the semiconductor device 201 of the second embodiment, the differences from the semiconductor device 201 will be mainly described below.

The current diffusion region 34 is an n ⁺ type semiconductor region formed in the lower part of the body region 3 so that the upper surface is in contact with the lower surface of the body region 3. The n-type impurity concentration in the current diffusion region 34 is higher than the n-type impurity concentration in the drift layer 2. That is, the current diffusion region 34 has a lower resistance than the drift layer 2.

Next, the manufacturing method of the semiconductor device 401 will be described with reference to FIG. 29, focusing on the differences from the manufacturing method of the semiconductor device 101 of the first embodiment or the manufacturing method of the semiconductor device 201 of the second embodiment.

First, after forming the drift layer 2 as shown in FIG. 4, the body region 3, the source region 4, and the body are formed as shown in FIG. 29 in the same manner as in the manufacturing method of the semiconductor device 101 described in the first embodiment. The contact region 5 and the current diffusion region 34 are formed by ion implantation, respectively. All of these may be formed by epitaxial growth.

By doing so, the current diffusion region 34 can be formed below the body region 3. Other parts can be manufactured in the same manner as the semiconductor device 201 of the second embodiment.

Even the semiconductor device 401 configured in this way has the same effect as the semiconductor device 201 of the second embodiment. Further, in the semiconductor device 401 of the present embodiment, since the current diffusion region 34 is formed at the bottom of the body region 3, the JFET resistance between the body region 3 and the first bottom protection region 15 can be reduced. , It has the effect that the loss can be reduced by lowering the on-resistance.

Further, in the semiconductor device 401 of the present embodiment, since the Schottky current also flows in the vicinity of the body region 3 during the reflux operation, the bipolar operation in which the current flows in the pn junction between the body region 3 and the drift layer 2 is suppressed. It has an effect that can be achieved.

Embodiment 5.
In this embodiment, the semiconductor device according to any one of the above-described first to fourth embodiments is applied to a power conversion device. Although the present disclosure is not limited to a specific power conversion device, the case where the present disclosure is applied to a three-phase inverter will be described below as the fifth embodiment.

FIG. 30 is a block diagram showing a configuration of a power conversion system to which the power conversion device according to the present embodiment is applied.

The power conversion system shown in FIG. 30 includes a power supply 500, a power conversion device 600, and a load 700. The power supply 500 is a DC power supply, and supplies DC power to the power conversion device 600. The power supply 500 can be configured with various things, for example, it can be configured with a DC system, a solar cell, a storage battery, or it can be configured with a rectifier circuit or an AC / DC converter connected to an AC system. May be good. Further, the power supply 500 may be configured by a DC / DC converter that converts the DC power output from the DC system into a predetermined power.

The power conversion device 600 is a three-phase inverter connected between the power supply 500 and the load 700, converts the DC power supplied from the power supply 500 into AC power, and supplies AC power to the load 700. As shown in FIG. 30, the power conversion device 600 has a main conversion circuit 601 that converts input DC power into AC power and outputs it, and a drive that outputs a drive signal that drives each switching element of the main conversion circuit 601. It includes a circuit 602 and a control circuit 603 that outputs a control signal for controlling the drive circuit 602 to the drive circuit 602.

The load 700 is a three-phase electric motor driven by AC power supplied from the power converter 600. The load 700 is not limited to a specific application, and is an electric motor mounted on various electric devices. For example, the load 700 is used as an electric motor for a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioning device.

The details of the power conversion device 600 will be described below. The main conversion circuit 601 includes a switching element and a freewheeling diode (not shown), and by switching the switching element, the DC power supplied from the power supply 500 is converted into AC power and supplied to the load 700. There are various specific circuit configurations of the main conversion circuit 601. The main conversion circuit 601 according to the present embodiment is a two-level three-phase full bridge circuit, and has six switching elements and each switching element. It can be composed of six freewheeling diodes connected in antiparallel. The semiconductor device according to any one of the above-described embodiments 1 to 4 is applied to at least one of each switching element and each freewheeling diode of the main conversion circuit 601. Of these, the MOSFET structure arranged in the MOS region 19 can be used as a switching element, and the SBD arranged in the SBD region 20 can be used as a freewheeling diode. The six switching elements are connected in series for each of the two switching elements to form an upper and lower arm, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full bridge circuit. Then, the output terminals of each upper and lower arm, that is, the three output terminals of the main conversion circuit 601 are connected to the load 700.

The semiconductor device according to the first to fourth embodiments has an integrated structure in which a switching element and a freewheeling diode are built in one chip. Therefore, by using the MOSFET structure arranged in the MOS region 19 as the switching element of the main conversion circuit 601 and using the SBD arranged in the SBD region 20 as the freewheeling diode, the switching element and the freewheeling diode are formed separately. The mounting area can be reduced as compared with the case of using two or more chips.

The drive circuit 602 generates a drive signal for driving the switching element of the main conversion circuit 601 and supplies it to the gate electrode of the switching element of the main conversion circuit 601. Specifically, according to the control signal from the control circuit 603 described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the gate electrode of each switching element. When the switching element is kept on, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when the switching element is kept off, the drive signal is a voltage equal to or lower than the threshold voltage of the switching element. It becomes a signal (off signal).

The control circuit 603 controls the switching element of the main conversion circuit 601 so that the desired power is supplied to the load 700. Specifically, the time (on time) in which each switching element of the main conversion circuit 601 should be in the on state is calculated based on the electric power to be supplied to the load 700. For example, the main conversion circuit 601 can be controlled by PWM control that modulates the on-time of the switching element according to the voltage to be output. Then, a control command (control signal) is output to the drive circuit 602 so that an on signal is output to the switching element that should be turned on at each time point and an off signal is output to the switching element that should be turned off. The drive circuit 602 outputs an on signal or an off signal as a drive signal to the gate electrode of each switching element according to this control signal.

In the power conversion device according to the present embodiment, the semiconductor device according to any one of the first to fourth embodiments is applied as the switching element of the main conversion circuit 601. Therefore, the semiconductor device has high reliability in which bipolar deterioration is suppressed. By using it, the reliability of the power conversion device can be improved. Further, by applying the semiconductor device according to any one of the first to fourth embodiments as the switching element of the main conversion circuit 601 it is possible to reduce the mounting area, so that the size of the entire device can be reduced. can.

Further, any of the semiconductor devices of the first to fourth embodiments can suppress the dielectric breakdown of the gate insulating film 7 in the MOS region 19 and suppress the increase of the reverse leakage current in the SBD region 20. Therefore, the power conversion device according to the present embodiment has the effect that the withstand voltage can be improved and the reliability can be improved by applying the semiconductor device according to any one of the first to fourth embodiments. Play.

In the present embodiment, an example of applying the present disclosure to a two-level three-phase inverter has been described, but the present disclosure is not limited to this, and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is used, but a three-level or multi-level power conversion device may be used, and when power is supplied to a single-phase load, the present disclosure is disclosed to a single-phase inverter. You may apply it. Further, when supplying electric power to a DC load or the like, the present disclosure can be applied to a DC / DC converter or an AC / DC converter.

Further, the power conversion device to which the present disclosure is applied is not limited to the case where the above-mentioned load is an electric motor, and is, for example, a power supply device of a discharge machine, a laser machine, an induction heating cooker, or a non-contact power supply system. It can also be used as a power conditioner for a photovoltaic power generation system, a power storage system, or the like.

In the above-described embodiments 1 to 5 according to the present disclosure, the case where the semiconductor material is silicon carbide has been described, but other semiconductor materials may be used. That is, the semiconductor layer 21 including the substrate 1, the drift layer 2, the body region 3, the source region 4, the body contact region 5, and the like can be made of other semiconductor materials. Examples of other semiconductor materials include so-called wide bandgap semiconductors, which have a wider bandgap than silicon. Examples of the wide bandgap semiconductor other than silicon carbide include gallium nitride, aluminum nitride, aluminum gallium nitride, gallium oxide, and diamond. The same effect can be obtained even when these wide bandgap semiconductors are used.

In each of the above embodiments described in the present specification, the material, material, size, shape, relative arrangement relationship, implementation conditions, etc. of each component may be described, but all of them are described. It is an example in the aspect of, and is not limited to the one in which each embodiment is described. Therefore, innumerable variations not illustrated are assumed within the scope of each embodiment. For example, it includes a case where an arbitrary component is modified, a case where it is added or omitted, and a case where at least one component in at least one embodiment is extracted and combined with a component in another embodiment. ..

Further, as long as there is no contradiction, "one or more" components described as being provided in each of the above embodiments may be provided. Further, each component is a conceptual unit, and includes a case where one component is composed of a plurality of structures and a case where one component corresponds to a part of a structure.

In addition, none of the explanations in this specification is recognized as a prior art.

It should be noted that it is also included in the scope of the present disclosure that each embodiment is appropriately combined, modified or omitted.

1 Substrate, 2 Drift layer, 3 Body region, 4 Source region, 5 Body contact region, 6 Gate trench, 7 Gate insulating film, 8 Gate electrode, 9 Interlayer insulating film, 11 Schottky trench, 12 Schottky electrode, 13 Source Electrodes, 14 drain electrodes, 15 first bottom protection region, 16 second bottom protection region, 17 contact region, 19 MOS region, 20 SBD region, 21 semiconductor layer, 22 Schottky interface, 25, 27 first drift layer, 26. 2nd drift layer, 31 1st low resistance region, 32 2nd low resistance region, 33 low resistance region, 34 current diffusion region, 40 active region, 41 termination region,
101, 201, 301, 302, 401 Semiconductor devices,
500 power supply, 600 power converter, 601 main converter circuit, 602 drive circuit, 603 control circuit, 700 load

Claims

The first conductive type drift layer and
The second conductive type body region provided on the drift layer and
The first conductive type source region provided on the body region and
A gate insulating film provided in a gate trench penetrating the body region and the source region in the thickness direction of the drift layer.
A gate electrode provided in the gate trench and facing the source region via the gate insulating film, and a gate electrode.
A shot key electrode provided in a shot key trench penetrating the body region in the thickness direction of the drift layer, and a shot key electrode.
The gate trench is provided with a bottom surface, a part of a side surface thereof, and a second conductive type first bottom protection area provided in contact with a corner portion between the bottom surface and the side surface.
The shot key trench is a semiconductor device characterized in that the depth of the drift layer in the thickness direction is formed shallower than that of the gate trench.
The semiconductor device according to claim 1, wherein the bottom surface of the shot key trench is located above the upper surface of the first bottom protection region.
The semiconductor device according to claim 1 or 2, further comprising a second conductive type second bottom protection region provided below the shot key electrode.
The semiconductor according to claim 3, further comprising a second low resistance region of the first conductive type provided on the side of the shot key trench and having a concentration of impurities of the first conductive type higher than that of the drift layer. Device.
One of claims 1 to 4, which is provided on the side of the gate trench and further includes a first low resistance region of the first conductive type having an impurity concentration of the first conductive type higher than that of the drift layer. The semiconductor device according to item 1.
The invention according to any one of claims 1 to 3, further comprising a first conductive type current diffusion region provided below the body region and having a concentration of impurities of the first conductive type higher than that of the drift layer. The semiconductor device described.
The drift layer has a main surface provided with an off angle larger than 0 ° in the <11-20> axial direction.
The semiconductor device according to any one of claims 1 to 6, wherein the gate trench and the shot key trench are formed in a stretching direction parallel to the <11-20> axial direction.
The semiconductor device according to any one of claims 1 to 7, wherein a wide bandgap semiconductor is used as the semiconductor material for the drift layer.
A main conversion circuit having the semiconductor device according to any one of claims 1 to 8 and converting and outputting input power.
A drive circuit that outputs a drive signal to the semiconductor device,
A control circuit that outputs a control signal to the drive circuit,
Power conversion device equipped with.
The process of forming the second conductive type body region on the upper part of the first conductive type drift layer, and
A step of selectively forming a first conductive type source region on the upper part of the body region,
A step of forming a shot key trench that penetrates the body region and reaches the drift layer.
A step of forming a gate trench that penetrates the source region and the body region and reaches the drift layer deeper than the shot key trench.
The step of forming the first bottom protection region of the second conductive type below the gate trench, and
A step of forming a gate insulating film on the bottom and side surfaces of the gate trench, and
A step of forming a gate electrode so as to embed the gate trench through the gate insulating film, and
The process of forming a shot key electrode in the shot key trench and
A method for manufacturing a semiconductor device including.
A step of selectively forming a first bottom protection region of the second conductive type on the upper part of the first drift layer of the first conductive type, and a step of selectively forming the first bottom protection region of the second conductive type.
A step of forming a first conductive type second drift layer by epitaxial growth on the first drift layer and the first bottom protection region.
A step of forming a second conductive type body region on the upper part of the second drift layer, and
A step of selectively forming a first conductive type source region on the upper part of the body region,
A step of forming a shot key trench that penetrates the body region and reaches the second drift layer.
A step of forming a gate trench that penetrates the source region and the body region and reaches the first bottom protection region deeper than the shot key trench.
A step of forming a gate insulating film on the bottom and side surfaces of the gate trench, and
A step of forming a gate electrode so as to embed the gate trench through the gate insulating film, and
The process of forming a shot key electrode in the shot key trench and
A method for manufacturing a semiconductor device including.