WO2016084131A1 - Semiconductor device and power conversion device - Google Patents
Semiconductor device and power conversion device Download PDFInfo
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- WO2016084131A1 WO2016084131A1 PCT/JP2014/081102 JP2014081102W WO2016084131A1 WO 2016084131 A1 WO2016084131 A1 WO 2016084131A1 JP 2014081102 W JP2014081102 W JP 2014081102W WO 2016084131 A1 WO2016084131 A1 WO 2016084131A1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Definitions
- the present invention relates to a semiconductor device, a power conversion device using the semiconductor device, and an application thereof.
- SiC Silicon carbide
- SiC-MOSFETs Metal-Oxide-Semiconductor Field-Effect Transistors
- SiC has a wider band gap than Si and has a high dielectric breakdown strength.
- SiC-MOSFETs and SiC-IGBTs the electric field applied to the gate insulating film becomes a problem. For this reason, a structure with good symmetry is required so that the electric field applied to the gate insulating film is not biased.
- SiC-DMOSFET Double-Diffused MOSTET
- W channel width
- a structure having a long channel width (W) and good symmetry a structure in which p-type base regions are arranged in a rectangular or hexagonal shape is well known.
- a structure in which rectangular p-type base regions are arranged in a square lattice pattern is referred to as a BOX structure.
- FIG. 15 is a top view showing a cell pattern arrangement of a conventional general SiC-DMOSFET in a BOX structure. The positional relationship among the p-type base region 10, the source region 20, and the base contact region 11 is shown.
- the (unit) cell means a unit including at least the base region 10 and the source region 20. These cells have the same shape in design, and are regularly arranged at regular intervals. However, there may be a slight difference in shape due to process restrictions.
- FIG. 16 is a cross-sectional view taken along the line A-A ′ of FIG.
- 1 is a substrate
- 2 is a drift layer
- 10 is a base region
- 11 is a base contact region
- 20 is a source region
- 21 is a drain region
- 32 is a gate insulating film
- 33 is an interlayer film
- 40 is a gate material film.
- 41 is a source-base contact common electrode
- 42 is a drain contact electrode
- 51 is a source-base common contact
- 52 is a drain contact.
- an n ⁇ type drift layer 2 and a p type base region 10 are formed on an n + type silicon carbide substrate 1 by epitaxial growth or ion implantation, and an n + type source region 20 and p + A type base contact region 11 and an n + type drain region 21 are formed by ion implantation.
- a gate insulating film 32 is formed on such a silicon carbide substrate 1 using a thermal oxidation method or a deposited oxide film, and a gate electrode is formed via the gate insulating film 32.
- SiC ⁇ A DMOSFET is completed.
- FIG. 17 is a plan view of a conventional vertical silicon carbide semiconductor device, and the position of electric field concentration is indicated by a dotted circle.
- the DMOSFET is off, that is, when a voltage lower than the on-voltage is applied to the gate electrode and a voltage is applied to the drain contact electrode, the BOX structure is surrounded by cells as shown in FIG. It is known that the electric field concentrates at the center of the JFET (junction field effect transistor) region, and the electric field strength applied to the gate insulating film increases.
- JFET junction field effect transistor
- Step flow growth is a method of performing epitaxial growth on a surface into which an offset angle (hereinafter referred to as an off angle) of, for example, several degrees (for example, 4 degrees or 8 degrees) is introduced from the ⁇ 0001 ⁇ plane.
- an off angle is introduced into the surface of the substrate 1 and epitaxial growth is performed thereon.
- FIG. 18 is a cross-sectional view showing the surface shape of an epitaxial wafer using step flow growth.
- an epitaxial wafer using this step flow growth has an off-angle in principle, and the ⁇ 0001 ⁇ plane is asymmetric with respect to the wafer surface 1800 by the off-angle.
- Wafer surface (principal surface) 1800 can be considered geometrically as a plane connecting the lowest point or the highest point of the substrate surface.
- FIG. 18 is a principle diagram, and in an actual product, surfaces and corners may not form strict planes and corners. In practice, it can be considered that the fine irregularities on the wafer surface shown in FIG. 18 are averaged or ignored. For convenience, when a wafer is grasped as a plate (disk) as shown in FIG.
- a surface having a relatively large area ( ⁇ 0001 ⁇ surface in FIG. 18) is regarded as a step surface of the staircase, and the upper step side of the staircase is the upstep side and the lower step side is the downstep side. Call it. That is, the direction in which the surface having a relatively large area faces is the upstep side. Furthermore, the direction from the up-step side to the down-step side is defined as the off direction.
- FIG. 19 shows the results of a computer experiment of implanting aluminum ions (Al +) into an epitaxial layer on a 4H—SiC substrate by a two-dimensional Monte Carlo simulation conducted by the inventors.
- Al + aluminum ions
- the curvature of the Al concentration distribution below the mask edge is larger in the [11-20] direction than in the [-1-120] direction, and the Al after implantation is increased. Wide diffusion range. This indicates that the electric field relaxation effect of the electric field applied to the gate oxide film is greater on the down step side than on the up step side of the cell.
- FIG. 20 is a plan view showing the electric field concentration position of the vertical silicon carbide semiconductor device examined based on the above examination.
- the electric field applied to the gate oxide film shifts from the center of the JFET region surrounded by the cells in the down-step direction.
- the breakdown voltage in the gate insulating film is reduced in the conventional structure, and the design is different.
- the present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device, in particular, an SiC-DMOSFET and an SiC-IGBT in consideration of breakdown voltage characteristics.
- the present application includes a plurality of means for solving the above-mentioned problems.
- One aspect of the present invention is a semiconductor substrate of a first conductivity type, a drift region of the first conductivity type formed on the semiconductor substrate, and a plurality of periodically formed with a gap in the surface layer of the drift region. It is a semiconductor device provided with a unit cell. Each of the unit cells of the semiconductor device is formed in contact with the base region, the base region of the second conductivity type, the source region of the first conductivity type formed in the base region so as to be surrounded by the base region. And a second contact base contact region having a higher impurity concentration than the base region. And it has the 2nd conductivity type electric field relaxation area
- the area occupied by the electric field relaxation region can be reduced, and the influence on the channel region can be reduced.
- the first external connection electrode formed so as to cover at least a part of each region, and on the source region, the base region, the drift region, and the electric field relaxation region, It is desirable to include a gate insulating film formed so as to cover at least a part of each region.
- the shape of the unit cell can be defined by the shape of the base region for convenience, and can be expressed as a rectangle, a square, or a hexagon when viewed from directly above the surface layer of the drift region.
- the second cell when a group of cells is defined by a set of unit cells closest to each other, the second cell is covered so as to cover a point shifted from the geometric center of gravity of the unit cell group to the off-direction side.
- the conductivity type electric field relaxation region extends. By forming the electric field relaxation region at a necessary portion, the influence on the channel region can be further reduced.
- the set of unit cells closest to each other is composed of, for example, four unit cells whose sides are in contact with each other when the unit cells are square and arranged in a square lattice pattern.
- the unit cell is a hexagonal hexagonal lattice array, the unit cell is composed of three unit cells that are in contact with each other.
- the electric field relaxation region of the second conductivity type is extended from at least one of the corner portions of the unit cell not facing the off direction side toward the shifted position, Furthermore, since the electric field relaxation region can be reduced, the influence on the channel region can be further reduced.
- the other side surface of the semiconductor device of the present invention is formed periodically with a gap between the first conductivity type semiconductor substrate, the first conductivity type drift region formed on the semiconductor substrate, and the surface layer of the drift region.
- Each of the unit cells includes a second conductivity type base region, a first conductivity type source region formed to be surrounded by the base region in the base region, and the base region formed in contact with the base region. And a base contact region of a second conductivity type having a higher impurity concentration.
- a first external connection electrode formed on the second conductivity type electric field relaxation region extending from the base region of the unit cell, the source region, and the base contact region so as to cover at least a part of each region.
- a gate insulating film formed on the source region, the base region, the drift region, and the electric field relaxation region so as to cover at least a part of each region.
- the electric field of the second conductivity type is directed toward a point shifted to the off direction side from the geometric center of gravity of the group of unit cells. Mitigation area is expanding. In this manner, by forming the electric field relaxation region in a necessary portion, the influence on the channel region can be further reduced.
- the electric field relaxation region of the second conductivity type is extended from the base region of the unit cell in a range not connected to the base region of another unit cell.
- the area of the electric field relaxation region can be further reduced, and the influence on the channel region can be reduced.
- the second conductivity type electric field relaxation region can be extended from the base region of the unit cell so as to be connected to the base region of another unit cell. In this way, the potential of the base region can be easily fixed, and a highly reliable device can be realized.
- the impurity concentration of the electric field relaxation region of the second conductivity type is in a range that can be formed using the base region or the base contact region and the common mask, the manufacturing efficiency is good, and in a preferable mode. is there.
- another aspect of the present invention is a power conversion device using the semiconductor device as a switching element.
- a power conversion device using the semiconductor device as a switching element.
- an inverter or a converter using the semiconductor device as an element, it is possible to improve the performance of the power conversion device.
- a three-phase motor system using the power converter can achieve high performance by the switching element.
- another aspect of the present invention is a transportation device such as an automobile or a railway vehicle equipped with the motor system.
- the semiconductor device of the present invention it is possible to provide a semiconductor device with excellent breakdown voltage in the gate insulating film.
- 1 is a plan view of a silicon carbide semiconductor device in a first embodiment.
- 1 is a plan view of a silicon carbide semiconductor device in a first embodiment.
- 1 is a cross sectional view of a silicon carbide semiconductor device in a first embodiment.
- 1 is a cross sectional view of a silicon carbide semiconductor device in a first embodiment.
- 1 is a cross sectional view of a silicon carbide semiconductor device in a first embodiment.
- 1 is a cross sectional view of a silicon carbide semiconductor device in a first embodiment.
- 1 is a cross sectional view of a silicon carbide semiconductor device in a first embodiment.
- 1 is a cross sectional view of a silicon carbide semiconductor device in a first embodiment.
- FIG. 1 is a cross sectional view of a silicon carbide semiconductor device in a first embodiment.
- 1 is a cross sectional view of a silicon carbide semiconductor device in a first embodiment.
- 1 is a cross sectional view of a silicon carbide semiconductor device in a first embodiment.
- 1 is a cross sectional view of a silicon carbide semiconductor device in a first embodiment.
- FIG. 6 is a plan view of a silicon carbide semiconductor device in a second embodiment.
- FIG. 6 is a cross sectional view of a silicon carbide semiconductor device in a second embodiment.
- FIG. 6 is a cross sectional view of a silicon carbide semiconductor device in a second embodiment.
- FIG. 6 is a cross sectional view of a silicon carbide semiconductor device in a second embodiment.
- FIG. 7 is a plan view of a silicon carbide semiconductor device in a third embodiment.
- FIG. 6 is a cross sectional view of a silicon carbide semiconductor device in a third embodiment.
- FIG. 6 is a cross sectional view of a silicon carbide semiconductor device in a third embodiment.
- FIG. 6 is a cross sectional view of a silicon carbide semiconductor device in the third and fourth embodiments.
- FIG. 7 is a plan view of a silicon carbide semiconductor device in a fourth embodiment.
- FIG. 10 is a plan view of a silicon carbide semiconductor device in a fifth embodiment. It is a circuit diagram of the power converter device (inverter) of the Example of this invention. It is a circuit diagram of the power converter device (inverter) of the Example of this invention.
- FIG. 1 is a circuit diagram of a boost converter according to an embodiment of the present invention.
- 1 is a configuration diagram of a railway vehicle according to an embodiment of the present invention.
- It is a top view of the conventional vertical silicon carbide semiconductor device. It is sectional drawing of the conventional vertical silicon carbide semiconductor device. It is a top view of the conventional vertical silicon carbide semiconductor device.
- FIG. 5 is a schematic cross-sectional view showing a 4H—SiC epitaxial wafer surface shape using step flow growth.
- FIG. 5 is a schematic cross-sectional view showing a 4H—SiC epitaxial wafer surface shape using step flow growth.
- notations such as “first”, “second”, and “third” are attached to identify the constituent elements, and do not necessarily limit the number or order.
- a number for identifying a component is used for each context, and a number used in one context does not necessarily indicate the same configuration in another context. Further, it does not preclude that a component identified by a certain number also functions as a component identified by another number.
- plan views showing the semiconductor devices of the third to fifth embodiments the description of the electric field relaxation region connected to the outer cell than the outermost cell is omitted.
- a silicon carbide semiconductor device having a so-called MOS (Metal-Oxide-Semiconductor) structure will be described.
- MOS Metal-Oxide-Semiconductor
- Each plan view shows only the ion implantation region for simplicity, but in an actual device structure, a source contact, drain contact, gate insulating film, gate electrode, source base contact common electrode, drain contact electrode, surface protective film, etc. Needless to say, it exists.
- the conductivity type of implanted ions is referred to as n-type, n-type, n + -type, p-type, p-type, p + -type, but the impurity implanted into the region desired to be n-type, n-type, n + -type is
- boron (B) or aluminum (Al) ions are used as an impurity for injecting nitrogen (N) ions or phosphorus (P) into regions desired to be p-type, p-type, and p + -type.
- FIG. 1A is a plan view (upper surface) of an ion implantation region showing a cell structure of a SiC-MOSFET which is a silicon carbide semiconductor device according to the present embodiment.
- FIG. 2K is a cross-sectional view taken along the line A-A′B-B ′ of FIG. 1.
- the SiC-MOSFET which is a silicon carbide semiconductor device has the following characteristics.
- a surface layer of the drift region 2 has a plurality of p-type base regions 10 formed at intervals, for example, arranged in a square lattice pattern.
- the p-type base region 10 has, for example, a square shape.
- the arrangement and shape of the p-type base region 10 may be a rectangular lattice or a rectangular shape. Note that the sides constituting the p-type base region 10 are substantially parallel to or substantially perpendicular to the off direction.
- the p + -type base contact region 11 is a region for establishing electrical connection with the base region 10.
- the p + -type base contact region 11 is formed so as to be surrounded by the source region 20.
- the p + -type base contact region 11 only needs to be surrounded by the base region 10.
- it is not necessarily formed so as to be surrounded by the source region 20.
- the base region 10 and the p + -type base contact region 11 are in contact with each other in order to make contact with the base region 10. Need to be formed. The same applies to the other embodiments described below.
- the first adjacent cell of a certain cell is a cell closest to a certain cell, and in the example of FIG. 1A, is another cell whose sides face each other and contact a certain rectangular cell.
- the distance between the cells can be, for example, the distance between the geometric centroids of the cells.
- the second adjacent cell is the second closest cell, and is another cell whose corners face each other and are in contact with a rectangular cell in the example of FIG. 1A.
- the p-type electric field relaxation region 60 is extended from the four corners of the rectangular unit cell in the direction of the other cell corner that is in the second proximity so as not to be connected to other cells.
- the MOS when the MOS is turned on, the vicinity of the four corners of the unit cell is depleted and the channel width (W) is reduced.
- a decrease in channel width (W) leads to an increase in on-resistance. Therefore, in order to suppress the decrease in W as much as possible, it is preferable to provide a p-type electric field relaxation region 60 at one corner of the cell.
- the electric field applied to the gate insulating film becomes strong because the unit cell of the base region 10 and the center line (adjacent to the cell) adjacent to the cell in the direction perpendicular to the off direction.
- the base region corner that is on the same distance from the cell and the base region corner that is in contact with the p-type electric field relaxation region and the base region corner that is in the second vicinity thereof are connected by lines. It exists on the down-step side from the intersection.
- providing the p-type electric field relaxation region on the up-step side of the cell requires less area than the p-type electric field relaxation region on the down-step side of the cell. It can be made smaller and the influence on the channel area can be reduced. Therefore, as shown in FIG. 1A, it is preferable to provide a p-type electric field relaxation region on the up-step side of the cell.
- a group of cells is defined by a set of unit cells closest to each other (for example, four cells adjacent in FIG. 1A).
- the electric field relaxation region of the second conductivity type is extended toward a point shifted to the off direction side from the geometric gravity center position of the unit cell group.
- the center line of the electric field relaxation region is designed to be shifted from a line (for example, A-A ′ line) connecting opposing corners of the unit cell. The same applies to the following embodiments.
- the contour of the end portion of the electric field relaxation region is composed of two corners, but may be a polygonal shape or a curved surface shape.
- the shape of the electric field relaxation region on the cell side may be a curved shape instead of connecting with corners. When it has a corner, an obtuse angle is preferable to an acute angle.
- the contour of the electric field relaxation region is preferably as smooth as possible. The same applies to the other embodiments described below.
- the length of the p-type electric field relaxation region is designed to satisfy the following inequality (1).
- L J2 -L J1 ⁇ L E ⁇ L J2 (1) L E : Length from the corner of the base region serving as the base point to the end of the electric field relaxation region
- L J1 The distance between the corner of the base region serving as the base point and the other cell corner serving as the first proximity
- L J2 as shown in distance diagram 1B between the corner and the other cell corners to be the second proximity base region of the base point, the longer L E than L J2 -L J1, base adjacent to the electric-field relaxation region Since the distance between the corners of the region is shorter than the distance between the cells, the electric field applied to the gate insulating film can be effectively reduced.
- L J1 and L J2 are shown except for the corners that are the base points of the electric field relaxation region. However, if it is assumed that the cells are periodically arranged, The measured distance is the same value (the same applies to FIG. 3).
- the p-type electric field relaxation region 60 may be formed simultaneously with the formation of the base region 10 or the base contact region 11 in order to reduce the process cost by reducing the number of masks. For this reason, the impurity concentration of the p-type electric field relaxation region 60 can be created simultaneously in the process by making it the same as the concentration of the base region 10 or the base contact region 11. Specifically, when the range satisfies 5 ⁇ 10 18 to 1 ⁇ 10 21 cm ⁇ 3 , the process can be shared by using a base region, a base contact region, and a common mask. The same applies to the other embodiments described below.
- FIG. 2K will be described in detail.
- FIG. 2A to FIG. 2K are cross-sectional views in respective steps when manufacturing the silicon carbide semiconductor device of the first embodiment in A-A ′ and B-B ′ of FIG. 1.
- the cross-sectional view shows only the configuration of the main part in the process, and does not correspond to an accurate cross-sectional view.
- the semiconductor device described above is manufactured using an epitaxial wafer as shown in FIG. 2A.
- the impurity concentration having an offset of 8 °, 4 °, 2 °, 0.5 °, etc. is 1 ⁇ 10 18 to 1 ⁇ 10 21 cm ⁇ 3 .
- a silicon carbide epitaxial layer 2 having an impurity concentration of, for example, 1 ⁇ 10 14 to 1 ⁇ 10 18 cm ⁇ 3 was stacked on the n + type 4H—SiC wafer.
- the surface of the epitaxial layer 2 has geometric anisotropy as shown in FIGS. 18A and 18B.
- a mask 30B is used to implant ions into the p-type base region 10, and as shown in FIG. 2B, Al ions are implanted into the surface layer portion of the silicon carbide epitaxial layer 2 to form a p-type base. Region 10 was formed.
- the impurity implantation depth is, for example, about 1 ⁇ m.
- the impurity concentration is, for example, in the range of 5 ⁇ 10 16 to 1 ⁇ 10 19 cm ⁇ 3 .
- the ions implanted into the p-type base region 10 may be B ions.
- a p-type silicon carbide epitaxial layer may be further formed on silicon carbide epitaxial layer 2 to form p-type base region 10. Also in this case, the surface of the p-type base region 10 has geometric anisotropy as shown in FIGS. Thereafter, the mask 30B was removed.
- a mask 30C is used to implant ions into the source region 20, and as shown in FIG. 2C, N ions are implanted into the surface layer portion of the silicon carbide epitaxial layer 2 via the mask 30C. Region 20 was formed.
- the impurity implantation depth is, for example, in the range of 0.1 to 0.5 ⁇ m.
- the impurity concentration is, for example, in the range of 1 ⁇ 10 18 to 1 ⁇ 10 21 cm ⁇ 3 .
- the ions implanted into the source region 20 may be P ions. Thereafter, the mask 30C was removed.
- a mask 30D is used to implant ions into the base contact region 11, and as shown in FIG. 2D, Al ions are implanted into the surface layer portion of the silicon carbide epitaxial layer 2 via the mask 30D.
- a base contact region 11 was formed.
- the impurity implantation depth is, for example, in the range of 0.1 to 0.5 ⁇ m.
- the impurity concentration is set to about 1 ⁇ 10 18 to 1 ⁇ 10 21 cm ⁇ 3 , for example.
- the ions implanted into the base contact region 11 may be B ions. Thereafter, the mask 30D was removed.
- FIG. 2E Next, a mask 30E is implanted to implant ions into the electric field relaxation region 60, and as shown in FIG. 2E, Al ions are implanted into the surface layer portion of the silicon carbide epitaxial layer 2 via the mask 30E. An electric field relaxation region 60 was formed. Thereafter, the mask 30E was removed.
- the impurity implantation depth is, for example, about 0.1 to 1 ⁇ m.
- the impurity concentration is, for example, in the range of 5 ⁇ 10 16 to 1 ⁇ 10 21 cm ⁇ 3 . Therefore, in this embodiment, the mask 30E for forming the electric field relaxation region 60 is used. However, if the Al ion implantation concentration is in the range of 5 ⁇ 10 16 to 1 ⁇ 10 21 cm ⁇ 3 , for example,
- the electric field relaxation region 60 may be formed simultaneously when Al ions are implanted into the p-type base region 10 or the base contact region 11.
- the ions implanted into the electric field relaxation region 60 may be B ions.
- N ions were implanted into the back surface of the silicon carbide substrate 1 to form a drain region 21.
- the impurity concentration is, for example, in the range of 1 ⁇ 10 16 to 1 ⁇ 10 19 cm ⁇ 3 .
- the ions implanted into the drain region 21 may be P ions.
- a carbon film as a cap material for impurity activation annealing is deposited around the silicon carbide substrate 1 and the silicon carbide epitaxial layer 2, and impurity activation annealing is performed at a temperature of 1600 to 1800 ° C., for example. It was. Thereafter, the carbon layer of the cap material was removed by oxygen plasma ashing, and in order to obtain a cleaner surface, a thermal oxide film was formed and removed using a diluted hydrofluoric acid solution.
- a gate insulating film 32 is formed on the semiconductor substrate.
- a deposited oxide film having a thickness of about 10 to 100 nm is formed.
- FIG. 2H Subsequently, as shown in FIG. 2H, a gate material film 40 made of an n-type polycrystalline silicon film having a thickness of about 100 to 300 nm was deposited.
- the interlayer film 33 is etched using a resist as a mask to form contact holes. Then, a metal for silicide is deposited, and silicidation is performed, for example, by annealing at 700 ° C. to 1000 ° C., and the source base common contact 51 is formed. Thereafter, in order to make contact with the gate electrode, the interlayer film 33 was etched to form a gate contact hole.
- a source-base contact common electrode 41 as shown in FIG. 2K was formed.
- the drain region 21 on the back surface is also silicided to form a drain contact 52 and a drain contact electrode 42.
- a metal material such as Ni or Al is used.
- a semiconductor device is completed through a step of forming a surface protective film covering the entire surface made of an insulator for device protection and a step of wiring to the electrodes.
- the electric field applied to the gate oxide film is strengthened, and the point shifted in the down-step direction from the center of the JFET region surrounded by the cell is protected by the electric field relaxation region.
- the decrease in breakdown voltage and the difference from the design caused by the gate insulating film are eliminated.
- FIG. 3 is a plan view of an ion implantation region showing a cell structure of a SiC-MOSFET which is a silicon carbide semiconductor device according to the present embodiment.
- FIG. 4B is a cross-sectional view of the same.
- the SiC-MOSFET which is a silicon carbide semiconductor device has the following characteristics.
- a surface layer of the drift region 2 has a plurality of p-type base regions 10 formed at intervals, for example, arranged in a hexagonal lattice shape.
- the p-type base region 10 has, for example, a hexagonal shape.
- an n + -type source region 20 formed on the surface layer so as to be surrounded by the base region 10 and in the base region 10, a region other than the source region 20 so as to be surrounded by the base region 10 on the surface layer
- the p + -type base contact region 11 having a higher impurity concentration than the base region 10 formed in FIG.
- the p + -type base contact region 11 is a region for establishing electrical connection with the base region 10.
- the unit cell of the base region 10 in which the source region 20 and the base contact region 11 are formed and arranged in a hexagonal lattice shape for example, from one corner of the base region 10, two corners of other cells that are close to each other It has a p-type electric field relaxation region 60 extending in a range not connected to other cells in the middle point direction connected by a straight line.
- the p-type electric field relaxation region 60 has a single hexagonal shape, for example, a midpoint obtained by connecting two corners of other cells that are in the first proximity from six corners with straight lines.
- the vicinity of the six corners is depleted when the MOS is turned on.
- the first adjacent cell is another cell whose sides are opposed to a certain hexagonal cell
- the second adjacent cell is the first adjacent to a certain cell.
- other cells whose sides are opposed to each other (excluding cells that are in the first proximity).
- the point where the electric field applied to the gate insulating film becomes strong is a point shifted from the center of the JFET region surrounded by the cells.
- the location is a position where the down-step direction component and the component in the direction perpendicular to the off direction are combined. For this reason, it is possible to shorten the length of the electric field relaxation region by providing the p-type electric field relaxation region 60 on the up-step side of the cell, compared to providing the p-type electric field relaxation region 60 on the down-step side of the cell.
- the influence on the area can be reduced. Therefore, as shown in FIG. 3, it is preferable to provide a p-type electric field relaxation region on the upstep side of the cell.
- the length of the p-type electric field relaxation region is designed to satisfy the following inequality (2).
- FIG. 4 is a diagram showing a part different from the first embodiment in the method for manufacturing a semiconductor device in the second embodiment.
- the second embodiment is the same as the semiconductor device according to the first embodiment shown in FIGS. 1 and 2 except that the cross-sectional view when forming the electric field relaxation region 60 is FIG. 4A and the cross-sectional view when completed is 4B. is there.
- the electric field applied to the gate oxide film is strengthened, and the point shifted in the down-step direction from the center of the JFET region surrounded by the cell is protected by the electric field relaxation region.
- the decrease in breakdown voltage and the difference from the design caused by the gate insulating film are eliminated.
- FIG. 5 is a plan view of an ion implantation region showing a cell structure of a SiC-MOSFET which is a silicon carbide semiconductor device according to the present embodiment.
- FIG. 6B is a cross-sectional view.
- the SiC-MOSFET that is a silicon carbide semiconductor device is basically the same as that shown in FIGS. 1A, B, and 2K. In particular, the differences will be described below.
- the gate insulating film 32 is formed in a region surrounded by four unit cells of the base region 10 in which the source region 20 and the base contact region 11 are formed and arranged in a square lattice pattern.
- a cross-shaped p-type electric field relaxation region 60 is disposed so as to include a point where an applied electric field becomes strong.
- the cross-shaped p-type electric field relaxation region 60 is arranged so that the point where the electric field applied to the gate insulating film 32 becomes strong is the center.
- the point where the electric field applied to the gate insulating film 32 becomes strong exists on the unit cell of the base region 10 and the center line of the cell adjacent to the cell in the direction perpendicular to the off direction, and the p-type It exists on the down-step side from the intersection where the base region corner which is the base point of extension of the electric field relaxation region and the base region corner which is the second proximity thereof are connected by lines. Therefore, as shown in FIG. 5, the cell center line C and the cross-shaped electric field relaxation region are arranged off the intersection.
- FIG. 7 shows a cross-sectional view of the unit cell in the base region 10 and the center line of the cell adjacent to the cell in the direction perpendicular to the off direction (D-D ′ region in FIG. 5).
- a unit cell in the base region and a point C indicating the position of the center line of the cell adjacent to the cell in the off direction are attached.
- the central point of the p-type electric field relaxation region in the vicinity of the SiC / SiO 2 interface that is, the point where the electric field applied to the gate insulating film becomes strong exists at a position shifted from the point C to the down step side by the length N.
- the length N depends on the off angle and the ion implantation depth, but at least the length N takes the range of the inequality (3).
- N Distance between the intersection of the base region corner and the base region corner of the second adjacent cell with a line and the point where the electric field applied to the gate insulating film becomes strong
- L J1 Corner of the base region serving as the base point And the distance between the other cell corners that are in the first proximity (similar to that shown in FIG. 1B)
- the shape of the region surrounded by the drift region of the p-type electric field relaxation region is such that if there are corners, electric field concentration occurs at the corners, and the breakdown voltage becomes a problem. In the present embodiment, it is preferable to round the corners of the cross-shaped intersection.
- FIG. 6 is a diagram showing portions different from those in the first embodiment in the semiconductor device manufacturing method in the third embodiment.
- the third embodiment is the same as the semiconductor device according to the first embodiment shown in FIGS. 1 and 2 except that the cross-sectional view when the electric field relaxation region 60 is formed is FIG. 6A and the cross-sectional view when completed is 6B. is there.
- the electric field applied to the gate oxide film is strengthened, and the point shifted in the down-step direction from the center of the JFET region surrounded by the cell is protected by the electric field relaxation region.
- the decrease in breakdown voltage and the difference from the design caused by the gate insulating film are eliminated.
- the semiconductor device described in the first embodiment when there is a contact failure in the p-type base contact region in one cell, the potential of the p-type base region cannot be fixed. Cause.
- the semiconductor device in this embodiment since the p-type base region of each cell is connected, contact can be made in another cell. Therefore, the potential of the p-type base region can be fixed more easily than in the semiconductor device described in Embodiment 1, and a highly reliable device can be realized.
- FIG. 8 is a plan view of an ion implantation region showing a cell structure of a SiC-MOSFET which is a silicon carbide semiconductor device according to the present embodiment.
- the SiC-MOSFET which is a silicon carbide semiconductor device is basically the same as that shown in FIGS. 1A, B and 2K. In particular, the differences will be described below.
- the source region 20 and the base contact region 11 are arranged so as to include a point where the electric field applied to the gate insulating film 32 becomes strong.
- a linear p-type electric field relaxation region 60 is provided. In the present embodiment, the linear p-type electric field relaxation region 60 is arranged so that the point where the electric field applied to the gate insulating film 32 becomes strong is the center.
- the point where the electric field applied to the gate insulating film becomes strong exists on the unit cell of the base region 10 and the center line C of the cell adjacent to the cell in the direction perpendicular to the off direction, and the p-type
- the base region corner portion serving as the base point of the extension of the electric field relaxation region and the base region corner portion adjacent to the base region corner portion thereof are present on the down-step side from the intersections respectively connected by lines.
- the center line of the linear p-type electric field relaxation region 60 that connects the corners of the base region 10 may be arranged at a position shifted from the center line C of the cell. desirable.
- FIG. 7 shows a cross-sectional view of a unit cell in the base region and a center line (DD ′ region in FIG. 8) of a cell adjacent to the cell in a direction perpendicular to the off direction.
- a unit cell of the base region and a point C indicating the position of the center line of the cell adjacent to the cell in the off direction are attached.
- the central point of the p-type electric field relaxation region in the vicinity of the SiC / SiO 2 interface that is, the point where the electric field applied to the gate insulating film becomes strong exists at a position shifted from the point C to the down step side by the length N.
- the length N depends on the off angle and the ion implantation depth, but at least the length N takes the range of the inequality (4).
- N Distance between the intersection of the base region corner and the base region corner of the second adjacent cell with a line and the point where the electric field applied to the gate insulating film becomes strong
- L J1 Corner of the base region serving as the base point And the distance between the other cell corners that are in the first proximity (similar to that shown in FIG. 1B)
- the semiconductor device in the fourth embodiment can be manufactured in the same manner as the semiconductor device described in the third embodiment.
- the electric field applied to the gate oxide film is strengthened, and the point shifted in the down-step direction from the center of the JFET region surrounded by the cell is protected by the electric field relaxation region.
- the decrease in breakdown voltage and the difference from the design caused by the gate insulating film are eliminated.
- the semiconductor device described in the first embodiment when there is a contact failure in the p-type base contact region in one cell, the potential of the p-type base region cannot be fixed. Cause.
- the p-type base region of each cell is connected. In the example of FIG. 8, the p-type base regions of the second neighboring cells are connected. For this reason, contact can be made in another cell.
- the potential of the p-type base region can be fixed more easily than in the semiconductor device described in Embodiment 1, and a highly reliable device can be realized.
- the cross-shaped p-type field relaxation region is used.
- the semiconductor device in this embodiment uses a bridge-type structure, the area occupied by the p-type field relaxation region is large. Few. Therefore, the influence on the channel region can be reduced, so that the on-resistance can be made smaller than that of the semiconductor device described in Embodiment 3.
- FIG. 9 is a plan view of an ion implantation region showing a cell structure of a SiC-MOSFET which is a silicon carbide semiconductor device according to the present embodiment.
- the SiC-MOSFET which is a silicon carbide semiconductor device is basically the same as that shown in FIGS. 1A, 1B and 2K. In particular, the differences will be described below.
- the p-type electric field relaxation region extends from the two corners to the point where the electric field applied to the gate insulating film becomes stronger, and the two p-type electric field relaxation regions are connected. That is, the p-type electric field relaxation region has a V-shape.
- the point where the electric field applied to the gate insulating film becomes strong is that the unit cell in the base region exists on the center line of the cell adjacent to the cell in the direction perpendicular to the off direction, and is a p-type electric field. It exists on the down-step side from the intersection where the base region corner which is the base point of extension of the relaxation region and the base region corner which is the second proximity thereof are connected by lines.
- FIG. 7 shows a cross-sectional view of a unit cell in the base region and a center line (a DD ′ region in FIG. 9) of a cell adjacent to the cell in a direction perpendicular to the off direction.
- a unit cell of the base region and a point C indicating the position of the center line of the cell adjacent to the cell in the off direction are attached.
- the central point of the p-type electric field relaxation region in the vicinity of the SiC / SiO 2 interface that is, the point where the electric field applied to the gate insulating film becomes strong exists at a position shifted from the point C to the down step side by the length N.
- the length N depends on the off angle and the ion implantation depth, but at least the length N takes the range of the inequality (5).
- N Distance between the intersection of the base region corner and the base region corner of the second adjacent cell with a line and the point where the electric field applied to the gate insulating film becomes strong
- L J1 Corner of the base region serving as the base point And other cell corners that are in the first proximity (similar to that shown in FIG. 1B) It is better to select two points on the up-step side as the two corner portions that are the first proximity. This is because at the two points on the down step side, the area occupied by the p-type electric field relaxation region becomes larger than the area on the up step side, the influence on the channel region increases, and the on-resistance increases.
- the manufacturing method of the semiconductor device in the fifth embodiment is the same as that of the semiconductor device described in the first embodiment.
- the electric field applied to the gate oxide film is strengthened, and the point shifted in the down-step direction from the center of the JFET region surrounded by the cell is protected by the electric field relaxation region.
- the decrease in breakdown voltage and the difference from the design caused by the gate insulating film are eliminated.
- the semiconductor device described in the first embodiment when there is a contact failure in the p-type base contact region in one cell, the potential of the p-type base region cannot be fixed. Cause.
- the semiconductor device in this embodiment since the p-type base region of each cell is connected, contact can be made in another cell. In the example of FIG. 9, the p-type base regions of the first neighboring cells are connected. Therefore, the potential of the p-type base region can be fixed more easily than in the semiconductor device described in Embodiment 1, and a highly reliable device can be realized.
- a cross-shaped p-type field relaxation region is used. However, since the semiconductor device in this embodiment uses a V-shaped structure, the area occupied by the p-type field relaxation region is Less is. Further, by providing the p-type electric field relaxation region on the up-step side, the area of the p-type electric field relaxation region can be further reduced. Therefore, the influence on the channel region can be reduced, so that the on-resistance can be made smaller than that of the semiconductor device described in Embodiment 3.
- FIG. 10 is a circuit diagram of the power conversion device (inverter) of the present embodiment.
- the inverter according to the present embodiment includes a SiC-MOSFET 304 that is a switching element and a diode 305 in a power module 302.
- SiC-MOSFET 304 and diode 305 are connected in antiparallel between the power supply voltage (Vcc) and the input potential of load (for example, motor) 301 via the terminal (upper arm).
- the SiC-MOSFET element 304 and the diode 305 are also connected in antiparallel between the input potential of the load 301 and the ground potential (GND) (lower arm).
- the inverter can drive the load 301 by controlling the current flowing through the SiC-MOSFET 304 constituting the power module 302 by the control circuit 303.
- the function of the SiC-MOSFET 304 in the power module 302 will be described below.
- the control circuit 303 controls the SiC-MOSFET 304 to perform a pulse width modulation operation that dynamically changes the pulse width of the rectangular wave.
- the output rectangular wave is smoothed by passing through the inductor, and becomes a pseudo desired sine wave.
- the SiC-MOSFET 304 generates a rectangular wave for performing this pulse width modulation operation.
- the semiconductor device of the first embodiment or the second embodiment as the SiC-MOSFET 304, for example, since the on-resistance of the SiC-MOSFET 304 is small, the structure of a heat sink or the like for cooling is reduced, and the power module 302 can be reduced in size and weight, and thus the power converter can be reduced in size and weight. Moreover, since the reliability of the gate insulating film of the SiC-MOSFET 304 is high, the life of the power module 302 can be extended.
- the power conversion device of the present embodiment can be a three-phase motor system.
- the load 301 shown in FIG. 10 is a three-phase motor.
- the power conversion device including the semiconductor device described in the first embodiment or the second embodiment as a switching element, the load 301 is reduced in size. And high performance can be realized.
- FIG. 11 is a circuit diagram showing the power conversion device (inverter) of the present embodiment.
- the inverter includes a SiC-MOSFET 404 as a switching element in the power module 402.
- SiC-MOSFET 404 is connected between the power supply voltage (Vcc) and the input potential of load (eg, motor) 401 (upper arm) via a terminal.
- An SiC-MOSFET element 404 is also connected between the input potential of the load 401 and the ground potential (GND) (lower arm). That is, in the load 401, two SiC-MOSFETs 404 are provided for each single phase, and six switching elements 404 are provided for three phases.
- a control circuit 403 is connected to the gate electrode of each SiC-MOSFET 304 via terminals 410 and 411, and the SiC-MOSFET 404 is controlled by this control circuit 403. Therefore, in the inverter of the present embodiment, the load 401 can be driven by controlling the current flowing through the SiC-MOSFET 404 in the power module 402 by the control circuit 403.
- SiC-MOSFET 404 in the power module 402 will be described below.
- this embodiment also has a function of generating a rectangular wave for performing a pulse width modulation operation, as in the sixth embodiment.
- SiC-MOSFET 404 also plays a role of diode 305 of the sixth embodiment.
- the load 401 includes an inductance like a motor
- the SiC-MOSFET 404 is turned off, the energy stored in the inductance must be released (reflux current).
- the diode 305 plays this role.
- the SiC-MOSFET 404 plays a role of flowing a circulating current.
- the gate of the SiC-MOSFET 404 is turned on at the time of reflux, and the SiC-MOSFET 404 is turned on in reverse.
- the conduction loss at reflux is determined not by the characteristics of the diode but by the characteristics of the SiC-MOSFET 404. Further, when performing synchronous rectification drive, in order to prevent the upper and lower arms from being short-circuited, a non-operation time is required in which both the upper and lower SiC-MOSFETs are turned off. During this non-operation time, the built-in PN diode formed by the drift layer and the p-type body layer of the SiC-MOSFET 404 is driven. However, SiC has a shorter carrier travel distance than Si and a small loss during the non-operation time, which is equivalent to, for example, the case where the diode 305 of the sixth embodiment is a SiC Schottky barrier diode.
- the loss of the reflux at the time of the high performance of the SiC-MOSFET 404 is achieved. It can be made smaller, and higher performance can be achieved. Further, since the free wheel diode is not provided separately from the SiC-MOSFET 404, the power module 402 can be further reduced in size.
- the power conversion device of the present embodiment can be a three-phase motor system.
- the load 401 shown in FIG. 11 is a three-phase motor, and the power module 402 includes the semiconductor device described in the first to fifth embodiments, thereby realizing a reduction in size and performance of the three-phase motor system. be able to.
- the three-phase motor system described in the sixth embodiment or the seventh embodiment can be used for a vehicle such as a hybrid vehicle, an electric vehicle, and a fuel cell vehicle.
- a vehicle such as a hybrid vehicle, an electric vehicle, and a fuel cell vehicle.
- an automobile equipped with a three-phase motor system will be described with reference to FIGS.
- FIG. 12 is a schematic diagram showing the configuration of the electric vehicle of the present embodiment.
- the electric vehicle of the present embodiment drives a three-phase motor 503 that allows power to be input / output to / from a drive shaft 502 to which the drive wheels 501a and 501b are connected, and the three-phase motor 503.
- the electric vehicle of this embodiment includes a boost converter 508, a relay 509, and an electronic control unit 510.
- Boost converter 508 is connected to power line 506 to which inverter 504 is connected and to power line 507 to which battery 505 is connected.
- the three-phase motor 503 is a synchronous generator motor including a rotor embedded with permanent magnets and a stator wound with a three-phase coil.
- the inverter 504 the inverter described in Embodiment 6 or 7 described above can be used.
- FIG. 13 shows a circuit diagram of the boost converter 508 of this embodiment.
- boost converter 508 has a configuration in which a reactor 511 and a smoothing capacitor 112 are connected to inverter 513.
- the inverter 513 can have the same configuration as the inverter described in the seventh embodiment, and the element configuration in the inverter is the same.
- the switching element is the SiC-MOSFET 514 as in the seventh embodiment, and synchronous rectification driving is performed. In FIG. 12, only one phase of the inverter is shown, but it may be multiphase.
- the electronic control unit 510 shown in FIG. 12 includes a microprocessor, a storage device, and an input / output port.
- a signal from a sensor for detecting the rotor position of the three-phase motor 503, a charge / discharge value of the battery 505, and the like. Receive. Then, a signal for controlling inverter 504, boost converter 508, and relay 509 is output.
- the power conversion device of the sixth embodiment or the seventh embodiment can be used for the inverter 504 and the boost converter 508 which are power conversion devices.
- the three-phase motor system of the sixth embodiment or the seventh embodiment described above can be used for a three-phase motor system including the three-phase motor 503 and the inverter 504.
- the electric vehicle has been described.
- the above-described three-phase motor system can be similarly applied to a hybrid vehicle that also uses an engine and a fuel cell vehicle in which the battery 505 is a fuel cell stack. .
- the three-phase motor system of the sixth embodiment and the seventh embodiment can be used for a railway vehicle.
- a railway vehicle using a three-phase motor system will be described.
- FIG. 14 is a circuit diagram including a converter and an inverter of the railway vehicle according to the present embodiment.
- electric power is supplied to the railway vehicle from an overhead line OW (for example, 25 kV) via a pantograph PG.
- the voltage is stepped down to 1.5 kV via the transformer 609 and converted from alternating current to direct current by the converter 607.
- the inverter 602 converts the direct current into the alternating current through the capacitor 608, and the three-phase motor as the load 601 is driven.
- the element configuration in converter 607 may be a SiC-MOSFET and a diode used together as in the sixth embodiment, or a SiC-MOSFET alone as in the seventh embodiment.
- the switching element is synchronously rectified and driven as the SiC-MOSFET 604 as in the seventh embodiment.
- the control circuit described in the seventh embodiment is omitted.
- symbol RT indicates a track
- symbol WH indicates a wheel.
- the converter 607 can use the power conversion device of the sixth embodiment or the seventh embodiment. Further, the three-phase motor system according to the sixth embodiment or the seventh embodiment can be used for the three-phase motor system including the load 601, the inverter 602, and the control circuit. As a result, energy saving of the railway vehicle and reduction in floor and weight by downsizing the underfloor parts including the three-phase motor system can be achieved.
- the present invention is not limited to the above-described embodiment, and includes various modifications.
- a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment.
- source and drain of the transistor may be switched when a transistor with a different polarity is used or when the direction of current changes during circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.
- Electrode and “wiring” do not functionally limit these components.
- an “electrode” may be used as part of a “wiring” and vice versa.
- the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.
- the present invention is effective when applied to a semiconductor device using silicon carbide, a method for manufacturing the semiconductor device, and a power module, an inverter, an automobile, and a railway vehicle using the semiconductor device.
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Abstract
Description
図1Aは、本実施の形態に係わる炭化珪素半導体装置であるSiC-MOSFETのセル構造を示したイオン注入領域の平面(上面)図である。 [Semiconductor device]
FIG. 1A is a plan view (upper surface) of an ion implantation region showing a cell structure of a SiC-MOSFET which is a silicon carbide semiconductor device according to the present embodiment.
LE:基点となるベース領域の角部から電界緩和領域端部までの長さ
LJ1:基点となるベース領域の角部と第1近接となる他のセル角部の間の距離
LJ2:基点となるベース領域の角部と第2近接となる他のセル角部の間の距離
図1Bに示すように、LEがLJ2-LJ1よりも長ければ、電界緩和領域と隣接するベース領域角部間の距離がセル間の距離よりも短くなるため、効果的にゲート絶縁膜に掛かる電界を緩和することが出来る。なお、図1Bでは、便宜的にLJ1、LJ2は電界緩和領域の基点となる角部以外で示しているが、セルが周期的に配列されていることを前提とすれば、この部分で測定した距離でも同じ値となる(図3でも同様)。 L J2 -L J1 <L E <L J2 (1)
L E : Length from the corner of the base region serving as the base point to the end of the electric field relaxation region L J1 : The distance between the corner of the base region serving as the base point and the other cell corner serving as the first proximity L J2 : as shown in distance diagram 1B between the corner and the other cell corners to be the second proximity base region of the base point, the longer L E than L J2 -L J1, base adjacent to the electric-field relaxation region Since the distance between the corners of the region is shorter than the distance between the cells, the electric field applied to the gate insulating film can be effectively reduced. In FIG. 1B, for convenience, L J1 and L J2 are shown except for the corners that are the base points of the electric field relaxation region. However, if it is assumed that the cells are periodically arranged, The measured distance is the same value (the same applies to FIG. 3).
次に上記SiC-MOSFETの製造方法について説明する。 [Method for Manufacturing Semiconductor Device]
Next, a method for manufacturing the SiC-MOSFET will be described.
図3は、本実施の形態に係わる炭化珪素半導体装置であるSiC-MOSFETのセル構造を示したイオン注入領域の平面図である。 [Semiconductor device]
FIG. 3 is a plan view of an ion implantation region showing a cell structure of a SiC-MOSFET which is a silicon carbide semiconductor device according to the present embodiment.
ベース領域10において表層にそのベース領域10に囲まれるように形成されるn+型のソース領域20と、ベース領域10において表層にそのベース領域10に囲まれるように、且つソース領域20以外の領域に形成されるベース領域10よりも高不純物濃度のp+型のベースコンタクト領域11を有する。p+型のベースコンタクト領域11とは、ベース領域10に電気的な接続を取るための領域である。 n-type silicon
In the
LE:基点となるベース領域の角部から電界緩和領域端部までの長さ
LJ1:基点となるベース領域の角部と第1近接となる他のセル角部の間の長さ
[半導体装置の製造方法]
図4は実施の形態2における半導体装置の製造方法において、特に実施の形態1と異なる部分を示す図である。実施の形態2では、電界緩和領域60形成時の断面図が図4Aとなり、完成時の断面図が4Bとなる以外、図1~図2で示した実施の形態1記載の半導体装置と同様である。 L E <L J1 ... (2 )
L E : Length from the corner of the base region serving as the base point to the end of the electric field relaxation region L J1 : Length between the corner of the base region serving as the base point and another cell corner serving as the first proximity [Semiconductor Device manufacturing method]
FIG. 4 is a diagram showing a part different from the first embodiment in the method for manufacturing a semiconductor device in the second embodiment. The second embodiment is the same as the semiconductor device according to the first embodiment shown in FIGS. 1 and 2 except that the cross-sectional view when forming the electric
図5は、本実施の形態に係わる炭化珪素半導体装置であるSiC-MOSFETのセル構造を示したイオン注入領域の平面図である。 [Semiconductor device]
FIG. 5 is a plan view of an ion implantation region showing a cell structure of a SiC-MOSFET which is a silicon carbide semiconductor device according to the present embodiment.
N:ベース領域角部と第2近接となるセルのベース領域角部をそれぞれ線で結んだ交点とゲート絶縁膜に掛かる電界が強くなる点間の距離
LJ1:基点となるベース領域の角部と第1近接となる他のセル角部の間の距離(図1Bに示したものと同様である)
また、p型の電界緩和領域のドリフト領域に囲まれる領域の形状は、角が存在すると角部に電界集中が生じ耐圧が問題となるため、角の曲率を大きくすると良い。本実施例では、十字形状の交差部分の角部にアールをつける等するとよい。 0 <N <L J1 / 2 (3)
N: Distance between the intersection of the base region corner and the base region corner of the second adjacent cell with a line and the point where the electric field applied to the gate insulating film becomes strong L J1 : Corner of the base region serving as the base point And the distance between the other cell corners that are in the first proximity (similar to that shown in FIG. 1B)
In addition, the shape of the region surrounded by the drift region of the p-type electric field relaxation region is such that if there are corners, electric field concentration occurs at the corners, and the breakdown voltage becomes a problem. In the present embodiment, it is preferable to round the corners of the cross-shaped intersection.
図6は実施の形態3における半導体装置の製造方法において、実施の形態1と異なる部分を示す図である。実施の形態3では、電界緩和領域60形成時の断面図が図6Aとなり、完成時の断面図が6Bとなる以外、図1~図2で示した実施の形態1記載の半導体装置と同様である。 [Method for Manufacturing Semiconductor Device]
FIG. 6 is a diagram showing portions different from those in the first embodiment in the semiconductor device manufacturing method in the third embodiment. The third embodiment is the same as the semiconductor device according to the first embodiment shown in FIGS. 1 and 2 except that the cross-sectional view when the electric
図8は、本実施の形態に係わる炭化珪素半導体装置であるSiC-MOSFETのセル構造を示したイオン注入領域の平面図である。 [Semiconductor device]
FIG. 8 is a plan view of an ion implantation region showing a cell structure of a SiC-MOSFET which is a silicon carbide semiconductor device according to the present embodiment.
N:ベース領域角部と第2近接となるセルのベース領域角部をそれぞれ線で結んだ交点とゲート絶縁膜に掛かる電界が強くなる点間の距離
LJ1:基点となるベース領域の角部と第1近接となる他のセル角部の間の距離(図1Bに示したものと同様である)
実施の形態4における半導体装置は実施の形態3記載の半導体装置と同様に製造することができる。 0 <N <L J1 / 2 (4)
N: Distance between the intersection of the base region corner and the base region corner of the second adjacent cell with a line and the point where the electric field applied to the gate insulating film becomes strong L J1 : Corner of the base region serving as the base point And the distance between the other cell corners that are in the first proximity (similar to that shown in FIG. 1B)
The semiconductor device in the fourth embodiment can be manufactured in the same manner as the semiconductor device described in the third embodiment.
図9は、本実施の形態に係わる炭化珪素半導体装置であるSiC-MOSFETのセル構造を示したイオン注入領域の平面図である。 [Semiconductor device]
FIG. 9 is a plan view of an ion implantation region showing a cell structure of a SiC-MOSFET which is a silicon carbide semiconductor device according to the present embodiment.
N:ベース領域角部と第2近接となるセルのベース領域角部をそれぞれ線で結んだ交点とゲート絶縁膜に掛かる電界が強くなる点間の距離
LJ1:基点となるベース領域の角部と第1近接となる他のセル角部の間の長さ(図1Bに示したものと同様である)
上記第1近接となる角部2点は、アップステップ側の2点を選択する方が良い。ダウンステップ側の2点では、p型の電界緩和領域の占める面積が、アップステップ側の面積よりも大きくなり、チャネル領域への影響が増加し、オン抵抗が増加してしまうためである。 0 <N <L J1 / 2 (5)
N: Distance between the intersection of the base region corner and the base region corner of the second adjacent cell with a line and the point where the electric field applied to the gate insulating film becomes strong L J1 : Corner of the base region serving as the base point And other cell corners that are in the first proximity (similar to that shown in FIG. 1B)
It is better to select two points on the up-step side as the two corner portions that are the first proximity. This is because at the two points on the down step side, the area occupied by the p-type electric field relaxation region becomes larger than the area on the up step side, the influence on the channel region increases, and the on-resistance increases.
実施の形態5における半導体装置の製造方法は実施の形態1記載の半導体装置と同様である。 [Method for Manufacturing Semiconductor Device]
The manufacturing method of the semiconductor device in the fifth embodiment is the same as that of the semiconductor device described in the first embodiment.
2 ドリフト層
10 ベース領域
11 ベースコンタクト領域
20 ソース領域
21 ドレイン領域
30 マスク
32 ゲート絶縁膜
33 層間膜
40 ゲート材料膜
41 ソースベースコンタクト共通電極
42 ドレインコンタクト電極
51 ソースベース共通コンタクト
52 ドレインコンタクト
301 負荷
302 パワーモジュール
303 制御回路
304 SiC-MOSFET
305 ダイオード
306~312 端子
401 負荷
402 パワーモジュール
403 制御回路
404 SiC-MOSFET
405~411 端子
501a 駆動輪
501b 駆動輪
502 駆動軸
503 3相モータ
504 インバータ
505 バッテリ
506 電力ライン
507 電力ライン
508 昇圧コンバータ
509 リレー
510 電子制御ユニット
511 リアクトル
512 平滑用コンデンサ
513 インバータ
514 SiC-MOSFET
601 負荷
602 インバータ
607 コンバータ
608 キャパシタ
609 トランス
OW 架線
PG パンタグラフ
RT 線路
WH 車輪 DESCRIPTION OF
305 Diodes 306 to 312
405 to 411
601
Claims (15)
- 第1導電型の半導体基板と、
前記半導体基板上に形成された第1導電型のドリフト領域と、
前記ドリフト領域の表層に間隔を開けて周期的に形成された複数の単位セルを備え、
前記単位セルの其々は、
第2導電型のベース領域と、
前記ベース領域において当該ベース領域に囲まれるように形成される第1導電型のソース領域と、
前記ベース領域に接して形成される前記ベース領域よりも高不純物濃度の第2導電型のベースコンタクト領域と、を有し、
前記単位セルの前記ベース領域から、前記他の単位セルのベース領域と接続しない範囲で伸展する第2導電型の電界緩和領域と、
前記ソース領域、及び前記ベースコンタクト領域上に、それぞれの領域の少なくとも一部に被る様に形成された第一の外部接続電極と、
前記ソース領域、前記ベース領域、前記ドリフト領域、及び前記電界緩和領域上に、それぞれの領域の少なくとも一部に被る様に形成されたゲート絶縁膜と、
を備えることを特徴とする半導体装置。 A first conductivity type semiconductor substrate;
A drift region of a first conductivity type formed on the semiconductor substrate;
A plurality of unit cells periodically formed at intervals in the surface layer of the drift region,
Each of the unit cells is
A base region of a second conductivity type;
A source region of a first conductivity type formed so as to be surrounded by the base region in the base region;
A second contact type base contact region having a higher impurity concentration than the base region formed in contact with the base region,
An electric field relaxation region of a second conductivity type extending from the base region of the unit cell in a range not connected to the base region of the other unit cell;
A first external connection electrode formed on the source region and the base contact region so as to cover at least a part of each region;
A gate insulating film formed on the source region, the base region, the drift region, and the electric field relaxation region so as to cover at least a part of each region;
A semiconductor device comprising: - 相互に最も近接した前記単位セルの組でセルのグループを定義した場合、当該単位セルのグループの幾何学的重心位置よりオフ方向側にシフトした点をカバーするように、前記第2導電型の電界緩和領域が伸展していることを特徴とする請求項1記載の半導体装置。 When a group of cells is defined by a set of the unit cells closest to each other, the second conductivity type of the second conductivity type is covered so as to cover a point shifted to the off direction side from the geometric center of gravity of the unit cell group. 2. The semiconductor device according to claim 1, wherein the electric field relaxation region extends.
- 前記単位セルの形状を前記ベース領域の形状で定義した場合、
前記単位セルの其々は前記ドリフト領域の表層直上から見た形状が多角形であり、
当該単位セルの角部のうち、オフ方向側を向いていない角部の少なくとも一つから、前記シフトした位置に向けて、前記第2導電型の電界緩和領域が伸展していることを特徴とする請求項2記載の半導体装置。 When the shape of the unit cell is defined by the shape of the base region,
Each of the unit cells has a polygonal shape as viewed from directly above the surface layer of the drift region,
The electric field relaxation region of the second conductivity type extends from at least one of the corner portions of the unit cell not facing the off direction side toward the shifted position. The semiconductor device according to claim 2. - 前記単位セルの形状は、矩形、正方形、あるいは六角形であり、
前記単位セルは矩形格子、正方格子、あるいは六角格子状に配列されることを特徴とする請求項3記載の半導体装置。 The unit cell has a rectangular, square, or hexagonal shape,
4. The semiconductor device according to claim 3, wherein the unit cells are arranged in a rectangular lattice, a square lattice, or a hexagonal lattice. - 前記第2導電型の電界緩和領域の前記ドリフト領域の表層直上から見た形状が、曲線で構成されるか、あるいは、2つ以上の角で構成され一つの角度が90度以上となる事を特徴とする請求項1記載の半導体装置。 The shape of the electric field relaxation region of the second conductivity type viewed from directly above the surface layer of the drift region is configured with a curve, or configured with two or more corners, and one angle is 90 degrees or more. The semiconductor device according to claim 1.
- 前記第2導電型の電界緩和領域の不純物濃度が、5×1018~1×1021cm-3を満たす範囲であることを特徴とする請求項1記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the impurity concentration of the second conductivity type electric field relaxation region is in a range satisfying 5 × 10 18 to 1 × 10 21 cm −3 .
- 前記単位セルの形状が矩形あるいは正方形であり、
前記単位セルは矩形格子あるいは正方格子状に配列され、
前記第2導電型の電界緩和領域は、
前記単位セルの前記ベース領域の複数ある角部の少なくとも一つから、第2近接となる他の単位セルのベース領域の複数ある角部のうち最も近い角部方向に、当該他の単位セルのベース領域と接続しない範囲で伸展し、
当該第2導電型の電界緩和領域の伸展長さが、以下の不等式を満足する、請求項2記載の半導体装置。
LJ2-LJ1<LE<LJ2
LE:基点となる前記ベース領域の角部から前記電界緩和領域端部までの長さ
LJ1:基点となる前記ベース領域の角部と第1近接となる他の前記単位セルのベース領域角部の間の距離
LJ2:基点となる前記ベース領域の角部と第2近接となる他の前記単位セルのベース領域角部の間の距離 The unit cell has a rectangular or square shape;
The unit cells are arranged in a rectangular lattice or a square lattice,
The electric field relaxation region of the second conductivity type is
From at least one of the plurality of corners of the base region of the unit cell to the closest corner of the plurality of corners of the base region of another unit cell that is in the second proximity, the other unit cell Extends within the range not connected to the base area,
The semiconductor device according to claim 2, wherein the extension length of the electric field relaxation region of the second conductivity type satisfies the following inequality.
L J2 -L J1 <L E <L J2
L E : Length from the corner of the base region serving as a base point to the end of the electric field relaxation region L J1 : The base region angle of another unit cell that is close to the corner of the base region serving as a base point L J2 : Distance between the corners of the base region serving as the base point and the base region corners of the other unit cells serving as the second proximity - 前記単位セルの形状が六角形であり、
前記単位セルは六角格子状に配列され、
前記第2導電型の電界緩和領域は、
前記単位セルの前記ベース領域の複数ある角部の少なくとも一つから、第1近接となる他の2つの単位セルのベース領域の角部を直線で結んだ中点の方向に他のセル角部と接続しない範囲で伸展し、
当該第2導電型の電界緩和領域の伸展長さが、以下の不等式を満足する、請求項2記載の半導体装置。
LE<LJ1
LE:基点となるベース領域の角部から前記電界緩和領域端部までの長さ
LJ1:基点となるベース領域の角部と第1近接となる他のセル角部の間の距離 The unit cell has a hexagonal shape;
The unit cells are arranged in a hexagonal lattice,
The electric field relaxation region of the second conductivity type is
Other cell corners in the direction of the midpoint connecting the corners of the base regions of the other two unit cells in the first proximity with a straight line from at least one of the plurality of corners of the base region of the unit cell Extend within the range not connected to
The semiconductor device according to claim 2, wherein the extension length of the electric field relaxation region of the second conductivity type satisfies the following inequality.
L E <L J1
L E : Length from the corner of the base region serving as the base point to the end of the electric field relaxation region L J1 : The distance between the corner of the base region serving as the base point and the other cell corner serving as the first proximity - 半導体装置をスイッチング素子として用いた電力変換装置であって、
前記半導体装置は、
第1導電型の半導体基板と、
前記半導体基板上に形成された第1導電型のドリフト領域と、
前記ドリフト領域の表層に間隔を開けて周期的に形成された複数の単位セルを備え、
前記単位セルの其々は、
第2導電型のベース領域と、
前記ベース領域において当該ベース領域に囲まれるように形成される第1導電型のソース領域と、
前記ベース領域に接して形成される前記ベース領域よりも高不純物濃度の第2導電型のベースコンタクト領域と、を有し、
前記単位セルの前記ベース領域から、前記他の単位セルのベース領域と接続しない範囲で伸展する第2導電型の電界緩和領域と、
前記ソース領域、及び前記ベースコンタクト領域上に、それぞれの領域と少なくとも一部に被る様に形成された第一の外部接続電極と、
前記ソース領域、前記ベース領域、前記ドリフト領域、及び前記電界緩和領域上に、それぞれの領域と少なくとも一部に被る様に形成されたゲート絶縁膜と、
を備えることを特徴とする電力変換装置。 A power conversion device using a semiconductor device as a switching element,
The semiconductor device includes:
A first conductivity type semiconductor substrate;
A drift region of a first conductivity type formed on the semiconductor substrate;
A plurality of unit cells periodically formed at intervals in the surface layer of the drift region,
Each of the unit cells is
A base region of a second conductivity type;
A source region of a first conductivity type formed so as to be surrounded by the base region in the base region;
A second contact type base contact region having a higher impurity concentration than the base region formed in contact with the base region,
An electric field relaxation region of a second conductivity type extending from the base region of the unit cell in a range not connected to the base region of the other unit cell;
A first external connection electrode formed on the source region and the base contact region so as to cover at least a part of each region;
A gate insulating film formed on the source region, the base region, the drift region, and the electric field relaxation region so as to cover at least a part of each region;
A power conversion device comprising: - 第1導電型の半導体基板と、
前記半導体基板上に形成された第1導電型のドリフト領域と、
前記ドリフト領域の表層に間隔を開けて周期的に形成された複数の単位セルを備え、
前記単位セルの其々は、
第2導電型のベース領域と、
前記ベース領域において当該ベース領域に囲まれるように形成される第1導電型のソース領域と、
前記ベース領域に接して形成される前記ベース領域よりも高不純物濃度の第2導電型のベースコンタクト領域と、を有し、
前記単位セルの前記ベース領域から伸展する第2導電型の電界緩和領域と、
前記ソース領域、及び前記ベースコンタクト領域上に、それぞれの領域と少なくとも一部に被る様に形成された第一の外部接続電極と、
前記ソース領域、前記ベース領域、前記ドリフト領域、及び前記電界緩和領域上に、それぞれの領域と少なくとも一部に被る様に形成されたゲート絶縁膜とを備え、
相互に最も近接した前記単位セルの組でセルのグループを定義した場合、当該単位セルのグループの幾何学的重心位置よりオフ方向側にシフトした点に向けて、前記第2導電型の電界緩和領域が伸展していることを特徴とする半導体装置。 A first conductivity type semiconductor substrate;
A drift region of a first conductivity type formed on the semiconductor substrate;
A plurality of unit cells periodically formed at intervals in the surface layer of the drift region,
Each of the unit cells is
A base region of a second conductivity type;
A source region of a first conductivity type formed so as to be surrounded by the base region in the base region;
A second contact type base contact region having a higher impurity concentration than the base region formed in contact with the base region,
A second conductivity type electric field relaxation region extending from the base region of the unit cell;
A first external connection electrode formed on the source region and the base contact region so as to cover at least a part of each region;
On the source region, the base region, the drift region, and the electric field relaxation region, each region and a gate insulating film formed to cover at least part of the region,
When a cell group is defined by the set of unit cells closest to each other, the electric field relaxation of the second conductivity type toward a point shifted to the off-direction side from the geometric center of gravity of the unit cell group. A semiconductor device characterized in that a region is extended. - 前記単位セルの形状が矩形あるいは正方形であり、
前記単位セルは矩形格子あるいは正方格子状に配列され、
前記第2導電型の電界緩和領域は、
前記単位セルの前記ベース領域の角部の一つから、第2近接となる他の単位セルの前記ベース領域の直近の角部方向に伸展し、
当該電界緩和領域は、前記ベース領域の角部の一つと、前記第2近接となる他の単位セルのベース領域の直近の角部を結ぶ直線から、オフ方向側にシフトした位置に配置されていることを特徴とする請求項10記載の半導体装置。 The unit cell has a rectangular or square shape;
The unit cells are arranged in a rectangular lattice or a square lattice,
The electric field relaxation region of the second conductivity type is
Extending from one of the corners of the base region of the unit cell in the direction of the nearest corner of the base region of the other unit cell in the second proximity,
The electric field relaxation region is arranged at a position shifted to the off-direction side from a straight line connecting one corner of the base region and the nearest corner of the base region of another unit cell in the second proximity. The semiconductor device according to claim 10. - X方向をオフ方向とし、Y方向をオフ方向と垂直とし、4つの前記単位セルに囲まれた領域の幾何学的重心を原点としたとき、
前記囲まれた領域における前記第2導電型の電界緩和領域は、
前記4つの単位セルのうち第2近接の関係にある第1および第2の単位セルのベース領域の対向する角部を接続するとともに、第2近接の関係にある第3および第4の単位セルのベース領域の対向する角部を接続する、十字形状のp型の電界緩和領域であり、
当該十字形状の電界緩和領域の幾何学的重心位置が(N,0)となり、Nが以下の不等式を満たす事を特徴とする請求項11記載の半導体装置。
0<N<LJ1/2
N:ベース領域角部と第2近接となるセルのベース領域角部をそれぞれ線で結んだ交点とゲート絶縁膜に掛かる電界が強くなる点間の距離
LJ1:基点となるベース領域の角部と第1近接となる他のセル角部の間の距離 When the X direction is the off direction, the Y direction is perpendicular to the off direction, and the geometric center of gravity of the region surrounded by the four unit cells is the origin,
The electric field relaxation region of the second conductivity type in the enclosed region is
Among the four unit cells, third and fourth unit cells that connect opposite corners of the base regions of the first and second unit cells that are in a second proximity relationship and that are in a second proximity relationship. A cross-shaped p-type electric field relaxation region connecting opposite corners of the base region of
12. The semiconductor device according to claim 11, wherein the geometric gravity center position of the cross-shaped electric field relaxation region is (N, 0), and N satisfies the following inequality.
0 <N <L J1 / 2
N: Distance between the intersection of the base region corner and the base region corner of the second adjacent cell with a line and the point where the electric field applied to the gate insulating film becomes strong L J1 : Corner of the base region serving as the base point Between the other cell corner and the first proximity - X方向をオフ方向とし、Y方向をオフ方向と垂直とし、4つの単位セルに囲まれた領域の重心を原点としたとき、
前記囲まれた領域における前記第2導電型の電界緩和領域は、
前記4つの単位セルのうち第2近接の関係にある第1および第2の単位セルのベース領域の対向する角部を接続するとともに、第2近接の関係にある第3および第4の単位セルのベース領域の対向する角部を接続しない、直線形状のp型の電界緩和領域であり、
当該直線形状のp型の電界緩和領域の重心位置が(N,0)となり、Nが以下の不等式を満たす事を特徴とする請求項11記載の半導体装置。
0<N<LJ1/2
N:ベース領域角部と第2近接となるセルのベース領域角部をそれぞれ線で結んだ交点とゲート絶縁膜に掛かる電界が強くなる点間の距離
LJ1:基点となるベース領域の角部と第1近接となる他のセル角部の間の距離 When the X direction is the off direction, the Y direction is perpendicular to the off direction, and the center of gravity of the area surrounded by the four unit cells is the origin,
The electric field relaxation region of the second conductivity type in the enclosed region is
Among the four unit cells, third and fourth unit cells that connect opposite corners of the base regions of the first and second unit cells that are in a second proximity relationship and that are in a second proximity relationship. A linear p-type electric field relaxation region that does not connect opposite corners of the base region of
12. The semiconductor device according to claim 11, wherein the gravity center position of the linear p-type electric field relaxation region is (N, 0), and N satisfies the following inequality.
0 <N <L J1 / 2
N: Distance between the intersection of the base region corner and the base region corner of the second adjacent cell with a line and the point where the electric field applied to the gate insulating film becomes strong L J1 : Corner of the base region serving as the base point Between the other cell corner and the first proximity - X方向をオフ方向とし、Y方向をオフ方向と垂直とし、4つの単位セルに囲まれた領域の重心を原点としたとき、
前記囲まれた領域における前記第2導電型の電界緩和領域は、
前記4つの単位セルのうち第1近接の関係にある第1および第2の単位セルのベース領域の対向する角部を接続するとともに、第1近接の関係にある第3および第4の単位セルのベース領域の対向する角部を接続しない、V字形状のp型の電界緩和領域であり、
当該V字形状の電界緩和領域の屈曲部が座標(N,0)を覆い、Nが以下の不等式を満たす事を特徴とする請求項11記載の炭化珪素半導体装置。
0<N<LJ1/2
N:ベース領域角部と第2近接となるセルのベース領域角部をそれぞれ線で結んだ交点とゲート絶縁膜に掛かる電界が強くなる点間の距離
LJ1:基点となるベース領域の角部と第1近接となる他のセル角部の間の距離 When the X direction is the off direction, the Y direction is perpendicular to the off direction, and the center of gravity of the area surrounded by the four unit cells is the origin,
The electric field relaxation region of the second conductivity type in the enclosed region is
Among the four unit cells, the first and second unit cells in the first proximity relationship connect the opposite corners of the base region, and the third and fourth unit cells in the first proximity relationship A V-shaped p-type field relaxation region that does not connect opposite corners of the base region of
The silicon carbide semiconductor device according to claim 11, wherein the bent portion of the V-shaped electric field relaxation region covers coordinates (N, 0), and N satisfies the following inequality.
0 <N <L J1 / 2
N: Distance between the intersection of the base region corner and the base region corner of the second adjacent cell with a line and the point where the electric field applied to the gate insulating film becomes strong L J1 : Corner of the base region serving as the base point Between the other cell corner and the first proximity - 前記第2導電型の電界緩和領域の不純物濃度が、前記ベース領域または前記ベースコンタクト領域と、共通マスクを用いて形成できる濃度であることを特徴とする請求項10記載の半導体装置。 11. The semiconductor device according to claim 10, wherein the impurity concentration of the electric field relaxation region of the second conductivity type is a concentration that can be formed using the base region or the base contact region and a common mask.
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JP2019517149A (en) * | 2016-05-23 | 2019-06-20 | ゼネラル・エレクトリック・カンパニイ | Electric field shielding in silicon carbide metal oxide semiconductor (MOS) device cells using channel region extensions |
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JP2019517149A (en) * | 2016-05-23 | 2019-06-20 | ゼネラル・エレクトリック・カンパニイ | Electric field shielding in silicon carbide metal oxide semiconductor (MOS) device cells using channel region extensions |
JP7102048B2 (en) | 2016-05-23 | 2022-07-19 | ゼネラル・エレクトリック・カンパニイ | Electric Field Shield in Silicon Carbide Metal Oxide Semiconductor (MOS) Device Cell with Channel Region Expansion |
JP7466938B2 (en) | 2016-05-23 | 2024-04-15 | ゼネラル・エレクトリック・カンパニイ | Electric field shielding in silicon carbide metal oxide semiconductor (MOS) device cells using body region extensions - Patents.com |
JP2018064047A (en) * | 2016-10-13 | 2018-04-19 | 富士電機株式会社 | Semiconductor device and semiconductor device manufacturing method |
CN110431677A (en) * | 2017-02-14 | 2019-11-08 | 加州理工学院 | High temperature superconducting materia |
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