JPWO2016084131A1 - Semiconductor device and power conversion device - Google Patents

Abstract

Provided is a semiconductor device having a high breakdown voltage in a gate insulating film. A semiconductor device comprising: a first conductivity type semiconductor substrate; a first conductivity type drift region formed on the semiconductor substrate; and a plurality of unit cells periodically formed at intervals in a surface layer of the drift region. . Each of the unit cells of the semiconductor device is formed in contact with the base region, the base region of the second conductivity type, the source region of the first conductivity type formed in the base region so as to be surrounded by the base region. And a second contact base contact region having a higher impurity concentration than the base region. And it has the electric field relaxation area | region of the 2nd conductivity type extended in the range which is not connected with the base area | region of another unit cell from the base area | region of a unit cell.

Description

  The present invention relates to a semiconductor device, a power conversion device using the semiconductor device, and an application thereof.

  Silicon carbide (SiC) is characterized by a large band gap and a dielectric breakdown electric field that is about one digit larger than silicon. For this reason, it is regarded as a promising next-generation power device, and various devices such as diodes and transistors have been studied. In particular, SiC-MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are elements that can theoretically achieve high withstand voltage, low loss, and high-speed switching. ) Is expected to significantly reduce power loss, and research and development of SiC-MOSFETs are actively conducted.

  SiC has a wider band gap than Si and has a high dielectric breakdown strength. However, in SiC-MOSFETs and SiC-IGBTs, the electric field applied to the gate insulating film becomes a problem. For this reason, a structure with good symmetry is required so that the electric field applied to the gate insulating film is not biased. In SiC-DMOSFET (Double-Diffused MOSTET), it is required to increase the channel width (W) for the purpose of improving current density. As a structure having a long channel width (W) and good symmetry, a structure in which p-type base regions are arranged in a rectangular or hexagonal shape is well known. Hereinafter, a structure in which rectangular p-type base regions are arranged in a square lattice pattern is referred to as a BOX structure.

  FIG. 15 is a top view showing a cell pattern arrangement of a conventional general SiC-DMOSFET in a BOX structure. The positional relationship among the p-type base region 10, the source region 20, and the base contact region 11 is shown. Here, the (unit) cell means a unit including at least the base region 10 and the source region 20. These cells have the same shape in design, and are regularly arranged at regular intervals. However, there may be a slight difference in shape due to process restrictions.

  16 is a cross-sectional view taken along the line A-A ′ of FIG. In FIG. 16, 1 is a substrate, 2 is a drift layer, 10 is a base region, 11 is a base contact region, 20 is a source region, 21 is a drain region, 32 is a gate insulating film, 33 is an interlayer film, and 40 is a gate material film. , 41 is a source-base contact common electrode, 42 is a drain contact electrode, 51 is a source-base common contact, and 52 is a drain contact.

  In the SiC-DMOSFET as shown in FIG. 16, an n − type drift layer 2 and a p type base region 10 are formed on an n + type silicon carbide substrate 1 by epitaxial growth or ion implantation, and an n + type source region 20 and p + A type base contact region 11 and an n + type drain region 21 are formed by ion implantation. A gate insulating film 32 is formed on such a silicon carbide substrate 1 using a thermal oxidation method or a deposited oxide film, and a gate electrode is formed via the gate insulating film 32. Further, a source-base common contact electrode 41, a drain contact electrode 42, an interlayer film 33, and a surface protective film are formed so as to be in contact with the n + -type source region 20 and the p + -type base contact region 11, thereby forming a SiC − A DMOSFET is completed.

  FIG. 17 is a plan view of a conventional vertical silicon carbide semiconductor device, and the position of electric field concentration is indicated by a dotted circle. When the DMOSFET is off, that is, when a voltage lower than the on-voltage is applied to the gate electrode and a voltage is applied to the drain contact electrode, the BOX structure is surrounded by cells as shown in FIG. It is known that the electric field concentrates at the center of the JFET (junction field effect transistor) region, and the electric field strength applied to the gate insulating film increases. For the purpose of relaxing the electric field applied to the gate insulating film, there is a technique of adding a p-type or p + -type electric field relaxation region to the electric field concentration region as shown in Patent Document 1 or Patent Document 2.

JP2009-094314 JP2013-247252A

  In order to use an SiC crystal for an electronic device, an epitaxial growth technique of an SiC single crystal that does not include different polytypes is important. The step flow growth method is often used as a high quality epitaxial growth technique. Step flow growth is a method of performing epitaxial growth on a surface into which an offset angle (hereinafter referred to as an off angle) of, for example, several degrees (for example, 4 degrees or 8 degrees) is introduced from the {0001} plane. For example, in the configuration of FIG. 16, an off angle is introduced into the surface of the substrate 1 and epitaxial growth is performed thereon.

  FIG. 18 is a cross-sectional view showing the surface shape of an epitaxial wafer using step flow growth. As shown in FIGS. 18A and 18B, an epitaxial wafer using this step flow growth has an off-angle in principle, and the {0001} plane is asymmetric with respect to the wafer surface 1800 by the off-angle. Crystal. Wafer surface (principal surface) 1800 can be considered geometrically as a plane connecting the lowest point or the highest point of the substrate surface. Note that FIG. 18 is a principle diagram, and in an actual product, surfaces and corners may not form strict planes and corners. In practice, it can be considered that the fine irregularities on the wafer surface shown in FIG. 18 are averaged or ignored. For convenience, when a wafer is grasped as a plate (disk) as shown in FIG.

  In this specification, on the wafer surface, a surface having a relatively large area ({0001} surface in FIG. 18) is regarded as a step surface of the staircase, and the upper step side of the staircase is the upstep side and the lower step side is the downstep side. Call it. That is, the direction in which the surface having a relatively large area faces is the upstep side. Furthermore, the direction from the up-step side to the down-step side is defined as the off direction.

  FIG. 19 shows the result of a computer experiment of implanting aluminum ions (Al +) into an epitaxial layer on a 4H—SiC substrate by a two-dimensional Monte Carlo simulation conducted by the inventors. As shown in the figure, the aluminum ions are incident on the wafer surface perpendicularly. When calculating the ion implantation profile in consideration of the asymmetry of the crystal due to the off angle, it was found that the profile on the down-step side spreads more in the crystal than the up-step side as the ion implantation becomes deeper. . This is because the surface of the epitaxial layer has an off-angle, so that the influence of scattering that Al + ions receive during implantation differs between the [11-20] direction and the [−1-120] direction. Due to the difference in the distribution of Al distribution, the curvature of the Al concentration distribution below the mask edge is larger in the [11-20] direction than in the [-1-120] direction, and the Al after implantation is increased. Wide diffusion range. This indicates that the electric field relaxation effect of the electric field applied to the gate oxide film is greater on the down step side than on the up step side of the cell.

  FIG. 20 is a plan view showing the electric field concentration position of the vertical silicon carbide semiconductor device examined based on the above examination. For example, in the BOX structure shown in FIG. 20, the electric field applied to the gate oxide film shifts from the center of the JFET region surrounded by the cells in the down-step direction. By shifting the point where the electric field applied to the gate oxide film becomes stronger in the down-step direction, the breakdown voltage in the gate insulating film is reduced in the conventional structure, and the design is different.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device, particularly a SiC-DMOSFET and a SiC-IGBT, in consideration of the breakdown voltage characteristics.

  The present application includes a plurality of means for solving the above-mentioned problems. Examples thereof are given below.

  One aspect of the present invention is a semiconductor substrate of a first conductivity type, a drift region of the first conductivity type formed on the semiconductor substrate, and a plurality of periodically formed with a gap in the surface layer of the drift region. It is a semiconductor device provided with a unit cell. Each of the unit cells of the semiconductor device is formed in contact with the base region, the base region of the second conductivity type, the source region of the first conductivity type formed in the base region so as to be surrounded by the base region. And a second contact base contact region having a higher impurity concentration than the base region. And it has the 2nd conductivity type electric field relaxation area | region extended in the range which is not connected with the base area | region of another unit cell from the base area | region of a unit cell. With such a configuration, the area occupied by the electric field relaxation region can be reduced, and the influence on the channel region can be reduced. Further, on the source region and the base contact region, on the first external connection electrode formed so as to cover at least a part of each region, and on the source region, the base region, the drift region, and the electric field relaxation region, It is desirable to include a gate insulating film formed so as to cover at least a part of each region.

  For convenience, the shape of the unit cell can be defined by the shape of the base region, and can be expressed as a rectangle, a square, or a hexagon as viewed from directly above the surface layer of the drift region.

  As a preferred configuration, when a group of cells is defined by a set of unit cells closest to each other, the second cell is covered so as to cover a point shifted from the geometric center of gravity of the unit cell group to the off-direction side. The conductivity type electric field relaxation region extends. By forming the electric field relaxation region at a necessary portion, the influence on the channel region can be further reduced. The set of unit cells closest to each other is composed of, for example, four unit cells whose sides are in contact with each other when the unit cells are square and arranged in a square lattice pattern. When the unit cell is a hexagonal hexagonal lattice array, the unit cell is composed of three unit cells that are in contact with each other.

  Further, as a preferred embodiment, if the electric field relaxation region of the second conductivity type is extended from at least one of the corner portions of the unit cell not facing the off direction side toward the shifted position, Furthermore, since the electric field relaxation region can be reduced, the influence on the channel region can be further reduced.

  The other side surface of the semiconductor device of the present invention is formed periodically with a gap between the first conductivity type semiconductor substrate, the first conductivity type drift region formed on the semiconductor substrate, and the surface layer of the drift region. A plurality of unit cells. Each of the unit cells includes a second conductivity type base region, a first conductivity type source region formed to be surrounded by the base region in the base region, and the base region formed in contact with the base region. And a base contact region of a second conductivity type having a higher impurity concentration. A first external connection electrode formed on the second conductivity type electric field relaxation region extending from the base region of the unit cell, the source region, and the base contact region so as to cover at least a part of each region. And a gate insulating film formed on the source region, the base region, the drift region, and the electric field relaxation region so as to cover at least a part of each region. Here, when a group of cells is defined by a set of unit cells closest to each other, the electric field of the second conductivity type is directed toward a point shifted to the off direction side from the geometric center of gravity of the group of unit cells. Mitigation area is expanding. In this manner, by forming the electric field relaxation region in a necessary portion, the influence on the channel region can be further reduced.

  In addition, the second conductivity type electric field relaxation region can be extended from the base region of the unit cell in a range not connected to the base region of another unit cell. Thereby, the area of the electric field relaxation region can be further reduced, and the influence on the channel region can be reduced.

  Further, the second conductivity type electric field relaxation region can be extended from the base region of the unit cell so as to be connected to the base region of another unit cell. In this way, the potential of the base region can be easily fixed, and a highly reliable device can be realized.

  In the above semiconductor device, in terms of process, if the impurity concentration of the electric field relaxation region of the second conductivity type is in a range that can be formed using the base region or the base contact region and the common mask, the manufacturing efficiency is good, and in a preferable mode. is there.

  Another aspect of the present invention is a power conversion device using the semiconductor device as a switching element. By configuring an inverter or a converter using the semiconductor device as an element, it is possible to improve the performance of the power conversion device. Furthermore, as another aspect of the present invention, a three-phase motor system using the power converter can achieve high performance by the switching element. Furthermore, another aspect of the present invention is a transportation device such as an automobile or a railway vehicle equipped with the motor system.

  According to the semiconductor device of the present invention, it is possible to provide a semiconductor device having an excellent breakdown voltage in the gate insulating film.

  Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

1 is a plan view of a silicon carbide semiconductor device in a first embodiment. 1 is a plan view of a silicon carbide semiconductor device in a first embodiment. 1 is a cross sectional view of a silicon carbide semiconductor device in a first embodiment. 1 is a cross sectional view of a silicon carbide semiconductor device in a first embodiment. 1 is a cross sectional view of a silicon carbide semiconductor device in a first embodiment. 1 is a cross sectional view of a silicon carbide semiconductor device in a first embodiment. 1 is a cross sectional view of a silicon carbide semiconductor device in a first embodiment. 1 is a cross sectional view of a silicon carbide semiconductor device in a first embodiment. 1 is a cross sectional view of a silicon carbide semiconductor device in a first embodiment. 1 is a cross sectional view of a silicon carbide semiconductor device in a first embodiment. 1 is a cross sectional view of a silicon carbide semiconductor device in a first embodiment. 1 is a cross sectional view of a silicon carbide semiconductor device in a first embodiment. 1 is a cross sectional view of a silicon carbide semiconductor device in a first embodiment. FIG. 6 is a plan view of a silicon carbide semiconductor device in a second embodiment. FIG. 6 is a cross sectional view of a silicon carbide semiconductor device in a second embodiment. FIG. 6 is a cross sectional view of a silicon carbide semiconductor device in a second embodiment. FIG. 7 is a plan view of a silicon carbide semiconductor device in a third embodiment. FIG. 6 is a cross sectional view of a silicon carbide semiconductor device in a third embodiment. FIG. 6 is a cross sectional view of a silicon carbide semiconductor device in a third embodiment. FIG. 6 is a cross sectional view of a silicon carbide semiconductor device in the third and fourth embodiments. FIG. 7 is a plan view of a silicon carbide semiconductor device in a fourth embodiment. FIG. 10 is a plan view of a silicon carbide semiconductor device in a fifth embodiment. It is a circuit diagram of the power converter device (inverter) of the Example of this invention. It is a circuit diagram of the power converter device (inverter) of the Example of this invention. It is a block diagram of the electric vehicle of the Example of this invention. 1 is a circuit diagram of a boost converter according to an embodiment of the present invention. 1 is a configuration diagram of a railway vehicle according to an embodiment of the present invention. It is a top view of the conventional vertical silicon carbide semiconductor device. It is sectional drawing of the conventional vertical silicon carbide semiconductor device. It is a top view of the conventional vertical silicon carbide semiconductor device. It is a schematic cross section which shows the 4H-SiC epitaxial wafer surface shape using step flow growth. It is a schematic cross section which shows the 4H-SiC epitaxial wafer surface shape using step flow growth. It is sectional drawing which shows the result of the computer experiment of the injection | pouring to the epitaxial layer on a 4H-SiC board | substrate of aluminum ion. It is a top view which shows the electric field concentration position of the vertical silicon carbide semiconductor device examined by this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. In particular, for functions corresponding to different embodiments, the same reference numerals are given even if there are differences in shape, impurity concentration, crystallinity, and the like. Further, for simplification of the description, the drawing shows only the configuration of the main part, and the scale and dimensions of the drawing are not matched with the actual ones. For this reason, the present invention is not necessarily limited to the position, size, shape, range, and the like disclosed in the drawings and the like.

  The present invention is not construed as being limited to the description of the embodiments below. Those skilled in the art will readily understand that the specific configuration can be changed without departing from the spirit or the spirit of the present invention.

  In the present specification and the like, notations such as “first”, “second”, and “third” are attached to identify the components, and do not necessarily limit the number or order. In addition, a number for identifying a component is used for each context, and a number used in one context does not necessarily indicate the same configuration in another context. Further, it does not preclude that a component identified by a certain number also functions as a component identified by another number.

  In the plan views showing the semiconductor devices of the third to fifth embodiments, the description of the electric field relaxation region connected to the outer cell than the outermost cell is omitted. In the first to fifth embodiments, a silicon carbide semiconductor device having a so-called MOS (Metal-Oxide-Semiconductor) structure will be described. Each plan view shows only the ion implantation region for simplicity, but in an actual device structure, a source contact, drain contact, gate insulating film, gate electrode, source base contact common electrode, drain contact electrode, surface protective film, etc. Needless to say, it exists. In the following, the conductivity type of implanted ions is referred to as n-type, n-type, n + -type, p-type, p-type, p + -type, but the impurity implanted into the region desired to be n-type, n-type, n + -type is For example, boron (B) or aluminum (Al) ions are used as an impurity for injecting nitrogen (N) ions or phosphorus (P) into regions desired to be p-type, p-type, and p + -type.

Embodiment 1

[Semiconductor device]
FIG. 1A is a plan (top) view of an ion implantation region showing a cell structure of a SiC-MOSFET which is a silicon carbide semiconductor device according to the present embodiment.

  2K is a cross-sectional view taken along the line A-A'B-B 'of FIG.

  1A and 2K, a SiC-MOSFET which is a silicon carbide semiconductor device has the following characteristics.

  n-type silicon carbide semiconductor substrate 1 and n-type drift region 2 formed on the main surface of semiconductor substrate 1. A surface layer of the drift region 2 has a plurality of p-type base regions 10 formed at intervals, for example, arranged in a square lattice pattern. Here, the p-type base region 10 has, for example, a square shape. The arrangement and shape of the p-type base region 10 may be a rectangular lattice or a rectangular shape. Note that the sides constituting the p-type base region 10 are substantially parallel to or substantially perpendicular to the off direction.

  In the base region 10, an n + -type source region 20 formed on the surface layer so as to be surrounded by the base region 10, and in the base region 10, a region other than the source region 20 so as to be surrounded by the base region 10 on the surface layer The p + -type base contact region 11 having a higher impurity concentration than the base region 10 formed in FIG. The p + -type base contact region 11 is a region for establishing electrical connection with the base region 10.

  In this embodiment, the p + -type base contact region 11 is formed so as to be surrounded by the source region 20. However, the p + -type base contact region 11 only needs to be surrounded by the base region 10. However, it is not necessarily formed so as to be surrounded by the source region 20. When the p + -type base contact region 11 is formed so as to be surrounded by the source region 20, the base region 10 and the p + -type base contact region 11 are in contact with each other in order to make contact with the base region 10. Need to be formed. The same applies to the other embodiments described below.

  In the configuration of FIGS. 1A and 2K, in the unit cell of the base region 10 in which the source region 20 and the base contact region 11 are formed and arranged in a square lattice, for example, from one corner of the base region 10 to the corner It has a p-type electric field relaxation region 60 extending in a range not connected to another base region 10 in the direction of the other cell corner that is in the second proximity. With such a configuration, the area occupied by the electric field relaxation region can be reduced, and the influence on the channel region can be reduced.

  Here, the first adjacent cell of a certain cell is a cell closest to a certain cell, and in the example of FIG. 1A, is another cell whose sides face each other and touch a certain rectangular cell. The distance between the cells can be, for example, the distance between the geometric centroids of the cells. Also, the second adjacent cell is the second closest cell, and is another cell whose corners face each other and are in contact with a rectangular cell in the example of FIG. 1A.

  In the embodiment of FIG. 1A, the p-type electric field relaxation region 60 is extended from the four corners of the rectangular unit cell in the direction of the other cell corner that is in the second proximity so as not to be connected to other cells. However, in this method, when the MOS is turned on, the vicinity of the four corners of the unit cell is depleted and the channel width (W) is reduced. A decrease in channel width (W) leads to an increase in on-resistance. Therefore, in order to suppress the decrease in W as much as possible, it is preferable to provide a p-type electric field relaxation region 60 at one corner of the cell.

  In addition, as shown in FIG. 20 described above, the electric field applied to the gate insulating film becomes strong because the unit cell of the base region 10 and the center line (adjacent to the cell) adjacent to the cell in the direction perpendicular to the off direction. The base region corner that is on the same distance from the cell and the base region corner that is in contact with the p-type electric field relaxation region and the base region corner that is in the second vicinity thereof are connected by lines. It exists on the down-step side from the intersection. For this reason, as shown in FIG. 1A, providing the p-type electric field relaxation region on the up-step side of the cell requires less area than the p-type electric field relaxation region on the down-step side of the cell. It can be made smaller and the influence on the channel area can be reduced. Therefore, as shown in FIG. 1A, it is preferable to provide a p-type electric field relaxation region on the up-step side of the cell.

  In addition, since the point where the electric field becomes strong is shifted to the down step side as described above, a group of cells is defined by a set of unit cells closest to each other (for example, four cells adjacent in FIG. 1A). Preferably, the electric field relaxation region of the second conductivity type is extended toward a point shifted to the off direction side from the geometric gravity center position of the unit cell group. Specifically, for example, in FIG. 1A, it is desirable that the center line of the electric field relaxation region is designed to be shifted from a line (for example, A-A ′ line) connecting opposing corners of the unit cell. The same applies to the following embodiments.

  Further, if the shape of the region surrounded by the drift region of the p-type electric field relaxation region 60 is constituted by one corner, electric field concentration occurs at the end of the electric field relaxation region, and the breakdown voltage becomes a problem. Good to configure. For example, as shown in FIG. 1A, in the planar shape, the contour of the end portion of the electric field relaxation region is composed of two corners, but may be a polygonal shape or a curved surface shape. In addition, the shape of the electric field relaxation region on the cell side may be a curved shape instead of connecting with corners. When it has a corner, an obtuse angle is preferable to an acute angle. As described above, the contour of the electric field relaxation region is preferably as smooth as possible. The same applies to the other embodiments described below.

  On the other hand, if the length of the p-type field relaxation region is too long, the influence on the channel region increases and the on-resistance increases. If the length of the p-type electric field relaxation region is too short, the intended electric field applied to the gate insulating film becomes insufficient and the gate insulating film is destroyed. For this reason, it is necessary to design the length of the p-type electric field relaxation region within an appropriate range as follows. The length of the p-type electric field relaxation region is designed to satisfy the following inequality (1).

_{L J2 -L J1 <L E <} L J2 ... (1)
L _E : Length from the corner of the base region serving as the base point to the end of the electric field relaxation region L _J1 : The distance between the corner of the base region serving as the base point and the other cell corner serving as the first proximity L _J2 : as shown in distance diagram 1B between the corner and the other cell corners to be the second proximity base region of the base point, the longer L _E than L _J2 -L _J1, base adjacent to the electric-field relaxation region Since the distance between the corners of the region is shorter than the distance between the cells, the electric field applied to the gate insulating film can be effectively reduced. In FIG. 1B, for convenience, L _{J1 and} L _J2 are shown except for the corners that are the base points of the electric field relaxation region. However, if it is assumed that the cells are periodically arranged, The measured distance is the same value (the same applies to FIG. 3).

The p-type electric field relaxation region 60 may be formed simultaneously with the formation of the base region 10 or the base contact region 11 in order to reduce the process cost by reducing the number of masks. For this reason, the impurity concentration of the p-type electric field relaxation region 60 can be created simultaneously in the process by making it the same as the concentration of the base region 10 or the base contact region 11. Specifically, if the range satisfies 5 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ , the process can be shared by using a base region, a base contact region, and a common mask. The same applies to the other embodiments described below.

  Further, FIG. 2K will be described in detail. The first external connection electrode formed on the source region 20 and the base contact region 11 so as to cover at least a part of each region, a part of the source region 20, And the gate insulating film 32 formed on the base region 10, the drift region 2, and the electric field relaxation region 60, the source base contact 51 in contact with the source region 20 and the base region 10, and the n-type on the back surface of the wafer. The drain region 21, the drain contact 52 in contact with the drain region 21, the gate electrode 40 in contact with the gate insulating film 32 above the channel region, the source base contact common electrode 41 in contact with the source base contact 51, and the drain contact 52. It has a drain contact electrode 42 and a surface protective film. Further, a p-type region may be added on the back surface to form a SiC-IGBT. The same applies to the other embodiments described below.

[Method for Manufacturing Semiconductor Device]
Next, a method for manufacturing the SiC-MOSFET will be described.

  2A to 2K are cross-sectional views in respective steps when manufacturing the silicon carbide semiconductor device of the first embodiment taken along the lines A-A ′ and B-B ′ of FIG. 1. In addition, in order to avoid complexity, the cross-sectional view shows only the configuration of the main part in the process, and does not correspond to an accurate cross-sectional view.

2A] The semiconductor device described above is manufactured using an epitaxial wafer as shown in FIG. 2A. In silicon carbide substrate 1 of the present embodiment, for example, the impurity concentration having an offset of 8 °, 4 °, 2 °, 0.5 ° or the like is, for example, 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ . A silicon carbide epitaxial layer 2 having an impurity concentration of, for example, 1 × 10 ¹⁴ to 1 × 10 ¹⁸ cm ⁻³ was stacked thereon using a certain n + type 4H—SiC wafer. The surface of the epitaxial layer 2 has geometric anisotropy as shown in FIGS. 18A and 18B.

[FIG. 2B] Next, a mask 30B is used to implant ions into the p-type base region 10, and as shown in FIG. 2B, Al ions are implanted into the surface layer portion of the silicon carbide epitaxial layer 2 to form a p-type base. Region 10 was formed. The impurity implantation depth is, for example, about 1 μm. Moreover, impurity concentration is the range of 5 * 10 < ¹⁶ > ^-1 * 10 < ¹⁹ > cm < ^-3 >, for example. The ions implanted into the p-type base region 10 may be B ions. Further, a p-type silicon carbide epitaxial layer may be further formed on silicon carbide epitaxial layer 2 to form p-type base region 10. Also in this case, the surface of the p-type base region 10 has geometric anisotropy as shown in FIGS. Thereafter, the mask 30B was removed.

[FIG. 2C] Next, a mask 30C is used to implant ions into the source region 20, and as shown in FIG. 2C, N ions are implanted into the surface layer portion of the silicon carbide epitaxial layer 2 via the mask 30C. Region 20 was formed. The impurity implantation depth is, for example, in the range of 0.1 to 0.5 μm. Moreover, impurity concentration is the range of 1 * 10 < ¹⁸ > -1 * 10 < ²¹ > cm < ^-3 >, for example. The ions implanted into the source region 20 may be P ions. Thereafter, the mask 30C was removed.

[FIG. 2D] Next, a mask 30D is used to implant ions into the base contact region 11, and as shown in FIG. 2D, Al ions are implanted into the surface layer portion of the silicon carbide epitaxial layer 2 via the mask 30D. A base contact region 11 was formed. The impurity implantation depth is, for example, in the range of 0.1 to 0.5 μm. The impurity concentration is set to, for example, about 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ . The ions implanted into the base contact region 11 may be B ions. Thereafter, the mask 30D was removed.

  [FIG. 2E] Next, a mask 30E is implanted to ion-implant the electric field relaxation region 60. As shown in FIG. 2E, Al ions are implanted into the surface layer portion of the silicon carbide epitaxial layer 2 via the mask 30E. An electric field relaxation region 60 was formed. Thereafter, the mask 30E was removed.

The impurity implantation depth is, for example, about 0.1 to 1 μm. The impurity concentration is, for example, in the range of 5 × 10 ¹⁶ to 1 × 10 ²¹ cm ⁻³ . For this reason, in this embodiment, the mask 30E for forming the electric field relaxation region 60 is used. However, if the Al ion implantation concentration is in the range of 5 × 10 ¹⁶ to 1 × 10 ²¹ cm ⁻³ , for example, The electric field relaxation region 60 may be formed simultaneously when Al ions are implanted into the p-type base region 10 or the base contact region 11. The ions implanted into the electric field relaxation region 60 may be B ions.

[FIG. 2F] Next, as shown in FIG. 2F, N ions were implanted into the back surface of the silicon carbide substrate 1 to form a drain region 21. The impurity concentration is, for example, in the range of 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ . The ions implanted into the drain region 21 may be P ions.

  Subsequently, a carbon film as a cap material for impurity activation annealing is deposited around the silicon carbide substrate 1 and the silicon carbide epitaxial layer 2, and impurity activation annealing is performed at a temperature of, for example, 1600 to 1800 ° C. It was. Thereafter, the carbon layer of the cap material was removed by oxygen plasma ashing, and in order to obtain a cleaner surface, a thermal oxide film was formed and removed using a diluted hydrofluoric acid solution.

  [FIG. 2G] Next, as shown in FIG. 2G, a gate insulating film 32 is formed on the semiconductor substrate. In this embodiment, a deposited oxide film having a thickness of about 10 to 100 nm is formed.

  [FIG. 2H] Subsequently, as shown in FIG. 2H, a gate material film 40 made of an n-type polycrystalline silicon film having a thickness of about 100 to 300 nm was deposited.

  2I] Subsequently, as shown in FIG. 2I, an interlayer film 33 was formed so as to cover the gate material film 40.

[FIG. 2J] Subsequently, as shown in FIG. 2J, in order to make contact with the n ⁺ -type source region 20 and the p ⁺ -type base contact region 11, the interlayer film 33 is etched using a resist as a mask to form contact holes. Then, a metal for silicide is deposited and silicidation is performed by, for example, annealing at 700 ° C. to 1000 ° C. to form the source base common contact 51. Thereafter, in order to make contact with the gate electrode, the interlayer film 33 was etched to form a gate contact hole.

  [FIG. 2K] Subsequently, a source-base contact common electrode 41 as shown in FIG. 2K was formed. At the same time, the drain region 21 on the back surface is also silicided to form a drain contact 52 and a drain contact electrode 42. For the silicide metal or the source base contact common electrode 41 and the drain contact electrode 42, for example, a metal material such as Ni or Al is used. Thereafter, a semiconductor device is completed through a step of forming a surface protective film covering the entire surface made of an insulator for device protection and a step of wiring to the electrodes.

  According to the silicon carbide semiconductor device of this example, the electric field applied to the gate oxide film is strengthened, and the point shifted in the down-step direction from the center of the JFET region surrounded by the cell is protected by the electric field relaxation region. The decrease in breakdown voltage and the difference from the design caused by the gate insulating film are eliminated.

Embodiment 2

[Semiconductor device]
FIG. 3 is a plan view of an ion implantation region showing a cell structure of an SiC-MOSFET which is a silicon carbide semiconductor device according to the present embodiment.

  FIG. 4B is a sectional view of the same.

  3 and 4B, SiC-MOSFET which is a silicon carbide semiconductor device has the following characteristics.

n-type silicon carbide semiconductor substrate 1 and n-type drift region 2 formed on the main surface of semiconductor substrate 1. A surface layer of the drift region 2 has a plurality of p-type base regions 10 formed at intervals, for example, arranged in a hexagonal lattice shape. Here, the p-type base region 10 has, for example, a hexagonal shape.
In the base region 10, an n + -type source region 20 formed on the surface layer so as to be surrounded by the base region 10, and in the base region 10, a region other than the source region 20 so as to be surrounded by the base region 10 on the surface layer The p + -type base contact region 11 having a higher impurity concentration than the base region 10 formed in FIG. The p + -type base contact region 11 is a region for establishing electrical connection with the base region 10.

  In the unit cell of the base region 10 in which the source region 20 and the base contact region 11 are formed and arranged in a hexagonal lattice shape, for example, from one corner of the base region 10, two corners of other cells that are close to each other It has a p-type electric field relaxation region 60 extending in a range not connected to other cells in the middle point direction connected by a straight line. In the present embodiment, in the unit cell in which the p-type electric field relaxation region 60 has a single hexagonal shape, for example, a midpoint obtained by connecting two corners of other cells that are in the first proximity from six corners with straight lines. Although six electric field relaxation regions extended in a direction not connected to other cells may be disposed in the direction, the vicinity of the six corners is depleted when the MOS is turned on. In this method, since a region that cannot be used as a channel increases, it is preferable to provide a p-type electric field relaxation region at two corners. In FIG. 3, the first adjacent cell is another cell whose sides are opposed to a certain hexagonal cell, and the second adjacent cell is the first adjacent to a certain cell. And other cells whose sides are opposed to each other (excluding cells that are in the first proximity).

  In addition, when hexagonal cells are arranged in a hexagonal lattice shape, the point where the electric field applied to the gate insulating film becomes strong is a point shifted from the center of the JFET region surrounded by the cells. The location is a position where the down-step direction component and the component in the direction perpendicular to the off direction are combined. For this reason, it is possible to shorten the length of the electric field relaxation region by providing the p-type electric field relaxation region 60 on the up-step side of the cell, compared to providing the p-type electric field relaxation region 60 on the down-step side of the cell. The influence on the area can be reduced. Therefore, as shown in FIG. 3, it is preferable to provide a p-type electric field relaxation region on the upstep side of the cell.

  On the other hand, if the length of the p-type field relaxation region is too long, the influence on the channel region increases and the on-resistance increases. If the length of the p-type electric field relaxation region is too short, the intended electric field applied to the gate insulating film becomes insufficient and the gate insulating film is destroyed. For this reason, it is necessary to design the length of the p-type electric field relaxation region within an appropriate range as follows. The length of the p-type electric field relaxation region is designed to satisfy the following inequality (2).

_{L E <L J1 ... (2} )
L _E : Length from the corner of the base region serving as the base point to the end of the electric field relaxation region L _J1 : Length between the corner of the base region serving as the base point and another cell corner serving as the first proximity [Semiconductor Device manufacturing method]
FIG. 4 is a diagram showing a part different from the first embodiment in the method for manufacturing a semiconductor device in the second embodiment. The second embodiment is the same as the semiconductor device according to the first embodiment shown in FIGS. 1 to 2 except that the cross-sectional view when forming the electric field relaxation region 60 is FIG. 4A and the cross-sectional view when completed is 4B. is there.

  According to the silicon carbide semiconductor device of this example, the electric field applied to the gate oxide film is strengthened, and the point shifted in the down-step direction from the center of the JFET region surrounded by the cell is protected by the electric field relaxation region. The decrease in breakdown voltage and the difference from the design caused by the gate insulating film are eliminated.

Embodiment 3

[Semiconductor device]
FIG. 5 is a plan view of an ion implantation region showing a cell structure of a SiC-MOSFET which is a silicon carbide semiconductor device according to the present embodiment.

  FIG. 6B is a sectional view of the same.

  5 and 6B, the SiC-MOSFET that is the silicon carbide semiconductor device is basically the same as that shown in FIGS. 1A, B, and 2K. In particular, the differences will be described below.

  In the present embodiment, as shown in FIG. 5, the gate insulating film 32 is formed in a region surrounded by four unit cells of the base region 10 in which the source region 20 and the base contact region 11 are formed and arranged in a square lattice pattern. A cross-shaped p-type electric field relaxation region 60 is disposed so as to include a point where an applied electric field becomes strong.

  In the present embodiment, the cross-shaped p-type electric field relaxation region 60 is arranged so that the point where the electric field applied to the gate insulating film 32 becomes strong is the center. Here, the point where the electric field applied to the gate insulating film 32 becomes strong exists on the unit cell of the base region 10 and the center line of the cell adjacent to the cell in the direction perpendicular to the off direction, and the p-type It exists on the down-step side from the intersection where the base region corner which is the base point of extension of the electric field relaxation region and the base region corner which is the second proximity thereof are connected by lines. Therefore, as shown in FIG. 5, the cell center line C and the cross-shaped electric field relaxation region are arranged off the intersection.

  FIG. 7 shows a cross-sectional view of a unit cell in the base region 10 and a center line (D-D ′ region in FIG. 5) of cells adjacent to the cell in a direction perpendicular to the off direction. In the sectional view, a unit cell in the base region and a point C indicating the position of the center line of the cell adjacent to the cell in the off direction are attached. The central point of the p-type electric field relaxation region in the vicinity of the SiC / SiO 2 interface, that is, the point where the electric field applied to the gate insulating film becomes strong exists at a position shifted from the point C to the down step side by the length N. Here, the length N depends on the off angle and the ion implantation depth, but at least the length N takes the range of the inequality (3).

0 <N <L _J1 / 2 (3)
N: Distance between the intersection of the base region corner and the base region corner of the second adjacent cell with a line and the point where the electric field applied to the gate insulating film becomes strong L _J1 : Corner of the base region serving as the base point And the distance between the other cell corners that are in the first proximity (similar to that shown in FIG. 1B)

In addition, the shape of the region surrounded by the drift region of the p-type electric field relaxation region is such that if there are corners, electric field concentration occurs at the corners, and the breakdown voltage becomes a problem. In the present embodiment, it is preferable to round the corners of the cross-shaped intersection.

[Method for Manufacturing Semiconductor Device]
FIG. 6 is a diagram showing portions different from those in the first embodiment in the semiconductor device manufacturing method in the third embodiment. The third embodiment is the same as the semiconductor device according to the first embodiment shown in FIGS. 1 to 2 except that the cross-sectional view when forming the electric field relaxation region 60 is FIG. 6A and the cross-sectional view when completed is 6B. is there.

  According to the silicon carbide semiconductor device of this example, the electric field applied to the gate oxide film is strengthened, and the point shifted in the down-step direction from the center of the JFET region surrounded by the cell is protected by the electric field relaxation region. The decrease in breakdown voltage and the difference from the design caused by the gate insulating film are eliminated. In the semiconductor device described in the first embodiment, when there is a contact failure in the p-type base contact region in one cell, the potential of the p-type base region cannot be fixed. Cause. In the semiconductor device in this embodiment, since the p-type base region of each cell is connected, contact can be made in another cell. Therefore, the potential of the p-type base region can be fixed more easily than in the semiconductor device described in Embodiment 1, and a highly reliable device can be realized.

Embodiment 4

[Semiconductor device]
FIG. 8 is a plan view of an ion implantation region showing a cell structure of a SiC-MOSFET which is a silicon carbide semiconductor device according to the present embodiment.

  In FIG. 8, the SiC-MOSFET which is a silicon carbide semiconductor device is basically the same as that shown in FIGS. 1A, B and 2K. In particular, the differences will be described below.

  In a region surrounded by four unit cells of the base region 10 in which the source region 20 and the base contact region 11 are formed and arranged in a square lattice pattern, the source region 20 and the base contact region 11 are arranged so as to include a point where the electric field applied to the gate insulating film 32 becomes strong. A linear p-type electric field relaxation region 60 is provided. In the present embodiment, the linear p-type electric field relaxation region 60 is arranged so that the point where the electric field applied to the gate insulating film 32 becomes strong is the center. Here, the point where the electric field applied to the gate insulating film becomes strong exists on the unit cell of the base region 10 and the center line C of the cell adjacent to the cell in the direction perpendicular to the off direction, and the p-type The base region corner portion serving as the base point of the extension of the electric field relaxation region and the base region corner portion adjacent to the base region corner portion thereof are present on the down-step side from the intersections respectively connected by lines. For this reason, as shown in FIG. 8, the center line of the linear p-type electric field relaxation region 60 that connects the corners of the base region 10 may be arranged at a position shifted from the center line C of the cell. desirable.

  FIG. 7 shows a cross-sectional view of the unit cell in the base region and a center line (D-D ′ region in FIG. 8) of cells adjacent to the cell in a direction perpendicular to the off direction. In the sectional view, a unit cell of the base region and a point C indicating the position of the center line of the cell adjacent to the cell in the off direction are attached. The central point of the p-type electric field relaxation region in the vicinity of the SiC / SiO 2 interface, that is, the point where the electric field applied to the gate insulating film becomes strong exists at a position shifted from the point C to the down step side by the length N. Here, the length N depends on the off angle and the ion implantation depth, but at least the length N takes the range of the inequality (4).

0 <N <L _J1 / 2 (4)
N: Distance between the intersection of the base region corner and the base region corner of the second adjacent cell with a line and the point where the electric field applied to the gate insulating film becomes strong L _J1 : Corner of the base region serving as the base point And the distance between the other cell corners that are in the first proximity (similar to that shown in FIG. 1B)
The semiconductor device in the fourth embodiment can be manufactured in the same manner as the semiconductor device described in the third embodiment.

  According to the silicon carbide semiconductor device of this example, the electric field applied to the gate oxide film is strengthened, and the point shifted in the down-step direction from the center of the JFET region surrounded by the cell is protected by the electric field relaxation region. The decrease in breakdown voltage and the difference from the design caused by the gate insulating film are eliminated. In the semiconductor device described in the first embodiment, when there is a contact failure in the p-type base contact region in one cell, the potential of the p-type base region cannot be fixed. Cause. In the semiconductor device in the present embodiment, the p-type base region of each cell is connected. In the example of FIG. 8, the p-type base regions of the second neighboring cells are connected. For this reason, contact can be made in another cell. Therefore, the potential of the p-type base region can be fixed more easily than in the semiconductor device described in Embodiment 1, and a highly reliable device can be realized. In the semiconductor device described in Embodiment 3, the cross-shaped p-type field relaxation region is used. However, since the semiconductor device in this embodiment uses a bridge-type structure, the area occupied by the p-type field relaxation region is large. Few. Therefore, the influence on the channel region can be reduced, so that the on-resistance can be made smaller than that of the semiconductor device described in Embodiment 3.

Embodiment 5

[Semiconductor device]
FIG. 9 is a plan view of an ion implantation region showing a cell structure of a SiC-MOSFET which is a silicon carbide semiconductor device according to the present embodiment.

  In FIG. 9, the SiC-MOSFET that is the silicon carbide semiconductor device is basically the same as that shown in FIGS. 1A, 1B, and 2K. In particular, the differences will be described below.

  A unit cell of the base region 10 in which the source region 20 and the base contact region 11 are formed and arranged in a square lattice pattern, and a cell adjacent to the cell in a direction perpendicular to the off direction, The p-type electric field relaxation region extends from the two corners to the point where the electric field applied to the gate insulating film becomes stronger, and the two p-type electric field relaxation regions are connected. That is, the p-type electric field relaxation region has a V-shape. Here, the point where the electric field applied to the gate insulating film becomes strong is that the unit cell in the base region exists on the center line of the cell adjacent to the cell in the direction perpendicular to the off direction, and is a p-type electric field. It exists on the down-step side from the intersection where the base region corner which is the base point of extension of the relaxation region and the base region corner which is the second proximity thereof are connected by lines.

  FIG. 7 shows a cross-sectional view of a unit cell in the base region and a center line (D-D ′ region in FIG. 9) of cells adjacent to the cell in a direction perpendicular to the off direction. In the sectional view, a unit cell of the base region and a point C indicating the position of the center line of the cell adjacent to the cell in the off direction are attached. The central point of the p-type electric field relaxation region in the vicinity of the SiC / SiO 2 interface, that is, the point where the electric field applied to the gate insulating film becomes strong exists at a position shifted from the point C to the down step side by the length N. Here, the length N depends on the off angle and the ion implantation depth, but at least the length N takes the range of the inequality (5).

0 <N <L _J1 / 2 (5)
N: Distance between the intersection of the base region corner and the base region corner of the second adjacent cell with a line and the point where the electric field applied to the gate insulating film becomes strong L _J1 : Corner of the base region serving as the base point And other cell corners that are in the first proximity (similar to that shown in FIG. 1B)
It is better to select two points on the up-step side as the two corner portions that are the first proximity. This is because at the two points on the down step side, the area occupied by the p-type electric field relaxation region becomes larger than the area on the up step side, the influence on the channel region increases, and the on-resistance increases.

  In addition, if there is a corner at the tip of the V-shape, electric field concentration occurs in the corner portion of the electric field relaxation region, and the breakdown voltage becomes a problem. Therefore, it is preferable to increase the curvature of the corner portion.

[Method for Manufacturing Semiconductor Device]
The manufacturing method of the semiconductor device in the fifth embodiment is the same as that of the semiconductor device described in the first embodiment.

  According to the silicon carbide semiconductor device of this example, the electric field applied to the gate oxide film is strengthened, and the point shifted in the down-step direction from the center of the JFET region surrounded by the cell is protected by the electric field relaxation region. The decrease in breakdown voltage and the difference from the design caused by the gate insulating film are eliminated. In the semiconductor device described in the first embodiment, when there is a contact failure in the p-type base contact region in one cell, the potential of the p-type base region cannot be fixed. Cause.

  In the semiconductor device in this embodiment, since the p-type base region of each cell is connected, contact can be made in another cell. In the example of FIG. 9, the p-type base regions of the first neighboring cells are connected. Therefore, the potential of the p-type base region can be fixed more easily than in the semiconductor device described in Embodiment 1, and a highly reliable device can be realized. In the semiconductor device described in Embodiment 3, a cross-shaped p-type field relaxation region is used. However, since the semiconductor device in this embodiment uses a V-shaped structure, the area occupied by the p-type field relaxation region is Less is. Further, by providing the p-type electric field relaxation region on the up-step side, the area of the p-type electric field relaxation region can be further reduced. Therefore, the influence on the channel region can be reduced, so that the on-resistance can be made smaller than that of the semiconductor device described in Embodiment 3.

Embodiment 6

  In this embodiment, a power conversion device including the semiconductor device described in any of the first to fifth embodiments will be described.

  FIG. 10 is a circuit diagram of the power conversion device (inverter) of the present embodiment. As illustrated in FIG. 10, the inverter according to the present embodiment includes a SiC-MOSFET 304 that is a switching element and a diode 305 in a power module 302. In each single phase, SiC-MOSFET 304 and diode 305 are connected in antiparallel between the power supply voltage (Vcc) and the input potential of load (for example, motor) 301 via the terminal (upper arm). The SiC-MOSFET element 304 and the diode 305 are also connected in antiparallel between the input potential of the load 301 and the ground potential (GND) (lower arm).

  That is, the load 301 is provided with two SiC-MOSFETs 304 and two diodes 305 in each single phase, and is provided with six switching elements 304 and six diodes 305 in three phases. A control circuit 303 is connected to the gate electrode of each SiC-MOSFET 304 via a terminal, and the SiC-MOSFET 304 is controlled by the control circuit 303. Therefore, the inverter according to the present embodiment can drive the load 301 by controlling the current flowing through the SiC-MOSFET 304 constituting the power module 302 by the control circuit 303.

  The function of the SiC-MOSFET 304 in the power module 302 will be described below. For example, in order to control and drive a motor as the load 301, it is necessary to input a sine wave having a desired voltage to the load 301. The control circuit 303 controls the SiC-MOSFET 304 to perform a pulse width modulation operation that dynamically changes the pulse width of the rectangular wave. The output rectangular wave is smoothed by passing through the inductor, and becomes a pseudo desired sine wave. The SiC-MOSFET 304 generates a rectangular wave for performing this pulse width modulation operation.

  By using the semiconductor device of the first embodiment or the second embodiment as the SiC-MOSFET 304, for example, since the on-resistance of the SiC-MOSFET 304 is small, the structure of a heat sink or the like for cooling is reduced, and the power module 302 can be reduced in size and weight, and thus the power converter can be reduced in size and weight. Moreover, since the reliability of the gate insulating film of the SiC-MOSFET 304 is high, the life of the power module 302 can be extended.

  Further, the power conversion device of the present embodiment can be a three-phase motor system. The load 301 shown in FIG. 10 is a three-phase motor. By using the power conversion device including the semiconductor device described in the first embodiment or the second embodiment as a switching element, the load 301 is reduced in size. And high performance can be realized.

Embodiment 7

  In the present embodiment, a power conversion device including the semiconductor device described in the first to fifth embodiments will be described. FIG. 11 is a circuit diagram showing the power conversion device (inverter) of the present embodiment.

  As shown in FIG. 11, the inverter according to the present embodiment includes a SiC-MOSFET 404 as a switching element in a power module 402. In each single phase, SiC-MOSFET 404 is connected between the power supply voltage (Vcc) and the input potential of load (eg, motor) 401 (upper arm) via a terminal. An SiC-MOSFET element 404 is also connected between the input potential of the load 401 and the ground potential (GND) (lower arm). That is, in the load 401, two SiC-MOSFETs 404 are provided for each single phase, and six switching elements 404 are provided for three phases. A control circuit 403 is connected to the gate electrode of each SiC-MOSFET 304 via terminals 410 and 411, and the SiC-MOSFET 404 is controlled by this control circuit 403. Therefore, in the inverter of the present embodiment, the load 401 can be driven by controlling the current flowing through the SiC-MOSFET 404 in the power module 402 by the control circuit 403.

  The function of the SiC-MOSFET 404 in the power module 402 will be described below. As one of the functions of the SiC-MOSFET, this embodiment also has a function of generating a rectangular wave for performing a pulse width modulation operation, as in the sixth embodiment. In the present embodiment, SiC-MOSFET 404 also plays a role of diode 305 of the sixth embodiment. For example, when the load 401 includes an inductance like a motor, when the SiC-MOSFET 404 is turned off, the energy stored in the inductance must be released (reflux current). In the sixth embodiment, the diode 305 plays this role. On the other hand, in the present embodiment, since the synchronous rectification drive is used, the SiC-MOSFET 404 plays a role of flowing a circulating current. In the synchronous rectification drive according to the present embodiment, the gate of the SiC-MOSFET 404 is turned on at the time of reflux, and the SiC-MOSFET 404 is turned on in reverse.

  Therefore, the conduction loss during reflux is determined not by the characteristics of the diode but by the characteristics of the SiC-MOSFET 404. Further, when performing synchronous rectification drive, in order to prevent the upper and lower arms from being short-circuited, a non-operation time is required in which both the upper and lower SiC-MOSFETs are turned off. During this non-operation time, the built-in PN diode formed by the drift layer and the p-type body layer of the SiC-MOSFET 404 is driven. However, SiC has a shorter carrier travel distance than Si and a small loss during the non-operation time, which is equivalent to, for example, the case where the diode 305 of the sixth embodiment is a SiC Schottky barrier diode.

  As described above, in the present embodiment, by using the semiconductor device of Example 1 or Example 2 described above for the SiC-MOSFET 404, for example, the loss of the reflux at the time of the high performance of the SiC-MOSFET 404 is achieved. It can be made smaller, and higher performance can be achieved. Further, since the free wheel diode is not provided separately from the SiC-MOSFET 404, the power module 402 can be further reduced in size.

  Further, the power conversion device of the present embodiment can be a three-phase motor system. A load 401 shown in FIG. 11 is a three-phase motor, and the power module 402 includes the semiconductor device described in any of the first to fifth embodiments, thereby realizing downsizing and higher performance of the three-phase motor system. be able to.

Embodiment 8

  The three-phase motor system described in the sixth embodiment or the seventh embodiment can be used for a vehicle such as a hybrid vehicle, an electric vehicle, and a fuel cell vehicle. In the present embodiment, an automobile equipped with a three-phase motor system will be described with reference to FIGS.

  FIG. 12 is a schematic diagram showing the configuration of the electric vehicle of the present embodiment.

  As shown in FIG. 12, the electric vehicle of the present embodiment drives a three-phase motor 503 that allows power to be input / output to / from a drive shaft 502 to which the drive wheels 501a and 501b are connected, and the three-phase motor 503. Inverter 504 and a battery 505. Further, the electric vehicle of this embodiment includes a boost converter 508, a relay 509, and an electronic control unit 510. Boost converter 508 is connected to power line 506 to which inverter 504 is connected and to power line 507 to which battery 505 is connected.

  The three-phase motor 503 is a synchronous generator motor including a rotor embedded with permanent magnets and a stator wound with a three-phase coil. As the inverter 504, the inverter described in Embodiment 6 or 7 described above can be used.

  FIG. 13 shows a circuit diagram of the boost converter 508 of this embodiment. As shown in FIG. 13, boost converter 508 has a configuration in which a reactor 511 and a smoothing capacitor 112 are connected to inverter 513. For example, the inverter 513 can have the same configuration as the inverter described in the seventh embodiment, and the element configuration in the inverter is the same. Also in the present embodiment, the switching element is the SiC-MOSFET 514 as in the seventh embodiment, and synchronous rectification driving is performed. In FIG. 12, only one phase of the inverter is shown, but it may be multiphase.

  The electronic control unit 510 shown in FIG. 12 includes a microprocessor, a storage device, and an input / output port. A signal from a sensor for detecting the rotor position of the three-phase motor 503, a charge / discharge value of the battery 505, and the like. Receive. Then, a signal for controlling inverter 504, boost converter 508, and relay 509 is output.

  As described above, according to the present embodiment, the power conversion device according to the sixth embodiment or the seventh embodiment can be used for inverter 504 and boost converter 508 which are power conversion devices. Further, the three-phase motor system of the sixth embodiment or the seventh embodiment described above can be used for a three-phase motor system including the three-phase motor 503 and the inverter 504. Thereby, the energy saving of an electric vehicle, size reduction, weight reduction, and space saving of a power converter device can be achieved.

  In the present embodiment, the electric vehicle has been described. However, the above-described three-phase motor system can be similarly applied to a hybrid vehicle that also uses an engine and a fuel cell vehicle in which the battery 505 is a fuel cell stack. .

Embodiment 9

  The three-phase motor system of the sixth embodiment and the seventh embodiment can be used for a railway vehicle. In the present embodiment, a railway vehicle using a three-phase motor system will be described.

  FIG. 14 is a circuit diagram including a converter and an inverter of the railway vehicle of the present embodiment.

  As shown in FIG. 14, electric power is supplied to the railway vehicle from an overhead line OW (for example, 25 kV) via a pantograph PG. The voltage is stepped down to 1.5 kV via the transformer 609 and converted from alternating current to direct current by the converter 607. Further, the inverter 602 converts the direct current into the alternating current through the capacitor 608, and the three-phase motor as the load 601 is driven. The element configuration in converter 607 may be a SiC-MOSFET and a diode used together as in the sixth embodiment, or a SiC-MOSFET alone as in the seventh embodiment.

  In the present embodiment, the switching element is synchronously rectified and driven as the SiC-MOSFET 604 as in the seventh embodiment. In FIG. 14, the control circuit described in the seventh embodiment is omitted. Moreover, in the figure, symbol RT indicates a track, and symbol WH indicates a wheel.

  As described above, according to the present embodiment, power converter of the sixth embodiment or seventh embodiment can be used for converter 607. Further, the three-phase motor system according to the sixth embodiment or the seventh embodiment can be used for the three-phase motor system including the load 601, the inverter 602, and the control circuit. As a result, energy saving of the railway vehicle and reduction in floor and weight by downsizing the underfloor parts including the three-phase motor system can be achieved.

  The present invention is not limited to the embodiments described above, and includes various modifications. For example, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, it is possible to add, delete, and replace the configurations of other embodiments with respect to a part of the configurations of the embodiments.

  The functions of the “source” and “drain” of the transistor may be switched when a transistor with a different polarity is used or when the direction of current changes during circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.

  In this specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, an “electrode” may be used as part of a “wiring” and vice versa. Furthermore, the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.

  The present invention is effective when applied to a semiconductor device using silicon carbide, a method for manufacturing the semiconductor device, and a power module, an inverter, an automobile, and a railway vehicle using the semiconductor device.

DESCRIPTION OF SYMBOLS 1 Silicon carbide substrate 2 Drift layer 10 Base region 11 Base contact region 20 Source region 21 Drain region 30 Mask 32 Gate insulating film 33 Interlayer film 40 Gate material film 41 Source base contact common electrode 42 Drain contact electrode 51 Source base common contact 52 Drain Contact 301 Load 302 Power module 303 Control circuit 304 SiC-MOSFET
305 Diode 306 to 312 Terminal 401 Load 402 Power module 403 Control circuit 404 SiC-MOSFET
405 to 411 Terminal 501a Drive wheel 501b Drive wheel 502 Drive shaft 503 Three-phase motor 504 Inverter 505 Battery 506 Power line 507 Power line 508 Boost converter 509 Relay 510 Electronic control unit 511 Reactor 512 Smoothing capacitor 513 Inverter 514 SiC-MOSFET
601 Load 602 Inverter 607 Converter 608 Capacitor 609 Transformer OW Overhead line PG Pantograph RT Line WH Wheel

Claims (15)

A first conductivity type semiconductor substrate;
A drift region of a first conductivity type formed on the semiconductor substrate;
A plurality of unit cells periodically formed at intervals in the surface layer of the drift region,
Each of the unit cells is
A base region of a second conductivity type;
A source region of a first conductivity type formed so as to be surrounded by the base region in the base region;
A second contact type base contact region having a higher impurity concentration than the base region formed in contact with the base region,
An electric field relaxation region of a second conductivity type extending from the base region of the unit cell in a range not connected to the base region of the other unit cell;
A first external connection electrode formed on the source region and the base contact region so as to cover at least a part of each region;
A gate insulating film formed on the source region, the base region, the drift region, and the electric field relaxation region so as to cover at least a part of each region;
A semiconductor device comprising:   When a group of cells is defined by a set of the unit cells closest to each other, the second conductivity type of the second conductivity type is covered so as to cover a point shifted to the off direction side from the geometric center of gravity of the unit cell group. 2. The semiconductor device according to claim 1, wherein the electric field relaxation region extends. When the shape of the unit cell is defined by the shape of the base region,
Each of the unit cells has a polygonal shape as viewed from directly above the surface layer of the drift region,
The electric field relaxation region of the second conductivity type extends from at least one of the corner portions of the unit cell not facing the off direction side toward the shifted position. The semiconductor device according to claim 2. The unit cell has a rectangular, square, or hexagonal shape,
4. The semiconductor device according to claim 3, wherein the unit cells are arranged in a rectangular lattice, a square lattice, or a hexagonal lattice.   The shape of the electric field relaxation region of the second conductivity type viewed from directly above the surface layer of the drift region is configured with a curve, or configured with two or more corners, and one angle is 90 degrees or more. The semiconductor device according to claim 1. 2. The semiconductor device according to claim 1, wherein an impurity concentration of the second conductivity type electric field relaxation region is in a range satisfying 5 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ . The unit cell has a rectangular or square shape;
The unit cells are arranged in a rectangular lattice or a square lattice,
The electric field relaxation region of the second conductivity type is
From at least one of the plurality of corners of the base region of the unit cell to the closest corner of the plurality of corners of the base region of another unit cell that is in the second proximity, the other unit cell Extends within the range not connected to the base area,
The semiconductor device according to claim 2, wherein the extension length of the electric field relaxation region of the second conductivity type satisfies the following inequality.

_{L J2 -L J1 <L E <} L J2
L _E : Length from the corner of the base region serving as a base point to the end of the electric field relaxation region L _J1 : The base region angle of another unit cell that is close to the corner of the base region serving as a base point L _J2 : Distance between the corners of the base region serving as the base point and the base region corners of the other unit cells serving as the second proximity The unit cell has a hexagonal shape;
The unit cells are arranged in a hexagonal lattice,
The electric field relaxation region of the second conductivity type is
Other cell corners in the direction of the midpoint connecting the corners of the base regions of the other two unit cells in the first proximity with a straight line from at least one of the plurality of corners of the base region of the unit cell Extend within the range not connected to
The semiconductor device according to claim 2, wherein the extension length of the electric field relaxation region of the second conductivity type satisfies the following inequality.

_{L E} <L _J1
L _E : Length from the corner of the base region serving as the base point to the end of the electric field relaxation region L _J1 : The distance between the corner of the base region serving as the base point and the other cell corner serving as the first proximity A power conversion device using a semiconductor device as a switching element,
The semiconductor device includes:
A first conductivity type semiconductor substrate;
A drift region of a first conductivity type formed on the semiconductor substrate;
A plurality of unit cells periodically formed at intervals in the surface layer of the drift region,
Each of the unit cells is
A base region of a second conductivity type;
A source region of a first conductivity type formed so as to be surrounded by the base region in the base region;
A second contact type base contact region having a higher impurity concentration than the base region formed in contact with the base region,
An electric field relaxation region of a second conductivity type extending from the base region of the unit cell in a range not connected to the base region of the other unit cell;
A first external connection electrode formed on the source region and the base contact region so as to cover at least a part of each region;
A gate insulating film formed on the source region, the base region, the drift region, and the electric field relaxation region so as to cover at least a part of each region;
A power conversion device comprising: A first conductivity type semiconductor substrate;
A drift region of a first conductivity type formed on the semiconductor substrate;
A plurality of unit cells periodically formed at intervals in the surface layer of the drift region,
Each of the unit cells is
A base region of a second conductivity type;
A source region of a first conductivity type formed so as to be surrounded by the base region in the base region;
A second contact type base contact region having a higher impurity concentration than the base region formed in contact with the base region,
A second conductivity type electric field relaxation region extending from the base region of the unit cell;
A first external connection electrode formed on the source region and the base contact region so as to cover at least a part of each region;
On the source region, the base region, the drift region, and the electric field relaxation region, each region and a gate insulating film formed to cover at least part of the region,
When a cell group is defined by the set of unit cells closest to each other, the electric field relaxation of the second conductivity type toward a point shifted to the off-direction side from the geometric center of gravity of the unit cell group. A semiconductor device characterized in that a region is extended. The unit cell has a rectangular or square shape;
The unit cells are arranged in a rectangular lattice or a square lattice,
The electric field relaxation region of the second conductivity type is
Extending from one of the corners of the base region of the unit cell in the direction of the nearest corner of the base region of the other unit cell in the second proximity,
The electric field relaxation region is arranged at a position shifted to the off-direction side from a straight line connecting one corner of the base region and the nearest corner of the base region of another unit cell in the second proximity. The semiconductor device according to claim 10. When the X direction is the off direction, the Y direction is perpendicular to the off direction, and the geometric center of gravity of the region surrounded by the four unit cells is the origin,
The electric field relaxation region of the second conductivity type in the enclosed region is
Among the four unit cells, third and fourth unit cells that connect opposite corners of the base regions of the first and second unit cells that are in a second proximity relationship and that are in a second proximity relationship. A cross-shaped p-type electric field relaxation region connecting opposite corners of the base region of
12. The semiconductor device according to claim 11, wherein the geometric gravity center position of the cross-shaped electric field relaxation region is (N, 0), and N satisfies the following inequality.

0 <N <L _J1 / 2
N: Distance between the intersection of the base region corner and the base region corner of the second adjacent cell with a line and the point where the electric field applied to the gate insulating film becomes strong L _J1 : Corner of the base region serving as the base point Between the other cell corner and the first proximity When the X direction is the off direction, the Y direction is perpendicular to the off direction, and the center of gravity of the area surrounded by the four unit cells is the origin,
The electric field relaxation region of the second conductivity type in the enclosed region is
Among the four unit cells, third and fourth unit cells that connect opposite corners of the base regions of the first and second unit cells that are in a second proximity relationship and that are in a second proximity relationship. A linear p-type electric field relaxation region that does not connect opposite corners of the base region of
12. The semiconductor device according to claim 11, wherein the gravity center position of the linear p-type electric field relaxation region is (N, 0), and N satisfies the following inequality.

0 <N <L _J1 / 2
N: Distance between the intersection of the base region corner and the base region corner of the second adjacent cell with a line and the point where the electric field applied to the gate insulating film becomes strong L _J1 : Corner of the base region serving as the base point Between the other cell corner and the first proximity When the X direction is the off direction, the Y direction is perpendicular to the off direction, and the center of gravity of the area surrounded by the four unit cells is the origin,
The electric field relaxation region of the second conductivity type in the enclosed region is
Among the four unit cells, the first and second unit cells in the first proximity relationship connect the opposite corners of the base region, and the third and fourth unit cells in the first proximity relationship A V-shaped p-type field relaxation region that does not connect opposite corners of the base region of
The silicon carbide semiconductor device according to claim 11, wherein the bent portion of the V-shaped electric field relaxation region covers coordinates (N, 0), and N satisfies the following inequality.

0 <N <L _J1 / 2
N: Distance between the intersection of the base region corner and the base region corner of the second adjacent cell with a line and the point where the electric field applied to the gate insulating film becomes strong L _J1 : Corner of the base region serving as the base point Between the other cell corner and the first proximity   11. The semiconductor device according to claim 10, wherein the impurity concentration of the second conductivity type electric field relaxation region is a concentration that can be formed using a common mask with the base region or the base contact region.

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