JP6880637B2 - Semiconductor devices and methods for manufacturing semiconductor devices - Google Patents

Description

The present invention relates to semiconductor devices and methods for manufacturing semiconductor devices.

Conventionally, silicon (Si) has been used as a constituent material of a power semiconductor device that controls a high voltage or a large current. There are multiple types of power semiconductor devices, such as bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors: Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors: Insulated Gate Field Effect Transistors). Has been done.

For example, bipolar transistors and IGBTs have a higher current density than MOSFETs and can increase the current, but they cannot be switched at high speed. Specifically, the bipolar transistor is limited to use at a switching frequency of about several kHz, and the IGBT is limited to use at a switching frequency of about several tens of kHz. On the other hand, the power MOSFET has a lower current density than the bipolar transistor and the IGBT, and it is difficult to increase the current, but high-speed switching operation up to about several MHz is possible.

However, there is a strong demand in the market for power semiconductor devices that have both large current and high speed, and efforts have been made to improve IGBTs and power MOSFETs, and development is now progressing to near the material limit. .. Silicon carbide alternatives to silicon are being studied from the perspective of power semiconductor devices, and silicon carbide (SiC) is a material with excellent low-on-voltage, high-speed, and high-temperature characteristics as a material for next-generation power semiconductor devices. Recently, it has been receiving particular attention.

Behind this, SiC is a chemically stable material, has a wide bandgap of 3 eV, and can be used extremely stably as a semiconductor even at high temperatures. This is also because the maximum electric field strength is more than an order of magnitude higher than that of silicon. Since SiC has a high possibility of exceeding the material limit of silicon, future growth is expected in power semiconductor applications, especially MOSFETs. In particular, it is expected that the on-resistance is small, but a vertical SiC-MOSFET having a lower on-resistance while maintaining high withstand voltage characteristics can be expected.

FIG. 9 is a cross-sectional view showing the configuration of a conventional vertical SiC-MOSFET. The n- ^{type silicon carbide epitaxial layer 2 is deposited on the front surface of the n +} type silicon carbide substrate 1, and the p-type base layer 4 is selectively provided on the surface of the n-type silicon carbide epitaxial layer 2. ^{Further, an n +} type source region 5 is selectively provided on the surface of the p-type base layer 4.

A gate electrode 9 is provided on the surface of the p-type base layer 4 and the n ⁺ -type source region 5 via a gate insulating film 8. Further, a source electrode 11 is provided on the surfaces of the n-type silicon carbide epitaxial layer 2, the p-type base layer 4, and the n ^{+ type source region 5.} Further, a back surface electrode 13 is provided on the back surface of the n ^{+ type silicon carbide substrate 1.}

Further, an IE MOSFET (Implantation and Epitaxial MOSFET) structure in which the bottom portion of the p-type base layer 4 (hereinafter referred to as p ⁺ type base layer 3) is formed by high-concentration ion implantation and the upper portion is formed by an epitaxial layer has also been proposed. There is.

In this way, SiC-MOSFETs are expected to be used as switching devices in power conversion devices such as motor control inverters and uninterruptible power supplies (UPS) as elements capable of high-speed switching with low on-resistance. Has been done. Since SiC is a wide bandgap semiconductor material, its breaking electric field strength is about 10 times higher than that of silicon as described above. Therefore, the load of the electric field on the oxide film when a high voltage is applied is also higher than that of a silicon element. Will grow. When a high voltage is applied (voltage is applied between the drain and source of the device), the silicon power device reaches the breaking electric field strength of silicon before a large electric field is applied to the oxide film, so this was not a problem in SiC. Since the breaking electric field strength of the semiconductor is extremely high, there is a concern that the oxide film will break first.

Specifically, a large electric field strength is applied to the gate insulating film 8 of the SiC-MOSFET shown in FIG. 9, and there is a possibility that the oxide film forming the gate electrode 9 may be destroyed or a serious problem may occur in reliability. is there. This applies not only to SiC-MOSFETs but also to SiC-IGBTs. It is also important to reduce the on-resistance of the device in order to reduce the loss when energized.

10A to 10D are top views showing the configuration of a conventional IE MOSFET (see, for example, Patent Document 1). In the conventional IE MOSFET, ^{the planar shape of the p +} type base layer 3 has the shape of a hexagonal cell. ^{In this case, the distance between the p +} type base layers 3 (width W in FIG. 10A) is important for ensuring the withstand voltage between the drain and the source of the device. If the interval W is too wide, the withstand voltage between the drain and the source will decrease. On the other hand, if the interval W is too narrow, the space between the p ⁺ type base layers 3 becomes narrow and the region of the n-type silicon carbide epitaxial layer 2 which is the current path decreases, so that the on-resistance increases.

In the case of the conventional Type-A shown in FIG. 10A, the point A (hereinafter referred to as the triple point) is ^{the farthest from the three ends of the p +} type base layer of the hexagonal cell (greater than W / 2), so that the p ⁺ type base When the layer 3 interval W becomes large, the electric field at the triple point becomes strong, and the withstand voltage between the drain and the source decreases.

In order to eliminate this decrease in pressure resistance, for example, as in the conventional Type-B shown in FIG. 10B and the conventional Type-C shown in FIG. 10C, a p ⁺ type base layer 3 is formed at the ^{triple point portion to p +.} The wide portion between the mold base layers 3 may be eliminated. Further, for example, as in the conventional Type-D shown in FIG. 10D, a p ⁺ type region may be formed at the triple point portion.

International Publication 2011/135995

However, in the above-mentioned Type-B and Type-C, the withstand voltage does not decrease due to ^{the p + type base layer 3 at the triple point portion, but the conduction region between the p +} type base layers 3 decreases, so that the on-resistance is turned on. There is a problem that the number increases. Further, in the above-mentioned Type-D, since the p ⁺ type region of the triple point portion is small, it is necessary to make the p + type region smaller than the design rule of the photo process that is usually used, and there is a problem that it becomes difficult to form the ^{p + type region.} is there.

An object of the present invention is to provide a semiconductor device and a method for manufacturing a semiconductor device capable of reducing on-resistance while ensuring a withstand voltage between a drain and a source in order to solve the above-mentioned problems caused by the prior art.

In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. A first conductive type first semiconductor layer having a lower impurity concentration than the semiconductor substrate is provided on the front surface of the first conductive type semiconductor substrate. A second conductive type second semiconductor layer is selectively provided on the surface layer of the first semiconductor layer on the side opposite to the semiconductor substrate side. A second conductive type third semiconductor layer having a lower impurity concentration than the second semiconductor layer is provided on the surface layers of the first semiconductor layer and the second semiconductor layer on the opposite side of the semiconductor substrate side. A first conductive type first semiconductor region is selectively provided on the surface layer of the third semiconductor layer on the side opposite to the semiconductor substrate side. A second conductive type third semiconductor region in contact with the first semiconductor region is selectively provided on the surface layer of the third semiconductor layer on the side opposite to the semiconductor substrate side. A first conductive type second semiconductor region that penetrates the third semiconductor layer and reaches the first semiconductor layer is provided. A gate electrode is provided on the surface of the third semiconductor layer sandwiched between the first semiconductor region and the second semiconductor region via a gate insulating film. An interlayer insulating film is provided on the gate electrode. Source electrodes are provided on the surfaces of the first semiconductor region and the third semiconductor region. A drain electrode is provided on the back surface of the semiconductor substrate. The second semiconductor layer has a shape in which a part of the corners protrudes in a convex shape. The distance between the second semiconductor layers is 3.0 μm or more and 3.5 μm or less, the on-resistance is 2.7 Ωcm ² or less, and the element withstand voltage is 1400 V or more. The planar shape of the second semiconductor layer is a hexagon, and only two opposing corners of the hexagon protrude in a convex shape.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the semiconductor material of the semiconductor substrate is silicon carbide.

In order to solve the above-mentioned problems and achieve the object of the present invention, the method for manufacturing a semiconductor device according to the present invention has the following features. First, a first step of forming a first conductive type first semiconductor layer having a lower impurity concentration than the semiconductor substrate is performed on the front surface of the first conductive type semiconductor substrate. Next, a second step of selectively forming the second conductive type second semiconductor layer on the surface layer of the first semiconductor layer opposite to the semiconductor substrate side is performed. Next, on the surface layers of the first semiconductor layer and the second semiconductor layer opposite to the semiconductor substrate side, a second conductive type third semiconductor layer having a lower impurity concentration than the second semiconductor layer is applied. The third step of forming is performed. Next, a fourth step of selectively forming the first conductive type first semiconductor region on the surface layer of the third semiconductor layer opposite to the semiconductor substrate side is performed. Next, a fifth step of selectively forming a second conductive type third semiconductor region in contact with the first semiconductor region on the surface layer of the third semiconductor layer opposite to the semiconductor substrate side is performed. Do. Next, a sixth step of forming a first conductive type second semiconductor region that penetrates the third semiconductor layer and reaches the first semiconductor layer is performed. Next, a seventh step of forming a gate electrode via a gate insulating film on at least a part of the surface of the third semiconductor layer sandwiched between the first semiconductor region and the second semiconductor region is performed. Next, an eighth step of forming an interlayer insulating film on the gate electrode is performed. Next, a ninth step of forming a source electrode on the surface of the first semiconductor region and the third semiconductor region and a tenth step of forming a drain electrode on the back surface of the semiconductor substrate are performed. In the second step, the second semiconductor layer has a shape in which a part of the corners protrudes in a convex shape, the distance between the second semiconductor layers is 3.0 μm or more and 3.5 μm or less , and the second semiconductor layer. The planar shape of the hexagon is formed into a hexagon, and only two opposite corners of the hexagon are formed in a convex shape, the on-resistance is 2.7 Ωcm ² or less, and the element withstand voltage is 1400 V or more.

According to the above-described invention, the p ⁺ type base layer (second conductive type second semiconductor layer) has a shape in which a part of the corners protrudes in a convex shape. As a result, ^{the spacing between the p +} type base layers will not be greater than the spacing between the straight sections. Therefore, even if the distance between the p-type base layer (the second conductive type third semiconductor layer) is increased, the depletion ^{layer tends to spread laterally along the p +} type base layer, so that the n-type backing layer is formed. A large electric field is not applied to the gate insulating film on the (first conductive type second semiconductor region), and a sufficient withstand voltage between the source and drain can be secured. As a result, ^{it is possible to realize a semiconductor device capable of increasing the distance between the p +} type base layers and reducing the on-resistance while maintaining sufficient device withstand voltage.

Further, the ^{shape in which a part of the corner of the p +} type base layer protrudes in a convex shape is formed by implanting ions into the surface of the n-type silicon carbide epitaxial layer (first conductive type first semiconductor layer) to form a p ⁺ type base layer. It is only necessary to change the mask when forming the. Therefore, it is possible to form the semiconductor device according to the design rules of the photo process that is usually used, and it is possible to manufacture the semiconductor device without incurring a cost increase.

According to the semiconductor device and the method for manufacturing the semiconductor device according to the present invention, there is an effect that the on-resistance can be reduced while ensuring the withstand voltage between the drain and the source.

It is sectional drawing which shows the structure of the silicon carbide semiconductor device which concerns on embodiment. It is a top view which shows the structure of the silicon carbide semiconductor device which concerns on embodiment. It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on embodiment (the 1). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on embodiment (the 2). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on embodiment (the 3). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on embodiment (the 4). It is an actual measurement result which shows the relationship between the ^{element withstand voltage and the spacing of a p +} type base layer in the silicon carbide semiconductor apparatus which concerns on embodiment. It is an actual measurement result which shows the relationship between the ^{on-resistance and the spacing of a p +} type base layer in the silicon carbide semiconductor device which concerns on embodiment. It is sectional drawing which shows the structure of the conventional vertical SiC-MOSFET. It is a top view which shows the structure of the conventional IE MOSFET (Type-A). It is a top view which shows the structure of the conventional IE MOSFET (Type-B). It is a top view which shows the structure of the conventional IE MOSFET (Type-C). It is a top view which shows the structure of the conventional IE MOSFET (Type-D).

Hereinafter, preferred embodiments of the semiconductor device and the method for manufacturing the semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that the electrons or holes are a large number of carriers in the layers and regions marked with n or p, respectively. Further, + and-attached to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region to which it is not attached, respectively. When the notation of n and p including + and-is the same, it means that the concentrations are close to each other, and the concentrations are not necessarily the same. In the following description of the embodiment and the accompanying drawings, the same reference numerals are given to the same configurations, and duplicate description will be omitted. In this specification, in the notation of the Miller index, "-" means a bar attached to the index immediately after that, and a "-" is added before the index to represent a negative index.

(Embodiment)
The semiconductor device according to the present invention is configured by using a wide bandgap semiconductor having a wider bandgap than silicon. In the embodiment, a silicon carbide semiconductor device manufactured by using, for example, silicon carbide (SiC) as a wide bandgap semiconductor will be described by taking IE MOSFET as an example. FIG. 1 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to an embodiment.

As shown in FIG. 1, the silicon carbide semiconductor device according to the embodiment is an n-type silicon carbide epitaxial on the main surface (front surface) ^{of the n + type silicon carbide substrate (first conductive type semiconductor substrate) 1.} Layer (first conductive type first semiconductor layer) 2 is deposited.

The n ⁺ type silicon carbide substrate 1 is, for example, a silicon carbide single crystal substrate doped with nitrogen (N). The n-type silicon carbide epitaxial layer 2 is a low-concentration n-type drift layer in which, for example, nitrogen is doped with an impurity concentration lower than that ^{of the n + type silicon carbide substrate 1.} Hereinafter, the n ⁺ type silicon carbide substrate 1 alone, or the n ⁺ type silicon carbide substrate 1 and the n-type silicon carbide epitaxial layer 2 are combined to form a silicon carbide semiconductor substrate.

As shown in FIG. 1, the silicon carbide semiconductor device according to the embodiment has a surface (silicon carbide semiconductor substrate) opposite to the n-type silicon carbide epitaxial layer 2 side of the ^{n + type silicon carbide substrate 1 which is a drain region.} A back surface electrode 13 is provided on the back surface). The back surface electrode 13 constitutes a drain electrode. In addition, a back electrode pad (not shown) for connecting to an external device is provided.

A MOS (insulated gate made of metal-oxide film-semiconductor) structure (element structure) is formed on the front surface side of the silicon carbide semiconductor substrate. Specifically, the surface layer of the n-type silicon carbide epitaxial layer 2 on the ^{side opposite to the n +} type silicon carbide substrate 1 side (front surface side of the silicon carbide semiconductor substrate) is a p ⁺ type base layer ( The second conductive type second semiconductor layer) 3 is selectively provided. The p ⁺ type base layer 3 is doped with, for example, aluminum (Al).

FIG. 2 is a top view showing the configuration of the silicon carbide semiconductor device according to the embodiment. As shown in FIG. 2, ^{the shape 20 is such that a part of the corner of the p +} type base layer 3 protrudes in a convex shape. Further, ^{the planar shape of the p +} type base layer 3 may be hexagonal. In this case, only two of the hexagons facing each other may have a convex shape. For example, as shown in FIG. 2, a shape in which only the corners of the p ⁺ -type base layer 3 facing the other p ⁺ -type base layer 3 in the x-axis direction protruding in a convex shape. In FIG. 2, although it is in the x-axis direction, it may be in another axial direction. Since ^{a part of the corner of the p +} type base layer 3 protrudes in a convex shape, ^{the distance between the p +} type base layer 3 does not become larger than the distance W of the straight line portion.

The p ⁺ -type base layer 3, and the adjacent p ⁺ -type base layer 3 sandwiched by n-type silicon carbide epitaxial layer 2 of the surface, the p-type silicon carbide epitaxial layer (hereinafter referred to as p-type base layer, the 2 Conductive type third semiconductor layer) 4 is selectively deposited. The impurity concentration of the p-type base layer 4 ^{is lower than the impurity concentration of the p +} type base layer 3. The p-type base layer 4 is doped with, for example, aluminum.

An ^{n +} type source region (first conductive type first semiconductor region) 5 and a p ⁺ type contact region 6 are provided on the surface of the p-type base layer 4 on the ^{p + type base layer 3.} Further, the n ⁺ type source region 5 and the p ⁺ type contact region 6 are in contact with each other. The n ⁺ type source region 5 is arranged on the outer periphery of the ^{p + type contact region 6.}

Further, in the portion of the p-type base layer 4 on the n-type silicon carbide epitaxial layer 2, an n-type backing layer (first) that penetrates the p-type base layer 4 in the depth direction and reaches the n-type silicon carbide epitaxial layer 2. A conductive second semiconductor region) 7 is provided. The n-type backing layer 7 constitutes a drift region together with the n-type silicon carbide epitaxial layer 2. A gate electrode 9 is provided on the surface of the p-type base layer 4 ^{sandwiched between the n +} type source region 5 and the n-type backing layer 7 via a gate insulating film 8. The gate electrode 9 may be provided on the surface of the n-type backing layer 7 via the gate insulating film 8.

Although only one and half MOS structures are shown in FIG. 1, a plurality of MOS structures may be arranged in parallel.

The interlayer insulating film 10 is provided on the entire surface of the silicon carbide semiconductor substrate on the front surface side so as to cover the gate electrode 9. ^{The source electrode 11 contacts the n +} type source region 5 and the p ⁺ type contact region 6 through the contact hole opened in the interlayer insulating film 10. The source electrode 11 is electrically insulated from the gate electrode 9 by the interlayer insulating film 10. An electrode pad 12 is provided on the source electrode 11.

(Manufacturing method of silicon carbide semiconductor device according to the embodiment)
Next, the method for manufacturing the silicon carbide semiconductor device according to the embodiment will be described by taking, for example, the case of producing an IE MOSFET having a withstand voltage class of 1200 V as an example. 3 to 6 are cross-sectional views showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment. First, for example, ^{an n +} type silicon carbide substrate 1 doped with nitrogen at an impurity concentration of about ^{2 × 10 19} / cm ^{3 is prepared.} The crystallographic surface index of the front surface of the n ⁺ type silicon carbide substrate 1 is a surface parallel to (000-1) or a surface inclined within 4 degrees. Next, an n-type silicon carbide epitaxial layer 2 having a thickness of about 10 μm, in which nitrogen is doped with an impurity concentration of ^{1.0 × 10 18} / cm ³ on the (000-1) surface of ^{the n + type silicon carbide substrate 1.} To grow. Here, the structure is as shown in FIG.

Next, an oxide film mask for ion implantation is formed by photolithography and etching, and a p ⁺ type base layer 3 is selectively formed on the surface layer of the n-type silicon carbide epitaxial layer 2 by ion implantation. Further, the oxide film mask is formed so that a part of the corner of the ^{p +} type base layer 3 as shown in FIG. 2 has a convexly protruding shape 20. In this ion implantation, for example, the dopant may be aluminum, and the dose amount may be set so that ^{the impurity concentration of the p +} type base layer 3 is 1.0 × 10 ¹⁸ / cm ^3. The width and depth of the p ⁺ type base layer 3 may be 13 μm and 0.5 μm, respectively. The distance W between the adjacent p ⁺ type base layers 3 may be, for example, 2.0 μm. Here, the structure is as shown in FIG.

Next, a p-type silicon carbide epitaxial layer to be a p-type base layer 4 is grown on the surface of the n-type silicon carbide epitaxial layer 2 to a thickness of, for example, 0.5 μm. At this time, for example, the p-type silicon carbide epitaxial layer doped with aluminum may be grown so that the impurity concentration of the p-type base layer 4 is 2.0 × 10 ¹⁸ / cm ^3.

Next, by photolithography and ion implantation, the conductive type of the portion of the p-type base layer 4 on the n-type silicon carbide epitaxial layer 2 is inverted to selectively form the n-type backed layer 7. The width and depth of the n-type backing layer 7 may be 2.0 μm and 1.5 μm, respectively. Nitrogen ions may be ion-implanted so that the impurity concentration of the n-type beating layer 7 is 5.0 × 10 ¹⁸ / cm ^3.

^{Next, the n +} type source region 5 is selectively formed on the surface layer of the p type base layer 4 on the ^{p +} type base layer 3 by photolithography and ion implantation. ^{Next, the p +} type contact region 6 is selectively formed on the surface layer of the p type base layer 4 on the ^{p +} type base layer 3 by photolithography and ion implantation. Here, the structure is as shown in FIG.

Heat treatment (annealing) is performed to activate the p ⁺ type base layer 3, the n ⁺ type source region 5, the p ⁺ type contact region 6, and the n-type backing layer 7. The heat treatment temperature and heat treatment time at this time may be 1620 ° C. and 20 minutes, respectively.

The ^{order of forming the p +} type base layer 3, the n ⁺ type source region 5, the p ⁺ type contact region 6, and the n-type countering layer 7 can be changed in various ways.

Next, the front surface side of the silicon carbide semiconductor substrate is thermally oxidized to form the gate insulating film 8 having a thickness of 100 nm. This thermal oxidation may be carried out by heat treatment at a temperature of about 1000 ° C. in a hydrogen (H _{2) atmosphere.} As a result, each region formed on the surfaces of the p-type base layer 4 and the n-type silicon carbide epitaxial layer 2 is covered with the gate insulating film 8.

Next, a polycrystalline silicon layer doped with phosphorus (P), for example, is formed as the gate electrode 9 on the gate insulating film 8. Next, the polycrystalline silicon layer is patterned and selectively removed ^{, leaving the polycrystalline silicon layer on the portion of the p-type base layer 4 sandwiched between the n +} type source region 5 and the n-type countered layer 7. .. At this time, the polycrystalline silicon layer may be left on the n-type backing layer 7.

Next, for example, phosphorus glass (NSB: Non-topped Silicate Glass) is formed as the interlayer insulating film 10 so as to cover the gate insulating film 8. The thickness of the interlayer insulating film 10 may be 1.0 μm. Next, the interlayer insulating film 10 and the gate insulating film 8 are patterned and selectively removed to form a contact hole, and the n ⁺ type source region 5 and the p ⁺ type contact region 6 are exposed. Next, a heat treatment (reflow) is performed to flatten the interlayer insulating film 10. Here, the structure is as shown in FIG.

Next, the source electrode 11 is formed on the surface of the interlayer insulating film 10. At this time, the source electrode 11 is also embedded in the contact hole, and the n ⁺ type source region 5 and the p ⁺ type contact region 6 are brought into contact with the source electrode 11. Next, the source electrode 11 other than the contact hole is selectively removed.

Next, ^{for example, a nickel film is formed on the front surface of the n +} type silicon carbide substrate 1 (the back surface of the silicon carbide semiconductor substrate) as the back surface electrode 13. Then, for example, heat treatment is performed at a temperature of 970 ° C. ^{to form an ohmic contact between the n +} type silicon carbide substrate 1 and the back surface electrode 13. Next, for example, by a sputtering method, the electrode pad 12 is deposited so as to cover the source electrode 11 and the interlayer insulating film 10 on the entire surface of the front surface of the silicon carbide semiconductor substrate. The thickness of the portion of the electrode pad 12 on the interlayer insulating film 10 may be, for example, 5 μm. The electrode pad 12 may be formed of, for example, aluminum (Al—Si) containing silicon at a ratio of 1%. Next, the electrode pad 12 is selectively removed.

Next, for example, titanium (Ti), nickel (Ni), and gold (Au) are formed on the front surface of the back surface electrode 12 as the back surface electrode pad 13 in this order. Next, a protective film may be formed on the surface. As a result, the IE MOSFET shown in FIG. 1 is completed.

Next, the measurement results of the electrical characteristics of the SiC-MOSFET created in this way are shown in FIGS. 7 and 8. FIG. 7 is an actual measurement result showing the relationship between the ^{device withstand voltage and the spacing between the p +} type base layers in the silicon carbide semiconductor device according to the embodiment. FIG. 8 is an actual measurement result showing the relationship between the ^{on-resistance and the spacing between the p +} type base layers in the silicon carbide semiconductor device according to the embodiment.

Here, the chip size of the silicon carbide semiconductor device measured in FIGS. 7 and 8 is 3 mm square, the area of the active region through which the current flows when turned on is 5.27 mm ² , and the rated current is 25 A.

For example, ^{the case where the distance between the p +} type base layers 3 is 2 μm is compared. As shown in FIGS. 7 and 8, in the case of Type-E of the embodiment, the on-resistance (RonA) ^{shows a sufficiently low value of 2.85 mΩcm 2,} and the initial element withstand voltage is 1450 V, which is sufficiently good as a 1200 V element. It shows various characteristics. For comparison, when the SiC-MOSFET created in the conventional Type-A shape was measured, the on-resistance ^{showed a sufficiently low value of 2.8 mΩcm 2} , which is the same, but the element withstand voltage is low, so the source and drain. When 880V was applied between them, the gate insulating film was destroyed.

The measured SiC-MOSFET created in the shape of a conventional Type-B and Type-C, the withstand voltage was good value and 1450V, on-resistance, respectively 2.9Emuomegacm ² and 2.95Emuomegacm ² It was big. From this, the silicon carbide semiconductor device of the embodiment can reduce the on-resistance while maintaining a sufficient element withstand voltage.

As described above, according to the silicon carbide semiconductor device according to the embodiment, the p ⁺ type base layer has a shape in which a part of the corners protrudes in a convex shape. As a result, ^{the spacing between the p +} type base layers will not be greater than the spacing between the straight sections. Therefore, even if the distance between the p-type base layers is increased, the depletion ^{layer tends to spread laterally along the p +} type base layer, so that a large electric field is applied to the gate insulating film on the n-type backing layer. However, a sufficient withstand voltage between the source and drain can be secured. As a result, ^{it is possible to realize a semiconductor device capable of increasing the distance between the p +} type base layers and reducing the on-resistance while maintaining sufficient device withstand voltage.

In addition, the ^{shape in which a part of the corner of the p +} type base layer protrudes in a convex shape can be obtained by simply changing the mask when ion-implanting the surface of the n-type silicon carbide epitaxial layer to form the p ^{+ type base layer.} Good. Therefore, it is possible to form the semiconductor device according to the design rules of the photo process that is usually used, and it is possible to manufacture the semiconductor device without incurring a cost increase.

In the above, the present invention can be variously modified without departing from the spirit of the present invention, and in each of the above-described embodiments, for example, the dimensions of each part, the impurity concentration, and the like are set in various ways according to the required specifications and the like. Further, in each of the above-described embodiments, MOSFETs are described as an example, but the present invention is not limited to this, and various types of silicon carbide that conduct and cut off current by being gate-driven and controlled based on a predetermined gate threshold voltage. It can be widely applied to semiconductor devices. For example, it can be applied to an IGBT by using a conductive type semiconductor substrate different from the MOSFET. Further, in each of the above-described embodiments, the case where silicon carbide is used as the wide bandgap semiconductor is described as an example, but it can also be applied to a widebandgap semiconductor such as gallium nitride (GaN) other than silicon carbide. Is. Further, in each embodiment, the first conductive type is n-type and the second conductive type is p-type, but in the present invention, the first conductive type is p-type and the second conductive type is n-type. It holds.

As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for high withstand voltage semiconductor devices used in power supply devices such as power conversion devices and various industrial machines.

1 n ⁺ type silicon carbide substrate 2 n type silicon carbide epitaxial layer 3 p ⁺ type base layer 4 p type base layer 5 n ⁺ type source area 6 p ⁺ type contact area 7 n type countersunk layer 8 gate insulating film 9 gate electrode 10 Interlayer insulating film 11 Source electrode 12 Electrode pad 13 Backside electrode 20 Convex protruding shape

Claims (3)

The first conductive type semiconductor substrate and
A first conductive type first semiconductor layer having a lower impurity concentration than the semiconductor substrate, which is provided on the front surface of the semiconductor substrate,
A second conductive type second semiconductor layer selectively provided on the surface layer of the first semiconductor layer opposite to the semiconductor substrate side,
A second conductive type third semiconductor layer having a lower impurity concentration than the second semiconductor layer, which is provided on the surface layer of the first semiconductor layer and the second semiconductor layer on the side opposite to the semiconductor substrate side. ,
A first conductive type first semiconductor region selectively provided on the surface layer of the third semiconductor layer on the side opposite to the semiconductor substrate side,
A second conductive type third semiconductor region in contact with the first semiconductor region, which is selectively provided on the surface layer of the third semiconductor layer on the side opposite to the semiconductor substrate side,
A first conductive type second semiconductor region that penetrates the third semiconductor layer and reaches the first semiconductor layer,
A gate electrode provided on the surface of the third semiconductor layer sandwiched between the first semiconductor region and the second semiconductor region via a gate insulating film, and
An interlayer insulating film provided on the gate electrode and
A source electrode provided on the surface of the first semiconductor region and the third semiconductor region,
The drain electrode provided on the back surface of the semiconductor substrate and
With
The second semiconductor layer has a shape in which a part of the corners protrudes in a convex shape.
Interval of the second semiconductor layer is at 3.0μm or 3.5μm or less, the on-resistance 2.7Omucm ² or less, the breakdown voltage is Ri der than 1400 V,
A semiconductor device characterized in that the planar shape of the second semiconductor layer is a hexagon, and only two opposing corners of the hexagon protrude in a convex shape. The semiconductor device according to claim 1, wherein the semiconductor material of the semiconductor substrate is silicon carbide. A first step of forming a first conductive type first semiconductor layer having a lower impurity concentration than the semiconductor substrate on the front surface of the first conductive type semiconductor substrate.
A second step of selectively forming a second conductive type second semiconductor layer on the surface layer of the first semiconductor layer opposite to the semiconductor substrate side.
A second conductive type third semiconductor layer having a lower impurity concentration than the second semiconductor layer is formed on the surface layers of the first semiconductor layer and the second semiconductor layer opposite to the semiconductor substrate side. 3 steps and
A fourth step of selectively forming a first conductive type first semiconductor region on the surface layer of the third semiconductor layer opposite to the semiconductor substrate side.
A fifth step of selectively forming a second conductive type third semiconductor region in contact with the first semiconductor region on the surface layer of the third semiconductor layer opposite to the semiconductor substrate side.
A sixth step of forming a first conductive type second semiconductor region that penetrates the third semiconductor layer and reaches the first semiconductor layer.
A seventh step of forming a gate electrode via a gate insulating film on at least a part of the surface of the third semiconductor layer sandwiched between the first semiconductor region and the second semiconductor region.
The eighth step of forming an interlayer insulating film on the gate electrode and
A ninth step of forming a source electrode on the surfaces of the first semiconductor region and the third semiconductor region,
The tenth step of forming the drain electrode on the back surface of the semiconductor substrate and
With
In the second step, the second semiconductor layer has a shape in which a part of the corners protrudes in a convex shape, the distance between the second semiconductor layers is 3.0 μm or more and 3.5 μm or less, and the second semiconductor layer. The planar shape of the hexagon is formed into a hexagon, and only the two opposite corners of the hexagon are formed in a convex shape, and the on-resistance is 2.7 Ωcm. ² Hereinafter, a method for manufacturing a semiconductor device, characterized in that the device withstand voltage is 1400 V or more.

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