JP2014060272A - Silicon carbide semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device and a manufacturing method of the same, which can improve switching characteristics while inhibiting reduction in drain current.SOLUTION: A manufacturing method of a silicon carbide semiconductor device 1 comprises the following steps of: preparing a silicon carbide substrate 10 which includes a principal surface 10a and has a first conductivity type region 17, a pair of second conductivity type well regions 13 which sandwich the first conductivity type region 17, and an n-type region 3 which is arranged between the pair of well regions 13 and contacts the first conductivity type region 17; and oxidizing the principal surface 10a of the silicon carbide substrate 10 to form a gate insulation film 15 which contacts the well regions 13 and the first conductivity type region 17. When the first conductivity type is n-type, an impurity concentration of the n-type region 3 is higher than an impurity concentration of the first conductivity type region 17. When the first conductivity type is p-type, an impurity concentration of the n-type region 3 is higher than an impurity concentration of each well region 13.

Description

  The present invention relates to a silicon carbide semiconductor device and a manufacturing method thereof, and more particularly to a silicon carbide semiconductor device capable of improving switching characteristics and a manufacturing method thereof.

  2. Description of the Related Art In recent years, silicon carbide has been increasingly used as a material for semiconductor devices in order to enable higher breakdown voltages, lower losses, and use in high-temperature environments for semiconductor devices such as MOSFETs (Metal Oxide Field Effect Transistors). It is being Silicon carbide is a wide band gap semiconductor having a larger band gap than silicon that has been widely used as a material for forming semiconductor devices. Therefore, by adopting silicon carbide as a material constituting the semiconductor device, it is possible to achieve a high breakdown voltage and a low on-resistance of the semiconductor device. In addition, a semiconductor device that employs silicon carbide as a material has an advantage that a decrease in characteristics when used in a high temperature environment is small as compared with a semiconductor device that employs silicon as a material.

  For example, Non-Patent Document 1 discloses a MOSFET having an n-type drift layer formed on a silicon carbide substrate, a pair of well regions, and a gate insulating film. Non-Patent Document 1 discloses a MOSFET whose switching energy loss is 9 mJ when switching from an on state in which the drain source current is 65 A to an off state in which the drain source voltage is 750 V.

Brett A. Hull et al., "Performance of 60A, 1200V 4H-SiC DMOSFETs", Materials Science Forum, Vols. 615-617, 2009, pp749-752

  In order to improve the switching characteristics, it is necessary to reduce the capacitance of the silicon carbide semiconductor device. The capacitance is inversely proportional to the thickness of the insulator sandwiched between the electrodes. Therefore, the capacitance can be reduced by increasing the thickness of the gate insulating film. However, increasing the thickness of the gate insulating film reduces the drain current flowing through the channel.

  The present invention has been made to solve such problems, and an object of the present invention is to provide a silicon carbide semiconductor device capable of improving the switching characteristics while suppressing the reduction of the drain current, and a method for manufacturing the same. That is.

  As a result of intensive studies, the inventors have obtained the following knowledge and have come up with the present invention. First, in order to improve the switching characteristics, it is necessary to reduce the capacitance of the device. Of the capacitance of the device, it is desirable to reduce the capacitance (feedback capacitance) of the JFET region sandwiched between the pair of well regions, the gate electrode, and the portion facing each other through the gate insulating film.

  In order to reduce the capacitance between the JFET region and the gate electrode, it is effective to increase the thickness of the gate insulating film on the JFET region. However, when the thickness of the entire gate insulating film is increased, the value of the drain current flowing through the channel is decreased. Therefore, it is desirable to increase the thickness of the gate insulating film on the JFET region and keep the thickness of the gate insulating film on the well region small.

  The inventors have formed an n-type region having a high impurity concentration in the JFET region, and then formed a gate insulating film in contact with the JFET region, thereby increasing the thickness of the gate insulating film on the JFET region. It was found that the thickness of the gate insulating film can be kept small. An n-type region having a high impurity concentration has a higher oxidation rate than a p-type region or a low impurity concentration n-type region. Therefore, by forming an n-type region having a high impurity concentration in the JFET region, the thickness of the gate insulating film on the JFET region can be changed to a gate insulation on a well region including a p-type region and a low impurity concentration n-type region. It can be larger than the thickness of the film.

  Therefore, a method for manufacturing a silicon carbide semiconductor device according to the present invention includes the following steps. A silicon carbide substrate having a main surface is prepared. The silicon carbide substrate includes a first conductivity type region having a first conductivity type, a pair of well regions having a second conductivity type different from the first conductivity type and sandwiching the first conductivity type region, and a pair of well regions And an n-type region in contact with the first conductivity type region. Each of the pair of well regions and the n-type region included in the silicon carbide substrate are formed exposed to the main surface of the silicon carbide substrate. A gate insulating film in contact with the well region and the first conductivity type region is formed by oxidizing the main surface of the silicon carbide substrate. When the first conductivity type is n-type, the impurity concentration of the n-type region is higher than the impurity concentration of the first conductivity type region. When the first conductivity type is p-type, the impurity concentration of the n-type region is higher than the impurity concentration of the well region.

  According to the method for manufacturing a silicon carbide semiconductor device of the present invention, the n-type region including the main surface of the silicon carbide substrate is formed in the first conductivity type region. When the first conductivity type is n-type, the impurity concentration of the n-type region is higher than the impurity concentration of the first conductivity type region. When the first conductivity type is p-type, the impurity concentration of the n-type region is higher than the impurity concentration of the well region.

  When the first conductivity type is n-type, the well region is p-type. The oxidation rate of the n-type region having an impurity concentration higher than that of the first conductivity type region is faster than the oxidation rate of the well region that is the p-type region. Therefore, the thickness of the gate insulating film on the first conductivity type region is larger than the thickness of the gate insulating film on the well region. When the first conductivity type is p-type, the well region is n-type. The oxidation rate of the n-type region having an impurity concentration higher than that of the well region is faster than the oxidation rate of the well region. Therefore, the thickness of the gate insulating film formed on the first conductivity type region is larger than the thickness of the gate insulating film on the well region.

  That is, regardless of whether the first conductivity type region is n-type or p-type, the thickness of the gate insulating film formed on the first conductivity type region is larger than the thickness of the gate insulating film on the well region. . Therefore, it is possible to reduce the capacitance of the silicon carbide semiconductor device while suppressing the reduction of the drain current. As a result, the switching characteristics of the silicon carbide semiconductor device can be improved while suppressing a decrease in drain current.

  In the method for manufacturing the silicon carbide semiconductor device according to the above, preferably, the first conductivity type is an n-type. Thereby, a silicon carbide semiconductor device with high mobility can be obtained.

  In the method for manufacturing a silicon carbide semiconductor device according to the above, preferably, the step of forming the n-type region is performed by ion implantation or diffusion. Thereby, an n-type region can be formed efficiently.

In the method for manufacturing a silicon carbide semiconductor device according to the above, preferably, the impurity concentration of the n-type region is not less than 1 × 10 ¹⁷ cm ^{−3 and not} more than 1 × 10 ²⁰ cm ⁻³ . Thereby, the thickness of the gate insulating film on the first conductivity type region can be sufficiently increased.

  Preferably in the method for manufacturing a silicon carbide semiconductor device according to the above, the thickness of the n-type region is not less than 10 nm and not more than 50 nm. If the thickness of the n-type region is less than 10 nm, the thickness of the gate insulating film on the first conductivity type region will not be sufficiently large. When the thickness of the n-type region is larger than 50 nm, the breakdown voltage is lowered because the n-type region having a high impurity concentration remains in the first conductivity type region even after the gate insulating film is formed. By setting the thickness of the n-type region to not less than 10 nm and not more than 50 nm, the thickness of the gate insulating film can be sufficiently increased while suppressing a decrease in breakdown voltage.

  Preferably, in the method for manufacturing a silicon carbide semiconductor device according to the above, the gate insulating film includes a first region in contact with the first conductivity type region and a second region in contact with the pair of well regions. The film thickness of the first region is larger than the film thickness of the second region. Thereby, the electrostatic capacitance of the silicon carbide semiconductor device can be reduced while suppressing the reduction of the drain current.

  In the method for manufacturing the silicon carbide semiconductor device according to the above, preferably, the film thickness of the first region is 3 nm or more larger than the film thickness of the second region. Thereby, the electrostatic capacitance of the silicon carbide semiconductor device can be reduced while efficiently suppressing the drain current.

  A silicon carbide semiconductor device according to the present invention has a silicon carbide substrate and a gate insulating film. The silicon carbide substrate includes a first conductivity type region having a main surface and having a first conductivity type. The gate insulating film is in contact with the main surface of the silicon carbide substrate. The silicon carbide substrate includes a pair of well regions having a second conductivity type different from the first conductivity type and arranged so as to sandwich the first conductivity type region. The gate insulating film includes a first region in contact with the first conductivity type region and a second region in contact with each of the pair of well regions. The film thickness of the first region is larger than the film thickness of the second region.

  According to the silicon carbide semiconductor device of the present invention, the gate insulating film includes the first region in contact with the first conductivity type region and the second region in contact with the pair of well regions, and the film thickness of the first region is It is larger than the film thickness of the second region. Thereby, the electrostatic capacitance of the silicon carbide semiconductor device can be reduced while suppressing the reduction of the drain current. As a result, the switching characteristics of the silicon carbide semiconductor device can be improved while suppressing a decrease in drain current.

  In the silicon carbide semiconductor device according to the above, preferably, the silicon carbide substrate has a second main surface opposite to the main surface. The main surface of the silicon carbide substrate includes a first region main surface in contact with the first region and a second region main surface in contact with the second region. The first region main surface is located closer to the second main surface than the second region main surface. Thereby, the capacitance of the silicon carbide semiconductor device can be reduced by increasing the thickness of the first region.

  In the silicon carbide semiconductor device according to the above, preferably, the thickness of the first region is 3 nm or more larger than the thickness of the second region. Thereby, the electrostatic capacitance of the silicon carbide semiconductor device can be reduced while efficiently suppressing the drain current.

  In the silicon carbide semiconductor device according to the above, preferably, the thickness of the first region is not less than 45 nm and not more than 70 nm. When the thickness of the first region is less than 45 nm, the leakage current is likely to occur because the thickness is small. When the film thickness of the first region is more than 70 nm, the difference between the film thickness of the first region and the film thickness of the second region becomes large, and a large step is formed between the first region and the second region. The electric field concentrates at the corner of the step, and a leak current is likely to occur. Therefore, the occurrence of leakage current can be suppressed by setting the film thickness of the first region to 45 nm or more and 70 nm or less.

  As is apparent from the above description, according to the present invention, it is possible to provide a silicon carbide semiconductor device capable of improving the switching characteristics while suppressing a decrease in drain current and a method for manufacturing the same.

1 is a schematic cross-sectional view schematically showing a structure of a silicon carbide semiconductor device according to one embodiment of the present invention. It is a flowchart which shows schematically the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention. It is a cross-sectional schematic diagram which shows schematically the 1st process of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention. It is a cross-sectional schematic diagram which shows schematically the 2nd process of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention. It is a cross-sectional schematic diagram which shows schematically the 3rd process of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention. It is a cross-sectional schematic diagram which shows schematically the 4th process of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention. It is a cross-sectional schematic diagram which shows schematically the 5th process of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention. FIG. 11 is a schematic cross-sectional view showing conductivity types of a well region, an n-type region, and a first conductivity type region in the first example of the third step of the method for manufacturing the silicon carbide semiconductor device according to one embodiment of the present invention. It is a cross-sectional schematic diagram which shows the conductivity type of the well area | region, n-type area | region, and 1st conductivity type area | region in the 2nd example of the 3rd process of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated. In the crystallographic description in this specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. As for the negative index, “−” (bar) is attached on the number in crystallography, but in this specification, a negative sign is attached before the number. The angle is described using a system in which the omnidirectional angle is 360 degrees.

  Referring to FIG. 1, MOSFET 1 which is a silicon carbide semiconductor device in the present embodiment mainly includes silicon carbide substrate 10, gate insulating film 15, gate electrode 27, source contact electrode 16, and drain electrode 20. Have.

  Silicon carbide substrate 10 is made of, for example, polytype 4H hexagonal silicon carbide. Main surface 10a of silicon carbide substrate 10 may be, for example, a surface that is off by about 8 ° or less from the (0001) surface, or may be a (0-33-8) surface. Preferably, main surface 10a is a surface having an off angle of 62 ° ± 10 ° macroscopically with respect to the {000-1} plane.

Silicon carbide substrate 10 mainly includes a base substrate 11, a drift layer 12, a well region 13, an n + region 14, and a p + region 18. The base substrate is an epitaxial layer made of silicon carbide and having n type conductivity (first conductivity type). Drift layer 12 is arranged on base substrate 11 and has n type conductivity. The impurity contained in the drift layer 12 is, for example, nitrogen (N). The concentration of nitrogen contained in the drift layer 12 is, for example, about 5 × 10 ¹⁵ cm ⁻³ . The drift layer 12 includes a first conductivity type region 17. The first conductivity type region 17 is a part of the drift layer 12 and is a JFET region sandwiched between a pair of well regions 13 described later. The drift layer 12 and the first conductivity type region 17 have the same conductivity type.

The pair of well regions 13 are disposed so as to sandwich the first conductivity type region 17, and are regions having a p type (second conductivity type) different from the n type (first conductivity type). Impurities contained in each of the pair of well regions 13 are, for example, aluminum (Al), boron (B), or the like. The concentration of aluminum or boron in the well region 13 is, for example, about 1 × 10 ¹⁷ cm ⁻³ .

The n + region 14 is formed inside each of the pair of well regions 13 so as to include the main surface 10 a and be surrounded by the well region 13. N + region 14 contains an impurity such as phosphorus (P) at a higher concentration (density) than the impurity contained in drift layer 12. The concentration of phosphorus in the n + region 14 is, for example, about 1 × 10 ²⁰ cm ⁻³ .

The p + region 18 includes the main surface 10 a, is surrounded by the well region 13, and is formed inside each of the pair of well regions 13 so as to be adjacent to the n + region 14. The p + region 18 is disposed in contact with the source contact electrode 16, the n + region 14 and the well region 13. The p + region 18 contains an impurity such as Al at a higher concentration (density) than the impurity contained in the well region 13. The concentration of Al in the p + region 18 is, for example, about 1 × 10 ²⁰ cm ⁻³ .

  Gate insulating film 15 is arranged in contact with main surface 10a of silicon carbide substrate 10. Gate insulating film 15 is made of, for example, silicon dioxide. The gate insulating film 15 includes a first region 15 a in contact with the first conductivity type region 17 and a second region 15 b in contact with the well region 13. The first region 15a in contact with the first conductivity type region 17 includes the case where the first conductivity type region 17 contacts the first region 15a via the n-type region 3 described later. The film thickness T1 of the first region 15a is larger than the film thickness T2 of the second region 15b. The thickness of the first region 15a on the first conductivity type region 17 is about 55 nm, for example, and the thickness of the second region 15b on the well region 13 is about 40 nm, for example.

  Preferably, the film thickness T1 of the first region 15a is larger than the film thickness T2 of the second region 15b by 3 nm or more, more preferably 5 nm or more. Preferably, the film thickness T1 of the first region 15a is not less than 45 nm and not more than 70 nm.

  The first region 15 a is in contact with each of the first conductivity type region 17 and the pair of well regions 13. Main surface 10a of silicon carbide substrate 10 includes a first region main surface 10c in contact with first region 15a and a second region main surface 10d in contact with second region 15b. First region main surface 10c is located closer to second main surface 10b of silicon carbide substrate 10 than second region main surface 10d.

  The first region 15 a has a surface 15 c that faces the first region main surface 10 c and contacts the gate electrode 27. The second region 15 b has a surface 15 d that faces the second region main surface 10 d and is in contact with the gate electrode 27. Surface 15c of first region 15a is located farther from second main surface 10b of silicon carbide substrate 10 than surface 15d of second region 15b.

  Gate electrode 27 is arranged in contact with gate insulating film 15 so as to extend from one n + region 14 to the other n + region 14. Gate electrode 27 is arranged in contact with gate insulating film 15 so as to sandwich gate insulating film 15 between silicon carbide substrate 10. The gate electrode 27 is made of a conductor such as polysilicon or Al to which impurities are added.

  Source contact electrode 16 is arranged in contact with n + region 14, p + region 18, and gate insulating film 15. The source contact electrode 16 is made of a material capable of making ohmic contact with the n + region 14 such as NiSi (nickel silicide).

  Drain electrode 20 is formed in contact with second main surface 10b opposite to the side where drift layer 12 is formed in silicon carbide substrate 10. The drain electrode 20 is made of a material that can be in ohmic contact with the n-type base substrate 11 such as NiSi, and is electrically connected to the base substrate 11. A pad electrode 23 is disposed in contact with the drain electrode 20. The source contact electrode 16 and the drain electrode 20 are configured such that the current flowing between the source contact electrode 16 and the drain electrode 20 can be controlled by the gate electrode 27 applied to the gate electrode 27.

  The interlayer insulating film 21 is formed so as to contact the gate insulating film 15 and surround the gate electrode 27. Interlayer insulating film 21 is made of, for example, silicon dioxide which is an insulator. Source wiring 19 surrounds interlayer insulating film 21 on main surface 10 a of silicon carbide substrate 10 and extends to the upper surface of source contact electrode 16. Source wiring 19 is made of a conductor such as Al, and is electrically connected to n + region 14 via source contact electrode 16.

  Next, the operation of MOSFET 1 will be described. Referring to FIG. 1, when the voltage of gate electrode 27 is lower than the threshold voltage, that is, in the off state, the pn junction between well region 13 and first conductivity type region 17 located immediately below gate insulating film 15 is It becomes reverse bias and becomes non-conductive. On the other hand, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 27, an inversion layer is formed in the channel region in the vicinity of the well region 13 in contact with the gate insulating film 15. As a result, the n + region 14 and the first conductivity type region 17 are electrically connected, and a current flows between the source wiring 19 and the drain electrode 20.

  Next, an example of a method for manufacturing MOSFET 1 in the present embodiment will be described with reference to FIGS.

  First, a substrate preparation step (S10: FIG. 2) is performed. Specifically, referring to FIG. 3, base substrate 11 made of single crystal silicon carbide is prepared, and n-type (first conductivity type) drift layer 12 is formed on base substrate 11 by epitaxial growth. The drift layer 12 contains impurities such as N (nitrogen) ions. Thus, silicon carbide substrate 10 including drift layer 12 having a main surface 10a and having the first conductivity type is prepared.

  Next, a well region forming step (S20: FIG. 2) is performed. Specifically, referring to FIG. 4, for example, Al (aluminum) ions are implanted into drift layer 12 to form well region 13. Next, ion implantation for forming n <+> region 14 is performed. Specifically, for example, P (phosphorus) ions are implanted into the well region 13 to form an n + region 14 in the well region 13. Further, ion implantation for forming the p + region 18 is performed. Specifically, for example, Al ions are implanted into the well region 13 to form a p + region 18 in the well region 13 and in contact with the n + region 14. The ion implantation can be performed, for example, by forming a mask layer made of silicon dioxide on the main surface 10a of the drift layer 12 and having an opening in a desired region where ion implantation is to be performed.

  Next, an n-type region forming step (S30: FIG. 2) is performed. Specifically, referring to FIG. 5, for example, P (phosphorus) ions are implanted into first conductivity type region 17 sandwiched between a pair of well regions 13 and in contact with main surface 10a of silicon carbide substrate 10. Thereby, the n-type region 3 is formed. The first conductivity type region 17 is a JFET region. N-type region 3 is formed to extend from main surface 10a of silicon carbide substrate 10 toward second main surface 10b opposite to main surface 10a.

The n-type region 3 is preferably formed by ion implantation or diffusion. When the n-type region 3 is formed by ion implantation, for example, phosphorus ions having a dose of about 1 × 10 ¹² cm ⁻² are implanted into the first conductivity type region 17 with an energy of 15 keV to 25 ekV. When formation of n-type region 3 is performed by diffusion, a phosphorus supply source such as spin-on glass is disposed in contact with first conductivity type region 17 of silicon carbide substrate 10 by a method such as coating. Thereafter, for example, by heating silicon carbide substrate 10 on which spin-on-glass is disposed in an inert gas at 1300 ° C. for about 10 hours, phosphorus is diffused into first conductivity type region 17 of silicon carbide substrate 10 to thereby form n-type. Region 3 is formed.

  Referring to FIG. 8, when first conductivity type region 17 is p-type, well region 13 is n-type. The first conductivity type region 17 sandwiched between the pair of well regions 13 is p-type. The n-type region 3 is formed between a pair of n-type well regions 13 and in contact with the p-type first conductivity type region 17. When the first conductivity type region 17 is p-type, the impurity concentration of the n-type region 3 is higher than the impurity concentration of the well region 13.

  Referring to FIG. 9, when first conductivity type region 17 is n-type, well region 13 is p-type. The n-type region 3 is formed between a pair of p-type well regions 13 and in contact with the n-type first conductivity type region 17. When the first conductivity type region 17 is n-type, the impurity concentration of the n-type region 3 is higher than the impurity concentration of the first conductivity type region 17. The first conductivity type region 17 is a portion sandwiched between the pair of well regions 13 in the first conductivity type region 17. The impurity concentration of the n-type region 3 is lower than the impurity concentration of the first conductivity type region 17.

In both cases where the first conductivity type region is p-type or n-type, the impurity concentration of the n-type region 3 is preferably 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less. More preferably, the n-type region 3 has an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less. The thickness T3 of the n-type region 3 is, for example, 100 nm, and preferably 10 nm or more and 50 nm or less.

  As described above, the first conductivity type region 17 having the first conductivity type, the pair of well regions 13 having the second conductivity type different from the first conductivity type and sandwiching the first conductivity type region 17, and the pair of wells Silicon carbide substrate 10 including n type region 3 disposed between each of regions 13 and in contact with first conductivity type region 17 is prepared. Each of the pair of well regions 13 and n-type region 3 included in silicon carbide substrate 10 are formed exposed to main surface 10a of silicon carbide substrate 10. Main surface 10a of silicon carbide substrate 10 is a (0001) plane which is turned off by, for example, about 8 ° or less.

  In the above description, the n-type region forming step (S30) is performed after the well region forming step (S20). However, the well region forming step (S20) is performed after the n-type region forming step (S30). It doesn't matter. In this case, for example, the n-type region 3 is formed in the first conductivity type region 17 and then a pair of well regions 13 are formed so as to sandwich the n-type region 3 therebetween.

  Next, an activation annealing step is performed. Specifically, heat treatment is performed in which the silicon carbide substrate 10 is heated to, for example, about 1700 ° C. and held for about 30 minutes in an inert gas atmosphere such as argon. As a result, the implanted impurities are activated.

  Next, a gate insulating film formation step (S40: FIG. 2) is performed. Specifically, for example, heat treatment is performed in which main surface 10a of silicon carbide substrate 10 is heated to, for example, about 1200 ° C. or higher and about 1300 ° C. or lower and held for about 60 minutes in an oxygen atmosphere. Thereby, gate insulating film 15 made of silicon dioxide in contact with well region 13 and first conductivity type region 17 of silicon carbide substrate 10 is formed.

Referring to FIG. 6, gate insulating film 15 formed in contact with main surface 10a of silicon carbide substrate 10 includes first region 15a formed in contact with first conductivity type region 17 and a pair of well regions. 13 and a second region 15b formed in contact with each of the first and second regions 13b. The film thickness T1 of the first region 15a is larger than the film thickness T2 of the second region 15b. For example, when the n-type region 3 has an impurity concentration of about 1 × 10 ¹⁷ cm ⁻³ , the silicon carbide substrate 10 is heat-treated at 1300 ° C. for 50 minutes in an oxygen atmosphere to thereby obtain the n-type first conductivity type region. The thickness T1 of the first region 15a on the top 17 is about 55 nm, and the thickness of the second region 15b on the p-type well region is about 40 nm.

  Preferably, the film thickness T1 of the first region 15a is larger than the film thickness T2 of the second region 15b by 3 nm or more, more preferably 5 nm or more. Preferably, the thickness of the first region 15a is not less than 45 nm and not more than 70 nm. In the gate insulating film formation step (S40), preferably, n type region 3 formed in first conductivity type region 17 is completely oxidized. A part of the n-type region 3 may remain between the first region 15 a and the first conductivity type region 17.

  When main surface 10a of silicon carbide substrate 10 is oxidized to form gate insulating film 15, a region having a certain depth from main surface 10a of silicon carbide substrate 10 is oxidized to silicon dioxide. At this time, the thickness of silicon dioxide is about twice the thickness of the region of oxidized silicon carbide substrate 10.

  Thereafter, a nitrogen annealing step is performed. Specifically, silicon carbide substrate 10 is held at a temperature of 1300 ° C. or higher and 1500 ° C. or lower for about 1 hour in a nitrogen monoxide atmosphere. Thereafter, heat treatment for heating silicon carbide substrate 10 is performed in an inert gas such as argon or nitrogen. In the heat treatment, silicon carbide substrate 10 is held at a temperature of 1100 ° C. or higher and 1500 ° C. or lower for about 1 hour.

  Next, a gate electrode formation step (S50: FIG. 2) is performed. Specifically, referring to FIG. 7, gate electrode 27 made of polysilicon, which is a conductor doped with impurities at a high concentration, is formed by, for example, CVD, photolithography, and etching. Thereafter, an interlayer insulating film 21 made of silicon dioxide, which is an insulator, is formed so as to surround the gate electrode 27 by, for example, a CVD method. Next, the interlayer insulating film 21 and the gate insulating film 15 in the region where the source contact electrode 16 is formed are removed by photolithography and etching.

  Next, an ohmic electrode formation step (S60: FIG. 2) is performed. Specifically, for example, a metal film formed by vapor deposition is formed on main surface 10a of silicon carbide substrate 10 so as to be in contact with n + region 14 and p + region 18. The metal film is, for example, Ni (nickel). The metal film may contain, for example, Ti (titanium) atoms and Al (aluminum) atoms. The metal film may contain, for example, Ni atoms and Si (silicon) atoms. After the metal film is formed, the metal film is heated at, for example, about 1000 ° C., whereby the nickel film is heated and silicided, so that the source contact is brought into ohmic contact with the n + region 14 of the silicon carbide substrate 10. An electrode 16 is formed. Similarly, a metal film such as Ni is formed in contact with second main surface 10b of silicon carbide substrate 10, and drain electrode 20 is formed by heating the metal film.

  Next, the source wiring 19 made of Al as a conductor is formed so as to surround the interlayer insulating film 21 and to be in contact with the source contact electrode 16 by, for example, vapor deposition. Further, a pad electrode 23 made of, for example, Al is formed in contact with the drain electrode 20. With the above procedure, MOSFET 1 (see FIG. 1) according to the present embodiment is completed.

  In the present embodiment, the case where the first conductivity type is n-type and the second conductivity type is p-type has been described, but the present invention is not limited to this embodiment. For example, the first conductivity type may be p-type and the second conductivity type may be n-type.

  In the present embodiment, the vertical MOSFET has been described as an example of the silicon carbide semiconductor device, but the present invention is not limited to this embodiment. For example, the silicon carbide semiconductor device may be a lateral MOSFET, for example. The MOSFET may be a planar type or a trench type. Further, the silicon carbide semiconductor device may be an IGBT (Insulated Gate Bipolar Transistor) or the like.

  Next, the function and effect of MOSFET 1 and the method for manufacturing the same according to the present embodiment will be described.

  According to the method for manufacturing MOSFET 1 according to the present embodiment, n type region 3 including main surface 10a of silicon carbide substrate 10 is formed in first conductivity type region 17. When the first conductivity type is n-type, the impurity concentration of the n-type region 3 is higher than the impurity concentration of the first conductivity-type region 17. When the first conductivity type is p-type, the impurity concentration of the n-type region 3 is higher than the impurity concentration of the well region 13.

  When the first conductivity type is n-type, the well region 13 is p-type. The oxidation rate of the n-type region 3 having an impurity concentration higher than that of the first conductivity type region 17 is faster than the oxidation rate of the well region 13 which is a p-type region. Therefore, the thickness of the gate insulating film 15 on the first conductivity type region 17 is larger than the thickness of the gate insulating film 15 on the well region 13. When the first conductivity type is p-type, the well region 13 is n-type. The oxidation rate of the n-type region 3 having an impurity concentration higher than that of the well region 13 is faster than that of the well region 13. Therefore, the thickness of the gate insulating film 15 formed on the first conductivity type region 17 is larger than the thickness of the gate insulating film 15 on the well region 13.

  That is, regardless of whether the first conductivity type region 17 is n-type or p-type, the thickness of the gate insulating film 15 formed on the first conductivity type region 17 is equal to the thickness of the gate insulating film 15 on the well region 13. It becomes larger than the thickness. Therefore, it is possible to reduce the capacitance of the MOSFET 1 while suppressing the reduction of the drain current. As a result, it is possible to improve the switching characteristics of the MOSFET 1 while suppressing the reduction of the drain current.

  Further, according to the method for manufacturing MOSFET 1 according to the present embodiment, the first conductivity type is n-type. Thereby, MOSFET1 with high mobility can be obtained.

  Furthermore, according to the method for manufacturing MOSFET 1 according to the present embodiment, the step of forming n-type region 3 is performed by ion implantation or diffusion. Thereby, the n-type region 3 can be formed efficiently.

Furthermore, according to the method for manufacturing MOSFET 1 according to the present embodiment, the impurity concentration of n-type region 3 is not less than 1 × 10 ¹⁷ cm ^{−3 and not} more than 1 × 10 ²⁰ cm ⁻³ . Thereby, the thickness of the gate insulating film 15 on the first conductivity type region 17 can be sufficiently increased.

  Furthermore, according to the method for manufacturing MOSFET 1 according to the present embodiment, the thickness of n-type region 3 is not less than 10 nm and not more than 50 nm. If the thickness of the n-type region 3 is less than 10 nm, the thickness of the gate insulating film 15 on the first conductivity type region 17 is not sufficiently increased. If the thickness of the n-type region 3 is larger than 50 nm, the breakdown voltage is lowered because the n-type region 3 having a high impurity concentration remains in the first conductivity type region 17 even after the gate insulating film 15 is formed. By setting the thickness of the n-type region 3 to 10 nm or more and 50 nm or less, the thickness of the gate insulating film 15 can be sufficiently increased while suppressing a decrease in breakdown voltage.

  Furthermore, according to the method of manufacturing MOSFET 1 according to the present embodiment, the gate insulating film 15 includes the first region 15a in contact with the first conductivity type region 17 and the second region 15b in contact with each of the pair of well regions 13. Including. The film thickness of the first region is larger than the film thickness of the second region. Thereby, the electrostatic capacitance of the silicon carbide semiconductor device can be reduced while suppressing the reduction of the drain current.

  Furthermore, according to the method for manufacturing MOSFET 1 according to the present embodiment, the film thickness T1 of the first region 15a is larger than the film thickness T2 of the second region 15b by 3 nm or more. Thereby, the electrostatic capacitance of MOSFET1 can be reduced, suppressing the reduction | decrease of drain current efficiently.

  According to the MOSFET 1 according to the present embodiment, the gate insulating film 15 includes the first region 15a in contact with the first conductivity type region 17 and the second region 15b in contact with each of the pair of well regions 13. The film thickness T1 of the region 15a is larger than the film thickness T2 of the second region 15b. Thereby, the electrostatic capacitance of MOSFET1 can be reduced, suppressing the reduction | decrease of drain current. As a result, it is possible to improve the switching characteristics of the MOSFET 1 while suppressing the reduction of the drain current.

  Further, according to MOSFET 1 according to the present embodiment, silicon carbide substrate 10 has second main surface 10b opposite to main surface 10a. Main surface 10a of silicon carbide substrate 10 includes a first region main surface 10c in contact with first region 15a and a second region main surface 10d in contact with second region 15b. The first region main surface 10c is located closer to the second main surface 10b than the second region main surface 10d. Thereby, the capacitance of MOSFET 1 can be reduced by increasing the thickness of first region 15a.

  Furthermore, according to MOSFET 1 according to the present embodiment, the film thickness T1 of the first region 15a is larger than the film thickness T2 of the second region 15b by 3 nm or more. Thereby, the electrostatic capacitance of MOSFET1 can be reduced, suppressing the reduction | decrease of drain current efficiently.

  Furthermore, according to MOSFET 1 according to the present embodiment, film thickness T1 of first region 15a is not less than 45 nm and not more than 70 nm. When the film thickness T1 of the first region 15a is less than 45 nm, a leak current is likely to occur because the film thickness is thin. When the film thickness of the first region 15a exceeds 70 nm, the difference between the film thickness T1 of the first region 15a and the film thickness T2 of the second region 15b becomes large, and a large step between the first region 15a and the second region 15b. Can do. The electric field concentrates at the corner of the step, and a leak current is likely to occur. Therefore, the occurrence of leakage current can be suppressed by setting the film thickness of the first region to 45 nm or more and 70 nm or less.

  The embodiment disclosed this time is to be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 MOSFET, 3 n-type region, 10 silicon carbide substrate, 10a main surface, 10b second main surface, 10c first region main surface, 10d second region main surface, 11 base substrate, 12 drift layer, 13 well region, 14 n + region, 15 gate insulating film, 15a first region, 15b second region, 15c, 15d surface, 16 source contact electrode, 17 first conductivity type region (JFET region), 18 p + region, 19 source wiring, 20 drain electrode, 21 interlayer insulating film, 23 pad electrode, 27 gate electrode.

Claims (11)

Providing a silicon carbide substrate having a main surface;
The silicon carbide substrate includes a first conductivity type region having a first conductivity type, a pair of well regions having a second conductivity type different from the first conductivity type and sandwiching the first conductivity type region, An n-type region disposed between each of the pair of well regions and in contact with the first conductivity type region, and each of the pair of well regions and the n-type region included in the silicon carbide substrate includes the carbonized region. Formed exposed on the main surface of the silicon substrate, and
Forming a gate insulating film in contact with the well region and the first conductivity type region by oxidizing the main surface of the silicon carbide substrate;
When the first conductivity type is n-type, the impurity concentration of the n-type region is higher than the impurity concentration of the first conductivity type region,
A method for manufacturing a silicon carbide semiconductor device, wherein when the first conductivity type is p-type, the impurity concentration of the n-type region is higher than the impurity concentration of the well region.   The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the first conductivity type is an n-type.   The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the step of forming the n-type region is performed by ion implantation or diffusion. 4. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein an impurity concentration of the n-type region is 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less.   The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the n-type region has a thickness of 10 nm or more and 50 nm or less. The gate insulating film includes a first region in contact with the first conductivity type region, and a second region in contact with the pair of well regions,
The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the film thickness of the first region is larger than the film thickness of the second region.   The method for manufacturing a silicon carbide semiconductor device according to claim 6, wherein the film thickness of the first region is 3 nm or more larger than the film thickness of the second region. A silicon carbide substrate including a first conductivity type region having a main surface and having a first conductivity type;
A gate insulating film in contact with the main surface of the silicon carbide substrate,
The silicon carbide substrate includes a pair of well regions having a second conductivity type different from the first conductivity type and arranged to sandwich the first conductivity type region,
The gate insulating film includes a first region in contact with the first conductivity type region, and a second region in contact with each of the pair of well regions,
The silicon carbide semiconductor device, wherein the film thickness of the first region is larger than the film thickness of the second region. The silicon carbide substrate has a second main surface opposite to the main surface,
The main surface of the silicon carbide substrate includes a first region main surface in contact with the first region and a second region main surface in contact with the second region,
The silicon carbide semiconductor device according to claim 8, wherein the first region main surface is located closer to the second main surface than the second region main surface.   10. The silicon carbide semiconductor device according to claim 8, wherein a film thickness of said first region is 3 nm or more larger than a film thickness of said second region.   11. The silicon carbide semiconductor device according to claim 8, wherein a film thickness of said first region is not less than 45 nm and not more than 70 nm.

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