JP2014127660A - Silicon carbide diode, silicon carbide transistor, and method of manufacturing silicon carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide diode which can be reduced in contact resistance between a p-type region and an electrode, and to provide a silicon carbide transistor and a method of manufacturing a silicon carbide semiconductor device.SOLUTION: The method of manufacturing a silicon carbide semiconductor device 1 comprises the following steps of: preparing a silicon carbide substrate 10 including a p-type region 2a and an n-type region 14 being in contact with the p-type region 2a; heating the p-type region 2a in an atmospheric gas containing a halogen element to form a carbon region 6 being in contact with the p-type region 2a; forming a first metal layer 5 being in contact with the carbon region 6; and heating the carbon region 6 and the first metal layer 5 to form an electrode 8 being in contact with the p-type region 2a.

Description

  The present invention relates to a method for manufacturing a silicon carbide diode, a silicon carbide transistor, and a silicon carbide semiconductor device, and more specifically, a silicon carbide diode having a p-type region and an n-type region, a silicon carbide transistor, and a silicon carbide semiconductor. The present invention relates to a device manufacturing method.

  2. Description of the Related Art In recent years, silicon carbide has been increasingly used as a material for semiconductor devices in order to enable higher breakdown voltages, lower losses, and use in high-temperature environments for semiconductor devices such as MOSFETs (Metal Oxide Field Effect Transistors). It is being Silicon carbide is a wide band gap semiconductor having a larger band gap than silicon that has been widely used as a material for forming semiconductor devices. Therefore, by adopting silicon carbide as a material constituting the semiconductor device, it is possible to achieve a high breakdown voltage and a low on-resistance of the semiconductor device. In addition, a semiconductor device that employs silicon carbide as a material has an advantage that a decrease in characteristics when used in a high temperature environment is small as compared with a semiconductor device that employs silicon as a material.

  For example, in Japanese Patent Laid-Open No. 2001-85704 (Patent Document 1), silicon carbide in which an electrode in contact with the n-type region and the p-type region is formed on a silicon carbide substrate having an n-type region and a p-type region. A Schottky diode is disclosed. Japanese Unexamined Patent Application Publication No. 2009-16603 (Patent Document 2) discloses a junction barrier Schottky diode in which electrodes are formed on a silicon carbide substrate in which a plurality of p-type regions are formed.

JP 2001-85704 A JP 2009-16603 A

  However, it has been difficult to sufficiently reduce the contact resistance between the p-type region and the electrode in the silicon carbide semiconductor devices described in Japanese Patent Application Laid-Open Nos. 2001-85704 and 2009-16603.

  The present invention has been made in view of the above problems, and an object thereof is to provide a silicon carbide diode, a silicon carbide transistor, and a method for manufacturing a silicon carbide semiconductor device capable of reducing the contact resistance between a p-type region and an electrode. That is.

  The method for manufacturing a silicon carbide semiconductor device according to the present invention includes the following steps. A silicon carbide substrate including a p-type region and an n-type region in contact with the p-type region is prepared. By heating the p-type region in an atmospheric gas containing a halogen element, a carbon region in contact with the p-type region is formed. A first metal layer in contact with the carbon region is formed. An electrode in contact with the p-type region is formed by heating the carbon region and the first metal layer.

  According to the method for manufacturing a silicon carbide semiconductor device of the present invention, a carbon region is formed between the first metal layer and the p-type region, and the first metal layer and the carbon region are heated. By forming a carbon region having high electrical conductivity at the interface between the first metal layer and the p-type region, the contact resistance between the electrode and the p-type region can be reduced.

  In the silicon carbide semiconductor device according to the above, preferably, the halogen element is chlorine. Thereby, since silicon can be removed efficiently, a carbon region can be formed efficiently.

  Preferably, in the silicon carbide semiconductor device according to the above, in the step of forming the carbon region, the p-type region is heated at 800 ° C. or higher and 1000 ° C. or lower. When the p-type region is heated below 800 ° C., the formation time of the carbon region becomes long because the silicon removal rate is slow. On the other hand, when the p-type region is heated above 1000 ° C., the removal rate of silicon is too fast, and it becomes difficult to control the formation of the carbon region. By heating the p-type region at 800 ° C. or higher and 1000 ° C. or lower, the carbon region can be formed at a practical silicon removal rate.

  Preferably, in the silicon carbide semiconductor device according to the above, in the step of forming the carbon region, a recess is formed in the p-type region by etching a part of the p-type region, and the carbon region is in contact with the surface on which the recess is formed. Is formed. Thereby, a carbon region can be formed on the p-type region with high accuracy.

  Preferably, the silicon carbide semiconductor device according to the above further includes a step of forming a second metal layer in contact with the first metal layer. The silicon carbide substrate includes a second p-type region in contact with the second metal layer and not in contact with the carbon region. Thus, a silicon carbide semiconductor device including the second p-type region that is in contact with the second metal layer and not in contact with the carbon region can be manufactured.

  In the silicon carbide semiconductor device according to the above, preferably, the first metal layer is made of a material containing titanium and aluminum. Thereby, the contact resistance between the electrode and the p-type region can be efficiently reduced.

  Preferably, the silicon carbide semiconductor device according to the above further includes a step of forming a gate insulating film in contact with the n-type region. Thereby, a silicon carbide semiconductor device having a gate insulating film can be manufactured.

  A silicon carbide diode according to the present invention includes a silicon carbide substrate and an electrode. The silicon carbide substrate includes a p-type region and an n-type region in contact with the p-type region. The electrode is disposed in contact with the p-type region. The electrode includes a first electrode portion that is in Schottky junction with the n-type region, and a carbon region that is in contact with the p-type region. Thereby, the contact resistance between the electrode and the p-type region can be reduced. As a result, resistance to forward surge can be improved.

  Preferably, in the silicon carbide diode according to the above, the silicon carbide substrate further includes a second p-type region that is in contact with the first electrode portion and not in contact with the carbon region. Thereby, a silicon carbide diode including a second p-type region that is in contact with the first electrode portion and not in contact with the carbon region can be manufactured.

  Preferably, in the silicon carbide diode according to the above, the electrode further includes a second electrode portion in contact with the first electrode portion. The second electrode part includes a carbon region. Thereby, the contact resistance between the second electrode portion and the p-type region can be reduced.

  In the silicon carbide diode according to the above, preferably, the second electrode portion includes a material having titanium and aluminum. Thereby, the contact resistance between the second electrode portion and the p-type region can be efficiently reduced.

  A silicon carbide transistor according to the present invention includes a silicon carbide substrate, an electrode, and a gate insulating film. The silicon carbide substrate includes a p-type region and an n-type region in contact with the p-type region. The electrode is disposed in contact with the p-type region and the n-type region. The gate insulating film is in contact with the n-type region. The electrode includes a carbon region in contact with the p-type region. Thereby, the contact resistance between the electrode and the p-type region can be reduced. As a result, the switching speed of the silicon carbide transistor can be improved.

  Preferably, in the silicon carbide transistor according to the above, the silicon carbide substrate includes a first main surface on which the p-type region is disposed, and a second main surface opposite to the first main surface. A second p-type region different from the p-type region is included in contact with the second main surface. Thereby, a silicon carbide transistor including a second p-type region different from the p-type region in contact with the second main surface can be obtained.

  In the silicon carbide transistor according to the above, preferably, the electrode includes any of a material having nickel and silicon and a material having titanium, aluminum, and silicon. Thereby, the contact resistance between the electrode and the p-type region can be efficiently reduced.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the silicon carbide diode which can reduce the contact resistance of a p-type area | region and an electrode, a silicon carbide transistor, and a silicon carbide semiconductor device can be provided.

1 is a schematic cross-sectional view schematically showing a structure of silicon carbide MPS (Merged Pin Schottky diode) according to Embodiment 1 of the present invention. It is a flowchart which shows schematically the manufacturing method of MPS which concerns on Embodiment 1 of this invention. It is a cross-sectional schematic diagram which shows schematically the 1st process of the manufacturing method of silicon carbide MPS which concerns on Embodiment 1 of this invention. It is a cross-sectional schematic diagram which shows schematically the 2nd process of the manufacturing method of silicon carbide MPS which concerns on Embodiment 1 of this invention. It is a cross-sectional schematic diagram which shows schematically the 3rd process of the manufacturing method of silicon carbide MPS which concerns on Embodiment 1 of this invention. FIG. 6 is an enlarged view of a region VI in FIG. 5. It is a cross-sectional schematic diagram which shows schematically the structure of the silicon carbide MOSFET which concerns on Embodiment 2 of this invention. It is a cross-sectional schematic diagram which shows schematically the 1st process of the manufacturing method of the silicon carbide MOSFET which concerns on Embodiment 2 of this invention. It is a cross-sectional schematic diagram which shows schematically the 2nd process of the manufacturing method of silicon carbide MOSFET which concerns on Embodiment 2 of this invention. It is a cross-sectional schematic diagram which shows schematically the 3rd process of the manufacturing method of the silicon carbide MOSFET which concerns on Embodiment 2 of this invention. It is a cross-sectional schematic diagram which shows roughly the structure of silicon carbide IGBT (Insulated Gate Bipolar Transistor) concerning Embodiment 3 of this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated. In the crystallographic description in this specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. As for the negative index, “−” (bar) is attached on the number in crystallography, but in this specification, a negative sign is attached before the number. The angle is described using a system in which the omnidirectional angle is 360 degrees.
(Embodiment 1)
First, the structure of MPS which is a silicon carbide diode according to the first embodiment of the present invention will be described with reference to FIG.

  As shown in FIG. 1, MPS 1 of the present embodiment mainly has silicon carbide substrate 10, electrode 8, ohmic electrode 30, and protective film 70. Silicon carbide substrate 10 is made of, for example, polytype 4H hexagonal silicon carbide and has n-type. Silicon carbide substrate 10 has a first main surface 10a and a second main surface 10b facing each other.

Silicon carbide substrate 10 includes a JTE (Junction Termination Extension) region 3, a field stop region 7, an n + substrate 11, an electric field stop layer 12, an n-type region 14, and a p-type region 2. The JTE region 3 is a p-type region into which impurities such as aluminum (Al) and boron (B) are ion-implanted. The impurity concentration of the p-type region is, for example, about 2 × 10 ¹⁷ cm ⁻³ . Silicon carbide substrate 10 has field stop region 7 so as to surround JTE region 3 when viewed from the normal direction of first main surface 10a. Field stop region 7 is an n + type region into which, for example, phosphorus (P) is ion-implanted. The impurity concentration in the field stop region is higher than the impurity concentration in the n-type region 14.

N + substrate 11 contains a single-crystal silicon carbide substrate containing impurities such as nitrogen (N). The impurity concentration contained in the n + substrate is, for example, about 5 × 10 ¹⁸ cm ⁻³ . The concentration of impurities such as nitrogen contained in the electric field stop layer 12 is, for example, about 5 × 10 ¹⁷ cm ⁻³ or more and about 1 × 10 ¹⁸ cm ⁻³ or less. The impurity concentration in n-type region 14 is, for example, 1 × 10 ¹⁶ cm ⁻³ . The impurity concentration of aluminum or the like in the p-type region 2 is, for example, about 1 × 10 ¹⁹ cm ⁻³ . N-type region 14 is in contact with p-type region 2. P type region 2 extends from first main surface 10a of silicon carbide substrate 10 toward second main surface 10b. The p-type region 2 is formed between the n-type regions 14.

  The p-type region 2 includes a first p-type region 2a in contact with a carbon region 6 of the second electrode portion 8a described later, and a second p-type region in contact with the first electrode portion 8b and not in contact with the carbon region 6. 2b and a third p-type region 2c in contact with the first electrode portion 8b and sandwiched between the JTE regions 3.

  Electrode 8 is provided on first main surface 10a of silicon carbide substrate 10, and includes first p-type region 2a, second p-type region 2b, third p-type region 2c, and n-type region. 14 and the JTE region 3. The electrode 8 includes a first electrode portion 8b that is in Schottky junction with the n-type region 14, and a second electrode portion 8a that is in contact with the first electrode portion 8b. The first electrode portion 8b is made of, for example, titanium (Ti). In addition to titanium, for example, nickel (Ni), titanium nitride (TiN), gold (Au), molybdenum (Mo), tungsten (W), or the like may be used as the first electrode portion 8b.

  Second electrode portion 8a includes first metal layer 5 and carbon region 6 in contact with first p-type region 2a. First metal layer 5 includes, for example, titanium (Ti) and aluminum (Al). The first metal layer 5 may be a TiAl alloy. The first metal layer 5 and the carbon region 6 may be integrated into an alloy containing Ti, Al, and C (carbon). The second electrode portion 8a has a region with a high carbon concentration in contact with the first p-type region 2a, and has a carbon concentration distribution such that the carbon concentration decreases as the distance from the surface 23 increases. It doesn't matter. Preferably, the second electrode portion 8a has a good ohmic junction with the first p-type region 2a.

  In the present embodiment, the electrode 8 includes a second electrode portion 8a and a first electrode portion 8b, and the second electrode portion 8a includes the first metal layer 5 and the carbon region 6. However, the first metal layer 5 may be omitted. In this case, the electrode 8 includes the first electrode portion 8 b and the carbon region 6. The first electrode portion 8 b is in contact with the carbon region 6. The first electrode portion 8b and the carbon region 6 may be integrated into an alloy. A part of the first electrode portion 8 b and the first p-type region 2 a have a good ohmic junction via the carbon region 6. That is, the first electrode portion 8 b has a portion that forms a Schottky junction with the n-type region 14 and a portion that forms an ohmic junction with the first p-type region 2 a via the carbon region 6.

  The carbon region 6 may exist alone in a state of graphite, graphene, or the like, or may be diffused into a metal layer that forms an adjacent electrode portion to form an alloy. Carbon region 6 has a region with a high carbon concentration in contact with adjacent first p-type region 2a, and has a carbon concentration distribution such that the carbon concentration decreases with distance from first p-type region 2a. It does not matter.

  Referring to FIG. 1, pad electrode 60 is formed in contact with electrode 8. The pad electrode 60 is made of aluminum, for example. A protective film 70 is formed in contact with pad electrode 60, electrode 8, and first main surface 10 a of silicon carbide substrate 10. An ohmic electrode 30 is disposed in contact with the n + substrate 11. The ohmic electrode 30 is made of nickel, for example. Further, a pad electrode 40 made of, for example, titanium, nickel, silver or an alloy made of these is disposed in contact with the ohmic electrode 30.

  Next, the manufacturing method of MPS1 which is a silicon carbide diode which concerns on embodiment of this invention is demonstrated with reference to FIGS.

Referring to FIG. 3, first, a substrate preparation step (S10: FIG. 2) is performed. Specifically, for example, by slicing an ingot (not shown) made of hexagonal silicon carbide having a polytype of 4H, n + substrate 11 having n type conductivity is prepared. The n + substrate contains impurities such as nitrogen (N). The impurity concentration contained in the n + substrate is, for example, about 5 × 10 ¹⁸ cm ⁻³ .

Next, the electric field stop layer 12 is formed on the n + substrate 11. Electric field stop layer 12 is an n-type silicon carbide layer. The concentration of impurities such as nitrogen contained in the electric field stop layer 12 is, for example, about 5 × 10 ¹⁷ cm ⁻³ or more and about 1 × 10 ¹⁸ cm ⁻³ or less. Thereafter, an n-type region 14 having an n-type conductivity is formed on the electric field stop layer 12 by epitaxial growth.

Next, an ion implantation process is performed. For example, Al (aluminum) ions are implanted into the n-type region 14, whereby the JTE region 3, the first p-type region 2 a, the second p-type region 2 b, and the third p-type conductivity type. A mold region is formed. The impurity concentration of JTE region 3 is, for example, about 2 × 10 ¹⁷ cm ⁻³ . The impurity concentration of the first p-type region 2a, the second p-type region 2b, and the third p-type region is, for example, about 1 × 10 ¹⁹ cm ⁻³ . Similarly, for example, P (phosphorus) or the like is implanted into n-type region 14 to form field stop region 7. The impurity concentration in the field stop region is higher than the impurity concentration in the n-type region 14.

  As described above, the n + substrate 11, the electric field stop layer 12, the n-type region 14, the first p-type region 2a, the second p-type region 2b, and the third p-type region 2c, A silicon carbide substrate 10 including JTE region 3 and field stop region 7 and having first main surface 10a and second main surface 10b facing each other is prepared.

  Next, an activation annealing step (S20: FIG. 2) is performed. Specifically, for example, by heating silicon carbide substrate 10 at a temperature of about 1800 ° C. in an inert gas atmosphere such as argon, first p-type region 2a, second p-type region 2b, Third p-type region 2c, JTE region 3 and field stop region 7 are annealed, and the impurities introduced in the ion implantation step are activated. As a result, desired carriers are generated in the region where the impurity is introduced.

  Next, a thermal oxide film forming step (S30: FIG. 2) is performed. Specifically, thermal oxide film is formed on the entire surface of first main surface 10a of silicon carbide substrate 10 by heating silicon carbide substrate 10 in an oxygen atmosphere. The thermal oxide film is made of, for example, silicon dioxide. Thereafter, referring to FIG. 4, the thermal oxide film is etched so that surface 10c of first p-type region 2a is exposed. Thus, silicon carbide in which surface 10c of first p-type region 2a is exposed and second p-type region 2b, third p-type region, JTE region 3 and field stop region 7 are covered with a thermal oxide film. A substrate 10 is formed.

  Next, a carbon region forming step (S40: FIG. 2) is performed. Specifically, silicon carbide substrate 10 including first p-type region 2a is heated in an atmospheric gas containing a halogen element. The halogen element is, for example, fluorine, chlorine and bromine, and preferably chlorine. The atmospheric gas preferably does not contain oxygen gas. The atmosphere gas may contain a carrier gas. As the carrier gas, for example, nitrogen gas, argon gas or helium gas can be used. Heating of silicon carbide substrate 10 is performed at about 800 ° C. or higher and about 1000 ° C. or lower, for example.

  Referring to FIG. 5, by heating surface 10c of first p-type region 2a of silicon carbide substrate 10 in the above atmospheric gas, silicon carbide constituting surface 10c of first p-type region 2a is heated. , Silicon is preferentially etched, and carbon is left on the surface 10c to form a carbon region 6. If the atmosphere gas contains a large amount of oxygen gas, silicon on the surface 10c becomes silicon dioxide, and it is difficult to selectively etch silicon. In other words, when the oxygen gas concentration in the atmospheric gas is low, silicon on the surface 10c is preferentially etched, and the carbon region 6 in contact with the surface 10c of the first p-type region 2a is likely to be formed. Preferably, the oxygen gas concentration in the atmospheric gas is 1% or less.

  Referring to FIG. 5, in the carbon region forming step, a recess 22 is formed in first p-type region 2a by etching a part of first p-type region 2a. Carbon region 6 is formed in contact with bottom wall surface 23 forming the recess of first p-type region 2a. Referring to FIG. 6, carbon region 6 is formed in contact with side wall surface 24 and bottom wall surface 23 that form recess 22. The carbon region 6 may be in contact with the contact point between the side wall surface 24 forming the recess 22 and the first main surface 10a. The carbon region 6 may be formed so that the thickness closer to the side wall surface 24 is thicker than the central portion of the bottom wall surface 23. The carbon region 6 may be formed in contact with the entire surface of the side wall surface 24 and the bottom wall surface 23 that form the recess 22.

  Next, an electrode formation step (S50: FIG. 2) is performed. Specifically, referring to FIG. 1, first metal layer 5 containing, for example, titanium (Ti) and Al (aluminum) is formed in contact with carbon region 6. Next, a second metal layer 8b containing, for example, titanium (Ti), nickel (Ni), molybdenum (Mo), tungsten (W), titanium nitride (TiN) or the like is formed into the first p-type region 2a and the first p-type region 2a. 2 p-type region 2 b, third p-type region, JTE region 3, and first metal layer 5. After the first metal layer 5 is formed, the first metal layer 5 and the carbon region 6 are heated to about 1000 ° C. by laser annealing, for example. After the second metal layer 8b is formed, the second metal layer 8b is heated to about 300 ° C. or lower and about 500 ° C. or higher by laser annealing, for example. As a result, the electrode 8 including the second electrode portion 8a that is in ohmic contact with the first p-type region 2a and the first electrode portion 8b that is in Schottky junction with the n-type region 14 is formed. The formation of the first metal layer 5 may be omitted. In this case, the second metal layer 8 b is formed in contact with the carbon region 6.

  Next, an ohmic electrode forming step is performed. Specifically, second main surface 10b of silicon carbide substrate 10 is ground, and ohmic electrode 30 made of, for example, nickel is formed in contact with second main surface 10b. Thereafter, a pad electrode 40 made of, for example, titanium, nickel, silver or an alloy made of them is formed in contact with the ohmic electrode 30.

Next, a protective film forming step is performed. Specifically, protective film 70 in contact with pad electrode 60, electrode 8, and first main surface 10a of silicon carbide substrate 10 is formed, for example, by plasma CVD (Chemical Vapor Deposition). The protective film 70 is made of, for example, silicon dioxide (SiO ₂ ), silicon nitride (SiN), or a laminated film thereof. Thereby, MPS1 as a silicon carbide diode shown in FIG. 1 is completed.

Next, the operational effects of the MPS 1 and the manufacturing method thereof according to Embodiment 1 will be described.
According to the method of manufacturing MPS 1 according to the present embodiment, carbon region 6 is formed between first metal layer 5 and first p-type region 2a, and first metal layer 5 and carbon region 6 are Is heated. By forming the carbon region 6 having high electrical conductivity at the interface between the first metal layer 5 and the first p-type region 2a, the contact resistance between the electrode and the p-type region can be reduced.

  Moreover, according to the manufacturing method of MPS1 which concerns on this Embodiment, a halogen element is chlorine. Thereby, since silicon can be removed efficiently, the carbon region 6 can be formed efficiently.

  Furthermore, according to the method for manufacturing MPS 1 according to the present embodiment, in the step of forming carbon region 6, first p-type region 2 a is heated at 800 ° C. or higher and 1000 ° C. or lower. When the first p-type region 2a is heated at less than 800 ° C., the formation time of the carbon region 6 becomes long because the silicon removal rate is slow. On the other hand, when the first p-type region 2a is heated above 1000 ° C., the removal rate of silicon is too fast, and it becomes difficult to control the formation of the carbon region 6. By heating first p-type region 2a at 800 ° C. or higher and 1000 ° C. or lower, carbon region 6 can be formed at a practical silicon removal rate.

  Furthermore, according to the method of manufacturing MPS 1 according to the present embodiment, in the step of forming carbon region 6, recess 22 is formed in first p-type region 2 a by etching part of first p-type region 2 a. The carbon region 6 is formed in contact with the bottom wall surface 23 and the side wall surface 24 that form the recess 22.

  Furthermore, according to the manufacturing method of MPS1 which concerns on this Embodiment, it has further the process of forming the 2nd metal layer 8b which contact | connects the 1st metal layer 5. FIG. Silicon carbide substrate 10 includes a second p-type region 2 b that contacts second metal layer 8 b and does not contact carbon region 6. Thereby, MPS1 including the second p-type region 2b in contact with the second metal layer 8b and not in contact with the carbon region 6 can be manufactured.

  Furthermore, according to the manufacturing method of MPS1 which concerns on this Embodiment, the 1st metal layer 5 consists of material containing titanium and aluminum. Thereby, the contact resistance between the electrode 8 and the first p-type region 2a can be efficiently reduced.

  According to the MPS 1 according to the present embodiment, the electrode 8 includes the first electrode portion 8b that is in Schottky junction with the n-type region 14 and the carbon region 6 that is in contact with the first p-type region 2a. Thereby, the contact resistance between the electrode 8 and the first p-type region 2a can be reduced. As a result, resistance to forward surge can be improved.

  Moreover, according to MPS1 according to the present embodiment, silicon carbide substrate 10 further includes second p-type region 2b that is in contact with first electrode portion 8b and not in contact with carbon region 6. Thereby, MPS1 containing the 2nd p-type area | region 2b which is in contact with the 1st electrode part 8b and is not in contact with the carbon area | region 6 can be manufactured.

  Furthermore, according to MPS1 according to the present embodiment, the electrode 8 further includes a second electrode portion 8a in contact with the first electrode portion 8b. The second electrode portion 8 a includes the carbon region 6. Thereby, the contact resistance between the second electrode portion 8a and the first p-type region 2a can be reduced.

Furthermore, according to MPS1 according to the present embodiment, second electrode portion 8a includes a material having titanium and aluminum. Thereby, the contact resistance between the second electrode portion 8a and the first p-type region 2a can be efficiently reduced.
(Embodiment 2)
First, the structure of MOSFET as a silicon carbide transistor according to the second embodiment of the present invention will be described.

  Referring to FIG. 7, MOSFET 101 according to the present embodiment includes silicon carbide substrate 110, gate insulating film 115, gate electrode 127, source electrode 108, drain electrode 130, source wiring 119, and back surface protection. The electrode 140 is mainly included.

  Silicon carbide substrate 110 is made of, for example, polytype 4H hexagonal silicon carbide, and has a first main surface 110a and a second main surface 110b facing each other. Silicon carbide substrate 110 mainly includes base substrate 111, drift region 112, first impurity region 117, well region 113, second impurity region 114, and p + region 102.

Base substrate 111 is made of hexagonal silicon carbide, for example, and has an n-type conductivity type. Base substrate 111 contains an impurity such as N (nitrogen) at a high concentration. The concentration of impurities such as nitrogen contained in the base substrate 111 is, for example, about 1.0 × 10 ¹⁸ cm ⁻³ .

Drift region 112 and first impurity region 117 are epitaxial layers made of hexagonal silicon carbide and having n-type. The first impurity region 117 is a region sandwiched between the pair of well regions 113. The impurity contained in drift region 112 and first impurity region 117 is, for example, nitrogen. The impurity concentration in drift region 112 and first impurity region 117 is lower than the impurity concentration in base substrate 111. The concentration of impurities such as nitrogen contained in drift region 112 and first impurity region 117 is, for example, about 7.5 × 10 ¹⁵ cm ⁻³ .

The well region 113 is a region having a p-type different from the n-type. Impurities contained in the well region 113 are, for example, Al (aluminum), B (boron), and the like. Preferably, the concentration of impurities such as aluminum contained in the well region 113 is about 1 × 10 ¹⁷ cm ⁻³ or more and about 1 × 10 ¹⁸ cm ⁻³ or less.

The second impurity region 114 is an n-type source region. The second impurity region is separated from first impurity region 117 and drift region 112 by well region 113. The second impurity region 114 is formed in the well region 113 so as to include the first main surface 110 a and be surrounded by the well region 113. Second impurity region 114 contains an impurity such as P (phosphorus) at a concentration of about 1 × 10 ²⁰ cm ⁻³ , for example. The concentration of impurities contained in the second impurity region 114 is higher than the concentration of impurities contained in the drift region 112.

The p + region 102 is a region having p type. The p + region 102 is formed so as to contact the well region 113 and penetrate the vicinity of the center of the second impurity region 114. The p + region 102 contains impurities such as aluminum and boron at a concentration of about 1 × 10 ²⁰ cm ⁻³ , for example. The impurity concentration contained in the p + region 102 is higher than the impurity concentration contained in the well region 113.

  The gate insulating film 115 extends from the upper surface of one second impurity region 114 to the upper surface of the other second impurity region 114, so that the first impurity region 117, the well region 113, and the second impurity region 114 are extended. It is formed in contact with the impurity region 114. Gate insulating film 115 is made of, for example, silicon dioxide. Preferably, the thickness of the gate insulating film 115 (the distance of the gate insulating film along the normal direction of the first main surface 110a) is about 45 nm or more and about 55 nm or less.

  Gate electrode 127 is arranged in contact with gate insulating film 115 so as to extend from one second impurity region 114 to the other second impurity region 114. Gate electrode 127 is made of a conductor such as polysilicon or aluminum.

  The source electrode 108 includes a first metal layer 104 and a carbon region 106. Carbon region 106 of source electrode 108 includes p + region 102 and second impurities on bottom wall surface 123 forming recess 22 (see FIG. 10) formed by etching first main surface 10a of silicon carbide substrate 10. It is in contact with the region 114. The source electrode 108 may be an alloy layer formed by diffusing the carbon region 106 into the first metal layer 104. Source electrode 108 is in contact with gate insulating film 115, second impurity region 114, and p + region 102. Preferably, source electrode 108 includes either a material having nickel and silicon and a material having titanium, aluminum and silicon. The source electrode 108 is in ohmic contact with the p + region 102.

  The carbon region 6 may exist by itself in a state of graphite, graphene, or the like, or may be diffused into the first metal layer 104 that forms the adjacent source electrode 108 to form an alloy. Carbon region 6 may have a carbon concentration distribution that has a region with a high carbon concentration in contact with adjacent p + region 102 and has a carbon concentration that decreases with distance from p + region 102.

  Drain electrode 130 is formed in contact with second main surface 110b of silicon carbide substrate 110. The drain electrode 130 may have the same configuration as that of the source electrode 108, for example, or may be made of another material that can make ohmic contact with the base substrate 111, such as Ni. Thereby, the drain electrode 130 is electrically connected to the base substrate 111. A back surface protective electrode 140 containing, for example, titanium, nickel and silver is disposed in contact with the drain electrode 130.

  The interlayer insulating film 121 is formed so as to be in contact with the gate insulating film 115 and surround the gate electrode 127. Interlayer insulating film 121 is made of, for example, silicon dioxide which is an insulator. Source wiring 119 surrounds interlayer insulating film 121 and is in contact with source electrode 108 above first main surface 110 a of silicon carbide substrate 110. Source wiring 119 is made of a conductor such as Al, and is electrically connected to second impurity region 114 via source electrode 108.

Next, a method for manufacturing MOSFET 101 according to the present embodiment will be described.
Referring to FIG. 8, first, silicon carbide substrate 110 is prepared by a substrate preparation step (S10: FIG. 2). Specifically, drift region 112 is formed on one main surface of base substrate 111 made of hexagonal silicon carbide by epitaxial growth. Epitaxial growth can be carried out, for example, using a mixed gas of SiH ₄ (silane) and C ₃ H ₈ (propane) as a raw material gas. At this time, for example, N (nitrogen) is introduced as an impurity. As a result, the drift region 112 containing impurities having a lower concentration than the impurities contained in the base substrate 111 is formed.

  Next, an oxide film made of silicon dioxide is formed on first main surface 110a of silicon carbide substrate 110 by, for example, CVD. Then, after a resist is applied on the oxide film, exposure and development are performed, and a resist film having an opening in a region corresponding to the shape of the desired well region 113 is formed. Then, using the resist film as a mask, the oxide film is partially removed by, for example, RIE (Reactive Ion Etching), thereby forming a mask made of an oxide film having an opening pattern on the drift region 112. A layer is formed.

  Next, an ion implantation process is performed. In the ion implantation step, ions are implanted into first main surface 110a of silicon carbide substrate 110, so that well region 113, second impurity region 114, and p + region 102 are formed. Specifically, after removing the resist film, an impurity such as Al is ion-implanted into the drift region 112 using the mask layer as a mask, whereby the well region 113 is formed. The second impurity region 114 is formed by introducing an n-type impurity such as P (phosphorus) into the drift region 112 by ion implantation. Next, impurities such as Al and B are introduced into the drift region 112 by ion implantation, whereby the p + region 102 is formed.

  Next, an activation annealing step (S20: FIG. 2) is performed. A heat treatment for activating the impurities introduced by the ion implantation is performed. Specifically, silicon carbide substrate 110 on which ion implantation has been performed is heated to, for example, about 1700 ° C. in an Ar (argon) atmosphere and held for about 30 minutes.

  Next, a thermal oxide film forming step (S30: FIG. 2) is performed. Specifically, referring to FIG. 9, first, silicon carbide substrate 110 on which an ion implantation region is formed is thermally oxidized. Thermal oxidation can be carried out, for example, by heating to about 1300 ° C. in an oxygen atmosphere and holding for about 40 minutes. Thereby, gate insulating film 115 made of silicon dioxide is formed on first main surface 110a of silicon carbide substrate 110.

Next, a gate electrode formation step is performed. Specifically, referring to FIG. 10, gate electrode 127 made of, for example, polysilicon, which is a conductor, or the like extends from one second impurity region 114 to the other second impurity region 114. It extends to be in contact with the gate insulating film 115. When polysilicon is employed as the material of the gate electrode 127, the polysilicon may contain phosphorus at a high concentration exceeding 1 × 10 ²⁰ cm ⁻³ . Thereafter, interlayer insulating film 121 made of, for example, silicon dioxide is formed so as to cover gate electrode 127.

  Next, a carbon region forming step (S40: FIG. 2) is performed. The carbon region forming step of the present embodiment is performed by the same method as the carbon region forming step described in the first embodiment. Referring to FIG. 10, gate insulating film 115 and interlayer insulating film 121 are removed so that p + region 102 and part of second impurity region 114 are exposed. Silicon carbide substrate 10 in which p + region 102 and part of second impurity region 114 are exposed is heated in an atmospheric gas containing a halogen element. The halogen element is, for example, fluorine, chlorine and bromine, and preferably chlorine. The atmospheric gas preferably does not contain oxygen gas. The atmosphere gas may contain a carrier gas. As the carrier gas, for example, nitrogen gas, argon gas or helium gas can be used. Heating of silicon carbide substrate 10 is performed at about 800 ° C. or higher and about 1000 ° C. or lower, for example.

  By heating the surfaces of the p + region 102 and the second impurity region of the silicon carbide substrate 10 in the above atmospheric gas, silicon is preferentially included in the silicon carbide constituting the surface of the first p-type region 2a. Etching is performed to leave carbon on the surface and form a carbon region 106. If the atmosphere gas contains a large amount of oxygen gas, the silicon on the surface becomes silicon dioxide, and it is difficult to selectively etch silicon. In other words, when the oxygen gas concentration in the atmospheric gas is low, silicon on the surface is preferentially etched, and the carbon region 6 in contact with the surfaces of the p + region 102 and the second impurity region 114 is likely to be formed. As described above, the p + region 102 and the second impurity region 114 are partially removed to form the recess 22, and the carbon region 106 in contact with the surface 123 that forms the recess 22 is formed.

  Next, an electrode formation step (S50: FIG. 2) is performed. Specifically, referring to FIG. 7, for example, first metal layer 104 made of a material containing nickel and silicon is formed in contact with carbon region 106. The first metal layer 104 may be a material including titanium, aluminum, and silicon. Similarly, drain electrode 130 in contact with second main surface 10b of silicon carbide substrate 10 is formed. The material forming the drain electrode 130 may be a material containing nickel and silicon, or may be a material containing titanium, aluminum and silicon. Thereafter, silicon carbide substrate 10 including first metal layer 104 and carbon region 106 is heated to about 1000 ° C., so that source electrode 108 that is in ohmic contact with p + region 102 of silicon carbide substrate 110 is formed. A source wiring 119 made of, for example, aluminum is formed in contact with the source electrode 108. In addition, back surface protective electrode 140 including, for example, titanium, nickel, and silver is formed. As described above, the MOSFET 101 shown in FIG. 1 is completed.

  In the present embodiment, a planar MOSFET has been described as an example of the silicon carbide transistor. However, the silicon carbide transistor may be a trench MOSFET.

  Next, the function and effect of MOSFET 101 and its manufacturing method according to the present embodiment will be described.

  The MOSFET 101 according to the present embodiment further includes a step of forming the gate insulating film 115 in contact with the second impurity region 114. Thereby, the MOSFET 101 having the gate insulating film 115 can be manufactured.

  Further, according to MOSFET 101 according to the present embodiment, source electrode 108 includes carbon region 106 in contact with p + region 102. Thereby, the contact resistance between the source electrode 108 and the p + region 102 can be reduced. As a result, the switching speed of the MOSFET 101 can be improved.

Furthermore, according to MOSFET 101 according to the present embodiment, source electrode 108 includes any one of a material having nickel and silicon and a material having titanium, aluminum, and silicon. Thereby, the contact resistance between the source electrode 108 and the p + region 102 can be efficiently reduced.
(Embodiment 3)
Next, the configuration of the IGBT as the silicon carbide transistor according to the third embodiment of the present invention will be described.

  Referring to FIG. 11, IGBT 201 of the present embodiment is an n-channel IGBT having a planar gate structure, and includes silicon carbide substrate 210, gate insulating film 215, gate electrode 227, interlayer insulating film 221, It mainly includes an emitter contact electrode 208, an emitter wiring 219, a collector electrode 230, and a collector wiring 240.

  Silicon carbide substrate 210 has a first main surface 210a and a second main surface 210b facing each other, and collector layer 211, drift layer 212, well region 213, emitter region 214, and p + region 202. Including. Collector layer 211 is a p-type region (second p-type region) disposed in contact with second main surface 210b of silicon carbide substrate 210. Each of collector layer 211, drift layer 212, well region 213, emitter region 214, and p + region 202 is made of hexagonal silicon carbide, and preferably has a crystal structure of polytype 4H. Each of collector layer 211, well region 213, and p + region 202 has a p-type, and each of drift layer 212 and emitter region 214 has an n-type. The impurity concentration of the emitter region 214 is higher than the impurity concentration of the drift layer 212. The impurity concentration of p + region 202 is higher than the impurity concentration of well region 213. The acceptor impurity for imparting p-type is, for example, aluminum (Al) or boron (B). The donor impurity for imparting n-type is, for example, nitrogen (N) or phosphorus (P).

The acceptor impurity contained in the collector layer 211 is introduced during the epitaxial growth of the collector layer 211, and the acceptor impurity concentration is preferably 1 × 10 ¹⁷ cm ³ or more and 1 × 10 ²¹ cm ³ or less, more preferably 1 It is not less than × 10 ¹⁹ cm ^{3 and not} more than 1 × 10 ²⁰ cm ³ . The thickness of the collector layer 211 is preferably 5 μm or more.

  The drift layer 212 is provided in contact with the collector layer 211. The thickness of the drift layer 212 is preferably 75 μm or more. The well region 213 is provided on the drift layer 212. The emitter region 214 is provided on the well region 213 so as to be separated from the drift layer 212 by the well region 213. The p + region 202 is provided in contact with the emitter region 214 and the well region 213.

  The gate insulating film 215 is provided on the well region 213 so as to connect the drift layer 212 and the emitter region 214. The surface of well region 213 facing gate insulating film 215 (that is, first main surface 210a of silicon carbide substrate 210) is preferably a {0-33-8} surface, and more preferably (0-33-). 8) Surface. The first main surface 210a may be a surface having an off angle of 62 ° ± 10 ° macroscopically with respect to the {000-1} plane. Gate insulating film 215 is, for example, a silicon dioxide film. The gate electrode 227 is provided on the gate insulating film 215. The gate electrode 227 is made of a conductor, for example, polysilicon made of impurities or aluminum (Al).

  The emitter contact electrode 208 includes a first metal layer 204 and a carbon region 206. Carbon region 106 of emitter contact electrode 208 is in contact with p + region 202 and emitter region 214 at bottom wall surface 223 that forms a recess. The emitter contact electrode 208 may be an alloy layer formed by diffusing the carbon region 206 into the first metal layer 204. The emitter contact electrode 208 is in contact with the gate insulating film 215. The emitter contact electrode 208 is an electrode that is ohmically connected to each of the emitter region 214 and the p + region 202, and is preferably made of silicide, for example, nickel silicide. The emitter contact electrode 208 may be a material including titanium, aluminum, and silicon. The emitter contact electrode 208 has a configuration similar to that of the source electrode 108 of the second embodiment.

  Emitter wiring 219 is provided on each of emitter contact electrode 208 and interlayer insulating film 221. The interlayer insulating film 221 is provided so as to electrically insulate between the gate electrode 227 and the emitter wiring 219. Interlayer insulating film 221 is, for example, a silicon dioxide film.

  Collector electrode 230 is provided in contact with collector layer 211 on second main surface 210b. The collector electrode 230 is an electrode that is ohmically connected to the collector layer 211, and is preferably made of silicide, for example, nickel silicide. The collector electrode 230 may be the same material as the emitter contact electrode 208.

Next, a method for manufacturing the IGBT 201 according to the present embodiment will be described.
First, a base substrate (not shown) made of silicon carbide having n-type is prepared. A collector layer 211 made of an epitaxial layer having a p-type conductivity is formed on the base substrate. The acceptor type impurity concentration of the collector layer 211 is set to be 1 × 10 ¹⁷ cm ³ or more and 1 × 10 ²¹ cm ³ or less, more preferably 1 × 10 ¹⁹ cm ³ or more and 1 × 10 ²⁰ cm ³ or less. To be done. The collector layer 211 can be formed by, for example, a CVD method. An n type drift layer 212 is formed on the collector layer 211.

  Next, an ion implantation step is performed by a method similar to the method described in the second embodiment. Thus, silicon carbide substrate 210 including n type emitter region 214 in contact with p + region 202 is prepared.

  Next, the activation annealing step (S20: FIG. 2), the thermal oxide film step (S30: FIG. 2), and the gate electrode formation step are performed by the same method as described in the second embodiment.

  Next, a carbon region forming step (S40: FIG. 4) is performed by the same method as that described in the second embodiment. Specifically, silicon carbide substrate 210 from which parts of p + region 202 and emitter region 214 are exposed is heated in an atmospheric gas containing a halogen element, so that carbon in contact with p + region 202 and emitter region 214 is exposed. Region 6 is formed. Preferably, the halogen element is chlorine. Preferably, in the carbon region forming step, p + region 202 is heated at 800 ° C. or higher and 1000 ° C. or lower. Preferably, in the carbon region forming step, a recess is formed in p + region 202 by etching a part of p + region 202, and carbon region 206 is formed in contact with bottom wall surface 223 forming the recess. .

  Next, an electrode formation step (S50: FIG. 2) is performed. Specifically, for example, first metal layer 204 containing nickel and silicon is formed in contact with carbon region 206. The n-type base substrate in contact with the collector layer 211 is removed, and the collector electrode 230 in contact with the p-type collector layer 211 is formed. Thereafter, the silicon carbide substrate 210 including the first metal layer 204, the carbon region 206, and the collector electrode 230 is heated to, for example, about 1000 ° C., so that the emitter contact is brought into ohmic contact with the p + region 202 of the silicon carbide substrate 210. An electrode 208 is formed. An emitter wiring 219 made of aluminum, for example, is formed in contact with the emitter contact electrode 208. As described above, the IGBT 201 of the present embodiment shown in FIG. 11 is obtained.

  Next, effects of the IGBT 201 and the manufacturing method thereof according to the present embodiment will be described.

  According to IGBT 201 according to the present embodiment, silicon carbide substrate 210 includes a first main surface 10a on which p + region 202 is disposed, and a second main surface 10b opposite to first main surface 10a. Including. A collector layer 211 different from p + region 202 is included in contact with second main surface 10b. Thereby, the contact resistance between the emitter contact electrode 208 of the IGBT 201 and the p + region 202 can be reduced. As a result, the switching characteristics of the IGBT 201 can be improved.

  The embodiments and examples disclosed herein are illustrative in all respects and should not be construed as being restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 MPS, 2 p-type region, 2a first p-type region, 2b second p-type region, 2c third p-type region, 3 JTE region, 5 first metal layer, 6, 106, 206 carbon region 7 field stop region, 8 electrodes, 8a second electrode part, 8b second metal layer (first electrode part), 10, 110, 210 silicon carbide substrate, 10a, 110a, 210a first main surface, 10b, 110b, 210b 2nd main surface, 10c surface, 11 n + substrate, 12 electric field stop layer, 14 n-type region, 22 recess, 23, 123, 223 bottom wall surface, 24 side wall surface, 30 ohmic electrode, 40, 60,140 pad electrode, 70 protective film, 101 MOSFET, 102,202 p + region, 104,204 first metal layer, 108 source electrode, 111 base substrate, 112 drift region Region, 113, 213 well region, 114 second impurity region, 115, 215 gate insulating film, 117 first impurity region, 119 source wiring, 121, 221 interlayer insulating film, 127, 227 gate electrode, 130 drain electrode, 201 IGBT, 208 emitter contact electrode, 211 collector layer, 212 drift layer, 214 emitter region, 219 emitter wiring, 230 collector electrode, 240 collector wiring.

Claims (14)

providing a silicon carbide substrate including a p-type region and an n-type region in contact with the p-type region;
Forming a carbon region in contact with the p-type region by heating the p-type region in an atmospheric gas containing a halogen element;
Forming a first metal layer in contact with the carbon region;
Forming the electrode in contact with the p-type region by heating the carbon region and the first metal layer.   The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the halogen element is chlorine.   3. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the step of forming the carbon region, the p-type region is heated at 800 ° C. or higher and 1000 ° C. or lower.   In the step of forming the carbon region, a recess is formed in the p-type region by etching a part of the p-type region, and the carbon region is formed in contact with a surface on which the recess is formed. Item 4. A method for manufacturing a silicon carbide semiconductor device according to any one of Items 1 to 3. Forming a second metal layer in contact with the first metal layer;
5. The silicon carbide semiconductor device according to claim 1, wherein said silicon carbide substrate includes a second p-type region that is in contact with said second metal layer and not in contact with said carbon region. Production method.   The method for manufacturing a silicon carbide semiconductor device according to claim 5, wherein said first metal layer is made of a material containing titanium and aluminum.   The method for manufacturing a silicon carbide semiconductor device according to claim 1, further comprising a step of forming a gate insulating film in contact with the n-type region. a silicon carbide substrate including a p-type region and an n-type region in contact with the p-type region;
An electrode disposed in contact with the p-type region,
The electrode includes a silicon carbide diode including a first electrode portion in Schottky junction with the n-type region and a carbon region in contact with the p-type region.   9. The silicon carbide diode according to claim 8, wherein the silicon carbide substrate further includes a second p-type region in contact with the first electrode portion and not in contact with the carbon region. The electrode further includes a second electrode portion in contact with the first electrode portion,
The silicon carbide diode according to claim 8 or 9, wherein the second electrode portion includes the carbon region.   The silicon carbide diode according to claim 10, wherein the second electrode portion includes a material having titanium and aluminum. a silicon carbide substrate including a p-type region and an n-type region in contact with the p-type region;
An electrode disposed in contact with the p-type region and the n-type region;
A gate insulating film in contact with the n-type region,
The silicon carbide transistor, wherein the electrode includes a carbon region in contact with the p-type region.   The silicon carbide substrate includes a first main surface on which the p-type region is disposed, and a second main surface opposite to the first main surface, and is in contact with the second main surface. The silicon carbide transistor according to claim 12, further comprising a second p-type region different from the p-type region.   The silicon carbide transistor according to claim 12 or 13, wherein the electrode includes any one of a material having nickel and silicon and a material having titanium, aluminum, and silicon.

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