JP6592083B2 - Semiconductor device, manufacturing method thereof, and power module - Google Patents

Description

  The present invention relates to a semiconductor device using silicon carbide, a method for manufacturing the same, and a power module.

  As background art of this technical field, Japanese Patent Application Laid-Open No. 2008-227236 (Patent Document 1) and Naoki Tsuji and three others, “Design and Fabrication of 20 kV Class SiCPiN Diodes with Spatial Modulation JTE”, 73rd Applied Physics There are academic conference lectures, lecture proceedings (autumn 2012), pages 15-282 (Non-patent Document 1).

Patent Document 1 describes a semiconductor device including a central region and a termination region formed around the central region, and the termination region is an n ⁻ type that is continuous from the central region to the termination region. Drift region, a p-type guard ring, an n ⁺ -type channel stopper region provided at the periphery of the termination region, and an n-type first surface provided at least in part between adjacent guard rings And a semiconductor region.

  Non-Patent Document 1 describes a SiCPiN diode having a JTE structure in which a two-zone JTE (Junction Termination Extension) and a spatial modulation type JTE are combined.

JP 2008-227236 A

Naoki Tsuji and three others, “Design and Fabrication of 20 kV Class SiCPiN Diodes with Spatial Modulation JTE”, The 73rd Japan Society of Applied Physics, Proceedings (Autumn 2012), 15-282

  In a semiconductor device used at a high voltage or a large current, in the termination region formed around the active region (active region), charges may accumulate near the interface between the semiconductor and the insulating film protecting the upper surface of the semiconductor. There is. However, there is a demand for a semiconductor device that can obtain stable breakdown voltage characteristics even when electric charges accumulate near the interface and the electric field distribution in the termination region varies.

In order to solve the above problems, a semiconductor device according to the present invention includes an active region and a termination region formed around the active region, and the termination region is p ⁺ toward the end of the substrate from the active region. A termination structure in which a p-type semiconductor region, a p-type termination region, an n-type termination region, and an n ⁺ -type semiconductor region are formed. Then, between the p-type termination region and the n ⁺ -type semiconductor region, the impurity concentration of the n-type impurity per unit area of the region in contact with the n ⁺ -type semiconductor region is determined per unit area of the region in contact with the p-type termination region. It is higher than the impurity concentration of the n-type impurity.

ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device using silicon carbide which can suppress the pressure | voltage resistant fluctuation | variation in the termination | terminus region resulting from the fluctuation | variation of electric charge can be provided.
Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

FIG. 3 is a cross-sectional view of a main part for explaining the structure of a terminal portion of the semiconductor device according to Example 1; 7 is a cross-sectional view of the principal part showing the production process of the semiconductor device according to Example 1. FIG. FIG. 3 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 2; (A) And (b) is a principal part top view explaining the 1st example and 2nd example of the planar shape of the mask material used when forming the active region by Example 1, respectively. (A), (b), and (c) are the principal planes for explaining the third example, the fourth example, and the fifth example of the planar shape of the mask material used when forming the active region according to Example 1, respectively. FIG. FIG. 4 is a principal part cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 3; FIG. 7 is an essential part cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 6; FIG. 8 is an essential part cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 7; FIG. 10 is a main part sectional view for explaining a first modification of the structure of the termination portion of the semiconductor device according to the first embodiment; FIG. 10 is a top view of relevant parts for explaining a first modification of the structure of the termination portion of the semiconductor device according to the first embodiment; (A), (b), (c), and (d) are main part top views showing various examples of the p-type termination region of the semiconductor device according to Example 1 (in the region B indicated by the one-dot broken line in FIG. 10). It is the principal part top view which expanded the applicable area | region. (A), (b), (c), and (d) are main part top views showing various examples of the n-type termination region of the semiconductor device according to Example 1 (in a region B indicated by a one-dot broken line in FIG. 10). It is the principal part top view which expanded the applicable area | region. FIG. 10 is a main part sectional view for explaining a second modification example of the structure of the terminal end portion of the semiconductor device according to the first embodiment; FIG. 11B is a schematic diagram showing the distribution of the sheet carrier concentration at the end portion of the semiconductor device along the line AA shown in FIG. 11B (when there is no charge near the interface between the n ⁻ -type SiC drift layer and the insulating film). is there. FIG. 11B is a schematic diagram showing the distribution of the sheet carrier concentration at the end portion of the semiconductor device along the line AA shown in FIG. 11B (in the case where there is a charge near the interface between the n ⁻ -type SiC drift layer and the insulating film). is there. FIG. 6 is a cross-sectional view of a main part for explaining the structure of a terminal portion of a semiconductor device according to Example 2. It is the schematic explaining the structure of the power module by Example 3, and the power converter device containing a power module.

  In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.

  In addition, when referring to “consisting of A”, “consisting of A”, “having A”, and “including A”, other elements are excluded unless specifically indicated that only that element is included. It goes without saying that it is not what you do. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Further, in the drawings used in the following embodiments, hatching may be added to make the drawings easy to see even if they are plan views. In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, the present embodiment will be described in detail with reference to the drawings.

  A semiconductor device used at a high voltage or a large current is mainly composed of an active region through which a current flows and a termination region formed around the active region. In the termination region, a termination structure that prevents the electric field from being concentrated is formed. However, when the semiconductor device is held at a high voltage, a high electric field is applied to the termination region, so that charges may accumulate near the interface between the semiconductor and the insulating film protecting the upper surface of the semiconductor. When charge is accumulated near the interface, the electric field distribution in the termination region varies, and the breakdown voltage characteristics of the semiconductor device may vary.

  By the way, in recent years, silicon carbide (SiC) semiconductors have the characteristics that the band gap is larger than that of silicon (Si) semiconductors, and the electric field strength of dielectric breakdown is about one digit larger. Therefore, semiconductor devices using SiC semiconductors are Promising as a low-loss semiconductor device. However, since the SiC semiconductor has a higher breakdown electric field strength inside the semiconductor, the electric field strength applied to the termination region is larger than that of the Si semiconductor. Therefore, when the semiconductor device is held at a high voltage, the SiC semiconductor may accumulate a large amount of electric charge near the interface between the semiconductor and the insulating film that protects the upper surface of the semiconductor as compared with the Si semiconductor.

As a method for improving the fluctuation of the breakdown voltage characteristics of the semiconductor device due to the above-described charge accumulation, there are techniques described in Patent Document 1 and Non-Patent Document 1, for example. By applying the structure of the termination region disclosed in Patent Document 1, it is possible to obtain stable breakdown voltage characteristics in a range of charge amount of about −4 × 10 ¹¹ to 4 × 10 ¹¹ cm ⁻² . In addition, by applying the structure of the peripheral region disclosed in Non-Patent Document 1, a stable withstand voltage characteristic can be obtained in a range of charge amount of about 1 × 10 ¹² to 1 × 10 ¹³ cm ^−3. .

However, in a semiconductor device using a SiC semiconductor, a stable breakdown voltage characteristic is required when the charge amount is in the range of about −1 × 10 ¹³ to 1 × 10 ¹³ cm ⁻² . For this reason, it is necessary to further examine the structure of the termination region.

  <Structure of semiconductor device>

  The structure of the semiconductor device according to Example 1 will be described with reference to FIG. FIG. 1 is a cross-sectional view of a principal part for explaining the structure of the terminal portion of the semiconductor device according to the first embodiment.

The semiconductor device (one semiconductor chip) according to the first embodiment is a diode. As shown in FIG. 1, specifically, an n ⁻ type SiC drift layer 2 is formed on the first surface of the n ⁺ type SiC substrate 1, and a flat surface is formed on the upper surface of the n ⁻ type SiC drift layer 2. A p ⁺ type semiconductor region 3 is formed in an active region located in the center of the semiconductor chip as viewed.

Furthermore, on the upper surface of n ⁻ type SiC drift layer 2, p ⁺ type semiconductor region 3, p type termination region 4, n type termination region 6, and n ⁺ are provided in termination regions located on the outer periphery of the semiconductor chip in plan view. A termination structure 10 made of a type semiconductor region 5 is formed. That is, the p-type termination region 4 and the p-type termination region 4 are separated from the p-type termination region 4 so as to surround the p ⁺ -type semiconductor region 3, and are arranged closer to the outer periphery (end portion) side of the semiconductor chip. An n ⁺ type semiconductor region (channel stopper region) 5 and a plurality of n type termination regions 6 formed between the p type termination region 4 and the n ⁺ type semiconductor region 5 are formed.

Here, between the p-type termination region 4 and the n ⁺ -type semiconductor region 5, the impurity concentration of the n-type impurity per unit area becomes closer to the outside of the termination structure 10 (the outer periphery (end portion) of the semiconductor chip). Each planar shape of the plurality of n-type termination regions 6 is set so as to gradually increase. Specifically, a plurality of annular n-type termination regions 6 are formed between the p-type termination region 4 and the n ⁺ -type semiconductor region 5 so as to be separated from each other. The width of the n-type termination region 6 is gradually increased as it approaches (edge).

That is, between the p-type termination region 4 and the n ⁺ -type semiconductor region 5, the impurity concentration of the n-type impurity per unit area in the region in contact with the n ⁺ -type semiconductor region 5 is in the region in contact with the p-type termination region 4. The impurity concentration is higher than the n-type impurity concentration per unit area.

Furthermore, an anode electrode (surface electrode) 7a connected to the p ⁺ type semiconductor region 3 and an outer peripheral electrode (channel stopper electrode) 7b connected to the n ⁺ type semiconductor region 5 are formed, and the first electrode of the n ⁺ type SiC substrate 1 is formed. A cathode electrode (back surface electrode) 8 connected to the second surface opposite to the surface is formed. An insulating film 9 is formed on the upper surface of the n ⁻ -type SiC drift layer 2, and a part of the anode electrode 7 a is exposed through an opening formed in the insulating film 9.

  The anode electrode 7a may be either a Schottky contact or an ohmic contact. The active region of the diode may be any structure such as a Schottky diode, a PN diode, or a junction barrier Schottky (JBS) diode. Here, the active region refers to an active region through which current flows when energized. The p-type termination region 4 has a junction termination structure (Junction Termination Extension: JTE) having a single-stage or multi-stage concentration distribution.

Note that “ ⁻ ” and “ ⁺ ” are signs representing relative impurity concentrations of n-type or p-type conductivity, for example, n-type in the order of “n ⁻ ”, “n”, and “n ⁺ ”. The impurity concentration of the impurity increases, and the impurity concentration of the p-type impurity increases in the order of “p ⁻ ”, “p”, and “p ⁺ ”.
<Method for Manufacturing Semiconductor Device>

  A method for manufacturing a semiconductor device according to the first embodiment will be described in the order of steps with reference to FIGS. 2, 3, and 6 to 8 are cross-sectional views illustrating the main part of the manufacturing process of the semiconductor device according to the first embodiment. FIGS. 4A and 4B are main part plan views for explaining a first example and a second example of a planar shape of a mask material used when forming an active region according to the first embodiment, respectively. a), (b), and (c) are principal planes for explaining a third example, a fourth example, and a fifth example of the planar shape of the mask material used when forming the active region according to the first embodiment, respectively. FIG.

First, as shown in FIG. 2, a SiC substrate in which an n ⁻ type SiC drift layer 2 is formed on the first main surface of the n ⁺ type SiC substrate 1 by an epitaxial growth method is prepared.

The impurity concentration of the n ⁺ -type SiC substrate 1 is, for example, about 1 × 10 ¹⁸ to 1 × 10 ¹⁹ cm ⁻³ . As the main surface of the n ⁺ -type SiC substrate 1, a (0001) plane, a (000-1) plane, a (11-20) plane, or the like is used.

Although the specifications of the n ⁻ type SiC drift layer 2 vary depending on the breakdown voltage specification to be set, the impurity concentration of the n ⁻ type SiC drift layer 2 is, for example, about 1 × 10 ¹⁴ to 1 × 10 ¹⁶ cm ⁻³ , and its thickness is For example, it is about 3 to 150 μm.

Next, as shown in FIG. 3, a mask material 11A is formed on the upper surface of the n ⁻ -type SiC drift layer 2, and the mask material 11A is patterned by a photolithography technique. As the mask material 11A, for example, silicon oxide (SiO ₂ ) formed by a CVD (Chemical Vapor Deposition) method is used.

  FIGS. 4A and 4B and FIGS. 5A, 5B and 5C show examples of various planar shapes of the mask material 11A. In the figure, symbol SC indicates a semiconductor chip.

  The mask material 11A includes an active region fully open pattern (FIG. 4A), a ring-shaped pattern (FIG. 4B) that opens only at the outer periphery of the active region, a striped pattern (FIG. 5A), and an island pattern. (FIG. 5B) or a lattice pattern (FIG. 5C). Since the first embodiment relates to the termination structure of the semiconductor device, the planar shape of the active region is not particularly limited.

The p-type impurity by ion implantation on the upper surface of the type SiC drift layer 2, as applied to a part of the termination region, n ^{- -} Subsequently, n exposed from the patterned mask material 11A type SiC drift layer 2 A p ⁺ type semiconductor region 3 is formed in the active region on the upper surface. The impurity concentration of the p ⁺ type semiconductor region 3 is, for example, about 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ , and the junction depth is, for example, about 0.3 to 2.0 μm. Aluminum (Al), boron (B), or the like is used as the p-type impurity. Here, aluminum (Al) is used as a p-type impurity, ion implantation is performed in multiple stages with varying acceleration energy, and the impurity concentration near the upper surface of the n ⁻ -type SiC drift layer 2 is about 9 × 10 ¹⁸ cm ⁻³ . The p ⁺ type semiconductor region 3 was formed so that the depth was about 0.7 μm.

Next, as shown in FIG. 6, after removing the mask material 11A, a mask material 11B is formed on the upper surface of the n ⁻ -type SiC drift layer 2, and the mask material 11B is patterned by a photolithography technique. For example, silicon oxide (SiO ₂ ) formed by the CVD method is used as the mask material 11B, and the mask material 11B is processed so as to have a ring-shaped pattern opening around the p ⁺ type semiconductor region 3.

Subsequently, a p-type impurity is ion-implanted into the upper surface of the n ⁻ -type SiC drift layer 2 exposed from the patterned mask material 11B, so that the outer periphery of the p ⁺ -type semiconductor region 3 on the upper surface of the n ⁻ -type SiC drift layer 2 is obtained. A p-type termination region 4 made of a p-type annular semiconductor region is formed so as to surround the p ⁺ -type semiconductor region 3. The impurity concentration of the p-type termination region 4 is, for example, about 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ , and the junction depth is, for example, about 0.3 to 2.0 μm. Aluminum (Al), boron (B), or the like is used as the p-type impurity. Here, aluminum (Al) is used as a p-type impurity, ion implantation is performed in multiple stages with different acceleration energies, and the impurity concentration in the vicinity of the upper surface of the n ⁻ -type SiC drift layer 2 is about 4 × 10 ¹⁷ cm ⁻³ . The p-type termination region 4 was formed so that the depth was about 0.9 μm. By this step, the p ⁺ type semiconductor region 3 has a structure in contact with the p type termination region 4.

Next, as shown in FIG. 7, after removing the mask material 11B, a mask material 11C is formed on the upper surface of the n ⁻ -type SiC drift layer 2, and the mask material 11C is patterned by photolithography. The mask material 11C is processed using, for example, silicon oxide (SiO ₂ ) formed by a CVD method so as to have a ring-shaped pattern opening around the p-type termination region 4.

Subsequently, n-type impurities are ion-implanted into the upper surface of the n ⁻ -type SiC drift layer 2 exposed from the patterned mask material 11C, so that the p-type termination region 4 on the upper surface of the n ⁻ -type SiC drift layer 2 is surrounded. Then, an n ⁺ type semiconductor region (channel stopper region) 5 made of an n-type annular semiconductor region is formed so as to surround the p-type termination region 4 apart from the p-type termination region 4. The impurity concentration of the n ⁺ -type semiconductor region 5 is, for example, about 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ , and the junction depth is, for example, about 0.3 to 1.0 μm. Nitrogen (N), phosphorus (P), or the like is used as the n-type impurity. Here, nitrogen (N) is used as an n-type impurity, ion implantation is performed in multiple stages with varying acceleration energy, and the impurity concentration near the upper surface of the n ⁻ -type SiC drift layer 2 is about 1 × 10 ²⁰ cm ⁻³ . The n ⁺ type semiconductor region 5 was formed so as to have a depth of about 0.6 μm.

Next, as shown in FIG. 8, after removing the mask material 11C, a mask material 11D is formed on the upper surface of the n ⁻ -type SiC drift layer 2, and the mask material 11D is patterned by photolithography. The mask material 11D uses, for example, silicon oxide (SiO ₂ ) formed by CVD, and has a plurality of ring-shaped pattern openings spaced apart from each other between the p-type termination region 4 and the n ⁺ -type semiconductor region 5. Is processed.

Subsequently, n-type impurities are ion-implanted into the upper surface of the n ⁻ -type SiC drift layer 2 exposed from the patterned mask material 11D, so that the p-type termination region 4 and the n ^{+ on} the upper surface of the n ⁻ -type SiC drift layer 2 are implanted. An n-type termination region 6 composed of a plurality of n-type annular semiconductor regions is formed between the n-type semiconductor region 5 and spaced apart from each other so as to surround the p-type termination region 4. The impurity concentration of the n-type termination region 6 is, for example, about 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ , and the junction depth is, for example, about 0.3 to 2.0 μm. Nitrogen (N), phosphorus (P), or the like is used as the n-type impurity. Here, nitrogen (N) is used as an n-type impurity, ion implantation is performed in multiple stages with varying acceleration energy, and the impurity concentration in the vicinity of the upper surface of the n ⁻ -type SiC drift layer 2 is about 5 × 10 ¹⁷ cm ⁻³ . The n-type termination region 6 was formed so that the depth was about 0.4 μm. By this step, the outermost annular n-type termination region 6 is in contact with the n ⁺ -type semiconductor region 5. However, this structure is not essential, and a structure in which the outermost annular n-type termination region 6 is not in contact with the n ⁺ -type semiconductor region 5 may be used.
Next, after removing the mask material 11D, activation annealing is performed on the implanted impurities.

Through the above steps, as shown in FIG. 1, a termination structure 10 composed of p ⁺ type semiconductor region 3, p type termination region 4, n type termination region 6 and n ⁺ type semiconductor region 5 is formed.

Next, as shown in FIG. 1, an ohmic contact cathode electrode 8 is formed on the second main surface of the n ⁺ -type SiC substrate 1, and an anode electrode 7 a is formed on the upper surface of the n ⁻ -type SiC drift layer 2. And the outer peripheral electrode 7b is formed. Here, the end portion of the anode electrode 7 a is formed to overlap the p ⁺ type semiconductor region 3 in plan view.

Then, after forming the insulating film 9 so as to cover the upper surface of the n ⁻ -type SiC drift layer 2, an opening is formed in the insulating film 9 so that a part of the upper surface of the anode electrode 7 a is exposed. Through the above steps, the semiconductor device according to the first embodiment is substantially completed.
<Modification of Semiconductor Device and Manufacturing Method of Semiconductor Device>
Next, a modification of the semiconductor device and the method for manufacturing the semiconductor device according to the first embodiment will be described.

(1) In Example 1, the n ⁻ type SiC drift layer 2 is formed of a single-layer SiC layer formed on the first main surface of the n ⁺ type SiC substrate 1, but the impurity concentration near the surface is low. A plurality of SiC layers in which the concentration distribution of n-type impurities is set to be high may be used.

(2) In the first embodiment, silicon oxide (SiO ₂ ) is applied to the mask materials 11A, 11B, 11C, and 11D. However, for example, silicon nitride (Si ₃ N ₄ ) or a resist material may be used. Any other material can be used as long as it is a material used as a mask.

  (3) In the first embodiment, the p-type termination region 4 has a JTE structure having a one-stage concentration distribution formed by one ion implantation of impurities. A JTE structure having a multistage concentration distribution formed by multiple ion implantations of impurities may be used.

  FIG. 9 is a fragmentary cross-sectional view illustrating the structure of the terminal portion of the semiconductor device having a JTE structure having a two-stage concentration distribution. FIG. 10 shows a top view of a principal part of a semiconductor device having a JTE structure having a two-stage concentration distribution. In FIG. 10, for example, the anode electrode 7a, the outer peripheral electrode 7b, and the insulating film 9 shown in FIG. 9 are omitted.

As shown in FIGS. 9 and 10, the JTE structure is composed of a first p-type termination region 4a and a second p-type termination region 4b, and the impurity concentration of the first p-type termination region 4a is the impurity of the second p-type termination region 4b. It is set higher than the concentration. Then, the first 1p type termination region 4a in contact with the outer periphery of the p ⁺ -type semiconductor regions 3, is formed annularly to surround the p ⁺ -type semiconductor region 3, the first 2p-type termination region 4b of the 1p-type termination region 4a On the outer side (opposite to the p ⁺ -type semiconductor region 3), an annular shape is formed so as to surround the first p-type termination region 4 a in contact with the outer periphery of the first p-type termination region 4 a.

  At this time, the first p-type termination region 4a and the second p-type termination region 4b may be formed so as to overlap each other in a partial region. Further, a JTE structure having an arbitrary number of concentration distributions may be formed by increasing the number of mask pattern formations and the number of impurity ion implantations.

  Moreover, although the 1st p-type termination region 4a and the 2nd p-type termination region 4b were formed as a ring-shaped pattern, it is not limited to this. For example, a lattice pattern, an island pattern, a dot pattern, or a combination thereof may be used, and the total dose amount (impurity concentration per unit area) of ion implantation gradually decreases as the outer periphery (end portion) of the semiconductor chip SC is approached. If it becomes the structure which becomes, it may be patterned into what kind of shape.

  FIGS. 11A, 11B, 11C, and 11D are top views of main parts showing various examples of patterns of the first p-type termination region 4a and the second p-type termination region 4b. 11A, 11B, 11C, and 11D are top views of main parts in which a region corresponding to the region B indicated by the one-dot broken line in FIG. 10 is enlarged.

  Here, a JTE structure having a two-stage concentration distribution of the first p-type termination region 4a and the second p-type termination region 4b is shown, but any number of concentration distributions may be combined, and the outer periphery of the semiconductor chip SC ( A structure in which the total dose of ion implantation (impurity concentration per unit area) gradually decreases as it approaches the edge).

(4) In the first embodiment, an example in which the p ⁺ -type semiconductor region 3 and the p-type termination region 4 are formed so as to be in contact with each other without overlapping each other is shown. You may design so that a mask pattern may be piled up so that the influence of deviation may become small.

  (5) In the first embodiment, the n-type termination region 6 is formed as a plurality of ring-shaped patterns. However, the present invention is not limited to this. For example, a lattice pattern, an island pattern, a dot pattern, or a combination thereof may be used. As the semiconductor chip SC approaches the outer periphery (end), the ratio of the implantation area in the ion implantation (impurity concentration per unit area) gradually increases. The pattern may be patterned in any shape as long as the structure becomes higher.

  FIGS. 12A, 12B, 12C, and 12D are top views of essential parts showing various examples of the pattern of the n-type termination region 6. FIG. FIGS. 12A, 12B, 12C, and 12D are top views of main parts in which a region corresponding to the region B indicated by the dashed line in FIG. 10 is enlarged.

  (6) In Example 1, the p-type termination region 4 and the n-type termination region 6 are formed to be separated from each other, but may overlap each other in some regions.

(7) In Example 1, the p ⁺ type semiconductor region 3, the p type termination region 4, the n ⁺ type semiconductor region 5, and the n type termination region 6 are formed by ion implantation in this order. These ion implantations may be completed before the activation annealing, and the order of formation may be changed.

(8) In the first embodiment, impurities are introduced into the upper surface of the n ⁻ -type SiC drift layer 2 by ion implantation to form the structures of the active region and the termination region. The n ⁺ -type SiC substrate 1 An impurity may be ion-implanted into the second main surface of the n ⁺ -type SiC substrate 1 for the purpose of reducing the contact resistance between the n ⁺ -type SiC substrate 1 and the cathode electrode 8. For example, nitrogen (N) is used as an impurity, ion implantation is performed in multiple stages with varying acceleration energy, the impurity concentration in the vicinity of the second main surface is about 1 × 10 ²⁰ cm ⁻³ , and the impurity concentration of the n ⁺ -type SiC substrate 1 is In comparison, the impurity is added so that the depth of the region where the impurity concentration is higher is about 0.5 μm.

(9) In the first embodiment, the anode electrode 7a, the outer peripheral electrode 7b, and the cathode electrode 8 are formed immediately after the activation annealing of the ion-implanted impurity. However, the activation annealing of the ion-implanted impurity is performed. After performing, oxidation treatment may be performed, and sacrificial oxidation may be performed to remove the damaged layer that has entered the upper surface of the n ⁻ -type SiC drift layer 2.

(10) In Example 1, the anode electrode 7a, the outer peripheral electrode 7b, and the cathode electrode 8 were formed immediately after the activation annealing of the ion-implanted impurity, but the n ⁻ type SiC drift layer 2 A surface protective film such as silicon oxide (SiO ₂ ) may be formed on the upper surface by a CVD method to protect the upper surface of the n ⁻ -type SiC drift layer 2.

  FIG. 13 is a cross-sectional view of a principal part for explaining the structure of the terminal portion of the semiconductor device on which the surface protective film according to the first embodiment is formed.

In this case, as shown in FIG. 13, after the surface protective film 12 is formed on the upper surface of the n ⁻ -type SiC drift layer 2, an opening is formed in the surface protective film 12 in the region where the anode electrode 7 a and the outer peripheral electrode 7 b are formed. Form. Thereafter, the anode electrode 7 a and the outer peripheral electrode 7 b are formed so as to run over a part of the surface protective film 12. Further, the surface protective film 12 may be formed after performing the above-described sacrificial oxidation.
<Effect>
Next, the effect by the present Example 1 is demonstrated using FIG. 14 and FIG.

FIG. 14 is a schematic diagram showing the distribution of the sheet carrier concentration at the end portion of the semiconductor device along the line AA shown in FIG. FIG. 14 shows the distribution of the sheet carrier concentration activated by activation annealing among the implanted impurities, and there is no charge accumulated near the interface between the n ⁻ -type SiC drift layer 2 and the insulating film 9. Is assumed.

As shown in FIG. 14, the ratio between the width and the interval of the n-type termination region 6 (width / (width + interval)) increases as it approaches the outside of the termination structure 10 (the outer periphery (end portion) of the semiconductor chip). The average sheet carrier concentration Sa (= sheet carrier concentration × width / (width + interval)) of the n-type termination region 6 is also high. For this reason, when a high voltage is applied and held, there is no region where the electric field is locally concentrated, and the n ⁻ -type SiC drift layer 2, the first p-type termination region 4 a and the second p-type termination region 4 b (or p Since the depletion layer with respect to the mold termination region 4) becomes difficult to extend as it approaches the outer periphery (end portion) of the semiconductor chip, the depletion layer does not reach the n ⁺ type semiconductor region 5 having a high impurity concentration. Obtainable.

FIG. 15 is a schematic diagram showing the distribution of the sheet carrier concentration at the end portion of the semiconductor device along the line AA shown in FIG. FIG. 15 shows the distribution of the sheet carrier concentration activated by activation annealing among the implanted impurities, and negative charges accumulated near the interface between the n ⁻ -type SiC drift layer 2 and the insulating film 9 are shown. The case is assumed.

As shown in FIG. 15, when negative charges are accumulated near the interface between the n ⁻ -type SiC drift layer 2 and the insulating film 9, an equivalent amount of positive charge is compensated on the upper surface of the n ⁻ -type SiC drift layer 2. In the first p-type termination region 4a and the second p-type termination region 4b (or the p-type termination region 4), positive carriers are effectively increased, and in the n-type termination region 6, there are effectively negative carriers. Decrease. As a result, the pn junction position approaches the outer periphery (end) of the semiconductor chip as compared with the case where charges are not accumulated near the interface between the n ⁻ -type SiC drift layer 2 and the insulating film 9 (see FIG. 14). It will be.

At this time, by making the sheet carrier concentration activated by the activation annealing out of the dose amount of the impurity implanted into the n-type termination region 6 larger than the assumed negative charge amount 1 × 10 ¹³ cm ⁻² , It is possible to prevent the n-type termination region 6 from being effectively extinguished by negative charges, and to prevent electric field concentration as the termination region. In general, since the activation rate of impurities is about 80 to 100%, if the n-type termination region 6 is formed with a dose amount higher than 1.25 × 10 ¹³ cm ⁻² , a negative charge amount is obtained. It is possible to suppress the breakdown voltage fluctuation in the termination region due to the fluctuation.

  The structure of the semiconductor device according to Example 2 will be described with reference to FIG. FIG. 16 is a cross-sectional view of a principal part for explaining the structure of the terminal portion of the semiconductor device according to the second embodiment.

  The semiconductor device (one semiconductor chip) according to the second embodiment is an example in which a field effect transistor, a so-called planar type DMOS (Double Diffused Metal Oxide Semiconductor) MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is formed in an active region. is there.

As shown in FIG. 16, on the first major surface of the ^{n +} -type SiC substrate 1, n ^- -type SiC drift layer 2 is formed, n of the active region ^- -type SiC drift layer 2, n ^- A plurality of p-type semiconductor regions (body regions, well regions) 14 are formed apart from each other with a first depth from the upper surface of type SiC drift layer 2.

In the p-type semiconductor region 14, an n ⁺ -type semiconductor region (source region) 15 is formed having a second depth shallower than the first depth from the upper surface of the n ⁻ -type SiC drift layer 2. In the p-type semiconductor region 14, a plurality of p ⁺ -type potential fixing regions (not shown) that fix the potential of the p-type semiconductor region 14 are formed. A region sandwiched between adjacent p-type semiconductor regions 14 is a part that functions as the JFET region 13.

Further, the end side surface of the p-type semiconductor region 14 (interface between the JFET region 13 and the p-type semiconductor region 14) and the end side surface of the n ⁺ -type semiconductor region 15 (p-type semiconductor region 14 and n ⁺ -type semiconductor region 15 and The p-type semiconductor region 14 located between the two regions) functions as a channel region. Further, the n ⁺ -type SiC substrate 1 is a part that functions as a drain layer.

A gate insulating film 16 is formed on the JFET region 13 and the channel region, and a gate electrode 7 c is formed on the gate insulating film 16. The gate insulating film 16 and the gate electrode 7c are covered with an insulating film (not shown). A plurality of connection holes are formed in the insulating film, and a part of the n ⁺ type semiconductor region 15 exposed on the bottom surface of the connection hole and the p ⁺ type potential fixing region are connected to the source wiring electrode (via the metal silicide layer). (Not shown).

The second main surface of n ⁺ type SiC substrate 1 is electrically connected to drain wiring electrode (back electrode) 8A. Similarly, the gate electrode 7c is electrically connected to a gate wiring electrode (not shown). A source potential is applied to the source wiring electrode from the outside, a drain potential is applied to the drain wiring electrode 8A from the outside, and a gate potential is applied to the gate wiring electrode from the outside.

Further, similarly to the above-described first embodiment, the semiconductor device according to the second embodiment has a plurality of n-type termination regions 6 between the p-type termination region 4 and the n ⁺ -type semiconductor region 5. The planar shape of each of the plurality of n-type termination regions 6 is set so that the impurity concentration of the n-type impurity per unit area gradually increases as it approaches the outside of the structure 10 (the outer periphery (end) of the semiconductor chip). Has been.

As described above, according to the second embodiment, even when the MOSFET is formed in the active region, the same effect as in the first embodiment can be obtained. That is, the average sheet carrier concentration Sa of the n-type termination region 6 increases as it approaches the outside of the termination structure 10 (the outer periphery (end portion) of the semiconductor chip). As a result, even when negative charges are accumulated near the interface between the n ⁻ -type SiC drift layer 2 and the insulating film 9, the region where the electric field is locally concentrated when a high voltage is applied is held. In addition, since the depletion layer between the n ⁻ -type SiC drift layer 2 and the p-type termination region 4 becomes difficult to extend as it approaches the outer periphery (end portion) of the semiconductor chip, the n ⁺ -type semiconductor region having a high impurity concentration Never reach 5. As a result, it is possible to suppress the withstand voltage fluctuation in the termination region due to the negative charge amount fluctuation.

  In the second embodiment, a MOSFET is formed in the active region, but a transistor such as a junction field effect transistor (JFET) or an insulated gate bipolar transistor (IGBT) may be formed. . In these cases as well, the withstand voltage fluctuation in the termination region due to the negative charge amount fluctuation can be suppressed.

  At least one of the diode described in the first embodiment and the transistor described in the second embodiment is incorporated in a power module, and a plurality of the power modules are used to constitute a power converter. Can do.

  In FIG. 17, the schematic explaining the structure of the power module by the present Example 3 and the power converter device containing a power module is shown.

  As shown in FIG. 17, a switching element (for example, IGBT) 24 and a diode 21 are connected in antiparallel in the power module 17. The power module 17 has at least three terminals. The first C terminal is connected to the collector electrode 27 of the IGBT and the cathode electrode 23 of the diode 21, and the second E terminal is connected to the emitter electrode 26 of the IGBT and the anode electrode 22 of the diode 21. The G terminal is connected to the gate electrode 25 of the IGBT.

  In each single phase, the power module 17 is connected between the power supply potential (Vcc) and the input potential of the load 18 (for example, a motor), and the power module 17 is connected between the input potential of the load 18 and the ground potential (GND). It is connected. That is, in the load 18, two power modules 17 are connected to each single phase, and six power modules 17 are connected in three phases. The power conversion device 20 includes these six power modules 17. A control circuit 19 is connected to the G terminal of each power module 17, and the switching element 24 is controlled by the control circuit 19.

  Therefore, the load 18 can be driven by controlling the current flowing through the switching element 24 constituting the power converter 20 by the control circuit 19.

  According to the third embodiment, the diode shown in the first embodiment described above or the transistor shown in the second embodiment described above is employed for either or both of the diode 21 and the switching element 24 constituting the power module 17. By doing so, it is possible to realize a stable power module 17 in which withstand voltage fluctuations due to negative charge fluctuations are suppressed. Furthermore, the low-loss power converter 20 can be realized.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

1 n ⁺ type SiC substrate 2 n ⁻ type SiC drift layer 3 p ⁺ type semiconductor region 4 p type termination region 4a first p type termination region 4b second p type termination region 5 n ⁺ type semiconductor region (channel stopper region)
6 n-type termination region 7a Anode electrode (surface electrode)
7b Perimeter electrode (channel stopper electrode)
7c Gate electrode 8 Cathode electrode (Back electrode)
8A Drain wiring electrode (Back electrode)
9 Insulating film 10 Termination structure 11A, 11B, 11C, 11D Mask material 12 Surface protective film 13 JFET region 14 p-type semiconductor region (body region, well region)
15 n ⁺ type semiconductor region (source region)
16 Gate insulating film 17 Power module 18 Load 19 Control circuit 20 Power converter 21 Diode 22 Anode electrode 23 Cathode electrode 24 Switching element 25 Gate electrode 26 Emitter electrode 27 Collector electrode Sa Average sheet carrier concentration SC Semiconductor chip

Claims (10)

A first conductivity type substrate made of silicon carbide;
A drift layer of the first conductivity type formed on the first main surface of the substrate;
An active region formed in the center of the drift layer in plan view;
A termination region formed in the drift layer around the active region in plan view;
A semiconductor device comprising:
The termination region is
A first semiconductor region of a second conductivity type different from the first conductivity type formed around the active region;
A second semiconductor of the second conductivity type, which is formed around the first semiconductor region, in contact with the first semiconductor region, closer to the end of the substrate than the first semiconductor region, and forms a junction termination structure Area,
A third semiconductor region of the first conductivity type formed around the second semiconductor region, spaced from the second semiconductor region, closer to the end of the substrate than the second semiconductor region;
A plurality of fourth semiconductor regions of the first conductivity type formed between the second semiconductor region and the third semiconductor region by three or more spaced apart from each other;
Have
Between the second semiconductor region and the third semiconductor region,
The impurity concentration of the first conductivity type per unit area of the region in contact with the third semiconductor region is higher than the impurity concentration of the first conductivity type per unit area of the region in contact with the second semiconductor region,
A semiconductor device in which the width of each of the plurality of fourth semiconductor regions is sequentially increased as it approaches the end side of the substrate. The semiconductor device according to claim 1,
A semiconductor device, wherein an impurity concentration of the first conductivity type per unit area increases from the second semiconductor region toward the third semiconductor region. The semiconductor device according to claim 1,
The semiconductor device, wherein a dose of the first conductivity type impurity implanted into the fourth semiconductor region is 1.25 × 10 ¹³ cm ⁻² or more. The semiconductor device according to claim 1,
The semiconductor device, wherein the first semiconductor region and the second semiconductor region contain aluminum. The semiconductor device according to claim 1,
The impurity concentration of the second semiconductor region is lower than the impurity concentration of the first semiconductor region,
The semiconductor device, wherein an impurity concentration of the fourth semiconductor region is higher than an impurity concentration of the drift layer and lower than an impurity concentration of the third semiconductor region. The semiconductor device according to claim 1,
A semiconductor device in which a diode, MOSFET, JFET, or IGBT is formed in the active region. (A) forming a drift layer of the first conductivity type on a first main surface of a first conductivity type substrate made of silicon carbide;
(B) forming a first semiconductor region of a second conductivity type different from the first conductivity type on an upper surface around a central portion of the drift layer;
(C) forming a second conductivity type first termination region on the upper surface of the first outer peripheral portion of the drift layer;
(D) forming a second termination region of the first conductivity type on an upper surface of a second outer peripheral portion located around the first outer peripheral portion of the drift layer;
Including
The step (d)
(D1) forming a first mask pattern having a plurality of openings in the second outer peripheral portion on the upper surface of the drift layer;
(D2) a step of ion-implanting the first impurity of the first conductivity type into the drift layer of the second outer peripheral portion through the first mask pattern;
Including
The first termination region is in contact with the first semiconductor region on the end side of the substrate with respect to the first semiconductor region,
The impurity concentration of the first termination region is lower than the impurity concentration of the first semiconductor region,
A method of manufacturing a semiconductor device, wherein an opening area of the plurality of openings increases from the first outer peripheral portion toward an end portion of the substrate. The method of manufacturing a semiconductor device according to claim 7.
The method of manufacturing a semiconductor device, wherein a dose amount of the first impurity ion-implanted in the step ( d2 ) is 1.25 × 10 ¹³ cm ⁻² or more. The method of manufacturing a semiconductor device according to claim 7.
The step (b)
(B1) forming a second mask pattern having an opening in the first outer peripheral portion on the upper surface of the drift layer;
(B2) ion-implanting the second impurity of the second conductivity type into the drift layer of the first outer peripheral portion through the second mask pattern;
Including
The method of manufacturing a semiconductor device, wherein the second impurity ion-implanted in the step (b2) is aluminum.   A power module comprising the semiconductor device according to claim 1.

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