KR100390153B1 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- KR100390153B1 KR100390153B1 KR1019960064996A KR19960064996A KR100390153B1 KR 100390153 B1 KR100390153 B1 KR 100390153B1 KR 1019960064996 A KR1019960064996 A KR 1019960064996A KR 19960064996 A KR19960064996 A KR 19960064996A KR 100390153 B1 KR100390153 B1 KR 100390153B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 45
- 229920005591 polysilicon Polymers 0.000 claims abstract description 45
- 238000000034 method Methods 0.000 claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- 239000010703 silicon Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 125000006850 spacer group Chemical group 0.000 claims description 8
- 239000002019 doping agent Substances 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 9
- 230000005669 field effect Effects 0.000 description 13
- 238000005468 ion implantation Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 명은 반도체소자에 관한 것으로, 특히 게이트전극을 구성하는 폴리실리콘층에 P-도전영역과 N-도전영역을 병존시켜 그 게이트진극에 전압을 인가하지 않는 경우에도 채널영역에 약한 반전층이 형성되도록 함으로써, 고미세 반도체소자의 쇼트채널효과를 개선하는데 적당하도록 한 반도체소자 및 그 반도체소자의 제조방법에 관한 것이다.The present invention relates to a semiconductor device. In particular, a P-conducting region and an N-conducting region coexist in a polysilicon layer constituting a gate electrode so that a weak inversion layer is formed in a channel region even when a voltage is not applied to the gate electrode. Thereby, the present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, which are suitable for improving the short channel effect of a high-fine semiconductor device.
종래의 일반적인 전계효과 트랜지스터(MOSFET)는 하나의 전도영역을 갖는 폴리실리콘으로 게이트전극을 형성하였다. 그리고, 상기와 같은 전계효과 트랜지스터가 고 미세화됨에 따라 나타나는 쇼트채널효과를 개선하기 위해서, 소오스/드레인영역을 엘디디(LDD) 구조로 형성하였다. 이하, 상기와 같은 종래의 엘디디 구조 전계효과 트랜지스터에 대해서 도 1a-도 1d에 도시된 공정 단면도를 참조하여 설명하면 다음과 같다.Conventional field effect transistors (MOSFETs) form gate electrodes of polysilicon having one conduction region. In addition, the source / drain regions are formed in the LDD structure in order to improve the short channel effect that occurs as the field effect transistors become finer. Hereinafter, the conventional LED structure field effect transistor will be described with reference to the process cross-sectional view shown in FIGS. 1A to 1D.
우선, 도 1a와 도 1b에 도시된 바와 같이 일반적인 로커스(LOCOS)공정으로 형성된 필드산화막(120)을 통해 액티브영역과 필드영역이 구분된 실리콘기판(110) 의에 게이트산화막(130)을 형성한 후, 그 게이트산화막(130) 위에 게이트전극을 형성하기 위한 N-도전형 폴리실리콘층(140)과 제 1 산화막(150)을 순차적으로 형성한다.First, as shown in FIGS. 1A and 1B, a gate oxide layer 130 is formed on a silicon substrate 110 in which an active region and a field region are separated through a field oxide layer 120 formed by a general LOCOS process. Thereafter, the N-conductive polysilicon layer 140 and the first oxide film 150 for forming the gate electrode are sequentially formed on the gate oxide film 130.
이후, 도 1c에 도시된 바와 같이 포토리소그래피 및 식각공정으로 상기 제 1 산화막(15O)과 N-도전형 폴리실리콘층(140), 게이트산화막(130)을 순차적으로 패터닝하여 절연게이트전극(131,141,151)을 형성한 후, 그 절연게이트전극(131,141,151) 및 필드산화막(120)을 마스크로 하는 선택적 이온주입공정으로 저농도 N형 소오스/드레인영역(161)을 형성한다.Subsequently, as illustrated in FIG. 1C, the first oxide film 15O, the N-conductive polysilicon layer 140, and the gate oxide film 130 are sequentially patterned by photolithography and etching processes to form insulating gate electrodes 131, 141, and 151. After the formation, the low concentration N-type source / drain region 161 is formed by a selective ion implantation process using the insulating gate electrodes 131, 141, 151 and the field oxide film 120 as masks.
이어서, 도 1d에 도시된 바와 같이 상기 절연게이트전극(131,141,151)의 측면에 제 2 산화막 측벽스페이서(156)를 형성한 후, 그 제 2 산화막 측벽스페이서(156)와 절연게이트전극(131,141,151), 필드산화막(120)을 마스크로 하는 선택적 이온주입공정으로 고농도 N형 소오스/드레인영역(162)을 형성함으로써, 엘디디 구조 전계효과 트랜지스터를 완성한다.Subsequently, as shown in FIG. 1D, a second oxide sidewall spacer 156 is formed on side surfaces of the insulating gate electrodes 131, 141, and 151, and then the second oxide sidewall spacer 156, the insulating gate electrodes 131, 141, 151, and a field are formed. The LED structure field effect transistor is completed by forming a high concentration N-type source / drain region 162 by a selective ion implantation process using the oxide film 120 as a mask.
이와 같은 방법으로 형성된 엘디디 구조 전계효과 트랜지스터는 통상적인 구조의 전계효과 트랜지스터에 비해서 쇼트채널효과가 개선된 것으로 알려져 있다.The LED structure field effect transistor formed by the above method is known to have an improved short channel effect compared to the field effect transistor of the conventional structure.
그러나, 상기와 같은 종래의 엘디디 구조 전계효가 트랜지스터도, 반도체소자의 고집적화에 따라 그의 게이트 길이(Gate length)가 더욱 감소하게 되면, 쇼트채널효과를 효과적으로 개선하지 못하게 되는 문제점이 있었다.However, the conventional LED structure field-efficiency transistor as described above also has a problem in that when the gate length thereof is further reduced due to high integration of the semiconductor device, the short channel effect cannot be effectively improved.
이에 본 발명은 상기와 같은 문제점을 해결하기 위하여 창안한 것으로, 게이트전극을 구성하는 폴리실리콘층에 P-도전영역과 N-도전영역을 병존시켜 그 게이트전극에 전압을 인가하지 않는 경우에도 채널영역에 약한 반전층이 형성되도록 함으로써, 고미세 반도체소자의 쇼트채널효과를 개선하는데 적당하도록 한 반도체소자 및 그 반도제소자의 제조방법을 제공함에 목적이 있다.Accordingly, the present invention has been made to solve the above problems, and the P-conducting region and the N-conducting region coexist in the polysilicon layer constituting the gate electrode, even when no voltage is applied to the gate electrode. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the semiconductor device, which are suitable for improving the short channel effect of a high-fine semiconductor device by forming a weak inversion layer.
도 1a-도 1d는 종래 기술에 따른 엘디디 구조 전계효과 트랜지스터의 제조방법을 나타낸 공정단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing an LED structure field effect transistor according to the prior art.
도 2는 본 발명에 따른 2도우프 폴리실리콘 게이트전극 및 엘디디 구조의 소오스/드레인영역을 갖는 전계효과 트랜지스터의 구성단면도.2 is a cross-sectional view of a field effect transistor having a source / drain region of a double doped polysilicon gate electrode and an LED structure according to the present invention;
도 3a-도 3g는 상기 도 2에 도시된 2도우프 폴리실리콘 게이트전극 및 엘디디 구조의 소오스/드레인영역을 갖는 전계효과 트랜지스터의 제조방법을 나타낸 공정단면도.3A to 3G are cross-sectional views illustrating a method of manufacturing a field effect transistor having a source / drain region of a double doped polysilicon gate electrode and an LED structure shown in FIG. 2;
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
210: P형 실리콘기판 230,231: 게이트산화막210: P-type silicon substrate 230,231: gate oxide film
240: 언도우프 폴리실리콘층 241: N형 도우프 폴리실리콘층240: undoped polysilicon layer 241: N-type dope polysilicon layer
242,242a: P형 도우프 폴리실리콘층 250,251: 제 1 산화막242,242a: P-type dope polysilicon layer 250,251: first oxide film
256: 제 2 산화막 측벽스페이서 261: 저농도 N형 소오스/드레인영역256: second oxide film sidewall spacer 261: low concentration N-type source / drain region
262: 고농도 N형 소오스/드레인영역 263: 반전층262: high concentration N-type source / drain region 263: inversion layer
상기 목적을 달성하기 위한 본 발명에 따른 반도체소자는, 제 1 도전형(P형 또는 N형) 실리콘기판에 형성된 엘디디 구조의 제 2 도전형 소오스/드레인영역과;게이트 산화막 위에 형성된 2도우프 폴리실리콘 게이트전극으로 구성되는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a semiconductor device comprising: a second conductivity type source / drain region having an LED structure formed on a first conductivity type (P type or N type) silicon substrate; It is characterized by consisting of a polysilicon gate electrode.
이때, 상기 2도우프 폴리실리콘 게이트전극은 그의 중심영역이 제 2 도전형으로 도우프되는 반면에, 양쪽의 가장자리영역이 제 1 도전형으로 도우프되는 것이 바람직하다.In this case, it is preferable that the two-doped polysilicon gate electrode is doped with the second conductive type while the center region thereof is doped with the second conductive type.
그리고, 상기와 같은 반도체소자를 형성하기 위한 본 발명에 따른 반도체소자 제조방법은, 제 1 도전형(P형 또는 N형) 실리콘기판 위에 게이트산화막을 형성한 후, 그 위에 언도우프(Undoped) 폴리실리콘을 증착하는 단계와; 그 언도우프 폴리실리콘층 위에 게이트영역의 중심부와 가장자리부를 각각 정의하는 제 1,2 레지스트패턴을 형성함과 아울러 그 각각의 레지스트패턴을 통해 제 1,2 도전형 도판트를 주입함으로써, 게이트영역의 중심부는 제 2 도전형으로 형성되고 가장자리부는 제 1 도전형으로 형성된 2도우프 폴리실리콘층을 형성하는 단계와; 상기 2도우프 폴리실리콘층 위에 제 1 절연막을 형성한 후, 포토리소그래피 및 식작공정으로 상기 제 1 절연막과 2도우프 폴리실리콘층, 게이트산화막을 순차적으로 패터닝하여 절연게이트전극을 형성하는 단계와; 저농도 제 1 도전형 도판트를 주입한 후, 절연게이트전극의 측면에 제 2 절연막 측벽스페이서를 형성하고, 이에 대해서 고농도 제 1 도전형 도판트를 주입함으로써, 엘디디 구조의 소오스/드레인영역을 형성하는 단계로 이루어지는 것을 특징으로 한다.In the semiconductor device manufacturing method according to the present invention for forming the semiconductor device as described above, a gate oxide film is formed on a first conductive (P-type or N-type) silicon substrate, and then an undoped poly is formed thereon. Depositing silicon; On the undoped polysilicon layer, first and second resist patterns defining the center and edge portions of the gate region are formed, and the first and second conductivity type dopants are implanted through the respective resist patterns to form the gate region. Forming a double-doped polysilicon layer having a central portion formed of a second conductivity type and an edge portion formed of a first conductivity type; Forming an insulating gate electrode by sequentially forming a first insulating film on the two-doped polysilicon layer, and then sequentially patterning the first insulating film, the two-doped polysilicon layer, and a gate oxide film by photolithography and a grafting process; After implanting the low concentration first conductivity type dopant, the second insulating film sidewall spacer is formed on the side of the insulated gate electrode, and the high concentration first conductivity type dopant is implanted to form the source / drain region of the LED structure. It is characterized by consisting of steps.
이하, 첨부된 도면을 참조하여 본 발명에 대해서 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
우선, 도 2에 도시된 단면도를 참조하여 본 발명의 바람직한 실시예에 따른 반도체소자의 구성 및 작용에 대해서 설명한다.First, the configuration and operation of a semiconductor device according to a preferred embodiment of the present invention will be described with reference to the cross-sectional view shown in FIG. 2.
본 발명의 바람직한 실시예에 따른 2도우프 폴리실리콘 게이트전극 및 엘디디 구조 소오스/드레인영역을 갖는 N채널 전계효과 트랜지스터는, 도 2에 도시된 바와 같이 필드산화막(220)에 의하여 액티브영역과 필드영역이 구분된 P형 실리콘기판(210)의 상기 액티브영역에 엘디디(LDD) 구조로 형성된 N형 소오스/드레인영역(261,262)과, 그 N형 소오스/드레인영역(261,262) 사이로 정의되는 채널영역 위로 형성된 게이트 산화막(231) 및 2도우프 폴리실리콘 게이전극(241,242a)으로 구성됨에 있어서, 상기 2도우프 폴리실리콘 게이트전극(241,242a)이 그의 중심영역은 N-도전형 폴리실리콘층(241)으로 형성되고, 양쪽의 가장자리영역은 P-도전형 폴리실리콘층(242a)으로 형성되는 것을 특징으로 하고 있다. 위에서, 설명하지 않은 251은 제 1 산화막(Top Oxide)이고, 256은 제 2 산화막 측벽스페이서이고, 263은 게이트전압이 0(Zero)일 경우에 채널영역의 가장자리에 형성되는 얇은 반전층을 나타낸다.An N-channel field effect transistor having a 2-doped polysilicon gate electrode and an LED structure source / drain region according to a preferred embodiment of the present invention is formed by the field oxide film 220 as shown in FIG. Channel regions defined between N-type source / drain regions 261 and 262 formed in the active region of the P-type silicon substrate 210 having the divided regions, and N-type source / drain regions 261 and 262 thereof. In the gate oxide film 231 and the two-doped polysilicon gay electrodes 241 and 242a, the center region of the two-doped polysilicon gate electrodes 241 and 242a is an N-conductive polysilicon layer 241. ) And both edge regions are formed of a P-conductive polysilicon layer 242a. In the above description, 251, which is not described above, is a first oxide film (Top Oxide), 256 is a second oxide film sidewall spacer, and 263 represents a thin inversion layer formed at the edge of the channel region when the gate voltage is zero.
이와 같은 2도우프 폴리실리콘 게이트전극 및 엘디디 구조 소오스/드레인영역을 갖는 N채널 전계효과 트랜지스터는, 도면에 표시된 바와 같이 게이트전극(G)의 전압(V)을 인가하지 않는 상태에서도 채널영역의 가장자리에 얇은 반전층(Thin inversion layer)(263)이 형성되는 특성을 갖게 되는데, 그와 같은 얇은 반전층(263)은 유효한 매우 얕은 소오스/드레인 정션(Effective ultra shallow souce/drain Junction)을 형성함으로써 그 소자의 쇼프채널효과를 개선하는 작용을한다. 이대, 상기 얇은 반전층(263)은 게이트전극의 양쪽 가장자리에 형성된 P-도전영역(242a)에 의하여 형성된다.The N-channel field effect transistor having such a double-doped polysilicon gate electrode and an LED structure source / drain region is formed in the channel region even when the voltage V of the gate electrode G is not applied as shown in the drawing. A thin inversion layer 263 is formed at the edge, such a thin inversion layer 263 is formed by forming an effective ultra shallow souce / drain junction. It acts to improve the channel effect of the device. In this case, the thin inversion layer 263 is formed by the P-conductive region 242a formed at both edges of the gate electrode.
그리고, 도 3a-도 3g의 공정 단면도를 참조하여 상기 도 2에 도시된 바와 같이 구성된 2도우프 폴리실리콘 게이트전극 및 엘디디 구조 소오스/드레인영역을 갖는 N채널 전계효과 트랜지스터의 제조방법에 대해서 상세히 설명한다.In addition, a method of manufacturing an N-channel field effect transistor having a double-doped polysilicon gate electrode and an LED structure source / drain region configured as shown in FIG. 2 with reference to the process cross-sectional view of FIGS. 3A to 3G is described in detail. Explain.
먼저, 도 3a와 도 3b에 도시된 바와 같이 일반적인 로커스(LOCOS)공정으로 형성된 필프산화막(220)을 통해 액티브영역과 필드영역이 구분된 실리콘기판(210) 위에 게이트산화막(230)을 형성한 후, 그 게이트산화막(230) 위에 게이트전극을 형성하기 위한 언도우프 폴리실리콘층(240)을 증착한다.First, as shown in FIGS. 3A and 3B, the gate oxide layer 230 is formed on the silicon substrate 210 having the active region and the field region separated by a film oxide layer 220 formed by a general LOCOS process. The undoped polysilicon layer 240 is formed on the gate oxide film 230 to form a gate electrode.
이후, 도 3c에 도시된 바와 같이 상기 언도우프 폴리실리콘층(240) 위에 게이트영역의 중심부를 정의하는 제 1 레지스트패턴(271)을 형성한 후 고농도 N형 이온을 주입하고, 도 3d와 같이 상기 제 1 레지스트패턴(271)과 반대되는 패턴구조를 갖는 제 2 레지스트패턴(272)을 형성한 후, 고농도 P형 이온을 주입한다.Thereafter, as shown in FIG. 3C, a first resist pattern 271 defining a center portion of the gate region is formed on the undoped polysilicon layer 240, and then high concentration N-type ions are implanted, as shown in FIG. 3D. After forming the second resist pattern 272 having a pattern structure opposite to that of the first resist pattern 271, high concentration P-type ions are implanted.
이어서, 도 3e와 같이 상기와 같이 게이트영역의 중심부는 고농도 N형 영역(241)으로 형성되고, 양쪽의 가장자리부는 고농도 P형 영역(242)으로 형성된 2도우프 폴리실리콘층 위에 제 1 산화막(250)을 증착한 후, 도 3f와 같이 포토리소그래피 및 식각공정으로 상기 제 1 산화막(250)과 2도우프 폴리실리콘층(241,242), 게이트산화막(230)을 순차적으로 패터닝하여 절연게이트전극(231,241,242a,251)을 형성하고 나서, 그 절연게이트전극(231,241,242a,251) 및 필드산화막(220)을 마스크로 하는 선택적 이온주입공정으로 저농도 N형 소오스/드레인영역(261)을 형성한다.Subsequently, as shown in FIG. 3E, the center portion of the gate region is formed of the heavily doped N-type region 241, and both edge portions thereof are formed on the two-doped polysilicon layer formed of the heavily doped P-type region 242. ), The first oxide layer 250, the second doped polysilicon layer 241, 242, and the gate oxide layer 230 are sequentially patterned by photolithography and etching processes as shown in FIG. 3F to insulate the gate electrodes 231, 241, and 242a. 251 is formed, and then a low concentration N-type source / drain region 261 is formed by a selective ion implantation process using the insulating gate electrodes 231, 241, 242a and 251 and the field oxide film 220 as a mask.
이후, 도 3g와 같이 상기 절연게이트전극(231,241,242a,251)의 측면에 제 2 산화막 측벽스페이서(256)를 형성한 후, 그 제 2 산화막 측벽스페이서(256)와 절연게이트전극(231,241,242a,151), 필드산화막(220)을 마스크로 하는 선택적 이온주입공정으로 고농도 N형 소오스/드레인영역(262)을 형성함으로써, 2도우프 폴리실리콘 게이트전극 및 엘디디 구조를 갖는 N-채널 진계효과 트랜지스터를 완성한다.Thereafter, as shown in FIG. 3G, a second oxide sidewall spacer 256 is formed on side surfaces of the insulating gate electrodes 231, 241, 242a and 251, and then the second oxide sidewall spacer 256 and the insulating gate electrodes 231, 241, 242a and 151 are formed. ), A high concentration N-type source / drain region 262 is formed by a selective ion implantation process using the field oxide film 220 as a mask, thereby forming an N-channel threshold effect transistor having a double-doped polysilicon gate electrode and an LED structure. Complete
상술한 바와 같이, 2도우프 폴리실리콘 게이트전극을 갖는 것을 특징으로 하는 본 발명에 따른 2도우프 폴리실리콘 게이트전극 및 엘디디 구조를 갖는 N-채널 전계효과 트랜지스터는, 상기 2도우프 폴리실리콘 게이트전극의 양쪽 가장자리부에 형성된 P형 도전영역이 게이트전극에 전압을 인가하지 않는 경우에도 그 아래에 있는 채널영역을 반전시킴으로써 쇼트채널효과를 개선하는 효과가 있다.As described above, the N-channel field effect transistor having the double-doped polysilicon gate electrode and the LED structure according to the present invention, which has a double-doped polysilicon gate electrode, the double-doped polysilicon gate Even when the P-type conductive regions formed at both edges of the electrode do not apply voltage to the gate electrode, the short channel effect is improved by inverting the channel region beneath it.
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