JPS62204574A - Insulated-gate field-effect semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a hot carrier from being produced by a method wherein an inversion preventive layer below a field insulating film is formed to be externally isolated from a channel region on the part near a drain region. CONSTITUTION:After forming a thermal oxide film 12 on the surface of a P-type silicon substrate 11, a silicon nitride film 13 is lamination-formed for patterning to leave the silicon nitride film 13 on an element region only. Resist patterns 141, 142 are formed to be entirely ion-implanted with boron. First, the resist patterns 141, 142 are removed to form a field oxide film 16. Next, the silicon nitride film 13 and the thermal oxide film 12 are removed to form a gate film 17 by thermal oxidation. Second, a polycrystalline silicon layer is deposited by CVD process for patterning to form a gate electrode 18. Furthermore, the element region is doped with arsenic to form an N-type source region 19 and a drain region 20 by self alignment.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to an insulated gate type electromagnetic effect semiconductor device, and particularly to a structure for preventing a decrease in reliability due to hot carriers.

(Prior Art) An MO8 type semiconductor device, which is a typical example of an insulated gate field effect semiconductor device, will be described below.

FIG. 4(A) is a pattern plan view showing a transistor portion of a conventional MO8 type semiconductor device, and FIG. 4(B) is a sectional view taken along line BB in FIG. 4(A). In these figures, 1 is a P-type silicon substrate. A thick field oxide Pa2 is selectively formed on the surface of the silicon substrate. The element 11i surrounded by the field oxide film 2
In the surface layer of 1a, an N+ type source region 3 and a drain region 4 are formed spaced apart from each other. A gate electrode 6 made of a polycrystalline silicon layer is formed in the channel region (the shaded area in FIG. 4A) with a thin gate oxide film 5 interposed therebetween. In addition, field oxide film 2
A P-type anti-inversion layer 7 is formed below.

In the above structure, when a voltage equal to or higher than a predetermined threshold is applied to the electrodes 1 to 6, the surface of the silicon substrate in the channel region is inverted from P type to N type, and the N+ type source region 3 and drain region 1j! 4 are connected through regions of the same conductivity type. As a result, the voltage applied between the source and drain causes a current to flow between them.

Furthermore, the P-type anti-inversion layers 7, 7 formed under the field oxide film 2 contribute to improving the isolation breakdown voltage between elements.

Incidentally, the anti-inversion layers 7, 7 are formed by ion-implanting P-type impurities such as boron into the field region prior to selective oxidation to form the field oxide film 2. That is, after forming a silicon nitride film pattern (the device region is defined by the nitride film pattern) used as an oxidation-resistant mask, boron ions are implanted into the field portion using the nitride film pattern as a blocking mask. Next, using this nitride film pattern as an oxidation-resistant mask, selective oxidation is performed to form field oxide film 2, and boron is activated by the thermal process at that time, and P+ type inversion layer 7 is formed.

In the above-mentioned conventional MO8 type semiconductor device, in most cases, the fourth
As indicated by O in the figure (B), the tip 7' of the P-type anti-inversion layer is formed by penetrating into the channel region. This is because the previously ion-implanted P-type impurity diffused into the element region during the thermal process during field oxidation.

The formation of this intrusion portion 7' is rather effective in preventing transistor leakage. but,
As will be described below, there was a problem in which the reliability decreased significantly due to the generation of hot carriers.

As mentioned above, P-type regions 7 are formed on both sides of the channel region.
′ is formed by penetrating the channel region, the impurity concentration is higher at both edges of the channel region than at the center of the channel region. Therefore, the spread of depletion in the vicinity of the drain region becomes narrower in the P-type regions at both side edges, and a larger electric field is concentrated.

Therefore, generation of hot carriers becomes significant in this portion, which adversely affects device characteristics.

(Problems to be Solved by the Invention) Currently, with the advancement of miniaturization of devices, the channel width itself has become narrower to such an extent that the penetration width 7' of the P-type anti-inversion layer cannot be ignored. The solution is expected to become extremely important in the future.

Therefore, an object of the present invention is to maintain the advantages of conventional MOS type semiconductor devices in preventing transistor leakage, and to improve reliability by preventing the generation of hot carriers.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above-mentioned problems, in the insulated gate field effect semiconductor device of the present invention, at least one of the vicinity of the source region and the vicinity of the drain region in the channel region is provided. In the vicinity of the drain region, the inversion prevention layer under the field insulation crotch is formed at a distance to the outside of the channel region, and in the other channel region areas, the inversion prevention layer is formed by penetrating into both side edges of the channel region as before. I decided to do so.

The structure according to the present invention described above can be easily formed, for example, as follows. In other words, it can be used as a blocking mask when ion-implanting impurities for the anti-inversion layer.
In addition to the oxidation-resistant film that covers the intended element region, a second blocking mask that covers a predetermined region may be used. As this second blocking mask, for example, a resist pattern or the like can be used.

(Function) In the insulated gate field effect semiconductor device of the present invention, the channel region near the drain region has a uniform impurity concentration in the width direction since there is no penetration of the anti-inversion layer. Therefore, the depletion layer from the drain region spreads uniformly, and does not become narrow at both side edges of the channel region. Therefore, generation of significant hot carriers due to electric field concentration at the side edges of the channel region can be prevented.

In addition, in the source/drain intermediate region, since the inversion prevention layer is formed by penetrating both side edges of the channel fr4ili as in the conventional case, channel leakage between elements does not occur easily.

(Example) Hereinafter, an example in which the present invention is applied to an N-channel MO8 type semiconductor device will be described together with a manufacturing method thereof.

(1) First, limit the area that will become the element region as shown in FIG. 1 (A>(B). Note that FIG. 1(A) is a plan view, and FIG. 1(B) is a FIG. 1 is a sectional view taken along line BB in FIG. 1 (A>).

That is, after the surface of the P-type silicon substrate 11 is thermally oxidized to form a thermally oxidized film 112 with a thickness of about 1000 layers, a silicon nitride film 13 with a thickness of about 2000 layers of IIN is laminated by vapor phase growth. Subsequently, the silicon nitride film 13 is patterned by photolithography, leaving silicon nitride 1113 only in the area that will become the element region.

(2) Next, as shown in FIG. 3(A), a resist pattern 141 that covers the vicinity of the end of the planned source part of the planned channel region, and a resist pattern 142 that covers the vicinity of the end of the planned drain part. and form respectively. These resist patterns 141 and 142 are formed so as to protrude outward from both ends of the silicon nitride film pattern 13, respectively. Next, using the resist patterns 141 and 142 and the silicon nitride film 13 as blocking masks, boron ions are implanted into the entire surface to form an anti-inversion layer.

Figure 2 (B) and Figure 2 (C) are respectively Figure 2 (A).
FIG. 2 is a cross-sectional view taken along line BB and line C-C. As shown in the figure, the silicon substrate 11 has P by the ion implantation.
- A mold region 15 is formed. This P° type region 15
In the portions not covered with the resist pattern, they are formed in self-alignment with the silicon nitride film pattern 13, but in the portions where the resist pattern 14 is formed, they are formed away from the edge of the silicon nitride film. .

(3) Next, after removing the resist patterns 141 and 142, selective oxidation is performed using the silicon nitride film pattern 13 as an oxidation-resistant mask to form a field oxide film 16 with a thickness of approximately 1-. Subsequently, after removing the silicon nitride film 13 and the thermal oxide film 12 to expose the element region, a film of about 500 thick films 1 to 11117 is formed by thermal oxidation. Next, a polycrystalline silicon layer with a thickness of 3,000 yen was coated with C.
The gate electrode 18 is formed by depositing by VD method and patterning it. Furthermore, after removing the gate oxide film 17 by etching using the gate electrode as a mask, arsenic is doped into the device region using the gate electrode as a mask.
N+ type source region 19 and drain region 20 which are spaced apart from each other are formed in a self-aligned manner.

FIG. 3(A) is a plan view showing this state, in which the hatched area is the channel wATO of the MOS transistor,
Teal. Figure 3 (B) and (C) are the same figure (A) respectively.
2A and 2B are cross-sectional views taken along line B-B and C-Cm, respectively, showing cross sections at positions corresponding to FIGS. 2(B) and 2(C). As shown, P-type inversion prevention 1i in FIG. 3(B)
115 does not invade into the channel region.
This is because P-115 is formed apart from the edge of the silicon nitride film 13 in FIG. Also, Figure 3 (C
), the P-type inversion prevention region 15 is formed by penetrating into the channel region because the P-region formed in self-alignment with the silicon nitride film pattern in FIG. This is because it extended into the channel region during the thermal process of oxidation.

In addition, in FIG. 3(A), the tip of this P-type anti-inversion layer 15 is indicated by a broken line X.

In the MO8 type semiconductor device according to the embodiment shown in FIG.
In the middle part in the channel length direction, the P-type inversion prevention layer 15 is formed by penetrating into both side edges of the channel region, so that transistor leakage, where current flows from the source to the drain through the side edges of the channel region, does not occur as in the conventional case. Similarly, it can be effectively prevented.

On the other hand, in the vicinity of the drain region 20, as shown in FIG.
), since the anti-inversion layer 15 is spaced apart from the channel region, it is possible to prevent hot carriers from being generated significantly at the side edges of the channel region. In other words, the depletion layer from the drain region spreads evenly in the channel width direction,
Abnormal electric field concentration at the edge of the channel region, which is conventional, is avoided. Therefore, generation of hot carriers is suppressed and reliability can be improved.

In the above embodiment, the inversion prevention layer 15 is formed at the end of the channel region on the source region side, as well as on the drain side, apart from the end of the channel region, but as described above, hot carriers mainly Occurs near the drain region. Therefore, even if an inversion prevention layer is formed in the vicinity of the source region by penetrating into the side edge of the channel region as in the conventional method, a certain degree of effectiveness can be obtained in suppressing hot carrier generation.

[Effects of the Invention] As detailed above, the insulated gate field effect semiconductor device according to the present invention can prevent transistor leakage and the generation of hot carriers, thereby improving reliability, etc. This has a remarkable effect.

[Brief explanation of drawings]

1 to 3 are diagrams showing an MO8 type semiconductor device according to an embodiment of the present invention together with its manufacturing process, and FIG.
1 is a diagram showing an O8 type semiconductor device and its problems; FIG. 11...P-type silicon substrate, 12...thermal oxide film, 1
3... Silicon nitride film, 141.142... Resist pattern, 15... P-type inversion prevention layer, 16...
Field oxide film, 17... Gate oxide film, 18...
・Gate electrode, 19...N" type source region, 20...
・N′″ type drain region applicant patent attorney Takehiko Suzue @ 1 Figure ifl 2 Figure (B) (C) (B)

Claims (1)

[Claims] A field insulating film selectively formed on the surface layer of a first conductive type semiconductor substrate, and a second conductive type source region and drain region formed spaced apart from each other in an element region surrounded by the field insulating film. a gate electrode formed on a channel region between the source region and the drain region via a gate insulating film; and a first conductivity type gate electrode formed in the semiconductor substrate in contact with and below the field insulating film. The inversion prevention layer is formed at least near the drain region in the vicinity of the source region and in the vicinity of the drain region in the channel region, and the inversion prevention layer is formed to be spaced apart from the channel region in other portions of the channel region. An insulated gate field effect semiconductor device characterized in that an anti-inversion layer is formed by penetrating into both side edges of a channel region.