KR0166859B1 - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- KR0166859B1 KR0166859B1 KR1019940024829A KR19940024829A KR0166859B1 KR 0166859 B1 KR0166859 B1 KR 0166859B1 KR 1019940024829 A KR1019940024829 A KR 1019940024829A KR 19940024829 A KR19940024829 A KR 19940024829A KR 0166859 B1 KR0166859 B1 KR 0166859B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 56
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 40
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 40
- 239000010703 silicon Substances 0.000 claims abstract description 40
- 239000004020 conductor Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 35
- 239000010410 layer Substances 0.000 claims description 31
- 230000008569 process Effects 0.000 claims description 28
- 239000012535 impurity Substances 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 9
- 230000010354 integration Effects 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 19
- 229920005591 polysilicon Polymers 0.000 description 19
- 238000005468 ion implantation Methods 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000008570 general process Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Abstract
본 발명은 반도체장치 및 그 제조방법에 관한 것으로, 측면확산이 없는 소오스 및 드레인을 형성하기 위한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and to forming a source and a drain without side diffusion.
본 발명은 실리콘기판과, 상기 실리콘기판상에 게이트절연막을 개재하여 형성된 게이트 및 상기 게이트 양측에지와 동일위치의 상기 실리콘기판에서부터 상기 게이트 양측으로 소정깊이의 상기 실리콘기판에 매립되어 형성된 도전물질층으로 이루어진 소오스 및 드레인을 포함하여 이루어진 반도체장치를 제공함으로써 측면확산이 일어나지 않는 소오스 및 드레인을 형성하여 채널길이의 감소를 막고, 소자의 집적도를 높일 수 있도록 한다.The present invention relates to a silicon substrate, a gate formed through a gate insulating film on the silicon substrate, and a conductive material layer embedded in the silicon substrate at a predetermined depth from both sides of the gate to the gate from the silicon substrate at the same position as both edges of the gate. By providing a semiconductor device including a source and a drain, a source and a drain in which side diffusion does not occur are formed to prevent a reduction in channel length and to increase the degree of integration of the device.
Description
제1도는 종래의 셀프얼라인공정을 이용한 MOSFET 제조방법을 도시한 공정순서도.1 is a process flowchart showing a MOSFET manufacturing method using a conventional self-aligned process.
제2도는 종래의 LDD구조를 갖춘 MOSFET 제조방법을 도시한 공정순서도.2 is a process flowchart showing a method for manufacturing a MOSFET having a conventional LDD structure.
제3도는 본 발명의 일실시예에 의한 MOSFET 단면구조도.3 is a cross-sectional view of the MOSFET according to an embodiment of the present invention.
제4도는 본 발명의 다른 실시예에 의한 MOSFET 단면구조도.4 is a cross-sectional view of a MOSFET according to another embodiment of the present invention.
제5도는 본 발명에 의한 MOSFET 제조방법을 도시한 공정순서도.5 is a process flowchart showing a MOSFET manufacturing method according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 실리콘기판 12 : 필드산화막11 silicon substrate 12 field oxide film
13 : 게이트절연막 14 : 게이트전극13 gate insulating film 14 gate electrode
15 : 포토레지스트 16 : 식각된 실리콘기판부위15 photoresist 16 etched silicon substrate
17 : 산화막 18 : 도전물질층17 oxide film 18 conductive material layer
19 : 소오스 및 드레인 20 : 층간절연막19 source and drain 20 interlayer insulating film
21 : 콘택용 금속층 22 : 저농도 불순물영역21: contact metal layer 22: low concentration impurity region
본 발명은 반도체장치 및 그 제조방법에 관한 것으로, 특히 측면확산이 없는 소오스 및 드레인구조를 갖춘 MOSFET(Metal Oxide Semiconductor Field Effect Transistor) 및 이의 제조방법에 관한 것이다.The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a source and drain structure without side diffusion and a method of manufacturing the same.
MOSFET에서 소오스 및 드레인은 채널을 통과하는 전자나 정공(正孔)을 전송선으로 빼내거나 캐리어들을 주입시킬 때 사용된다. 이 소오스 및 드레인은 일반적으로 불순물의 이온주입(ion implantation)에 의해 형성되며, 일련의 공정 중 폴리실리콘 게이트를 블로킹층(blocking layer)로 사용하여 집적도를 높이고 공정의 효율을 높이는 공정을 셀프얼라인(self-align)이라 하며 제1도에 이 셀프얼라인 공정을 이용한 MOSFET제조방법을 나타내었다.Sources and drains in MOSFETs are used to draw electrons or holes through a channel into a transmission line or to inject carriers. The source and drain are generally formed by ion implantation of impurities, and self-aligning the process of increasing the integration density and the efficiency of the process by using a polysilicon gate as a blocking layer in a series of processes The self-alignment method is shown in FIG. 1 and shows a method of manufacturing a MOSFET using this self-alignment process.
즉, 제1도 (a)와 같이 p형 실리콘기판(1)상에 산화막(2)과 질화막(3)을 차례로 형성한 후, 제1도 (b)와 같이 포토레지스트(4)를 이용한 사진식각공정을 통해 소자분리영역을 정의한 다음 채널스톱이온주입을 행한다.That is, the oxide film 2 and the nitride film 3 are sequentially formed on the p-type silicon substrate 1 as shown in FIG. 1A, and then the photoresist 4 is used as shown in FIG. The device isolation region is defined by an etching process and then channel stop ion implantation is performed.
이어서 제1도 (c)와 같이 필드산화막공정을 행하여 소자분리영역에 필드산화막(5)을 형성한 후, 상기 질화막을 제거하고, 게이트형성을 위한 폴리실리콘을 증착하고 이를 패터닝하여 게이트전극(6)을 형성한다.Subsequently, a field oxide film 5 is formed in the device isolation region by performing a field oxide film process as shown in FIG. 1C, and then the nitride film is removed, polysilicon is deposited and patterned to form a gate electrode 6. ).
다음에 제1도 (d)와 같이 상기 게이트전극(6)을 마스크로 이용하여 n형 불순물을 이온주입하여 게이트전극 양단의 기판부위에 소오스 및 드레인(7)을 형성한다.Next, as shown in FIG. 1 (d), n-type impurities are ion-implanted using the gate electrode 6 as a mask to form a source and a drain 7 on the substrate portions across the gate electrode.
상기와 같이 이온주입에 의해 소오스 및 드레인영역을 형성하는 셀프얼라인공정은 주입된 불순물이온들이 후속의 열처리공정 등에 의해 측면으로 확산되는 것을 막을 수 없기 때문에 소자를 집적시키는데 한계가 있고, 채널길이의 감소로 인한 소자의 문턱전압 감소, 펀치쓰루(punchthrough)전압 감소, 브레이크다운전압 감소 등이 일어나며, 핫캐리어 효과(hot carrier effect)등 숏채널효과(short channel effect)에 의한 영향을 받기가 쉽고, 소자의 동작특성이 저하된다. 이와 같은 측면확산으로 인한 문제점을 방지하기 위한 하나의 방법으로서 LDD(Lightly Doped Drain)구조가 제안되었는 바, 제2도를 참조하여 이를 설명하면 다음과 같다.As described above, the self-alignment process of forming the source and drain regions by ion implantation has a limitation in integrating devices because the implanted impurity ions cannot be prevented from spreading laterally by a subsequent heat treatment process. Due to the reduction, the threshold voltage of the device, the punchthrough voltage, the breakdown voltage, and the like are easily affected by the short channel effect such as the hot carrier effect. The operating characteristics of the device are deteriorated. As a method for preventing the problem caused by the side diffusion such as LDD (Lightly Doped Drain) structure has been proposed, referring to Figure 2 as follows.
먼저, 제2도 (a)와 같이 p형 실리콘기판(1)상에 게이트산화막(2)과 폴리실리콘층(6)을 차례로 형성한 후, 제2도 (b)와 같이 상기 폴리실리콘층(6)과 게이트산화막(2)을 게이트패턴으로 패터닝한 다음, n형 불순물을 저농도로 이온주입한다.First, as shown in FIG. 2A, the gate oxide film 2 and the polysilicon layer 6 are sequentially formed on the p-type silicon substrate 1, and then, as shown in FIG. 2B, the polysilicon layer ( 6) and the gate oxide film 2 are patterned by a gate pattern, and then ion implantation is carried out at low concentration with n-type impurities.
이어서 제2도 (c)와 같이 기판상에 절연막(8)을 형성한 후, 이를 에치백하여 제2도 (d)와 같이 게이트측면에 절연막(8)을 형성한 다음, 제2도 (e)와 같이 n형 불순물을 고농도로 이온주입한 후, 상기 측벽스페이서를 제거함으로써 제2도 (f)에 도시된 바와 같이 저농도 불순물영역과 고농도 불순물영역으로 이루어진 LDD구조의 소오스 및 드레인(9)을 형성한다.Subsequently, an insulating film 8 is formed on the substrate as shown in FIG. 2 (c), and then etched back to form an insulating film 8 on the gate side as shown in FIG. After ion implantation with high concentration of n-type impurity as shown in FIG. Form.
상기와 같은 LDD구조의 MOSFET는 측벽스페이서 형성을 위한 절연막 증착공정과 에치백공정 및 이온주입공정 등 추가되는 공정들로 인해 제조공정이 복잡해지는 문제가 있다.The MOSFET of the LDD structure as described above has a problem in that the manufacturing process is complicated due to additional processes such as an insulating film deposition process, an etch back process, and an ion implantation process for forming sidewall spacers.
본 발명은 상술한 문제를 해결하기 위한 것으로 측면확산이 없는 소오스 및 드레인을 갖춘 MOSFET구조 및 이의 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object thereof is to provide a MOSFET structure having a source and a drain without side diffusion and a method of manufacturing the same.
상기 목적을 달성하기 위한 본 발명의 반도체장치는 실리콘기판과; 상기 실리콘기판상에 게이트절연막을 개재하여 형성된 게이트; 및 상기 게이트 양측 에지와 동일위치의 상기 실리콘기판에서부터 상기 게이트 양측으로 소정깊이의 상기 실리콘기판에 매립되어 형성된 도전물질층으로 이루어진 소오스 및 드레인을 포함하여 이루어진다.A semiconductor device of the present invention for achieving the above object is a silicon substrate; A gate formed on the silicon substrate via a gate insulating film; And a source and a drain formed of a conductive material layer formed by embedding the silicon substrate at a predetermined depth from both the silicon substrate at the same position as the edges of the gate to both sides of the gate.
상기 목적을 달성하기 위한 본 발명의 반도체장치 제조방법은 실리콘기판상에 게이트절연막과 게이트 형성을 위한 도전층을 차례로 형성하는 단계와, 상기 도전층과 게이트절연막을 게이트패턴으로 패터닝하여 게이트를 형성하는 단계, 노출된 게이트 양측에지와 동일 위치의 상기 실리콘기판에서부터 상기 게이트 양측으로 소정거리만큼의 상기 실리콘기판부위를 소정깊이로 식각하는 단계, 열산화공정을 실시하여 게이트 표면 및 실리콘기판상에 산화막을 형성하는 단계, 상기 식각된 실리콘기판부위상에 형성된 산화막을 식각하는 단계, 기판 전면에 도전물질층을 증착하는 단계, 및 상기 도전물질층을 에치백하여 식각된 실리콘기판부위에 매립된 도전물질층만 남겨 놓아서 소오스 및 드레인을 형성하는 단계를 포함하여 이루어진다.A semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of sequentially forming a gate insulating film and a conductive layer for forming a gate on a silicon substrate, and forming a gate by patterning the conductive layer and the gate insulating film in a gate pattern Etching the silicon substrate portion by a predetermined depth from the silicon substrate at the same position as the exposed edges of both sides of the gate to the both sides of the gate, and performing a thermal oxidation process to deposit an oxide film on the gate surface and the silicon substrate. Forming, etching the oxide film formed on the etched silicon substrate, depositing a conductive material layer on the entire surface of the substrate, and etching the conductive material layer to embed the conductive material layer embedded in the etched silicon substrate. Forming a source and a drain, leaving only the source.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제3도에 본 발명의 일실시예에 의한 MOSFET의 단면구조를 도시하였다.3 shows a cross-sectional structure of a MOSFET according to an embodiment of the present invention.
제3도에 도시된 바와 같이 본 발명에 의한 MOSFET는 실리콘기판(11)상에 게이트절연막(13)을 개재하여 게이트전극(14)이 형성되고, 게이트전극(14) 양측에지와 동일위치의 상기 실리콘기판(11)에서부터 상기 게이트전극(14) 양측으로 소정깊이의 상기 실리콘기판(11)에 도전물질이 매립되어 소오스 및 드레인(19)이 형성되어 있다. 게이트전극(14)의 표면에는 절연막(17)이 형성되어 게이트전극(14)과 소오스 및 드레인(19)이 단락되는 것을 방지한다.As shown in FIG. 3, in the MOSFET according to the present invention, the gate electrode 14 is formed on the silicon substrate 11 via the gate insulating film 13, and the gate electrode 14 is formed at the same position as the edges on both sides of the gate electrode 14. As shown in FIG. A conductive material is embedded in the silicon substrate 11 at a predetermined depth from the silicon substrate 11 to both sides of the gate electrode 14 to form a source and a drain 19. An insulating film 17 is formed on the surface of the gate electrode 14 to prevent the gate electrode 14 and the source and drain 19 from being short-circuited.
상기 소오스 및 드레인(19)은 예컨대 n+폴리실리콘(기판이 p형일 경우)으로 형성할 수 있으며, 상기 절연막(17)으로는 열산화막을 사용할 수 있다.The source and drain 19 may be formed of, for example, n + polysilicon (when the substrate is p-type), and a thermal oxide film may be used as the insulating film 17.
상기 소오스 및 드레인(19)은 게이트전극 양단의 기판부위를 소정깊이로 식각하고, 이 식각된 부분에 도전물질이 매립됨으로써 이루어진 것이다.The source and drain 19 are formed by etching a substrate portion at both ends of a gate electrode to a predetermined depth, and filling a conductive material in the etched portion.
제4도는 본 발명의 다른 실시예에 의한 MOSFET 단면구조도로서, 소오스 및 드레인(19)주위에 소오스 및 드레인(19)보다 낮은 농도로 된 저농도 불순물영역(22), 예컨대 n-영역이 형성된 LDD구조를 나타낸 것이다. 상기 저농도 불순물영역(22)은 소오스 및 드레인(19)을 형성한 후, 열처리공정을 행하여 소오스 및 드레인을 이루는 도전물질층의 불순물을 기판쪽으로 확산시킴으로써 종래와 같은 측벽스페이서 형성공정 및 이온주입공정 등의 추가공정 필요없이 간단하게 형성할 수 있다.FIG. 4 is a cross-sectional view of a MOSFET according to another embodiment of the present invention. An LDD structure in which a low concentration impurity region 22, for example, an n-region, is formed around a source and a drain 19 at a lower concentration than the source and drain 19 is shown. It is shown. The low concentration impurity region 22 forms a source and a drain 19, and then performs a heat treatment to diffuse impurities from the conductive material layer constituting the source and drain toward the substrate, thereby forming a sidewall spacer and an ion implantation process. It can be formed simply without the need for additional steps.
소오스 및 드레인 형성을 위한 도전물질로는 상기한 바와 같은 n+폴리실리콘 이외에도 채널농도에 따라 다른 물질을 사용할 수도 있는데 일반적으로 채널농도가 5.0×1017/㎠ 이하이면 n+폴리실리콘 또는 p+폴리실리콘을 사용하는 것이 가능하나, 그 이상일 경우에는 nMOS에서는 Al을, pMOS에서는 W, Mo, Co, Pt 등을 사용할 수도 있다.In addition to n + polysilicon as described above, other materials may be used as the conductive material for source and drain formation. Generally, when the channel concentration is 5.0 × 10 17 / cm 2 or less, n + polysilicon or p + poly It is possible to use silicon, but in the case of more than that, Al may be used for nMOS, and W, Mo, Co, Pt, etc. may be used for pMOS.
이와 같이 본 발명의 MOSFET는 소오스 및 드레인(19)이 기판 소정부위에 불순물이 이온주입되어 형성된 영역이 아니라, 기판내에 매립되어 형성된 도전물질층으로 이루어지며, 기판의 실리콘과 소오스 및 드레인을 이루는 도전물질간의 일함수(work function)차에 의해 오믹콘택이 이루어지는 구조로 되어 있다.As described above, the MOSFET of the present invention is not a region in which the source and drain 19 are formed by ion implantation of impurities in a predetermined portion of the substrate, but a conductive material layer formed by being embedded in the substrate. It has a structure in which ohmic contact is made by a work function difference between materials.
이와 같이 소오스 및 드레인을 도전물질을 증착하여 형성하므로 종래와 같은 측면확산에 의한 채널길이의 감소를 막을 수 있고, 이로 인한 여러가지 문제점들을 해결할 수 있다.Thus, since the source and the drain are formed by depositing a conductive material, it is possible to prevent the reduction in the channel length due to side diffusion as in the prior art, and thus solve various problems.
다음에 제5도를 참조하여 본 발명에 의한 MOSFET제조방법을 설명한다.Next, a MOSFET manufacturing method according to the present invention will be described with reference to FIG.
먼저, 제5도 (a)에 도시된 바와 같이 제1도전형의 기판으로서, p형 실리콘기판(11)의 소정의 소자분리영역에 일반적인 공정을 통해 필드산화막(12)을 형성한 후, 기판전면에 게이트절연막(13)으로서, 예컨대 산화막을 얇게 형성하고, 이위에 게이트전극 형성을 위한 도전층으로서, 예컨대 n+폴리실리콘을 증착한다.First, as shown in FIG. 5A, as the first conductive substrate, the field oxide film 12 is formed in a predetermined device isolation region of the p-type silicon substrate 11 through a general process, and then the substrate. For example, a thin oxide film is formed as the gate insulating film 13 on the entire surface, and n + polysilicon is deposited thereon as a conductive layer for forming the gate electrode.
다음에 제5도(b)에 도시된 바와 같이 상기 n+폴리실리콘층상에 포토레지스트(15)를 도포한 후, 이를 사진공정을 통해 선택적으로 노광 및 현상하여 게이트패턴을 형성한다.Next, as shown in FIG. 5 (b), the photoresist 15 is coated on the n + polysilicon layer, and then it is selectively exposed and developed through a photo process to form a gate pattern.
이어서 제5도 (c)에 도시된 바와 같이 상기 포토레지스트(15)를 마스크로 하여 상기 n+폴리실리콘층을 식각하여 게이트전극(14)을 형성하고, 계속해서 상기 게이트절연막(13)을 식각하여 이에 따라 노출된 실리콘기판부위(16)를 상기 게이트전극(14) 양측에지와 동일 위치의 상기 실리콘기판(11)에서부터 상기 게이트전극(14) 양측으로 소정거리만큼 소정깊이 식각한 후, 상기 포토레지스트(15)를 제거한다. 이때, 상기 게이트전극(14)은 게이트산화막 및 실리콘기판 식각시 포토레지스트(15)에 의해 보호되므로 손상되는 일은 없다.Subsequently, as illustrated in FIG. 5C, the n + polysilicon layer is etched using the photoresist 15 as a mask to form a gate electrode 14, and then the gate insulating layer 13 is etched. Thus, the exposed silicon substrate portion 16 is etched a predetermined distance from the silicon substrate 11 at the same position as both edges of the gate electrode 14 to the both sides of the gate electrode 14 by a predetermined distance, and then the photo The resist 15 is removed. In this case, the gate electrode 14 is protected by the photoresist 15 during etching of the gate oxide film and the silicon substrate, so that the gate electrode 14 is not damaged.
다음에 제5도 (d)에 도시된 바와 같이 게이트전극이 후속공정에서 형성될 소오스 및 드레인용 도전층과의 단락을 방지하고 소오스 및 드레인용 도전층의 식각시 게이트전극을 보호하기 위해 열산화공정을 실시하여 산화막(17)을 형성한다. 이때, 게이트전극을 이루는 폴리실리콘상에 형성되는 산화막의 두께와 실리콘기판상에 형성되는 산화막의 두께비는 약 3:1정도이므로 예컨대 게이트전극상에는 약 600Å, 실리콘기판상에는 약 200Å정도 두께의 산화막(17)이 형성되도록 열산화공정을 진행한다. 산화막두께는 공정에 따라 다를수도 있으며, 실리콘기판상에 형성되는 산화막의 두께를 모니터하여 전체 산화막의 두께를 조절하는 것이 바람직하다. 제5도 (d)에 게이트전극(14) 일측면 및 식각된 기판부위의 일정부분을 확대도를 함께 나타낸 바, 도시된 바와 같이 상기 산화막(17)이 게이트전극(14) 상부 및 그 측면에는 두껍게 형성되고, 기판상에는 얇게 형성되며, 노출된 게이트절연막(13) 측면부위에는 매우 얇게 형성된 것을 알 수 있다. 이때, 상기 산화막(17)은 수직 및 수평한 방향뿐만 아니라 대각선으로도 산화되어 형성된다.Next, as shown in FIG. 5 (d), the gate electrode is thermally oxidized to prevent a short circuit between the source and drain conductive layers to be formed in a subsequent process, and to protect the gate electrode during etching of the source and drain conductive layers. The process is performed to form the oxide film 17. In this case, the thickness ratio of the oxide film formed on the polysilicon forming the gate electrode to the oxide film formed on the silicon substrate is about 3: 1. Thermal oxidation process is carried out to form). The thickness of the oxide film may vary depending on the process, and it is preferable to control the thickness of the entire oxide film by monitoring the thickness of the oxide film formed on the silicon substrate. An enlarged view of one side of the gate electrode 14 and a portion of the etched substrate is shown in FIG. 5 (d). As illustrated, the oxide layer 17 is disposed on the gate electrode 14 and on its side. It can be seen that it is formed thick, thin on the substrate, and very thin on the exposed side surface of the gate insulating film 13. At this time, the oxide film 17 is formed by oxidizing diagonally as well as vertical and horizontal directions.
다음에 제5도 (e)에 도시된 바와 같이 상기 산화막(17)을 예컨대 RIE(Reac tive Ion Etching)등의 방법을 이용하여 200Å정도, 즉, 실리콘기판(11)상에 형성된 산화막(17)의 두께만큼 식각해낸다. 이와 같이 하게 되면 산화막(17)이 두껍게 형성된 게이트전극(14)상에는 여전히 산화막(17)이 남아있게 되고(400Å정도), 식각된 실리콘기판(11)상의 산화막(17)은 모두 제거되게 된다.Next, as shown in FIG. 5E, the oxide film 17 is formed on the silicon substrate 11 by about 200 microseconds, for example, using a method such as Reactive Ion Etching (RIE). Etch as much as In this manner, the oxide film 17 remains on the gate electrode 14 having the thick oxide film 17 formed thereon (about 400 microns), and the oxide film 17 on the etched silicon substrate 11 is removed.
이어서 제5도 (f)에 도시된 바와 같이 기판 전면에 소오스 및 드레인전극 형성을 위한 도전물질층(18)을 형성한다. 이때, 실리콘기판(11)과 반대도전형의 n+폴리실리콘을 증착한다. (pMOS일 경우에는 n형 기판에 p형 폴리실리콘을 이용한다)Subsequently, as shown in FIG. 5 (f), the conductive material layer 18 for forming the source and drain electrodes is formed on the entire surface of the substrate. At this time, n + polysilicon of the opposite conductivity type to the silicon substrate 11 is deposited. (In case of pMOS, p-type polysilicon is used for n-type substrate.)
다음에 제5도 (g)에 도시된 바와 같이 상기 형성된 도전물질층(18)인 n+폴리실리콘층을 에치백하여 식각된 실리콘기판부위에 매립되어 형성된 소오스 및 드레인(19)을 각각 형성한다. 이때, 게이트전극(14)상의 산화막(17)에 의해 n+폴리실리콘의 에치백시 게이트전극(14)이 손상되는 것이 방지된다.Next, as shown in FIG. 5 (g), the n + polysilicon layer, which is the conductive material layer 18, is etched back to form a source and a drain 19 formed by being embedded in the etched silicon substrate. . At this time, the gate electrode 14 is prevented from being damaged by the oxide film 17 on the gate electrode 14 when n + polysilicon is etched back.
이어서 제5도 (h)에 도시된 바와 같이 기판 전면에 층간절연막(20)으로서, 예컨대 LTO(low temperature oxide) 또는 BPSG(borophospho-silicate glass)을 형성한 후, 이를 선택적으로 식각하여 상기 형성된 소오스 및 드레인(19)을 노출시키는 콘택개구부를 형성한 다음, 상기 콘택개구부를 포함한 층간절연막(20)상에 콘택용 금속층(21)을 증착하고 패터닝함으로써 MOSFET 제조공정을 완료한다. 상기 콘택용 금속으로는 실리콘과 금속이 오믹콘택을 이룰 수 있는 것이면 어느 것이든 사용이 가능하다.Subsequently, as shown in FIG. 5 (h), an interlayer insulating film 20 is formed on the entire surface of the substrate, for example, low temperature oxide (LTO) or borophospho-silicate glass (BPSG), and then selectively etched to form the source formed thereon. And forming a contact opening exposing the drain 19, and then depositing and patterning the contact metal layer 21 on the interlayer insulating film 20 including the contact opening to complete the MOSFET manufacturing process. As the contact metal, any one may be used as long as silicon and metal can make ohmic contact.
한편, 제5도 (i)에 도시된 바와 같이 소오스 및 드레인(19)에 열처리공정을 행하여 소오스 및 드레인(19)을 형성하는 n+폴리실리콘으로부터 불순물을 확산시켜 소오스 및 드레인(19)주위에 저농도의 불순물영역(22)을 형성하여 측벽스페이서 형성공정등과 같은 별도의 LDD공정없이도 LDD구조를 형성하여 핫캐리어효과를 줄이도록 한다.On the other hand, as shown in FIG. 5 (i), a heat treatment process is performed on the source and the drain 19 to diffuse impurities from n + polysilicon forming the source and the drain 19 so as to surround the source and the drain 19. The low concentration impurity region 22 is formed to form a LDD structure without a separate LDD process such as a sidewall spacer forming process and the like to reduce the hot carrier effect.
상기 실시예에서는 소오스 및 드레인 형성물질로서 n+폴리실리콘을 이용하였는데 소오스 및 드레인 형성물질을 채널농도에 따라 결정할 수 있다.In the above embodiment, n + polysilicon was used as the source and drain forming material, and the source and drain forming material may be determined according to the channel concentration.
일반적으로 채널농도가 5.0×1017/㎠이하이면 n+폴리실리콘 또는 p+폴리실리콘을 사용하는 것이 가능하나, 그 이상일 경우에는 nMOS에서는 Al을, pMOS에서는 W, Mo, Co, Pt 등을 사용할 수도 있다.In general, when the channel concentration is 5.0 × 10 17 / ㎠ or less, it is possible to use n + polysilicon or p + polysilicon, but if it is higher than that, Al is used in nMOS, and W, Mo, Co, Pt, etc. in pMOS. It may be.
이상과 같이 본 발명은 소오스 및 드레인을 이온주입에 의해 형성하지 않고 실리콘기판을 식각하여 이 식각된 부위에 도전물질을 매립하여 형성한다. 따라서 종래기술의 문제점이었던 측면확산으로 인한 채널길이의 감소를 막을 수 있을뿐 아니라 이로 인한 여러가지 문제를 해결할 수 있으며, 특히 측면확산이 방지되므로 소자의 집적도를 높일 수 있는 장점을 가진다.As described above, in the present invention, the silicon substrate is etched without forming the source and drain by ion implantation, and the conductive material is embedded in the etched portion. Therefore, it is possible to prevent the reduction of the channel length due to side diffusion, which is a problem of the prior art, and to solve various problems caused by this. In particular, since side diffusion is prevented, the integration of the device can be improved.
또한, 열처리공정만을 행함으로써 추가공정없이 LDD구조의 형성이 가능하게 된다.In addition, by performing only the heat treatment step, the LDD structure can be formed without an additional step.
그리고 이온주입 및 주입된 이온의 확산을 위한 어닐링공정이 필요없으므로 소자특성의 예측 및 공정의 조절이 용이하게 된다.And since the annealing process for the ion implantation and diffusion of the implanted ions is not necessary, it is easy to predict device characteristics and to control the process.
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