KR960012572A - Semiconductor device and manufacturing method - Google Patents

Semiconductor device and manufacturing method Download PDF

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KR960012572A
KR960012572A KR1019940024829A KR19940024829A KR960012572A KR 960012572 A KR960012572 A KR 960012572A KR 1019940024829 A KR1019940024829 A KR 1019940024829A KR 19940024829 A KR19940024829 A KR 19940024829A KR 960012572 A KR960012572 A KR 960012572A
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South Korea
Prior art keywords
drain
source
gate
forming
silicon substrate
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KR1019940024829A
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Korean (ko)
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KR0166859B1 (en
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정원영
이준성
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문정환
금성일렉트론 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

Abstract

본 발명은 반도체장치 및 그 제조방법에 관한 것으로, 측면확산이 없는 소오스 및 드레인을 형성하기 위한 것이다. 본 발명은 실리콘기판과, 상기 실리콘기판상에 게이트절연막을 개재하여 형성된 게이트 및 상기 게이트 양단의 실리콘기판내에 소정깊이로 매립되어 형성된 도전물질층으로 이루어진 소오스 드레인을 포함하여 이루어진 반도체장치를 제공함으로써 측면확산이 일어나지 않는 소오스 및 드레인을 형성하여 채널길이의 감소를 막고, 소자의 집적도를 높일 수 있도록 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and to forming a source and a drain without side diffusion. The present invention provides a semiconductor device comprising a semiconductor substrate comprising a silicon substrate, a gate formed on the silicon substrate via a gate insulating film, and a source drain formed of a conductive material layer embedded in a silicon substrate at both ends of the gate to a predetermined depth. A source and a drain which do not occur are formed to prevent the channel length from being reduced and to increase the degree of integration of the device.

Description

반도체장치 및 그 제조방법Semiconductor device and manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명의 일실시예에 의한 MOSFET 단면구조도,3 is a cross-sectional view of the MOSFET structure according to an embodiment of the present invention,

제4도는 본 발명의 다른 실시예에 의한 MOSFET 단면구조도.4 is a cross-sectional view of a MOSFET according to another embodiment of the present invention.

Claims (12)

실리콘기판과; 상기 실리콘기판상에 게이트절연막을 개재하여 형성된 게이트; 및 상기 게이트 양단의 실리콘기판내에 소정깊이로 매립되어 형성된 도전물질층으로 이루어진 소오스 및 드레인을 포함하여 이루어진 것을 특징으로 하는 반도체장치.A silicon substrate; A gate formed on the silicon substrate via a gate insulating film; And a source and a drain formed of a conductive material layer formed in the silicon substrate at both ends of the gate. 제1항에 있어서, 상기 도전물질층은 n+폴리실리콘 또는 p+폴리실리콘으로 형성된 것을 특징으로 하는 반도체장치.The semiconductor device of claim 1, wherein the conductive material layer is formed of n + polysilicon or p + polysilicon. 제1항에 있어서, 상기 도전물질층은 Al, W, Mo, Co, Pt중에서 선택된 어느 하나로 형성된 것을 특징으로 하는 반도체장치.The semiconductor device of claim 1, wherein the conductive material layer is formed of any one selected from Al, W, Mo, Co, and Pt. 제1항에 있어서, 상기 게이트 표면에 형성되어 게이트와 상기 소오스 및 드레인과의 단락을 방지하는 절연막을 더 포함하는 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 1, further comprising an insulating film formed on the gate surface to prevent a short circuit between the gate and the source and drain. 제4항에 있어서, 상기 절연막은 열산화막임을 특징으로 하는 반도체장치.The semiconductor device according to claim 4, wherein the insulating film is a thermal oxide film. 제1항에 있어서, 상기 소오스 및 드레인 주위에 형성되며 소오스 및 드레인과 같은 도전형을 가지면서 소오스 및 드레인보다 도전성이 낮은 영역을 더 포함하는 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 1, further comprising a region formed around the source and drain and having a conductivity type such as a source and a drain, and having a lower conductivity than the source and drain. 제6항에 있어서, 상기 소오스 및 드레인은 불순물이 고농도로 도핑된 폴리실리콘으로 형성되고, 상기 소오스 및 드레인 주위에 형성된 영역은 상기 소오스 및 드레인을 이루는 폴리실리콘의 불순물이 저농도로 도핑된 영역으로 이루어진 것임을 특징으로 하는 반도체장치.The method of claim 6, wherein the source and the drain are formed of polysilicon doped with a high concentration of impurities, and a region formed around the source and the drain is formed of a region doped with a low concentration of impurities of the polysilicon constituting the source and drain. And a semiconductor device. 실리콘기판상에 게이트절연막과 게이트 형성을 위한 도전층을 차례로 형성하는 단계와, 상기 도전층과 게이트절연막을 게이트패턴으로 패터닝하여 게이트를 형성하는 단계, 노출된 게이트 양단부분의 실리콘게판부이를 소정깊이로 식각하는 단계, 열산화공정을 실시하여 게이트 표면 및 실리콘기판상에 산화막을 형성하는 단계, 상기 식각된 실리콘기판부위상에 형성된 산화막을 식각하는 단계, 기판 전면에 도전물질을 증착시키는 단계, 및 상기 도전지리층을 에치백하여 식각된 실리콘기판부위에 매립시켜 소오스 및 드레인을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체장치 제조방법.Forming a gate insulating film and a conductive layer for forming a gate on a silicon substrate, forming a gate by patterning the conductive layer and the gate insulating film into a gate pattern, and forming a silicon substrate buried at both ends of the exposed gate Etching an oxide layer, forming an oxide film on a gate surface and a silicon substrate by performing a thermal oxidation process, etching an oxide film formed on the etched silicon substrate portion, depositing a conductive material on the entire surface of the substrate, and And etching the conductive geographic layer to bury the conductive geographic layer and bury it in the etched silicon substrate to form a source and a drain. 제8항에 있어서, 상기 도전물질층은 n+폴리실리콘 또는 p+폴리실리콘을 증착하여 형성하는 것을 특징으로 하는 반도체장치 제조방법.The method of claim 8, wherein the conductive material layer is formed by depositing n + polysilicon or p + polysilicon. 제8항에 있어서, 상기 도전물질층은 Al, W, Mo, Co, Pt중에서 선택한 어느 하나를 증착하여 형성하는 것을 특징으로 하는 반도체장치 제조방법.The method of claim 8, wherein the conductive material layer is formed by depositing any one selected from Al, W, Mo, Co, and Pt. 제8항에 있어서, 상기 소오스 및 드레인을 형성하는 단계후에 열처리공정을 행하여 소오스 및 드레인을 형성하는 도전물질층내의 불순물을 확산시켜 소오스 및 드레인주위에 저농도의 불순물영역을 형성하는 단계를 더 포함되는 것을 특징으로하는 반도체장치 제조방법.The method of claim 8, further comprising: performing a heat treatment after forming the source and drain to diffuse impurities in the conductive material layer forming the source and drain to form a low concentration impurity region around the source and drain. A semiconductor device manufacturing method, characterized in that. 제8항에 있어서, 상기 소오스 및 드레인을 형성하는 단계후에 기판 전면에 층간절연막을 형성하는 단계와, 상기 층간절연막을 선택적으로 식각하여 상기 소오스 및 드레인을 노출시키는 콘택개구부를 형성하는 단계, 상기 콘택개구부를 포함한 층간절연막상에 콘택용 금속을 증착하는 단계가 더 포함되는 것으 특징이로 하는 반도체장치 제조방법.The method of claim 8, after forming the source and drain, forming an insulating interlayer on the entire surface of the substrate, and selectively forming the contact openings to expose the source and drain by selectively etching the interlayer insulating layer. And depositing a contact metal on the interlayer insulating film including the openings. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임※ Note: The disclosure is based on the initial application.
KR1019940024829A 1994-09-29 1994-09-29 Semiconductor device manufacturing method KR0166859B1 (en)

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KR1019940024829A KR0166859B1 (en) 1994-09-29 1994-09-29 Semiconductor device manufacturing method

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KR1019940024829A KR0166859B1 (en) 1994-09-29 1994-09-29 Semiconductor device manufacturing method

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KR960012572A true KR960012572A (en) 1996-04-20
KR0166859B1 KR0166859B1 (en) 1999-01-15

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