JP3454076B2 - Silicon carbide semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to relates to the structure of the silicon carbide semiconductor device.

[0002]

2. Description of the Related Art One of semiconductor devices is a static induction transistor. This transistor has a source region on the front surface of the semiconductor substrate, a drain region on the back surface, and a high specific resistance region serving as a current path between the source region and the drain region. In the static induction transistor, the current flowing through the high resistivity region is turned on / off by controlling the voltage applied to the gate region on the semiconductor surface.

FIG. 2 shows a basic structure of a conventional static induction transistor, which is provided with a high impurity concentration n-type source region 4 and a high impurity concentration n-type drain region 2, and has a low impurity concentration between both regions 2 and 4. A concentration n-type drift region 1 is provided. High impurity concentration p-type on the same side as the n-type source region 4
The gate region 3 is provided, and the current is turned on / off by the action of the gate region 3.

In the static induction transistor as described above, the low impurity concentration n type drift region 1 between the high impurity concentration n type source region 4 and the high impurity concentration n type drain region 2 is used.
Is turned on / off by the expansion of the depletion layer due to the voltage applied to the high impurity concentration p-type gate region 3. As the electrostatic induction transistor is made higher in withstand voltage, the voltage applied to the high impurity concentration p-type gate region 3 in order to block the source-drain voltage is increased, so that the high impurity concentration p-type gate region 3 and the high impurity concentration are increased. Although it is necessary to increase the breakdown voltage of the n-type source region 4, the high impurity concentration p-type gate region 3 and the high impurity concentration n-type source region 4 are required.
It is not possible to secure the breakdown voltage between the gate and source with the direct junction of. Therefore, the low impurity concentration n-type drift region 1 is provided between the high impurity concentration p-type gate region 3 and the high impurity concentration n-type source region 4, and the high impurity concentration p-type gate region 3 and the high impurity concentration n-type source region 4 are connected to each other. Secure the withstand voltage of.

[0005]

The conventional gate and source structures are strictly required to have alignment accuracy on the gate side and finished dimensional accuracy. First, the static induction transistor is the source,
The specified voltage applied between drains is blocked by the reverse bias voltage between the gate and source. Here, the voltage amplification factor μ is defined as the gate voltage with respect to the controlled source-drain voltage. This is an electrostatic induction transistor with a withstand voltage of 5 kV class, and the withstand voltage between the gate and the source is 50 V when the voltage amplification factor μ is 100. When it is made of silicon, the distance between the gate region 3 and the source region 4 needs to be 2.5 μm or more. The conventional gate structure requires extremely strict processing accuracy, and the yield cannot be increased even if techniques such as the stepper exposure method and the self-alignment method are used.

By the way, recently, silicon carbide has attracted attention as a semiconductor material other than silicon. Silicon carbide has a maximum electric field strength higher than that of silicon by one digit or more and a large band gap, and is therefore considered to be optimal for high breakdown voltage elements and high temperature semiconductor elements. When a static induction transistor with a withstand voltage of 5 kV and a voltage amplification factor of 100 is made of silicon carbide, the distance between the gate and the source is 0.25 μm. Therefore, a fine processing of 10 times or more that of the silicon process is required, and it is extremely difficult to achieve such a processing accuracy with the existing device process technology.

When the gate-source distance is set to be wider than 0.25 μm and it is manufactured by a feasible processing technique, the following problems occur. The drift region concentration of a static induction transistor having a withstand voltage of 5 kV class is 10 ¹³ cm to ³ for silicon, whereas it is 10 ¹⁵ cm to ³ for silicon carbide. Therefore,
The extension of the depletion layer of silicon carbide is about 1/10 of that of silicon. If there is a margin in processing accuracy, the gate voltage required for blocking becomes high and the blocking characteristic deteriorates.

As another means, it is conceivable to lower the drift region concentration so that the depletion layer is likely to spread. However, if this measure is taken, the specific resistance of the drift region becomes large, and the low on-resistance which is an advantage of the static induction transistor using silicon carbide is sacrificed.

The present invention has been made in view of the above problems, and an object thereof is to provide a structure capable of realizing a high gate breakdown voltage and a high manufacturing yield when silicon carbide is applied to an electrostatic induction transistor. Is.

[0010]

A semiconductor device according to the present invention has a silicon carbide semiconductor substrate whose main material is silicon carbide (SiC). This silicon carbide semiconductor substrate has a first
A conductivity type drift region, a first conductivity type source region and a second conductivity type gate region that extend inward from the surface of the silicon carbide semiconductor substrate, are adjacent to the drift region, and have a higher impurity concentration than the drift region. And further,
The drain electrode is electrically connected to the drift region, and the source electrode and the gate electrode are in contact with the source region and the gate region, respectively. Here, a main current flows between the drain electrode and the source electrode, and ON / OFF of the main current is controlled by the voltage applied to the gate electrode. Here, one of the main features of the present invention is that the source region and the gate region are provided in contact with each other.

In the above semiconductor device according to the present invention,
Since the source region and the gate region are provided so as to be in contact with each other, the mask alignment when patterning these regions does not require so high accuracy. Moreover, since silicon carbide is used as the main material, a high gate breakdown voltage can be obtained even if the source region and the gate region having high impurity concentrations are brought into contact with each other. Therefore, a high gate breakdown voltage can be obtained with a high manufacturing yield.

Further, in order to increase the voltage amplification factor μ, the position where the distance between the gate regions facing each other across the source region is the smallest is deeper than the source region in the silicon carbide semiconductor substrate. It is preferable.

A semiconductor layer of a first conductivity type or a second conductivity type having an impurity concentration higher than that of the drift region may be interposed between the drain electrode and the drift layer. In the case of a semiconductor layer of the first conductivity type, the semiconductor device according to the invention operates as a static induction transistor (SIT), whereas in the case of a semiconductor layer of the second conductivity type, an electrostatic induction thyristor (SI thyristor). ) Acts as.

To form the gate region of the silicon carbide semiconductor device including the structure according to the present invention, ion implantation with high energy or under a high temperature condition is preferable. As a mask suitable for high energy ion implantation,
In the method for manufacturing a silicon carbide semiconductor according to the present invention,
A multilayer film in which an organic film, an inorganic film, and a resistor are sequentially stacked is used. A multilayer film in which silicon nitride and refractory metal silicide are sequentially stacked is used as a mask suitable for ion implantation under high temperature conditions. In the present invention, the first conductivity type and the second conductivity type are either p-type or n-type, which are conductivity types opposite to each other.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described. In the following structure, only one channel will be shown. To make a large current, a multi-channel structure in which a large number of these are arranged in parallel may be used.

FIG. 1 shows a sectional structure of a static induction transistor having a surface gate structure which is an embodiment of the present invention.

In a semiconductor substrate made of silicon carbide, an n-type drain region 2 having a relatively high impurity concentration extends from one surface (lower side of the figure) of the semiconductor substrate into the inside of the semiconductor substrate, and the n-type drain region 2 is formed. In addition, the n-type drift region 1 having a lower impurity concentration than this region is adjacent. Further, an n-type source region 4 having an impurity concentration higher than that of the n-type drift region 1 extends from the other surface (upper side of the drawing) of the semiconductor substrate in the semiconductor substrate and in the n-type drift region 1. At both ends of the n-type source region 4, a p-type gate region 3 having an impurity concentration higher than that of the n-type drift region 1 and extending from the other surface of the semiconductor substrate into the semiconductor substrate and into the n-type drift region 1 is formed.
It is provided so as to partially contact the mold source region 4 and to overlap both regions. The p-type gate region 3 is the n-type source region 4
Extends deeper into the semiconductor substrate than. That is, the depth of the pn junction between the p-type gate region 3 and the n-type drift region 1 is deeper than the depth of the junction between the n-type source region 4 and the n-type drift region 1. On one surface of the semiconductor substrate,
The drain electrode 22 contacts the n-type drain region 2 and n
It is electrically connected to the mold drift region 1. On the other surface of the semiconductor substrate, source electrode 21 contacts n-type source region 4 and gate electrode 20 contacts p-type gate region 3 at both ends of n-type source region 4. The drain electrode 22, the source electrode 21, and the gate electrode 20 are connected to the drain terminal 32, the source terminal 31, and the gate terminal 30, respectively. The electrostatic induction transistor of this embodiment is connected to an external circuit via these terminals.

In this embodiment, the p-type gate region 3 having a high impurity concentration and the n-type source region having a high impurity concentration are in contact with each other, but since the material of the semiconductor substrate is silicon carbide, the p-type gate region is formed. The breakdown voltage of the pn junction between the region 3 and the n-type source region 4, that is, the gate breakdown voltage can be increased. in this way,
Even if the p-type gate region 3 and the n-type source region 4 contact each other, the gate breakdown voltage can be increased, that is, the p-type gate region 3
Since a high gate breakdown voltage can be obtained between the n-type source region 4 and the n-type source region 4 without providing a semiconductor region having an impurity concentration lower than those of these regions, the pattern of the p-type gate region 3 and the n-type source region 4 can be obtained in the manufacturing process. High accuracy is not required for mask alignment for aligning the pattern of the region 4. Depending on the pattern shape, mask alignment may be unnecessary. Therefore, the variation in the gate breakdown voltage can be reduced in the manufacturing process, and the manufacturing yield is improved. Furthermore, since the area of the source region can be increased, a large current can be obtained.

FIG. 3 is a sectional structural view of a method for manufacturing the static induction transistor of FIG. (A) shows a low impurity concentration n-type drift region 1 formed by epitaxial growth on an n-type drain region 2 made of a high impurity concentration n-type semiconductor substrate. Subsequently, as shown in (b), a mask 10 for forming a gate region, which is a mask for ion shielding, is used to implant a p-type impurity such as aluminum into the surface of the low-impurity concentration n-type drift region 1 to implant a high impurity concentration. The p-type gate region 3 is formed. Further, as shown in (c), a high impurity concentration n-type source region 4 is formed by ion implantation of an n-type impurity such as nitrogen using the mask 11. At this time, the high impurity concentration n-type source region 4 is in contact with the high impurity concentration p-type gate region 3 so as to overlap each other. Subsequently, as shown in (d), the gate electrode 20, the source electrode 21, and the drain electrode 22 are formed.

Since the impurity diffusion coefficient of silicon carbide is as small as about 1/10000 that of silicon, thermal diffusion is not practical. Therefore, the ion implantation method is a preferable means for forming the high impurity concentration p-type gate region 3 of the silicon carbide static induction transistor. Therefore, the high impurity concentration p-type gate region 3 of the high withstand voltage static induction transistor is formed by the ion implantation method.
The examination of the present inventor regarding the formation of the above will be described below.

Conventionally, in the field of silicon semiconductors, the high impurity concentration p-type gate region 3 of the static induction transistor needs to be formed deeply, so that thermal diffusion of impurities is used. Normally, in a static induction transistor having a breakdown voltage of 5 kV class, the high impurity concentration p-type gate region 3 needs to have a depth of 60 μm. Even if the ion implantation is performed with a high energy of 10 Mev, the implantation depth is 10 μm, and it is difficult to implant up to the depth of 60 μm.

With silicon carbide, the high impurity concentration p-type gate region 3 can have a depth of about 5 μm. This depth can be formed by ion implantation of about 5 MeV. Therefore, in the case of silicon carbide, the high impurity concentration p-type gate region 3
Ion implantation can be used to form the.

When the gate is reversely biased, the depletion layer generated between the high impurity concentration p-type gate region 3 and the high impurity concentration n-type source region 4 is mainly high impurity concentration so as to extend toward the high impurity concentration p-type gate region 3. It is desirable to lower the impurity concentration of the high impurity concentration p-type gate region 3 as compared with the concentration n-type source region 4. The reasons 1, 2 and 3 will be described below.

1. Silicon carbide has a deeper impurity level than silicon, and is particularly prominent in the acceptor level.
When boron is used as the acceptor, the acceptor level of boron in silicon is 45 meV, while that of silicon carbide is as deep as about 300 meV. Therefore, the percentage of acceptors that are activated at room temperature among the acceptors at the lattice position is several percent. Therefore, in order to make the high impurity concentration p-type gate region 3 have a high carrier concentration such that the depletion layer does not spread, a large amount of ions must be implanted, which causes defects.

2. In order to increase the voltage amplification factor μ, the high impurity concentration p-type gate region 3 needs to form a deeper pn junction than the high impurity concentration n-type source region 4. Therefore, when forming the high impurity concentration p-type gate region 3, it is necessary to perform ion implantation with high energy. However, implanting deep and large amounts of ions causes defects. 3. When the high impurity concentration n-type source region 4 has a high concentration,
When a current flows in the on state, electrons are injected from the source. The injected electrons cause conductivity modulation, which lowers the substrate resistance.

FIG. 4 shows an example of a sectional structure of a static induction transistor formed by an ion implantation method by utilizing the fact that silicon carbide has a small impurity diffusion coefficient. Similar to FIG. 1, the high impurity concentration n-type source region 4 is formed so as to overlap the high impurity concentration p-type gate region 3, but a plurality of (two in this embodiment: The narrowest distance of the high impurity concentration p-type gate region 3 is deeper than that of the high impurity concentration n-type source region 4, and in this embodiment, it is substantially in the center in the depth direction of the p-type gate region. is there.
The reason why the high impurity concentration p-type gate region 3 shown in FIG. 4 can be formed will be described below.

FIG. 5 shows contour lines of the concentration of implanted ions when the silicon carbide substrate immediately after the ion implantation is viewed from the lateral direction. The ion concentration decreases in the order of the contour lines 40, 41, 42. The reason why the implanted ions wrap around to the back side of the mask is that the implanted ions are laterally scattered by the nuclear collision between the implanted ions and the substrate atoms. Immediately after the implantation, even in silicon, the ion concentration distribution has such a shape that the central portion bulges in the lateral direction. However, since the implanted ions are redistributed by annealing for defect recovery and activation of impurity ions, this distribution shape cannot be maintained. Since the impurity diffusion coefficient of silicon carbide is as small as 1/10000 of that of silicon, redistribution due to annealing does not occur and the shape immediately after implantation is maintained.

With the above structure, when turned off, the pn junction composed of the high impurity concentration p-type gate region 3 and the low impurity concentration n-type drift region 1 is separated from the high impurity concentration n-type source region 4. Since the depletion layer spreading to the low impurity concentration n-type drift region 1 contacts, the voltage amplification factor μ increases. Further, if the high impurity concentration p-type gate region 3 is formed by ion implantation, the position where the channel width is narrowest coincides with the position where the impurity concentration is highest, as shown in FIG. Therefore, the depletion layer spreads most toward the low impurity concentration n-type drift region 1 at the position where the channel width is narrowest. Therefore, the source-drain voltage can be blocked with a small gate voltage.

In order to increase the voltage amplification factor μ, the high impurity concentration p-type gate region 3 in FIG. 4 needs to have a depth of about several μm. Therefore, it is necessary to implant ions with high energy. A thick mask is needed to shield high energy ions. In order to realize the distribution shape of FIG. 5, it is necessary to avoid scattering of implanted ions on the side wall of the mask. Therefore, it is advantageous that the mask be as thin as possible. The material of the mask 10 may be an organic film, a resist, a metal, a silicide, SiO _2, or the like.

Further, by the multi-layer resist method, the side surface of the mask can be processed perpendicularly to the surface of the semiconductor substrate, and ion scattering on the side wall of the mask can be prevented. FIG. 6 shows a method of processing a multilayer resist. As shown in (a),
A laminated structure of an organic film 12, an inorganic intermediate layer 13, and a resist 14 is formed on the surface of a semiconductor substrate. The inorganic intermediate layer 13 is used to avoid mixing of the organic film 12 and the resist 14. Then, as shown in (b), the resist 14 is processed by an exposure process. Next, as shown in (c), the inorganic intermediate layer 13 is processed by etching using the resist 14 as a mask. Finally, as shown in (d), the organic film 1
The pattern 2 is formed by dry etching by O ₂ -RIE using the resist 14 and the inorganic intermediate layer 13 as a mask. The organic film 12 is specifically polyimide resin. After the step (c), ion implantation is performed using this multilayer mask.

Since the silicide has a large effect of shielding the implanted ions, the mask can be made thin and scattering of the implanted ions on the side wall of the mask can be suppressed. In addition, metal causes a phenomenon called channeling in which implanted ions pass through the mask. Therefore, when using metal, it is necessary to form an amorphous film between the metal and the surface of the semiconductor substrate in order to prevent channeling.

In silicon carbide, by implanting ions while heating at a high temperature, defects during implantation can be reduced. If the mask material has heat resistance, it can be used for high temperature ion implantation. FIG. 7 shows an embodiment using a mask material having high heat resistance, a large ion shielding effect even when thin, and easy removal after ion implantation. The mask has a laminated structure of refractory metal silicide 16 on silicon nitride 15. The refractory metal silicide satisfies the heat resistance and the shielding effect. By using silicon nitride for the portion in contact with the semiconductor substrate, the mask can be easily removed after the ion implantation. In addition,
The refractory metal silicide includes tungsten silicide and molybdenum silicide.

FIG. 8 shows another embodiment in which the contact resistance between the gate electrode and the high impurity concentration p-type gate region 3 is reduced as compared with FIG. The surface of the high-impurity-concentration p-type gate region 3 in contact with the gate electrode is used as the p-type region 5 having a higher impurity concentration. As shown in FIG. 5, the surface concentration is reduced by the one-step ion implantation. Therefore, using the same mask as when forming the high impurity concentration p-type gate region 3, p-type impurities are ion-implanted at a lower energy than in the first step. At this time, the ion species to be implanted may be the same as or different from that in the first step. Since this implantation is intended to reduce the contact resistance of the gate electrode, a shallow junction is sufficient.

FIG. 9 shows another embodiment of the static induction transistor in which the voltage amplification factor μ is further improved as compared with FIG. As in FIG. 4, FIG. 9 shows a high impurity concentration p at both ends of the n-type source region 4.
The position where the distance between the type gate regions 3 is the narrowest is deeper than the high impurity concentration n-type source region 4, but the position is characteristically deeper than that in FIG.

FIG. 10 shows a method of manufacturing the static induction transistor shown in FIG. An n-type drift region 1 having a low impurity concentration is formed by epitaxial growth on an n-type drain region 2 made of a high impurity concentration n-type semiconductor substrate. Subsequently, as shown in FIG. 10A, a first stage ion implantation region 6 is formed by ion implantation of p-type impurities such as aluminum on the surface of the low impurity concentration n-type drift region 1. If the side wall of the mask at the time of ion implantation is close to a right angle with respect to the substrate surface, the shape of the first-stage ion implantation region 6 reflects the effect of lateral scattering of implanted ions, and as shown in FIG. The narrowest position is inside the substrate surface. Next, as shown in FIG. 10B, the second stage ion implantation region 7 is formed by ion implantation with higher energy than the first stage. Scattering in the lateral direction is determined by energy loss due to nuclear collision between implanted ions and substrate atoms. As the implantation energy increases, the energy loss due to nuclear collision increases monotonically, and the lateral scattering distance increases. As described above, by implanting the same ion or different ions with different energies in multiple stages, FIG.
The shape as shown in (c) can be formed.

The energy loss due to nuclear collision is larger for the heavier element. Therefore, the heavier the element, the more the bottom is swollen. Finally, as shown in FIG. 10E, the n-type source region 4 is formed by ion implantation of an n-type impurity such as nitrogen. Next, electrodes are formed.

FIG. 11 is a perspective view of the silicon carbide static induction transistor of FIG. As described above, the impurity level of silicon carbide, especially the acceptor level is deep. When boron is used as the acceptor, even if the impurity concentration is on the order of 10 ¹⁸ cm ^{3 s} , only a few% are activated, so the substantial carrier concentration is about 10 ¹⁶ cm ^{3 s} . In this case, the resistivity of the p-type gate region 3 is several hundred mΩ · cm, and the voltage drop along the gate region cannot be ignored. Therefore, in the silicon carbide static induction transistor, it is necessary to form the gate electrode along the high impurity concentration p-type gate region 3. In FIG. 11, 20 is a gate electrode, 21 is a source electrode,
Reference numeral 30 is a gate terminal, and 31 is a source terminal. With the surface gate structure as shown in FIG. 11, the gate electrode 20 can be extended along the high impurity concentration p-type gate region 3. Therefore, the surface gate structure is a gate structure suitable for the silicon carbide static induction transistor.

FIG. 12 shows an embodiment in which polysilicon is used for the gate electrode. In the silicon carbide static induction transistor, the current flowing through the low impurity concentration n-type drift region 1 between the high impurity concentration n-type source region 4 and the high impurity concentration n-type drain region 2 is the high impurity concentration p-type gate region 3 The expansion of the depletion layer due to the voltage applied to
It is turned on and off. Therefore, since the current flowing through the gate electrode is only the capacitance of the depletion layer formed at the time of turning on / off, the polysilicon functions as the gate electrode even though the resistivity is higher than that of metal such as aluminum. By using polysilicon for the gate electrode, the high temperature characteristics are more stable than those of metal electrodes such as aluminum. In addition, since insulation with an oxide film or the like is facilitated, multilayer wiring is possible, and the source electrode can be vapor-deposited on one surface. Therefore, the alignment accuracy at the time of vapor deposition of the source electrode becomes unnecessary, and the manufacturing yield can be improved. As the gate electrode, silicide or salicide can be used in addition to polysilicon.

The present invention is not limited to the above embodiment, but p and n conductivity types may be different. Also,
The present invention can also be applied to an electrostatic induction thyristor. In the case of the electrostatic induction thyristor, in FIG.
The conductivity type may be changed to the p-type.

[0040]

As described above, according to the present invention,
Alignment accuracy between the source region and the gate region is unnecessary, and the high breakdown voltage static induction transistor can be easily manufactured. Also,
A large source area can be obtained and a large current can be obtained. Furthermore, by providing the position where the channel width is the narrowest inside the substrate, a large gate-source voltage can be blocked with a small gate voltage, and the voltage amplification factor μ is improved.

[Brief description of drawings]

FIG. 1 is a sectional view of a silicon carbide static induction transistor according to an embodiment of the present invention.

FIG. 2 is a sectional view of a conventional silicon static induction transistor.

3A to 3D are cross-sectional views showing manufacturing steps of the silicon carbide static induction transistor of FIG. 1 in the order of (a) to (d).

FIG. 4 is a cross-sectional view of a silicon carbide static induction transistor with further improved blocking characteristics according to another embodiment of the present invention.

FIG. 5 is a contour line of ion concentration immediately after ion implantation into a semiconductor substrate using a mask.

FIG. 6 is a cross-sectional view showing a multilayer resist processing method in the order of (a) to (c).

FIG. 7 is a cross-sectional view showing a mask for forming the structure of FIG.

FIG. 8 is a cross-sectional view of a silicon carbide static induction transistor whose contact resistance with the gate electrode is reduced as compared with FIG.

FIG. 9 is a sectional view of a silicon carbide static induction transistor with further improved blocking characteristics according to another embodiment of the present invention.

10A to 10E are cross-sectional views showing the manufacturing steps of the silicon carbide static induction transistor of FIG. 8 in the order of (a) to (e).

FIG. 11 is a perspective view of a silicon carbide static induction transistor after forming electrodes according to an embodiment of the present invention.

FIG. 12 is a cross-sectional view of a silicon carbide static induction transistor after forming an electrode according to an example of the present invention.

[Explanation of symbols]

1 ... n type drift region, 2 ... n type drain region, 3 ... p
N-type gate region, 4 ... N-type source region, 5 ... P-type region, 6
... 1st stage ion implantation region, 7 ... 2nd stage ion implantation region, 10 ... Gate region forming mask, 11 ... Source region forming mask, 12 ... Organic film, 13 ... Inorganic intermediate layer, 14
... resist, 15 ... silicon nitride, 16 ... refractory metal silicide, 20 ... gate electrode, 21 ... source electrode, 22 ...
Drain electrode, 23 ... Gate polysilicon electrode, 24
... Source metal electrode, 25 ... Oxide film, 30 ... Gate terminal, 31 ... Source terminal, 32 ... Drain terminal, 40 ... Ion concentration contour line (high), 41 ... Ion concentration contour line (medium), 42 ... Ion concentration Contour lines (low).

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-51-28765 (JP, A) JP-A-7-99325 (JP, A) JP-A-4-107819 (JP, A) JP-A-4- 107831 (JP, A) JP 6-260631 (JP, A) JP 6-89904 (JP, A) JP 1-282870 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/778-29/812 H01L 21/338

Claims (4)

(57) [Claims] 1. A silicon carbide semiconductor substrate, a drift region of a first conductivity type, and a silicon carbide semiconductor substrate extending inward from one surface of the silicon carbide semiconductor substrate, in contact with the drift region, and having an impurity concentration higher than that of the drift region. A source region of a first conductivity type and a gate region of a second conductivity type, a drain electrode is electrically connected to the other surface of the silicon carbide semiconductor substrate in the drift region, A source electrode is in contact with the region, a gate electrode is in contact with the gate region, the source region and the gate region are in contact with each other, and the plurality of gate regions are arranged along one surface of the silicon carbide semiconductor. Te extending while facing the source region is sandwiched between the gate region extends with the opposite, the
The impurity concentration of the gate region is the same as that of the source region.
And the narrowest distance between the facing gate regions.
Where the saw is located in the silicon carbide semiconductor substrate.
Depth from one surface of the silicon carbide semiconductor
In the gate region, the one portion of the silicon carbide semiconductor substrate in the gate region.
The impurity concentration of the part on the one surface is
Than the impurity concentration of the portion inside the semiconductor substrate
Silicon carbide semiconductor device characterized by high price. 2. The silicon carbide semiconductor device according to claim 1, wherein the material of the gate electrode is one material selected from polysilicon, silicide, and salicide. apparatus. 3. The silicon carbide semiconductor device according to claim 1, wherein the drain electrode is electrically connected to the drift region via a first conductivity type semiconductor layer having an impurity concentration higher than that of the drift region. A silicon carbide semiconductor device characterized by the following. 4. The silicon carbide semiconductor device according to claim 1, wherein the drain electrode is electrically connected to the drift region through a second conductivity type semiconductor layer having an impurity concentration higher than that of the drift region. And a silicon carbide semiconductor device.