JPH08330314A - Semiconductor device and its fabrication - Google Patents

Abstract

PURPOSE: To provide a local interconnect in which a full CMOS memory cell having small area can be realized. CONSTITUTION: A local interconnect is formed by a step for depositing a titanium nitride 12, a step (q) for depositing a mask of wet etching, i.e., an oxide 24, on the titanium nitride, a step (h) for dry etching the oxide 24 using photoresist as a mask, and a step (i) for wet etching the titanium nitride through a mask of dry etched oxide 24 using a mixture solution of hydrogen peroxide water and ammonia water. Since the titanium nitride can be etched without cutting the diffusion layer 46 on a silicon substrate 41 while reducing the side etching, an interconnection pattern of titanium nitride as fine as 0.3μm or less can be machined.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device using a refractory metal nitride as a wiring material and a manufacturing method thereof.

[0002]

2. Description of the Related Art Generally, as a memory cell structure of a static RAM, two transfer MOSFETs and two transfer MOSFETs are used.
One driver MOSFET and two load MOSFETs
The so-called full CMOS memory cell, which is composed of
Although the memory cell area is large because the FET, the driver MOSFET, and the p-channel load MOSFET are formed, the advantage that the manufacturing process is simple and that all are formed of active elements enable stable operation even at low voltage There is an advantage of doing. Due to such advantages, the full CMOS memory cell is used as a so-called on-chip memory memory cell mounted on the same chip as a processor or the like. In recent years, in large-scale integrated circuits (LSIs), the power supply voltage has been reduced in order to suppress the increase in power consumption due to the improvement in the degree of integration and the operating speed. Memory cells are being used.

In the case of a full CMOS memory cell, it is necessary to electrically connect both the n-channel MOSFET and the p-channel MOSFET in the memory cell.
To connect the two, there is a method called a local interconnect that uses a local wiring layer in the memory cell.
As a material for the local interconnect, titanium nitride is being considered because it is a material in which the impurities introduced into the diffusion layer are difficult to diffuse.

Further, in order to improve the performance of the LSI, there is a technique of reducing the resistance of the diffusion layer by reacting the diffusion layer with a refractory metal to form a silicide and reducing the resistance of the diffusion layer. As a local interconnect technology using this silicide, for example, titanium nitride produced during the silicide reaction of titanium is used as it is as a local interconnect, and this titanium nitride is dry-etched halfway using a photoresist as a mask and the rest is wet-etched. The technology of processing by EY
DM Technical Digest Nos. 590-59
Page 3 (1985 IEDM Technical Digest pp.590-593) and a similar technique is disclosed in JP-A-5-226591, but an oxide film is used as a mask when titanium nitride is wet-etched. ing.

On the other hand, a logic LSI represented by a processor
Requires high speed performance, and in order to reduce the capacitance of the source / drain of the MOSFET and the base of the bipolar transistor, the source / drain and the diffusion layer of the source / drain and the base are diffused by extracting the electrode from the base onto the field oxide film. There has been proposed a structure for reducing the area. Regarding this technique, for example, the technical digest No. 7 of I.D.M. in 1988.
60-762 (1988 IEDM Technical Digest pp.760-7
62). This is one in which the source / drain and base extraction electrodes are formed of polycrystalline silicon in a self-aligned manner.

[0006]

However, among the above-mentioned conventional techniques, the titanium nitride is processed by dry etching using a photoresist as a mask halfway and wet etching the rest, as described in 1985 IDM. According to the technique described in the technical digest of (1), in order to carry out wet etching of a fine wiring pattern having a width of about 0.3 μm using a photoresist as a mask, titanium nitride and a photoresist are used as described later in Example 1. It was difficult to realize a memory cell having a large side etch amount at the interface of 10 μm ^{2 and a} small area of 10 μm ² or less.

Further, Japanese Patent Laid-Open No. 5-226591 discloses that titanium nitride produced when titanium is deposited and then heat-treated in a nitrogen atmosphere to form titanium silicide is wet-etched using an oxide film as a mask. In order to realize a fine MOSFET with a gate length of 0.4 μm level by using the method described above, the junction depth of the source / drain diffusion layer is set to 0.15 in order to suppress the short channel effect.
It is necessary to make it as shallow as μm. In order to form the silicide in order to reduce the resistance of the source / drain diffusion layer having such a shallow junction, the diffusion layer having a depth of 0.15 μm may be penetrated or leaked unless the thickness of titanium is 30 nm or less. This causes an increase in current. This is because silicidation due to the solid-phase reaction between metal and silicon proceeds by eroding silicon, and thus thickening titanium increases the thickness of the silicide formed and the eroding thickness of the diffusion layer. When titanium having a thickness of 30 nm is annealed in a nitrogen atmosphere, 10 n is left on the field oxide film.
Although titanium nitride of m or more is formed, since titanium silicide is formed on the source / drain diffusion layer, only titanium silicide growing from the diffusion layer side and titanium nitride growing from the surface collide. Titanium nitride cannot grow and is at most 7-8 nm thick.

By the way, the titanium nitride on the silicide is
In order to serve as a stopper for dry etching when forming an oxide film mask, it is necessary to have a thickness that can withstand overetching of the oxide film. The amount of this over-etching is determined by the level difference of the base during etching. Micro MOSFET
The step in the case of forming is the thickness of the gate electrode, which is usually about 200 nm, so that the overetch amount needs to be at least 200 nm. If the selection ratio between the oxide film and titanium nitride is about 20, the thickness of titanium nitride needs to be at least 10 nm. Therefore, if the thickness of titanium to be deposited is 30 nm or less, titanium nitride having a thickness of 7 to 8 nm does not serve as a stopper, and the underlying titanium silicide is also etched. It could not be manufactured by the conventional technology. Furthermore, fine M such as 0.25 μm gate length
In order to realize the OSFET, the diffusion layer has to be made a shallower junction, so that the thickness of titanium that can be deposited becomes thinner, and the thickness of titanium nitride that is formed during silicidation also becomes thinner. Therefore, a MOSFET with a gate length of 0.4 μm or less cannot be realized, and a high-performance LS
There was a problem that I could not be obtained.

Further, the above-mentioned 1988 AI
The technique described in DM Technical Digest has a problem that the process is very complicated because the source / drain and base extraction electrodes are formed in a self-aligned manner.

In general, when titanium nitride is processed by dry etching, the titanium nitride and silicon substrate have a small selection ratio, and therefore titanium nitride cannot be finely processed under the condition that the silicon substrate is exposed. Since the selection ratio is small, it is necessary to secure a margin for the layout of the contact hole and the titanium nitride wiring. Therefore, it is difficult to realize a memory cell having a small area as described above.

Therefore, an object of the present invention is to eliminate the above-mentioned problems, and to provide a semiconductor device having an interconnect using a fine pattern of refractory metal nitride such as titanium nitride, and a method of manufacturing the same. To do.

The present invention provides a method of manufacturing a semiconductor device capable of processing a fine pattern of a refractory metal nitride such as titanium nitride without shaving the underlying silicon substrate even under the condition that the silicon substrate is exposed. It is also intended to be provided.

Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of processing a fine pattern of refractory metal nitride such as titanium nitride without scraping the silicide even if the diffusion layer is silicided. To do.

Another object of the present invention is to provide a semiconductor device having a small area full CMOS memory cell using a fine interconnect metal nitride refractory such as titanium nitride.

Still another object of the present invention is to provide a semiconductor device having source / drain and base extraction electrodes using an interconnect made of fine refractory metal nitride such as titanium nitride.

[0016]

A method of manufacturing a semiconductor device according to the present invention comprises a step of depositing a wiring material which is a nitride of a refractory metal and a silicon oxide serving as a mask for wet etching on the wiring material. A step of depositing a film or a nitride film, a step of processing the silicon oxide film or nitride film by dry etching using a photoresist as a mask, and a step of processing the wiring material by wet etching using the processed silicon oxide film or nitride film as a mask And a step of performing.

Further, the method of manufacturing a semiconductor device according to the present invention comprises a step of forming a field oxide film and an active region on the surface of a semiconductor substrate by a selective oxidation method, and a MOSFET.
Gate electrode of the MOSFET, a step of ion-implanting impurities into the active region and a heat treatment to form a diffusion layer, and a step of depositing an insulating film by a CVD method to etch back the entire surface of the gate of the MOSFET. A step of covering the sidewall of the electrode with an insulating film and exposing the diffusion layer; a step of depositing a wiring material which is a nitride of a refractory metal; and a silicon oxide film serving as a mask for wet etching on the wiring material, or Depositing a nitride film,
A manufacturing method comprising: a step of processing the silicon oxide film or nitride film by dry etching using a photoresist as a mask; and a step of processing the wiring material by wet etching using the processed silicon oxide film or nitride film as a mask. Yes.

Alternatively, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming a field oxide film and an active region on a surface of a semiconductor substrate by a selective oxidation method, and a MOSFE.
A step of forming a gate electrode of T, a step of ion-implanting impurities into the active region, and a heat treatment to form a diffusion layer, and a conductive film, that is, a conductive film, that is, directly over the required region of the diffusion layer, that is, via an insulating film. Gate electrode of the MOSFET by covering with a laminated film of a polycrystalline silicon film, a refractory metal film, a nitride of a refractory metal, etc. and an insulating film, and depositing the insulating film by a CVD method and etching back the entire surface. And a step of covering the side wall of the laminated film with an insulating film and exposing the diffusion layer, a step of depositing a wiring material which is a nitride of a refractory metal, and a silicon serving as a mask for wet etching on the wiring material. Depositing an oxide film or a nitride film, processing the silicon oxide film or the nitride film by dry etching using a photoresist as a mask, A step of processing the wiring material by wet etching the silicon oxide film or a nitride film engineering as a mask, may be a method of manufacturing a semiconductor device including a.

Furthermore, the method of manufacturing a semiconductor device according to the present invention comprises a step of forming a field oxide film and an active region on the surface of a semiconductor substrate by a selective oxidation method, and a MOSFET.
The step of forming the gate electrode of
Depositing by the D method and etching back the entire surface to cover the side wall of the gate electrode of the MOSFET with a silicon oxide film and expose the active region;
CVD of a silicon oxide film to be a through film for ion implantation
A step of depositing by a method, a step of ion-implanting impurities into the active region, a step of activating the ion-implanted impurities by heat treatment to form a diffusion layer,
The step of removing the silicon oxide film to be the through film by wet etching, the step of depositing a wiring material which is a nitride of a refractory metal, the silicon oxide film or the nitride to be a mask of wet etching on the wiring material. A step of depositing a film, a step of processing the silicon oxide film or nitride film by dry etching using a photoresist as a mask, and a step of processing the wiring material by wet etching using the processed silicon oxide film or nitride film as a mask. And are included.

Furthermore, a step of forming a field oxide film and an active region on the surface of a semiconductor substrate by a selective oxidation method, a step of forming a gate electrode of a MOSFET, ion implantation of impurities into the active region, and then heat treatment. A step of forming a diffusion layer, and a conductive film, that is, a polycrystalline silicon film, a refractory metal film, a nitride of a refractory metal, or the like and an insulating film are laminated on a required region of the diffusion layer directly or through an insulating film. Pre-cover with a film and CV the insulating film
Depositing by the D method and etching back the entire surface to cover the gate electrode of the MOSFET and the side wall of the laminated film with an insulating film and expose the diffusion layer;
CVD of a silicon oxide film to be a through film for ion implantation
Method, a step of ion-implanting impurities into the exposed diffusion layer, a step of activating the ion-implanted impurities by heat treatment, and a step of removing the silicon oxide film to be the through film by wet etching. A step of depositing a wiring material which is a nitride of a refractory metal, a step of depositing a silicon oxide film or a nitride film serving as a wet etching mask on the wiring material, and a step of depositing the silicon oxide film using a photoresist as a mask. The manufacturing method may include a step of processing the film or the nitride film by dry etching, and a step of processing the wiring material by wet etching using the processed silicon oxide film or nitride film as a mask.

In the method for manufacturing a semiconductor device, the required region of the diffusion layer is a region where wirings made of a refractory metal nitride intersect with each other on the diffusion layer and do not make contact with the wirings.

The gate electrode of the MOSFET is
It is preferable to use polycrystalline silicon, a laminated film of polycrystalline silicon and a silicide film of a refractory metal, a refractory metal, or a nitride of a refractory metal.

In the manufacturing method, between the step of exposing the diffusion layer by the etch-back and the step of depositing the wiring material which is the nitride of the refractory metal, or the ion-implanted through film. 650 to a step of depositing a refractory metal serving as a source of silicide between the step of removing the silicon oxide film to be the target by wet etching and the step of depositing the wiring material which is the nitride of the refractory metal. A step of performing heat treatment at 850 ° C. to form silicide on the diffusion layer, and forming the silicide in a step of processing the wiring material by wet etching using the processed silicon oxide film or nitride film as a mask. The refractory metal nitride and the unreacted refractory metal generated at this time may be processed.

Further, in the above-mentioned manufacturing method, after the step of exposing the diffusion layer by the etch back or after the step of removing the silicon oxide film to be the through film for the ion implantation by wet etching, it becomes a source of silicide. A step of adding a refractory metal, and a step of depositing a wiring material, which is a nitride of the refractory metal, followed by a heat treatment at 650 to 850 ° C. to form a silicide on the diffusion layer; In the step of processing the wiring material by wet etching using the processed silicon oxide film or nitride film as a mask, a nitride of a refractory metal generated when the silicide is formed and an unreacted refractory metal. May be processed.

Furthermore, in the manufacturing method, between the step of exposing the diffusion layer by the etch back and the step of depositing the wiring material which is the nitride of the refractory metal, or the ion-implanted through film. 650 to a step of depositing a refractory metal serving as a source of silicide between the step of removing the silicon oxide film to be the target by wet etching and the step of depositing the wiring material which is the nitride of the refractory metal. Addition of a step of performing heat treatment at 850 ° C. to form a silicide on the diffusion layer, and a step of removing a nitride of a refractory metal and an unreacted refractory metal generated when the silicide is formed by wet etching. You can also do it.

It is preferable that the wiring material of the refractory metal nitride is titanium nitride, and the refractory metal serving as the source of silicide is titanium or cobalt.

Further, when the wet etching mask is a silicon oxide film, it is preferable to deposit it by plasma CVD using tetraethoxysilane as a source,
In the case of a silicon nitride film, it is preferable to deposit it by plasma CVD.

Furthermore, it is preferable that the etching solution for the wet etching is hydrogen peroxide water or a mixed solution of hydrogen peroxide water and ammonia water.

The semiconductor device according to the present invention is a MOSFET
Source / drain electrodes and source / drain extraction electrodes for extracting the source and drain electrodes onto the field oxide film, or the base or collector electrode of the bipolar transistor and the base or collector electrode for extracting onto the field oxide film. It is characterized in that the base / collector extraction electrode is made of a nitride of a refractory metal.

Further, in the semiconductor device according to the present invention, a memory cell array composed of a plurality of memory cells and a logic circuit for selecting a memory cell to read / write information or a logic circuit forming a processing unit are integrated on one chip. Two transfer MOSFEs in a semiconductor device
T, two driver MOSFETs, two load MOSFs
Source / drain electrodes and local wiring in a memory cell of a static memory cell made of ET, source / drain electrodes of MOSFETs in the logic circuit section, and source / drain lead-out electrodes for leading the source / drain electrodes onto a field oxide film. And may be made of a high melting point metal nitride.

[0031]

According to the method of manufacturing the semiconductor device of the present invention,
Since the oxide film that serves as a mask during wet etching of a wiring material that is a nitride of a refractory metal such as titanium nitride has good adhesion, the amount of lateral etching at the interface with the refractory metal nitride is small, and Since the refractory metal nitride used is not formed at the time of silicidation, the crystal has directionality and the lateral etching amount is still small. Therefore, a fine refractory metal nitride having a line width of 0.3 μm or less is used. Pattern processing is possible. Further, the wet etching solution is hydrogen peroxide water or a mixed solution of hydrogen peroxide water and ammonia water that does not etch the silicon substrate at room temperature, and the silicon substrate is not etched even if it is exposed on the surface to be etched. Absent. Therefore, it is not necessary to lay out the diffusion layer and the refractory metal nitride with a margin in consideration of misalignment, and a memory cell having a small area can be realized.

Further, in order to connect the refractory metal nitride and the diffusion layer, the diffusion layer is exposed when the sidewall insulating film of the gate electrode is formed by etching the whole surface, instead of opening the contact hole with a mask. Connection is made by depositing a refractory metal nitride thereon. Therefore, a photo step for opening the contact hole can be omitted, and it is not necessary to lay out with a margin in consideration of misalignment between the diffusion layer and the contact hole, and a memory cell having a small area can be realized by a simple process. be able to.

Further, by depositing a refractory metal nitride such as titanium nitride, which serves as a stopper for dry etching, on the refractory metal nitride produced during the silicide reaction, the refractory metal nitride on the silicide is deposited. Even if the upper oxide film is dry-etched using a photoresist as a mask, the silicide is not etched. Therefore, the high melting point metal nitride can be wet-etched using the oxide film as a mask, and even if the diffusion layer is silicidized, it is necessary to lay out with a margin in consideration of misalignment between the diffusion layer and the high melting point metal nitride. Therefore, a fine memory cell area of 7 μm ² and a high-performance logic circuit can be realized on the same chip.

Furthermore, the refractory metal such as titanium and the refractory metal nitride such as titanium nitride are stacked and deposited before the silicidation reaction, so that the refractory metal nitride on the refractory metal silicide is deposited after the silicidation reaction. Even if the upper oxide film is dry-etched, the silicide is not etched. Therefore, also in this case, wet etching of the refractory metal nitride can be performed using the oxide film as a mask, and even if the diffusion layer is silicidized, there is a margin in consideration of misalignment between the diffusion layer and the refractory metal nitride. A similar fine memory cell area and a high-performance logic circuit can be realized on the same chip without the need for extra layout.

In addition, unreacted titanium or refractory metal nitride generated during the silicidation is removed after silicidation and the refractory metal nitride is deposited to deposit the refractory metal nitride on the deposited refractory metal nitride. Even if the oxide film is dry-etched, the silicide is not etched. By performing wet etching using the oxide film as a mask, it is not necessary to lay out the diffusion layer and the refractory metal nitride with a margin in consideration of misalignment, and a fine memory cell area and a high-performance logic circuit can be obtained. And can be realized on the same chip.

According to the semiconductor device of the present invention, the resistance value is lower than that of polycrystalline silicon, and the refractory metal nitride that can be selectively processed with the silicon substrate by wet etching is used for the source / drain extraction electrodes. By pulling up the source / drain extraction electrodes onto the field oxide film, the area of the source / drain diffusion layer can be reduced correspondingly, so that a high-performance MOSFET with reduced diffusion layer capacitance and parasitic resistance can be obtained.

According to the semiconductor device of the present invention,
A refractory metal nitride, which has a lower resistance value than polycrystalline silicon and can be selectively processed with a silicon substrate by wet etching, is used for the base / collector extraction electrode. Therefore, the base / collector extraction electrode is formed on the field oxide film. Since the area of the base / collector diffusion layer can be reduced by that much, it is possible to obtain a high-performance bipolar transistor that reduces the capacitance and parasitic resistance of the diffusion layer.

Further, according to the semiconductor device of the present invention, since the local wiring of the memory cell and the source / drain extraction electrodes of the MOSFET are made of the same refractory metal nitride, the manufacturing process can be made common. A fine full CMOS memory cell and a high-performance peripheral circuit can be realized on the same chip without increasing the number of steps.

[0039]

Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below in detail with reference to the accompanying drawings.

<Embodiment 1> FIG. 1 is a sectional view showing an embodiment of a method of manufacturing a semiconductor device according to the present invention. In FIG. 1, reference numeral 11 is titanium nitride, 21 is a silicon oxide film, 31 is a photoresist, and 41 is a silicon substrate.

First, as shown in FIG. 1A, titanium nitride 11 having a thickness of 70 nm is deposited on a silicon substrate 41 by a sputtering method or a CVD method, and an oxide film 21 is further formed on the titanium nitride 11 by a plasma CVD method. Of about 100 nm, and then the oxide film 2 is formed to pattern the oxide film 21.
A pattern of a photoresist 31 is formed on the surface 1 by a photolithography technique (hereinafter, simply referred to as a photo process).
Here, the source of the plasma CVD is titanium nitride 1
In order to avoid the oxidation and peeling off of No. 1, tetraethoxysilane (TEOS) or the like that can be deposited at a low temperature of 500 ° C. or lower is preferable.

Next, as shown in FIG. 3B, the oxide film 21 is processed by dry etching using, for example, CHF ₃ gas using the photoresist 31 as a mask, and then the photoresist 31 is removed.

Next, as shown in FIG. 3C, the oxide film 2
Using the mask 1 as a mask, the titanium nitride 11 is processed by wet etching. The amount of side etching of titanium nitride 11 generated at this time is smaller than that in the thickness direction, as described later. As the wet etching solution, a solution obtained by mixing hydrogen peroxide water and ammonia water at a ratio of 6: 1 was used. The wet etching solution may be only hydrogen peroxide solution.

Here, the etching of titanium nitride will be described. An attempt was made to dry-etch titanium nitride formed on a silicon substrate using Cl ₂ gas or the like with a photoresist as a mask and to perform the same dry etching with an oxide film as a mask. As a result, since the selection ratio between the silicon substrate and titanium nitride was small, the silicon substrate was scraped regardless of the mask material. On the other hand, when titanium nitride was etched at room temperature using a solution in which hydrogen peroxide water and ammonia water were mixed at a ratio of 6: 1, it was possible to perform etching without scraping the silicon substrate. However, as shown in the sectional view of FIG. 2, when the photoresist 31 is used as a mask for wet etching, the photoresist 31
The etching solution soaked into the interface between the titanium nitride 11 and the titanium nitride 11 and a part of the surface of the titanium nitride 11 was etched, and the photoresist 31 was peeled off when the pattern width was as thin as 0.3 μm. This is because the adhesion between the photoresist and titanium nitride is poor.

Further, as shown in the sectional view of FIG. 3, when the oxide film 21 is used as a mask for dry etching and the rest is wet etched, the silicon substrate 41 and the titanium nitride 11 are removed. The etching solution permeated into the interface, resulting in a shape in which the titanium nitride 11 was undercut, and when the pattern width was narrow, the titanium nitride 11 was peeled off. This is because the side surface of the titanium nitride 11 processed by dry etching is deteriorated and the wet etching does not proceed, whereas the portion processed only by wet etching has an etching rate higher than that of the side surface changed.

Therefore, the good etching shape of the titanium nitride 11 was obtained even in the case of a thin pattern, as shown in FIG. 1, only when the oxide film 21 was used as a mask for wet etching.

In general, when performing wet etching, there is a concern that a fine pattern cannot be formed due to the progress of etching in the lateral direction. However, when titanium nitride deposited by sputtering as in this embodiment is etched using an oxide film as a mask, the side etch amount is 20 to 30 nm even if the titanium nitride film having a thickness of 70 nm is overetched by 50%. There were few. The reason why horizontal etching is difficult to proceed is that titanium nitride deposited by the sputtering method has crystal orientation and a large vertical etching rate. In addition, the adhesion between the oxide film and titanium nitride is good and the etching solution is good. Does not soak into the interface between the oxide film and titanium nitride. On the other hand, titanium nitride, which is formed by performing annealing for silicidation in a nitrogen atmosphere after depositing titanium by a sputtering method, has a non-uniform crystal orientation, and even if wet etching is performed using an oxide film as a mask. It is isotropically etched, and it is difficult to form a fine pattern. Titanium nitride deposited by the CVD method also has crystallographic orientation, and good etching with less side etching can be performed.

Therefore, according to the present embodiment, since the side etching amount can be reduced without cutting the silicon substrate, when the silicon substrate is exposed by the fine titanium nitride pattern processing with the line width of 0.3 μm or less. But it is possible.

In this embodiment, the case where the oxide film is used as the mask material for the wet etching has been described. However, the same processing is also performed when the silicon nitride film deposited by the plasma CVD method is used as the mask material. can do. Further, not only titanium nitride but also other refractory metal nitrides that can be etched with hydrogen peroxide solution or a mixed solution of hydrogen peroxide solution and ammonia solution, such as tungsten nitride, are 0.3 μm or less by the same manufacturing method. Such a fine pattern can be processed.

<Embodiment 2> FIGS. 4A to 4C are sectional views showing another embodiment of the method of manufacturing a semiconductor device according to the present invention. As an example, full C having a gate length of 0.25 μm level is shown.
FIG. 6 is a diagram showing a method of manufacturing a MOS memory cell in the order of steps. FIG. 5 is a cell layout diagram showing an example of the layout of a full CMOS memory cell. 4A to
FIG. 4C is a sectional view schematically showing a section of a portion of the memory cell shown in FIG. 5 along the line AB.

In FIG. 5, reference numerals 101 and 102 are diffusion layers on the side connected to the data line of the transfer MOSFET, and 103 and 104 are storage nodes, which are the other diffusion layer of the transfer MOSFET and the driver MOSFE.
A diffusion layer that also serves as the drain of T, and 105 is a driver MOS
FET source diffusion layers, 106 and 107 are storage nodes and drain MOSFET drain diffusion layers, 108 load MOSFET source diffusion layers, 111 and 112 driver MOSFET gate electrodes, and 113 and 114 load M
Gate electrodes of OSFET, 115 and 116 are gate electrodes of a transfer MOSFET that also serves as wiring of word lines,
Reference numeral 117 is a wiring layer for supplying the ground potential, 118 is a contact hole for connecting the source diffusion layer of the driver MOSFET and the wiring layer for supplying the ground potential, 11
Reference numeral 9 is a wiring layer for supplying a power supply potential, and 120 is a load MOS.
Contact holes for connecting the source diffusion layer of the FET and the wiring layer for supplying the power supply potential, 121 and 122 lead electrodes for connecting the transfer MOSFET and the data line, and 123 and 124 storage nodes and driver MOSFE.
Layout of local interconnects for cross-connecting the gate electrodes of T and load MOSFETs, 125 and 126 are contact holes for connecting the gate electrodes and the local interconnects, and 131 and 132 are contact holes for connecting data lines. Each pattern is shown.

In this embodiment, the MO constituting the memory cell is
The gate electrode of the SFET is polycrystalline silicon of the first layer, the wiring for supplying the power supply potential and the ground potential is polycrystalline silicon of the second layer, the storage node and the driver MOSFE.
Titanium nitride is used for the local interconnects 123 and 124 for cross-connecting the gate electrodes of the T and load MOSFETs and the extraction electrodes 121 and 122 for connecting the transfer MOSFETs and the data lines.

The manufacturing method will be described below in order in (1) to (9) below with reference to FIGS. 4A to 4C.

(1): Referring to FIG. 4A (a), first, the field oxide film 6 is formed on the surface of the silicon substrate 41.
1, a p-well 42, an n-well 43 are formed, a 6 nm gate oxide film 62 is further formed on the surface of the active region, and n-type impurities are introduced into polycrystalline silicon with a thickness of 80 nm to obtain a 0.25 μm width. Gate electrode 81 and a tungsten silicide layer 8 for reducing the resistance of the gate electrode 81
2 is processed by dry etching using the oxide film 22 as a mask. The oxide film 22 not only serves as a mask for processing the gate electrode, but also has an effect of preventing the tungsten silicide layer 82 above the gate electrode 81 from being exposed when the oxide film is etched back in a later step. Further, using the gate electrode 81 as a mask, the source / drain diffused layer 44 of the nMOSFET and the source / drain diffused layer 45 of the pMOSFET having a junction depth of 0.1 μm are formed in a self-aligning manner, for example, by ion implantation.

(2): Referring to FIG. 4A (b), an interlayer insulating film 63 is deposited on the entire surface by a CVD method,
Second-layer n-type polycrystalline silicon wiring layer 83 having a thickness of 50 nm
After the p-type polycrystalline silicon wiring layer 84 and the p-type polycrystalline silicon wiring layer 84 are formed in required regions, respectively, tungsten is further deposited on the entire surface and annealed to reduce the resistance.
To form. The laminated film of the n-type polycrystalline silicon wiring layer 83 and the tungsten silicide layer 85 and the laminated film of the p-type polycrystalline silicon wiring layer 84 and the tungsten silicide layer 85 are processed by dry etching using the oxide film 23 as a mask. Here, the oxide film 23 not only serves as a mask for processing the second-layer polycrystalline silicon wiring layers 83 and 84, but also when the oxide film is etched back in a later step, the second-layer polycrystalline silicon wiring layer There is an effect that the upper portions of 83 and 84 are not exposed. The n-type polycrystalline silicon wiring layer 83 and the p-type polycrystalline silicon wiring layer 84 are formed by depositing non-doped polycrystalline silicon and then implanting n-type and p-type impurities by ion implantation. In addition, the interlayer insulating film 6
3 can be made as thin as possible to form a capacitance between the diffusion layer 44 and the polycrystalline silicon wiring layer 83 to improve the soft error resistance.

(3): Referring to FIG. 4A (c), after processing the laminated film of the second-layer polycrystalline silicon wiring layers 83 and 84 and the tungsten silicide 85, the oxide film 64 is formed to a thickness of 100 nm by the CVD method. It deposits.

(4): Referring to FIG. 4B (d), the entire surface is etched back by anisotropic dry etching to form the gate electrode 81, the tungsten silicide 82 and the second-layer polycrystalline silicon wiring layers 83, 84. The diffusion layers 44 and 45 are exposed while the side surfaces are covered with the oxide film 64.
At this time, if the diffusion layers 44 and 45 at the portions where the wiring layer made of titanium nitride is not desired to be contacted in the subsequent step are covered with the second-layer polycrystalline silicon layers 83 and 84, the diffusion layers at that portion will be formed by this step. Never exposed. For example, in FIG.
The source diffusion layers 105 and 108 of the driver MOSFET and the load MOSFET shown in the cell layout of FIG. 2 pass through the local wiring layers 123 and 124 made of titanium nitride and having a width of 0.25 μm. When these are connected, the storage node and the power supply or ground are connected. Since the potential is short-circuited, the wiring layer 11 including the second-layer polycrystalline silicon layers 83 and 84
It is completely covered by 7,119. In this way, the contact hole is not opened to connect the titanium nitride and the diffusion layer in the subsequent step, but the diffusion layer is exposed by etching back the entire surface to connect the contact hole. It is optional and simplifies the process. It is also possible to use a refractory metal such as titanium or a refractory metal nitride such as titanium nitride as a wiring layer instead of the wiring layer composed of the second-layer polycrystalline silicon layers 83 and 84.

(5): Referring to FIG. 4B (e), after depositing a CVD oxide film 65 to be a through film for ion implantation, n-type impurities (phosphorus or arsenic) are used as n-type with the photoresist 32 as a mask. Are ion-implanted into the diffusion layer region 46 of the.

(6): Referring to FIG. 4B (f), after removing the photoresist 32, the photoresist step is performed again to form a photoresist 33, and the photoresist 33 is used as a mask to remove p-type impurities (boron) from the p-type. Ions are implanted in the diffusion layer region 47. In the ion implantation step described in (5) and (6), when the diffusion layers 44 and 45 are exposed by the etch back in the step (3), the exposed surface of the diffusion layer is slightly shaved and diffused. There is a risk that the surface concentration of the layer will decrease and ohmic contact with titanium nitride may not be obtained, or the edge of the field oxide film 61 may be scraped off and the well 42,
Since there is a possibility that a part of 43 is exposed, this is done to eliminate these.

(7): Referring to FIG. 4C (g), next, a contact hole 1 for connecting the gate electrode and the local interconnect shown in the cell layout of FIG.
In order to form 25 and 126, the oxide film 64 is processed by dry etching using a photoresist as a mask, and the ion-implanted through oxide film 65 is removed by wet etching. Next, titanium nitride 12 to be a local interconnect is deposited by sputtering to a thickness of 70 nm, and an oxide film 24 is further deposited thereon to a thickness of 100 nm. Since this oxide film 24 is deposited on the titanium nitride 12, it can be deposited at a low temperature not exceeding 500 ° C.
It is deposited by plasma CVD using S as a source.
The titanium nitride 12 may be deposited by the CVD method, but it is preferable to use the sputtering method because it has good contact with the diffusion layer.

[0061] (8): Referring now to FIG. 4C (h), the photoresist as a mask, the minimum pattern width by dry etching using CHF ₃ gas 0.
After processing the 25 μm oxide film 24, the photoresist is removed.

(9): Referring to FIG. 4C (i), the titanium nitride 12 is processed by wet etching using the oxide film 24 as a mask. As the wet etching solution, hydrogen peroxide solution or a solution obtained by mixing hydrogen peroxide solution and ammonia water at a ratio of 6: 1 is used as in the first embodiment. In FIG. 4C (i), the titanium nitride 12 is entirely processed in the portion on the oxide film 64. However, depending on the misalignment in the photo process or the layout, as shown in FIG. In some cases, the titanium nitride 12 may be processed using the oxide film 24 as a mask. Even in that case, according to the present embodiment, the diffusion layers 46 and 47 and the field oxide film 61 are not etched because the etching is performed with hydrogen peroxide solution or a mixed solution of hydrogen peroxide solution and ammonia water. Therefore, it is not necessary to make a layout with a margin in consideration of misalignment between the diffusion layer and titanium nitride, and the memory cell area can be reduced accordingly. Of course, the wet etching of the titanium nitride 12 using the oxide film 24 of the present embodiment as a mask also has a small side etching amount as in the case of the first embodiment, so that the local interconnect of the titanium nitride 12 having a minimum line width of 0.2 μm can be processed. , A full CMOS static memory cell having a small area of about 7 μm ² could be obtained by a simple process.

Further, when the gate electrodes 81 and 82 are processed, the oxide film 22 is not used and the photoresist is used as a mask so that the oxide film 22 is not left on the gate electrodes. The top is also exposed, so
It is also possible to connect the gate electrode and the diffusion layer or the gate electrodes with titanium nitride by the same process.

<Embodiment 3> FIGS. 7A to 7C are sectional views showing another embodiment of the method for manufacturing a semiconductor device according to the present invention, in which titanium nitride is overlaid on polycrystalline silicon. 6A to 6D are diagrams showing the formation of a gate electrode having a different structure in the order of steps. In order to reduce the resistance of the gate electrode, a structure in which tungsten silicide is overlaid on polycrystalline silicon is generally used. And a fine MOSFE having a gate length of 0.25 μm or less
In T, in order to suppress the short channel effect, polycrystalline silicon doped with n-type impurities is used for the n-channel MOSFET, and polycrystalline silicon doped with p-type impurities is used for the p-channel MOSFET. It is said that a sex gate is needed. However, when a laminated film of polycrystalline silicon and tungsten silicide is used for the gate electrode, if the n-type gate electrode and the p-type gate electrode are directly connected, the impurities easily diffuse in the tungsten silicon due to the heat treatment. , N-type and p-type impurities interdiffuse and affect each other, and as a result, the impurity concentration in the gate polycrystalline silicon is lowered to affect the characteristics of the MOSFET. Therefore, the n-type gate electrode and p
It is impossible to directly connect the gate electrodes of the mold, and since they must be separated and connected by metal wiring, the area of the connection portion becomes large. On the other hand, when a laminated film of polycrystalline silicon and titanium nitride is used for the gate electrode, impurities do not easily diffuse in titanium nitride, so this is not the case.
Even if the n-type gate electrode and the p-type gate electrode are directly connected, a bipolar gate MOSFET having excellent characteristics can be obtained.

In FIG. 7, reference numeral 13 is titanium nitride, 25 is a silicon oxide film, 41 is a silicon substrate, and 61 is a silicon substrate.
Is a field oxide film, 62 is a gate oxide film, and 86 is a gate polycrystalline silicon layer.

Hereinafter, the manufacturing method will be described in the order of steps, taking as an example the case of forming a MOSFET having a gate length of 0.25 μm. First, as shown in FIG. 7A, the silicon substrate 4
A field oxide film 61 having a thickness of 350 nm is formed on the first layer by the LOCOS oxidation method, and then the active region is formed with a thickness of 6 nm.
A gate oxide film 62 having a thickness is formed, and then polycrystalline silicon 86 is deposited to a thickness of 80 nm by the CVD method. Further, titanium nitride 13 is deposited to a thickness of 70 nm by a sputtering method, and an oxide film 25 is deposited thereon to a thickness of 100 nm by a plasma CVD method. At this time, the plasma CVD source is preferably a source such as TEOS that can be deposited at a low temperature of 500 ° C. or lower in order to avoid oxidation and peeling of titanium nitride. Oxide film 25
Is processed by dry etching using the photoresist as a mask. Oxide film 25 at the portion forming the gate electrode
Is processed into a width of 0.25 μm.

Next, as shown in FIG. 7B, the oxide film 2
The titanium nitride 13 is processed by wet etching using 5 as a mask. As a solution for wet etching, hydrogen peroxide solution or a 6: 1 mixed solution of hydrogen peroxide solution and ammonia solution is used. Since wet etching is performed at a high selection ratio, titanium nitride can be processed without being left unetched at a step or the like. In addition, since titanium nitride formed by sputtering has crystal orientation and is etched using an oxide film having good adhesion as a mask, the side etch amount can be reduced.

Further, as shown in FIG. 7C, the oxide film 2
Using the mask 5 as a mask, the polycrystalline silicon 86 is processed by dry etching using Cl ₂ or Br ₂ gas. In the titanium nitride etching step, the titanium nitride is processed without being left in the step portion and the like, so that the polycrystalline silicon 86 can be finely processed to have a fine shape of 0.25 μm.

As described above, according to this embodiment, the gate electrode having the laminated film structure of polycrystalline silicon and titanium nitride can be processed into a good shape, and the n-type gate electrode and the p-type gate electrode can be formed. Even if it is directly connected, it is possible to obtain a 0.25 μm level fine MOSFET having a bipolar gate with excellent characteristics.
Incidentally, in the above manufacturing method, by omitting the step of depositing the polycrystalline silicon 86, a fine MOSF having the titanium nitride 14 as a gate electrode as shown in the sectional structure view of FIG.
Of course, ET can be obtained.

<Embodiment 4> FIG. 9 is a cross-sectional view of an essential part showing still another embodiment of the method for manufacturing a semiconductor device according to the present invention, which is a diffusion layer used in a MOSFET having a gate length of 0.25 μm level. 6A to 6D are diagrams showing the order of steps in the case of silicidizing. In FIG. 9, reference numeral 15 is titanium nitride, 26 is an oxide film, 41 is a silicon substrate, 48 is a diffusion layer, 49 is a titanium silicide layer, 61 is a field oxide film, and 71 and 72 are titanium nitride. .

First, as shown in FIG. 9A, the LOCO
After the diffusion layer 48 having a junction depth of 0.1 μm is formed on the silicon substrate 41 having the field oxide film 61 formed by the S method, the surface of the diffusion layer 48 is exposed and titanium is used for 10 to 10 μm.
After depositing 20 nm, heat treatment at about 650 to 850 ° C. is performed to react titanium and silicon on the diffusion layer to silicidize. At this time, unreacted titanium or titanium nitride 71 is formed on the field oxide film 61 by reacting with nitrogen during heat treatment. Further, thin titanium nitride 72 is formed on the titanium silicide 49.

Next, as shown in FIG. 9B, without removing the titanium nitrides 71 and 72 produced by the silicide reaction,
Titanium nitride 15 is deposited thereon to a thickness of 50 nm by sputtering or CVD.

Further, as shown in FIG. 9C, a CVD oxide film 26 serving as a mask is deposited to a thickness of 100 nm and, for example, CH
Example 1 was performed by dry etching using a photoresist as a mask using F ₃ gas, and using the oxide film 26 as a mask.
Similarly, the titanium nitride 15 is wet-etched with hydrogen peroxide solution or a mixed solution of hydrogen peroxide solution and ammonia solution in a ratio of 6: 1. At that time, the titanium nitrides 71 and 72 generated during the silicide reaction are also etched at the same time. Then, heat treatment is performed again at 800 ° C. or more to further reduce the resistance of the titanium silicide 49.

According to the present embodiment, since titanium nitride 15 serving as a stopper during the dry etching of the oxide film 26 is further deposited on the titanium nitride 71, 72 generated during the silicidation reaction, the titanium silicide is deposited on the titanium silicide. Titanium nitride 72
Even if the oxide film 26 on the above is dry-etched, titanium silicide is not etched as described in the prior art. Therefore, similarly to the second embodiment, even if the diffusion layer is silicidized, it is not necessary to lay out the diffusion layer and titanium with a margin in consideration of misalignment, and a memory cell area as small as 7 μm ² and a high-performance logic are provided. The circuit can be realized on the same chip. By making titanium thin and making titanium nitride 71, 72 thin at the time of forming titanium silicide, the influence of the side etching amount of titanium nitride 71, 72 at the time of wet etching can be made negligible. Further, the titanium nitride 15 is formed by sputtering or C
Since it is formed by the VD method and is not formed when the silicide is formed, the crystal has directionality and the side etch amount is small.

<Embodiment 5> FIG. 10 is a cross-sectional view of an essential part showing still another embodiment of the method for manufacturing a semiconductor device according to the present invention, which is a diffusion layer used in a MOSFET having a gate length of 0.25 μm level. 6A to 6D are diagrams showing the order of steps in the case of silicidizing. In FIG. 10, reference numeral 15 is titanium nitride, 26 is an oxide film, 41 is a silicon substrate, 48 is a diffusion layer, 49 is a titanium silicide layer, 61 is a field oxide film, and 73 is titanium.

First, as shown in FIG.
After forming the diffusion layer 48 having a junction depth of 0.1 μm on the silicon substrate 41 having the field oxide film 61 formed by the OS method, the surface of the diffusion layer 48 is exposed and titanium 73 is deposited in a thickness of 10 to 20 nm. Titanium nitride 15 is deposited to a thickness of 50 nm by sputtering or CVD.

Next, as shown in FIG.
A heat treatment at about 850 ° C. is applied to cause the titanium 73 on the diffusion layer 48 to react with silicon to form a silicide. At this time, unreacted titanium 73 remains on the field oxide film 61, and titanium nitride 15 having directionality in the deposited crystal remains on the titanium silicide 49.

Further, as shown in FIG. 10C, a CVD oxide film 26 serving as a mask is deposited to a thickness of 100 nm to form, for example, C
Dry etching is performed using a photoresist as a mask using HF ₃ gas, and nitriding is performed with hydrogen peroxide solution or a mixed solution of hydrogen peroxide solution and ammonia solution of 6: 1 in the same manner as in Example 1 using the oxide film 26 as a mask. The titanium 15 is wet-etched. At that time, the unreacted titanium 73 is also etched at the same time. Incidentally, titanium nitride 15 and titanium 73
Since the crystal has directionality and the side etching amount is small, it is possible to form a fine wiring pattern having a width of 0.25 μm. Then, heat treatment is performed again at 800 ° C. or more to further reduce the resistance of the titanium silicide 49.

As described above, according to this embodiment, by stacking and depositing titanium 73 and titanium nitride 15 before the silicidation reaction, the titanium 73 and titanium nitride 15 serve as a stopper for dry etching on the titanium silicide 49 even after the silicidation reaction. Since the titanium nitride 15 remains, the titanium silicide 49 is not etched when the oxide film 26 is dry-etched. Therefore, as in the second embodiment, even if the diffusion layer is silicidized, it is not necessary to lay out the diffusion layer and titanium nitride with a margin in consideration of misalignment.
^A small memory cell area of ² and a high-performance logic circuit can be realized on the same chip.

Further, as shown in FIG. 11, first, unreacted titanium after silicidation and titanium nitride generated during the silicidation reaction are removed, and then titanium nitride 15 is deposited and processed in the same manner as in Example 1. You may. In this case, not only titanium but also other metal materials such as cobalt and nickel having excellent chemical resistance can be used as the silicide material.

<Embodiment 6> FIG. 12 is a sectional view showing an embodiment of a semiconductor device according to the present invention. The method of manufacturing the semiconductor device shown in Embodiment 1 is applied to a MOSFET having a gate length of 0.25 μm level. This is the case when applied to the processing of source / drain extraction electrodes.

In FIG. 12, reference numeral 16 is titanium nitride, 27 is a silicon oxide film, 41 is a silicon substrate, 5
Reference numerals 0 and 51 are source / drain diffusion layers, 61 is a field oxide film, 62 is a gate oxide film, 66 is a sidewall oxide film, and 67 is a sidewall oxide film.
Is an interlayer insulating film, 75 is a metal wiring, 87 is a polycrystalline silicon gate electrode, and 88 is a tungsten silicide.

Conventionally, an MO having a gate length of 0.25 μm level
In the case of the structure in which the polycrystalline silicon is used for the source / drain extraction electrode in the SFET, since there is almost no etching selectivity between the polycrystalline silicon and the substrate silicon, a complicated self-alignment process is required for processing the source / drain extraction electrode. Was used.

On the other hand, in the case of the present embodiment, titanium nitride 16 which can be selectively processed with the silicon substrate 41 by wet etching is used for the source / drain extraction electrodes, and the source / drain can be formed by a relatively simple process. The extraction electrode can be processed. That is, in FIG.
After processing the gate electrodes 87 and 88, the source / drain diffusion layers 50 and 51 are formed, and the gate electrodes 87 and 8 are further formed.
By forming an oxide film 66 covering the side wall of the titanium oxide film 8, depositing titanium nitride 16 on the oxide film 66, and wet etching the titanium nitride 16 using the CVD oxide film 27 as a mask by the same method as described in FIG. Can be processed with a small amount of side etch. The source / drain extraction electrodes using the titanium nitride 16 are to be separated just above the gate electrodes 87 and 88. In the structure shown in FIG. 12, since the misalignment between the gate electrode and the source / drain lead-out electrode in the photo process is not taken into consideration, the source / drain lead-out electrode is formed on the oxide film 66 covering the gate electrode. Although they are separated, in actuality, due to misalignment, in the worst case, the separation region is deviated from above the oxide film 66 and the diffusion layer 50
Alternatively, it may be above 51. However, in this embodiment, the silicon substrate 41 is wet-etched.
Since the titanium nitride 16 which is the source / drain extraction electrode can be selectively processed with the diffusion layer 50 or 51,
Is not removed to deteriorate the characteristics of the MOSFET.
Therefore, the source / drain extraction electrodes can be processed by a simple process.

By adopting the structure in which titanium nitride is used for the source / drain lead-out electrodes as described above, the area of the source / drain diffused layer is further reduced, and the source / drain lead-out electrodes are formed on the field oxide film 61. Since it can be pulled up, the capacitance of the source / drain diffusion layer can be reduced. Further, since the resistance value of titanium nitride is lower than that of polycrystalline silicon and slightly higher than that of titanium silicide, the parasitic resistance of the source / drain can be reduced without silicifying the diffusion layer. Due to these effects, a high-performance MOSFET can be obtained.

Therefore, according to the present embodiment, titanium nitride, which has a lower resistance value than that of polycrystalline silicon and can be selectively processed with the silicon substrate by wet etching, is used for the source / drain extraction electrodes. Therefore, a high-performance fine MOSFET with a gate length of 0.25 μm level can be obtained by a simple process.

<Embodiment 7> FIG. 13 is a sectional view showing another embodiment of the semiconductor device according to the present invention. The semiconductor device shown in FIG. 13 is similar to that of the embodiment shown in FIG.
This is a case where the method of manufacturing a semiconductor device described in 1) is applied to processing of source / drain lead-out electrodes of a MOSFET. In FIG. 13, the same components as those shown in FIG. 12 are designated by the same reference numerals for convenience of description, and detailed description thereof will be omitted. That is, the structure of this embodiment is different from the structure of FIG. 12 in that the oxide film 66 covering the side walls of the gate electrodes 87 and 88 is not formed. To realize the structure of FIG. 13, the source / drain diffusion layers 50,
After forming 51, the surface of the diffusion layer is exposed, titanium nitride 16 is deposited thereon, and the titanium nitride 16 is processed by wet etching using the CVD oxide film 27 as a mask in the same manner as in FIG. As shown in FIG. 13, the source / drain extraction electrodes are separated slightly from the gate electrodes 87 and 88 so as not to short-circuit with the gate electrodes 87 and 88. Such a structure is possible because the silicon substrate 41 and the gate electrodes 87 and 88 and the titanium nitride 16 serving as the source / drain extraction electrode can be selectively processed by wet etching.

This embodiment also has substantially the same effect as that of the embodiment shown in FIG. 12, but the source / drain lead-out electrodes are arranged slightly apart from the gate electrodes 87 and 88 so as not to short-circuit with the gate electrodes 87 and 88. The area is increased accordingly, and the effect of reducing the diffusion layer capacitance is small, but there is an advantage that the process becomes simpler because the oxide film 66 covering the side wall of the gate electrode is not formed.

Therefore, according to this embodiment, titanium nitride, which has a resistance value lower than that of polycrystalline silicon and can be selectively processed with the silicon substrate or the gate electrode by wet etching, is used for the source / drain extraction electrodes. Therefore, a high-performance MOSFET having a fine gate length of 0.25 μm level can be obtained by a simple process.

Further, as shown in FIG. 14, the manufacturing process of the local wiring of the memory cell and the extraction electrode of the source / drain of the MOSFET can be made common, so that a fine full CMOS memory cell can be obtained without increasing the number of steps. High-performance peripheral circuits can be realized on the same chip. In particular, it is effective for a processor that requires a high-performance circuit and an internal cache memory having a relatively large capacity. In addition, in FIG.
Reference numeral 16 is titanium nitride, 27 is an oxide film, 41 is a silicon substrate, 42 is a p-well, 43 is an n-well, and 52 is an n-well.
A type diffusion layer, 53 is a p-type diffusion layer, 61 is a field oxide film, 75 is a metal wiring, 89 is a gate electrode, and 90 is a polycide wiring.

Although the so-called single drain MOSFET has been described in the sixth embodiment and the seventh embodiment, the present invention is not limited to this, and the lightly doped drain (the source / drain impurity concentration near the gate is reduced). It goes without saying that the present invention can also be applied to LDD) or double drain MOSFETs.

<Embodiment 8> FIG. 15 is a sectional view showing a further embodiment of the semiconductor device according to the present invention.
This is a case where the method of manufacturing a semiconductor device described in 1) is applied to processing of a base lead electrode of a bipolar transistor.
In FIG. 15, reference numeral 17 is titanium nitride, 28 is a silicon oxide film, 41 is a silicon substrate, 48 is a collector layer, 54 is a collector buried layer, 55 is a collector extraction layer, 56 is an intrinsic base layer, and 57 is an external base layer. , 58 is an emitter layer, 59 is an isolation layer, 61 is a field oxide film, 75 is a metal wiring, and 91 is a polycrystalline silicon emitter electrode.

Conventionally, a high-speed bipolar transistor having a base width of 0.05 to 0.1 μm in which a base electrode and an emitter electrode are formed in a self-aligned manner is polycrystalline silicon or a laminated film of polycrystalline silicon and tungsten silicide. Forming the base extraction electrode with so-called polycide,
The base extraction electrode is formed and then the emitter electrode is formed in a self-aligned manner. In that case, the area of the base layer can be made small, but the process is complicated, and it is difficult to apply it to BiCMOS (LSI in which a bipolar transistor and CMOS are integrated on the same chip) which requires low cost.

On the other hand, in the case of the bipolar transistor shown in FIG. 15 of the present embodiment, titanium nitride 17 that can be selectively processed with the silicon substrate by wet etching.
Since is used for the base extraction electrode, the base extraction electrode can be processed by a relatively simple process. That is,
In FIG. 15, the field oxide film 6 is formed by a known process.
1, isolation layer 59, collector buried layer 54,
After processing the collector extraction layer 55, the intrinsic base layer 56, the emitter layer 58, and the emitter electrode 91, an external base layer 57 is formed to cover the top and side walls of the emitter electrode 91 with an oxide film, and titanium nitride 17 is deposited thereon. Then Fig. 1
The CVD oxide film 28 is formed by the same method as that of the first embodiment described above.
Using the as a mask, the titanium nitride 17 is processed by wet etching. Even if the base extraction electrode is processed on the external base layer 57 due to misalignment in the photo process, the titanium nitride 17 which is the base extraction electrode can be selectively processed with the silicon substrate by wet etching. The external base layer 57 is not scraped to deteriorate the characteristics of the bipolar transistor. Therefore, the base extraction electrode can be processed by such a simple process. This makes it possible to reduce the area of the external base layer 57 and pull up the titanium nitride 17 serving as the base extraction electrode onto the field oxide film 61 to reduce the base capacitance. Moreover, since the resistance value of titanium nitride is lower than that of polycrystalline silicon and slightly higher than that of titanium silicide, the parasitic resistance attached to the base can be reduced. Due to these effects, a fine and high performance bipolar transistor having a cutoff frequency f _{T of} about 15 to 30 GHz can be obtained. Further, the ion implantation process of the external base layer 57 can be shared with the ion implantation process of the source / drain diffusion layers of the MOSFET, and the base and collector extraction electrode formation process can be shared with the source / drain extraction electrode process of the MOSFET.
It can be easily applied to BiCMOS.

Therefore, according to this embodiment, titanium nitride, which has a resistance value lower than that of polycrystalline silicon and can be selectively processed with the silicon substrate by wet etching, is used as the structure of the base / collector extraction electrode. Therefore, a high performance bipolar transistor can be obtained by a simple process. Further, since it is compatible with the MOS process, it can be easily applied to BiCMOS.

The preferred embodiment of the present invention has been described above. However, the present invention is not limited to the above-mentioned embodiment. For example, in the above-mentioned embodiment, a local interconnect or MO is used.
Titanium nitride was used as an example of the material for the source / drain extraction electrodes of the SFET and the base / collector extraction electrode of the bipolar transistor, but it can also be etched with hydrogen peroxide solution or a mixed solution of hydrogen peroxide solution and ammonia solution. A high melting point metal nitride such as tungsten nitride can be similarly applied, or the semiconductor device on the silicon substrate has been described in the above embodiments, but other semiconductors using an SOI (silicon-on-insulator) substrate, for example. It is needless to say that the present invention can be applied to a device and various design changes can be made without departing from the spirit of the present invention.

[0097]

As is apparent from the above-described embodiments, according to the present invention, the side-etching amount is small and the refractory metal nitride such as titanium nitride can be processed by wet etching without cutting the silicon substrate. Line width is 0.3
There is an effect that a fine refractory metal nitride pattern of μm or less can be processed on a silicon substrate.

Further, since the refractory metal nitride such as titanium nitride, which is the local interconnect, is etched with hydrogen peroxide solution or a mixed solution of hydrogen peroxide solution and ammonia solution, it is not possible to etch the diffusion layer and the field oxide film. Therefore, it is not necessary to lay out the diffusion layer and the refractory metal nitride with a margin in consideration of misalignment, and a full CMOS memory cell having a small memory cell area can be obtained by a simple process.

Further, since the refractory metal nitride serving as a stopper for dry etching is further deposited on the refractory metal nitride such as titanium nitride generated during the silicide reaction, the refractory metal nitride on the silicide is deposited. The oxide film on the object can be processed by dry etching, and the silicide is not etched. Therefore, 0.1 μm
Even if the shallow diffusion layer is silicided, it is not necessary to lay out the diffusion layer and the refractory metal nitride with a margin in consideration of misalignment, and a small memory cell area of 10 μm ² or less and a high performance peripheral circuit. There is an effect that both can be achieved.

Furthermore, since the resistance value is lower than that of polycrystalline silicon and a refractory metal nitride such as titanium nitride which can be selectively processed with the silicon substrate by wet etching is used for the extraction electrodes of the source / drain. A high-performance MOSFET can be obtained by a simple process.

Further, since a refractory metal nitride such as titanium nitride having a resistance value lower than that of polycrystalline silicon and capable of being selectively processed with a silicon substrate by wet etching is used for the extraction electrode of the base / collector, There is also an effect that a high-performance bipolar transistor can be obtained by a simple process.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing one embodiment of a method of manufacturing a semiconductor device according to the present invention.

FIG. 2 is a schematic diagram showing a cross-sectional shape when titanium nitride is wet-etched using a photoresist as a mask.

FIG. 3 is a schematic diagram showing a cross-sectional shape when titanium nitride is partially processed by dry etching and the rest is processed by wet etching.

FIG. 4A is a cross-sectional view showing another embodiment of the method for manufacturing a semiconductor device according to the present invention, which is a view showing main manufacturing steps of a full CMOS static memory cell in process order.

FIG. 4B is a diagram showing the next main manufacturing step shown in FIG. 4A in process order.

FIG. 4C is a diagram showing the next main manufacturing step shown in FIG. 4B in process order.

FIG. 5 is a cell layout diagram showing an example of a full CMOS static memory cell shown in FIGS. 4A to 4C.

FIG. 6 is a diagram showing a cross-sectional structure when titanium nitride is processed on a diffusion layer by the manufacturing process shown in FIGS. 4A to 4C.

FIG. 7 is a cross-sectional view showing yet another embodiment of the method for manufacturing a semiconductor device according to the present invention.

8 is a cross-sectional view showing an example of a case where the polycrystalline silicon deposition step is omitted in the manufacturing process shown in FIG. 7 and the gate electrode is made of only titanium nitride.

FIG. 9 is a cross-sectional view showing yet another embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 10 is a cross-sectional view showing yet another embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 11 is a cross-sectional view showing an example of processing by depositing titanium nitride after removing unreacted titanium and generated titanium nitride after the silicide reaction in the method for manufacturing a semiconductor device according to the present invention.

FIG. 12 is a sectional view showing an embodiment of a semiconductor device according to the present invention.

FIG. 13 is a cross-sectional view showing another embodiment of the semiconductor device according to the present invention.

FIG. 14 is a cross-sectional view showing an example in which a local wiring and a source / drain lead-out electrode of a memory cell of a semiconductor device according to the present invention are manufactured in a common process.

FIG. 15 is a sectional view showing still another embodiment of the semiconductor device according to the present invention.

[Explanation of symbols]

 11, 12, 13 ... Titanium nitride, 14 ... Titanium nitride gate electrode, 15, 16, 17 ... Titanium nitride, 21, 22, 23, 24 ... Silicon oxide film, 25, 26, 27, 28 ... Silicon oxide film, 31 , 32, 33 ... Photoresist, 41 ... Silicon substrate, 42 ... P well, 43 ... N well, 44, 46, 52 ... N type diffusion layer, 45, 47, 53 ... P type diffusion layer, 48, 50, 51 ... Diffusion layer, 49 ... Titanium silicide, 54 ... Collector buried layer, 55 ... Collector extraction layer, 56 ... Intrinsic base layer, 57 ... External base layer, 58 ... Emitter layer, 61 ... Field oxide film, 62 ... Gate oxide film, 63 , 64, 65 ... CVD oxide film, 66 ... Oxide film covering side wall of gate electrode, 67 ... Interlayer insulating film, 71, 72 ... Titanium nitride, 73 ... Titanium, 75 ... Metal wiring , 81, 86, 87 ... Polycrystalline silicon gate electrode, 82, 85, 88 ... Tungsten silicide, 83 ... N-type polycrystalline silicon wiring layer, 84 ... P-type polycrystalline silicon wiring layer, 89 ... Gate electrode, 90 ... Polycide Wiring, 91 ... Polycrystalline silicon emitter electrode, 121, 122 ... Extraction electrode, 123, 124 ... Local interconnect, 125, 126 ... Contact hole, 131, 132 ... Contact hole.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akira Fukami 5-20-1 Kamisuihonmachi, Kodaira-shi, Tokyo Hitachi Ltd. Semiconductor Division (72) Inventor Akira Sato 5 Sanmizumoto-cho, Kodaira-shi, Tokyo Chome No. 20-1 Hitate Cho-LS Engineering Co., Ltd.

Claims (23)

[Claims] 1. A step of depositing a wiring material which is a nitride of a refractory metal, a step of depositing a silicon oxide film or a nitride film serving as a mask for wet etching on the wiring material, and a step of using a photoresist as a mask. Manufacturing a semiconductor device, comprising: a step of processing a silicon oxide film or a nitride film by dry etching; and a step of processing the wiring material by wet etching using the processed silicon oxide film or nitride film as a mask. Method. 2. A step of forming a field oxide film and an active region on a surface of a semiconductor substrate by a selective oxidation method, a step of forming a gate electrode of a MOSFET, and ion implantation of impurities into the active region, followed by heat treatment to diffuse the impurity. A step of forming a layer, a step of depositing an insulating film by a CVD method and etching back the entire surface to cover the side wall of the gate electrode of the MOSFET with the insulating film and exposing the diffusion layer; A step of depositing a wiring material that is an object, a step of depositing a silicon oxide film or a nitride film serving as a wet etching mask on the wiring material, and a step of dry etching the silicon oxide film or the nitride film using a photoresist as a mask. A step of processing, and using the processed silicon oxide film or nitride film as a mask, A step of processing the wiring material by etching, and a method of manufacturing a semiconductor device. 3. A step of forming a field oxide film and an active region on the surface of a semiconductor substrate by a selective oxidation method, a step of forming a gate electrode of a MOSFET, and ion implantation of impurities into the active region, followed by heat treatment to diffuse the impurity. A step of forming a layer, a step of covering a required region of the diffusion layer with a laminated film of a conductive film and an insulating film directly or through an insulating film, and depositing the insulating film by a CVD method to etch back the entire surface. By covering the gate electrode of the MOSFET and the side wall of the laminated film with an insulating film and exposing the diffusion layer; depositing a wiring material which is a nitride of a refractory metal; And a step of depositing a silicon oxide film or a nitride film as a mask for wet etching, and using the photoresist as a mask, the silicon oxide film or the nitride film is removed. A method of manufacturing a semiconductor device, comprising: a step of processing the oxide film by dry etching; and a step of processing the wiring material by wet etching using the processed silicon oxide film or nitride film as a mask. 4. A step of forming a field oxide film and an active region on the surface of a semiconductor substrate by a selective oxidation method, a step of forming a gate electrode of a MOSFET, and a silicon oxide film deposited by a CVD method to etch back the entire surface. To cover the sidewall of the gate electrode of the MOSFET with a silicon oxide film and expose the active region, and a silicon oxide film serving as a through film for ion implantation is formed by CVD.
Method, a step of ion-implanting impurities into the active region, a step of activating the ion-implanted impurities by heat treatment to form a diffusion layer, and a step of wet-etching the silicon oxide film to be the through film. A step of removing, a step of depositing a wiring material which is a nitride of a refractory metal, a step of depositing a silicon oxide film or a nitride film serving as a mask for wet etching on the wiring material, and a step of using a photoresist as a mask. Manufacturing a semiconductor device, comprising: a step of processing a silicon oxide film or a nitride film by dry etching; and a step of processing the wiring material by wet etching using the processed silicon oxide film or nitride film as a mask. Method. 5. A step of forming a field oxide film and an active region on the surface of a semiconductor substrate by a selective oxidation method, a step of forming a gate electrode of a MOSFET, and ion implantation of impurities into the active region, followed by heat treatment for diffusion. A step of forming a layer, a step of previously covering a required region of the diffusion layer with a laminated film of a conductive film and an insulating film directly or via an insulating film, and an insulating film is deposited by a CVD method to etch the entire surface. By backing up the gate electrode of the MOSFET and the side wall of the laminated film with an insulating film and exposing the diffusion layer, and a silicon oxide film to be a through film for ion implantation is formed by CVD.
Method, a step of ion-implanting impurities into the exposed diffusion layer, a step of activating the ion-implanted impurities by heat treatment, and a step of removing the silicon oxide film to be the through film by wet etching. A step of depositing a wiring material which is a nitride of a refractory metal, a step of depositing a silicon oxide film or a nitride film serving as a mask for wet etching on the wiring material, and a step of depositing the silicon oxide film using a photoresist as a mask. A method of manufacturing a semiconductor device, comprising: a step of processing a film or a nitride film by dry etching; and a step of processing the wiring material by wet etching using the processed silicon oxide film or nitride film as a mask. 6. The required region of the diffusion layer is a region where wirings made of a nitride of the refractory metal intersect with each other on the diffusion layer and are not in contact with the wirings. A method of manufacturing a semiconductor device according to item 1. 7. The gate electrode of the MOSFET is made of polycrystalline silicon, a laminated film of polycrystalline silicon and a refractory metal silicide film, a refractory metal, or a refractory metal nitride. The method for manufacturing a semiconductor device according to claim 1. 8. A step of depositing a refractory metal to be a source of silicide between the step of exposing the diffusion layer by the etch back and the step of depositing a wiring material which is a nitride of the refractory metal. A heat treatment at 650 to 850 ° C. to form a silicide on the diffusion layer is added, and the wiring material is processed by wet etching using the processed silicon oxide film or nitride film as a mask. 4. The method for manufacturing a semiconductor device according to claim 2, wherein the refractory metal nitride and the unreacted refractory metal generated when the silicide is formed are processed. 9. A step of removing the silicon oxide film which becomes the through film of the ion implantation by wet etching,
Between the step of depositing the wiring material, which is a nitride of the refractory metal, the step of depositing the refractory metal that will be the source of the silicide and the heat treatment at 650 to 850 ° C. to form the silicide on the diffusion layer. In addition to the step of forming, in the step of processing the wiring material by wet etching using the processed silicon oxide film or nitride film as a mask, nitride and unreacted refractory metal generated when the silicide is formed. The method for manufacturing a semiconductor device according to claim 4, wherein the refractory metal is processed. 10. A step of depositing a refractory metal serving as a source of silicide after the step of exposing the diffusion layer by the etch back, and a step of depositing a wiring material which is a nitride of the refractory metal. And a step of performing a heat treatment at 650 to 850 ° C. to form silicide on the diffusion layer, and a step of processing the wiring material by wet etching using the processed silicon oxide film or nitride film as a mask. 4. The method of manufacturing a semiconductor device according to claim 2, wherein the refractory metal nitride and the unreacted refractory metal generated when the silicide is formed are processed. 11. A step of depositing a refractory metal to be a source of silicide after the step of removing the silicon oxide film to be the ion implantation through film by wet etching, and a nitride of the refractory metal. After the step of depositing the wiring material, the step of performing heat treatment at 650 to 850 ° C. to form silicide on the diffusion layer is added, and the processed silicon oxide film or nitride film is used as a mask for wet etching. The method for manufacturing a semiconductor device according to claim 4, wherein in the step of processing the wiring material, the nitride of the refractory metal generated when forming the silicide and the unreacted refractory metal are processed. 12. A step of depositing a refractory metal serving as a source of silicide between the step of exposing the diffusion layer by the etch back and the step of depositing a wiring material which is a nitride of the refractory metal. A heat treatment at 650 to 850 ° C. to form a silicide on the diffusion layer, and a wet-etching process for removing the nitride of the refractory metal and the unreacted refractory metal generated when the silicide is formed. 4. The method for manufacturing a semiconductor device according to claim 2, further comprising: 13. A silicide source is provided between the step of removing the silicon oxide film which becomes the through film of the ion implantation by wet etching and the step of depositing the wiring material which is the nitride of the refractory metal. A step of depositing a refractory metal, a step of performing a heat treatment at 650 to 850 ° C. to form a silicide on the diffusion layer, a nitride of the refractory metal generated when the silicide is formed, and an unreacted high melting point The method for manufacturing a semiconductor device according to claim 4, further comprising a step of removing metal by wet etching. 14. The method of manufacturing a semiconductor device according to claim 1, wherein the wiring material of the refractory metal nitride is titanium nitride. 15. The method of manufacturing a semiconductor device according to claim 8, wherein the refractory metal serving as a source of silicide is titanium. 16. The method of manufacturing a semiconductor device according to claim 8, wherein the refractory metal serving as a source of silicide is cobalt. 17. The semiconductor according to claim 1, wherein the step of depositing the silicon oxide film serving as the wet etching mask is a step of depositing by plasma CVD using tetraethoxysilane as a source. Device manufacturing method. 18. The method of manufacturing a semiconductor device according to claim 1, wherein the step of depositing the silicon nitride film serving as the mask for the wet etching is a step of depositing by plasma CVD. 19. The method for manufacturing a semiconductor device according to claim 1, wherein the etching solution for the wet etching is hydrogen peroxide solution or a mixed solution of hydrogen peroxide solution and ammonia water. Method. 20. A semiconductor device, characterized in that the source / drain electrodes of the MOSFET and the source / drain extraction electrodes for extracting the source and drain electrodes on the field oxide film are made of a refractory metal nitride. . 21. A semiconductor characterized in that a base or collector electrode of a bipolar transistor and a base / collector lead electrode for drawing the base or collector electrode onto a field oxide film are made of a refractory metal nitride. apparatus. 22. A semiconductor device in which a memory cell array composed of a plurality of memory cells and a logic circuit for selecting and reading and writing information from the memory cells or a logic circuit forming a processing unit are integrated on one chip, and two transfer MOSFETs are provided. Two drivers MO
Source / drain electrodes and local wiring in a memory cell of a static memory cell including an SFET and two load MOSFETs, source / drain electrodes of the MOSFET in the logic circuit section, and the source / drain electrodes are drawn on a field oxide film. A semiconductor device, wherein the source / drain lead-out electrodes are made of a high melting point metal nitride. 23. The semiconductor device according to claim 20, wherein the nitride of the refractory metal is titanium nitride.