JP4054673B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a semiconductor device and a manufacturing method thereof. More specifically, regarding a dynamic threshold transistor in which a gate electrode and a well region are connected, a semiconductor device having a structure in which the gate electrode and the well region are reliably connected and the capacitance associated with the source / drain region is reduced, and its manufacture Regarding the method.
[0002]
[Prior art]
  Mobile device terminals such as mobile phones continue to make remarkable progress, but low power consumption of CMOS (Complementary Metal Oxide Semiconductor) LSIs (Large Scale Integrated Circuits) is eager to extend the battery life. Has been. Since the power consumption of this CMOS LSI is proportional to the square of the power supply voltage, it is most effective to lower the power supply voltage to reduce power consumption. However, when the power supply voltage is lowered, the driving capability of the transistor is reduced, which causes a problem that the delay time of the circuit increases. This becomes more prominent as the power supply voltage is lowered.
[0003]
  One way to improve this is to lower the threshold voltage of the transistor. However, as the threshold voltage decreases, the gate-off leakage current, that is, the standby leakage current increases, which is acceptable. The lower limit of the threshold is limited by the standby leakage current.
[0004]
  In order to solve such a problem, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) capable of low-voltage driving, low power consumption, and high-speed operation utilizing a substrate bias effect generated by changing the bias of the well region. As a technique, a dynamic threshold operation transistor (hereinafter referred to as DTMOS) using a bulk substrate has been proposed (see, for example, Patent Document 1).
[0005]
  FIG. 19A shows a planar layout of such a DTMOS, FIG. 19B shows a cross section in the AA ′ direction in FIG. 19A, and FIG. 19C shows FIG. The cross section of BB 'direction in a) is shown. In this DTMOS, a deep well region 302 is formed in a semiconductor substrate 301, and a shallow well region 303 is formed on the deep well region 302 so as to be electrically isolated for each element by an element isolation region 304. The gate electrode 306 formed on the gate insulating film 305 is connected to the shallow well region 303 of the second conductivity type through the high melting point silicide film 361. In order to connect the gate electrode 306 and the second conductivity type shallow well region 303, a part of the gate electrode 306 and the gate insulating film 305 is removed and contacted to the surface of the second conductivity type shallow well region 303. Region 308 is provided. A second conductivity type high concentration diffusion layer 321 for ohmic connection between the refractory silicide film 361 and the shallow well region 303 is formed in the second conductivity type shallow well region 303. Reference numeral 307 denotes a source / drain region, and a refractory silicide film 361 is also formed on these regions.
[0006]
  In the DTMOS, the gate electrode 306 and the shallow well region 303 are electrically connected. Therefore, the potential of the shallow well region 303 rises only when a high level potential is applied to the gate electrode 306, and the effective threshold is lowered due to the substrate bias effect, so that the drive current is normal MOSFET. Compared to increase. Therefore, a large drive current can be obtained while maintaining a low leakage current with a low power supply voltage. Therefore, a low voltage drive and low power consumption MOSFET is realized.
[0007]
  However, as shown in FIG. 19B, when the minimum processing dimension is L, the distance between the gate electrode 306 and the element isolation region 304 is about 3L. Therefore, there is a problem that the junction capacitance related to the source / drain region 307 is large. It is very important to reduce the junction capacitance in DTMOS. This is because DTMOS connects a gate electrode and a well, and when a voltage is applied to the gate electrode, a junction capacitance is generated between the source electrode and the well and between the drain electrode and the well, respectively. In particular, twice the capacitance between the source electrode and the well is generated between the drain electrode and the well due to the mirror effect during the switching operation of the transistor. This is a total of three times the junction capacitance of a transistor with a normal structure that is not DTMOS. Therefore, it is very important for DTMOS to reduce the junction capacitance, that is, to reduce the junction area. Further, as shown in FIG. 3, when a series transistor is formed, a transistor having a normal structure (not shown) does not require an element isolation region between elements because a gate electrode and a well are not connected. Therefore, the distance between the gate electrodes could be formed with the minimum processing dimension L. On the other hand, in DTMOS, an element isolation region having a minimum processing dimension width L and each source / drain region are necessarily required. Therefore, the element size in the direction perpendicular to the longitudinal direction of the gate electrode of the DTMOS is larger than that of the transistor having the normal structure. As described above, it is very important for DTMOS to reduce the active layer width of the source / drain regions from the viewpoint of both increasing the capacitance and increasing the dimension in the direction perpendicular to the longitudinal direction of the gate electrode.
[0008]
  In order to solve the above problem, a semiconductor device is disclosed in which the junction capacitance relating to the source / drain region is reduced, that is, the junction area of the source / drain region is reduced (see, for example, Patent Document 2).
[0009]
  A schematic structure of this semiconductor device is shown in FIG. FIG. 20A shows the planar layout, and FIG. 20B shows a cross section in the A-A ′ direction in FIG. An element isolation region 402 is formed in the semiconductor substrate 401, and a gate insulating film 403 and a gate electrode 404 are sequentially formed on the semiconductor substrate 401. A semiconductor layer 408 is stacked on both sides of the gate electrode 404 above the surface of the semiconductor substrate 401 with a gate electrode sidewall insulating film 405 interposed therebetween. A refractory silicide film 409 is formed on the gate electrode 404 and the semiconductor layer 408. The width of the semiconductor layer 408 in the direction perpendicular to the longitudinal direction of the gate electrode 404 is the distance between the gate electrode sidewall insulating film 405 and the element isolation region 402, that is, the source / drain on the surface where the semiconductor substrate 401 and the gate insulating film 403 are in contact. It is formed larger than the active region width of the region. Therefore, the contact hole 411 is formed without reducing the contact area between the contact hole 411 provided in the interlayer insulating film 410 and the refractory silicide film 409, that is, without increasing the contact resistance, and the junction area is reduced. Thus, the junction capacity can be reduced.
[0010]
[Patent Document 1]
          Japanese Patent Laid-Open No. 10-163342
[Patent Document 2]
          JP 2000-82815 A
[0011]
[Problems to be solved by the invention]
  However, the conventional techniques shown in FIGS. 19 and 20 have the following problems.
[0012]
  First, the problem of the DTMOS shown in FIG. 19 will be described with reference to FIG. FIG. 21A is an enlarged view of the vicinity of the contact region 308 connecting the gate electrode 306 and the high concentration diffusion layer 321 of the shallow well region 303. The gate electrode 306 and the shallow well region 303 are connected to each other in the contact region 308 through the high melting point silicide film 361. However, as shown in FIG. 21A, this contact region 308 has a structure having a vertical step in which the refractory silicide film 361 is hardly formed because the gate electrode 306 is formed by anisotropic etching. It has become. For this reason, there is a problem that the region of the high melting point silicide film 361 formed at the bottom indicated by a dotted circle in the drawing of the contact region 308 becomes thin and the resistance increases, or in the worst case, the contact is broken. is there. This occurs because the refractory silicide film 361 is generally formed using a physical sputtering method with poor step coverage. This causes a delay in the propagation speed of the electric signal from the gate electrode 306 to the shallow well region 303, which causes a decrease in the operating speed of the DTMOS. On the other hand, the contact region 308 may have a tapered shape in which the silicide film 361 can be easily formed. However, the tapered shape is not suitable for miniaturization because an extra area is required in the longitudinal direction of the gate electrode. .
[0013]
  Therefore, as shown in FIG. 21 (b), the present inventors use a well-known processing technique and wiring formation technique to form the gate electrode and the shallow well using the contact metal plug 350 and the upper wiring 351 (and 361). Connected. Then, the gate electrode 306 and the high-concentration diffusion layer 321 in the shallow well region 303 could be connected without disconnection or high resistance. However, as shown in FIG. 21B, in order to provide the contact metal plug 350 and the upper wiring 351, if the minimum processing dimension is L, a large dimension of 3L is required in the longitudinal direction of the gate electrode. Therefore, it has been found that the device area in the longitudinal direction of the gate electrode becomes large and cannot be miniaturized. In addition, since it is necessary to always provide the upper wiring 351 on the contact region 308, the degree of freedom in designing the upper wiring is reduced, and as a result, the element area becomes very large.
[0014]
  In addition, the semiconductor device illustrated in FIG. 20 has a problem in that the capacitance collected between the gate electrode 404 and the semiconductor layer 408 increases. For example, in an element having a minimum processing dimension of 0.24 μm, if the thickness of the gate electrode 404 is 250 nm and the active region width of the source / drain region is 0.24 μm, the gate electrode 404 and the semiconductor layer 408 are combined. The capacity will occupy about 10% of the total capacity of the device. In order to suppress the short channel effect with the miniaturization of the element, the junction depth below the surface where the semiconductor substrate 401 and the gate insulating film are in contact with each other is formed shallower, and accordingly, the thickness of the gate electrode sidewall insulating film 405 is also reduced. The For this reason, the ratio of the capacity | capacitance put together between the gate electrode 404 and the semiconductor layer 408 with respect to the capacity | capacitance of the whole element becomes large. Therefore, this problem becomes more serious as device miniaturization progresses. The semiconductor layer 408 is also formed in regions 440 and 450 other than the region operating as a transistor, that is, the so-called source / drain active region. Accordingly, the capacitance between the gate electrode 404 and the semiconductor layer 408 increases accordingly. Further, by using the semiconductor layer 408 as a local wiring, the degree of freedom of wiring can be improved to some extent, but the semiconductor layer 408 can be formed only to a certain width (about 300 nm to 500 nm) from the gate electrode. Therefore, since it cannot be formed on other element isolation regions, the degree of freedom of wiring is insufficient. Further, although the demand for the system LSI is increasing, the semiconductor device shown in FIG. 20 needs to form the semiconductor layer 408 after the gate electrode 404 is formed. Since a transistor having a normal structure does not have such a process, it is difficult to simultaneously form them on the same chip. Even if it can be formed, it becomes a very complicated process, which increases the cost and impairs the production efficiency of the mass production line.
[0015]
  SUMMARY OF THE INVENTION Accordingly, a first object of the present invention is to provide a semiconductor device that can reduce the connection resistance between the gate electrode and the well without disconnection with a simple configuration and can stably obtain a high driving force, and a method for manufacturing the same. There is to do.
[0016]
  A second object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can reduce the capacitance combined with the source / drain regions and the junction capacitance of the source / drain regions even when miniaturized.
[0017]
[Means for Solving the Problems]
  In order to solve the above problems, a semiconductor device of the present invention is formed in a semiconductor substrate, a first conductivity type deep well region formed in the semiconductor substrate, and a first conductivity type deep well region. A shallow well region of a second conductivity type divided by an element isolation region, a gate insulating film formed on the shallow well region of the second conductivity type, and a gate electrode formed on the gate insulating film, The contact region formed in the vicinity of the end of the gate electrode in the shallow well region of the second conductivity type and the gate electrode and the contact region are formed across the step at the end of the gate electrode. A contact conductor, a source / drain region of the second well-type shallow well region, and a region overlying an upper portion of the element isolation region, and the gate above the surface of the semiconductor substrate; A source / drain conductor formed in a position at a distance from the electrodes, the minimum feature size is L, and the width direction of the contact conductor that spans the step of the gate electrode and Wpl,
      4L / 3 ≤ Wpl ≤ 2L
Meets the requirements ofIn addition, if the shortest distance between the gate electrode and the source / drain conductor is Sgppl,
      L / 3 ≦ Sgppl ≦ 2L / 3
Meets the requirements ofIt is characterized by that.
[0018]
  According to the semiconductor device having the above configuration, the gate electrode and the shallow well region are reliably connected by the presence of the contact conductor formed so as to connect the gate electrode and the contact region across the step at the end of the gate electrode. It becomes possible. Therefore, the connection resistance between the gate electrode and the well can be reduced without disconnection with a simple configuration, and a high driving force can be stably obtained.
[0019]
[0020]
  In addition, a contact hole with the upper electrode can be formed on the source / drain conductor formed in the element isolation region. That is, since the contact holes can be laid out on the element isolation region, the degree of freedom of layout of the contact holes is increased. Therefore, the degree of freedom of the upper wiring is improved and the element can be miniaturized. Further, since the distance between the gate electrode and the element isolation region can be reduced, the junction capacitance of the source / drain region can be reduced.
[0021]
[0022]
  Further, by setting the width Wpl of the contact conductor to 4L / 3 or more, the gate electrode and the shallow well region are connected with a sufficiently low contact resistance even if a positional shift occurs with respect to the connection region between the gate electrode and the shallow well. can do. On the other hand, when the width Wpl of the contact conductor is 2 L or less, miniaturization in the longitudinal direction of the gate electrode is not impaired.
[0023]
[0024]
  furtherBy setting the shortest distance Sgppl between the gate electrode and the source / drain conductor to be L / 3 or more, the capacitance integrated between the gate electrode and the source / drain region does not increase. On the other hand, by setting the shortest distance Sgppl between the gate electrode and the source / drain conductor to 2L / 3 or less, the area of the source / drain region is not increased and the junction capacitance is not increased.
[0025]
  The semiconductor device according to an embodiment is characterized in that the source / drain conductor is thinner than the gate electrode.
[0026]
  According to the semiconductor device having the above configuration, the capacity of the source / drain conductor and the gate electrode can be reduced.
[0027]
  In one embodiment, the semiconductor device of the present invention is characterized in that the source / drain conductor is formed in two or more locations in each of the source / drain regions.
[0028]
  According to the semiconductor device having the above configuration, since there is a region where the source / drain conductor is not formed, the capacity of the source / drain conductor and the gate electrode in the region can be reduced. Further, since the area intersecting the upper wiring is reduced, the capacitance between the source / drain conductor and the upper wiring can be reduced.
[0029]
  The method of manufacturing a semiconductor device according to the present invention includes a step of forming a first conductivity type deep well region in a semiconductor substrate, and an element shallower than the first conductivity type deep well region so as to partition the surface of the semiconductor substrate. A step of forming an isolation region, a step of forming a shallow well region of a second conductivity type shallower than the element isolation region in a state partitioned by the element isolation region, and a step of forming on the shallow well region of the second conductivity type A step of sequentially forming a gate insulating film, a gate electrode extending in one direction, a gate electrode side wall insulating film covering the side wall of the gate electrode, and the gate insulating film and the gate electrode on the shallow well region of the second conductivity type Forming a contact region in the vicinity of the end of the gate electrode in the second conductivity type shallow well region, and forming the contact region; A step of forming an insulating film; a step of removing a region of the interlayer insulating film on a region straddling a step at an end of the gate electrode to form a first removal region; and a shallow well region of the second conductivity type Forming a second removal region by removing a region of the interlayer insulating film on a region straddling the source / drain region and the element isolation region, and forming the second removal region in the first removal region and the second removal region And a step of embedding a conductor.
[0030]
  According to the method for manufacturing a semiconductor device of the present invention, the connection resistance between the gate electrode and the well can be reduced without using a special manufacturing apparatus, without disconnection with a simple structure, and a high driving force can be stably obtained. In addition, it is possible to form a semiconductor device with good controllability that can reduce the capacitance combined with the source / drain regions and the junction capacitance of the source / drain regions even when miniaturized. Further, since the conductor for connecting the gate electrode and the shallow well region and the conductor formed in the source / drain region are formed at the same time, the number of steps can be reduced and the cost can be reduced.
[0031]
  In the method of manufacturing a semiconductor device according to one embodiment, a gate insulating film, a gate electrode extending in one direction, and a gate electrode side wall insulating film covering the side wall of the gate electrode are sequentially formed on the second well type shallow well region. Forming the gate insulating film and a part of the gate electrode on the second conductivity type shallow well region to connect the gate electrode and the second conductivity type shallow well; The step of forming the contact region is characterized by being performed simultaneously.
[0032]
  According to the manufacturing method of the semiconductor device of the above-described embodiment, a mask for forming the contact region is not necessary, and the cost can be reduced.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be described in detail with reference to embodiments shown in the drawings.
[0034]
(First embodiment)
  The semiconductor device according to the first embodiment provides a semiconductor device having a structure in which a gate electrode and a well are reliably connected and a manufacturing method thereof in order to realize a DTMOS that can stably obtain a high driving force. The semiconductor substrate that can be used in the present invention is not particularly limited, but a silicon substrate is preferable. The semiconductor substrate may have a P-type or N-type conductivity type.
[0035]
  First, the configuration of the semiconductor device according to the first embodiment will be described with reference to FIG. FIG. 1A shows a planar layout of the semiconductor device according to the first embodiment, and FIG. 1B shows a cross section taken along the line AA ′ in FIG. ) Shows a cross section in the BB ′ direction in FIG. FIG. 1A is a plan view of the state without an interlayer insulating film as viewed from above.
[0036]
  As shown in FIGS. 1A to 1C, a first conductivity type deep well region 103 is formed in a second conductivity type semiconductor substrate 101, and the first conductivity type deep well region 103 is formed on the first conductivity type deep well region 103. A shallow well region 104 of two conductivity type is formed. The shallow well region 104 is divided by the element isolation region 102 and is electrically isolated for each element.
[0037]
  In the semiconductor device of the first embodiment, a gate electrode 106 made of a semiconductor film doped to the first conductivity type is formed on a channel region 130 via a gate insulating film 105. On the other hand, in the contact region 120 for connecting the gate electrode 106 and the shallow well region 104, the gate insulating film 105 and the gate electrode 106 are removed, and the contact region 120 is gated by the refractory silicide film 112 and the contact conductor 115. The electrode 106 and the shallow well region 104 are connected. The diffusion layer 111 doped with the second conductivity type impurity at a higher concentration than the shallow well region 104 is formed in the entire contact region 120 so that the refractory silicide film 112 and the shallow well region 104 are ohmic-connected with good controllability. Is formed. For this reason, when the second conductivity type is P-type, that is, in NMOS, the impurity concentration of the shallow well region 104 is reduced, and the leakage current from the gate electrode 106 to the source electrode through the shallow well region 104 increases. Can be prevented. At this time, in order to make ohmic contact between the refractory silicide film 112 and the shallow well region 104 with good controllability, the concentration of the diffusion layer 111 is 1 × 10 6.²⁰~ 1x10^{twenty one}/ Cm^ThreeIt is preferable that it is formed with a degree.
[0038]
  The contact conductor 115 is formed in a region connecting the gate electrode 106 and the shallow well region 104, and the source / drain conductor 155 is formed on the source / drain regions 131 and 132 and the element isolation region 102. .
[0039]
  First, the contact conductor 115 formed in the contact region 120 in order to connect the gate electrode 106 and the shallow well region 104 will be described.
[0040]
  The interlayer insulating film 116 is removed so as to straddle the step at the end of the gate electrode 106 and a part of the contact region 120, and the contact conductor 115 is buried in the removed region. Therefore, as described with reference to FIG. 21A, the gate electrode 106 and the shallow well region 104 can be reliably connected even when the refractory silicide film 112 is disconnected at the lower part of the step. Further, since the gate electrode 106 and the shallow well region 104 are connected by the contact conductor 115, it is not necessary to use an upper wiring (not shown) as described with reference to FIG. Therefore, the element dimension in the longitudinal direction of the gate electrode is not increased, and an upper wiring (not shown) can be freely laid out on the contact region 120. Accordingly, the element can be miniaturized and the design freedom of the upper wiring can be improved, so that a high-density integrated circuit can be formed.
[0041]
  Here, a preferred layout of the contact conductor 115 used for reliably connecting the gate electrode 106 and the shallow well region 104 will be described.
[0042]
  12A and 12B are enlarged cross-sectional views of the contact region 120 where the gate electrode 106 and the shallow well region 104 are connected. 12A and 12B, the same components as those in FIG. 1 are denoted by the same reference numerals.
[0043]
  FIG. 12A shows an example in which the width of the contact conductor 115 is 4L / 3 with respect to the longitudinal direction of the gate electrode 106 and the stepped portion of the gate electrode 106 is laid out at the center of the contact conductor 115. The contact width between the gate electrode 106 and the contact conductor 115 and the contact width between the contact conductor 115 and the contact region 120 are 2L / 3, respectively, and the gate electrode 106 and the shallow well region 104 are controlled with sufficiently low contact resistance. It can be connected with good performance.
[0044]
  At this time, the positional misalignment generated between the contact region 120 and the contact conductor 115 is generally about L / 3 when the minimum processing dimension is L. Therefore, the position of the contact conductor 115 is L toward the element isolation region 102. In the case of a deviation of about / 3, the positional relationship between the contact region 120 and the contact conductor 115 is as shown in FIG. Thus, if the width of the contact conductor 115 in the longitudinal direction of the gate electrode is designed to be 4L / 3, the position of the contact conductor 115 is shifted toward the element isolation region as shown in FIG. However, the gate electrode 106 and the contact conductor 115 are connected with a sufficient width of about L / 3. For this reason, the contact resistance does not increase. This has been confirmed by experiments.
[0045]
  Although not shown, even when the position of the contact conductor 115 is shifted in the direction of the gate electrode 106, the contact conductor 115 and the contact region 120 are connected with a sufficient width of about L / 3. Therefore, the contact resistance does not increase.
[0046]
  As described above, in the semiconductor device according to the first embodiment, the gate electrode 106 and the shallow well region 104 can be connected with good controllability without increasing the resistance even if process fluctuation occurs. The width of the contact conductor 115 in the direction perpendicular to the longitudinal direction of the gate electrode only needs to be equal to or larger than the minimum processing dimension L, and the contact area increases and the contact resistance decreases. In the present embodiment, the width of the contact conductor 115 in the longitudinal direction of the gate electrode is 4L / 3. However, this is only an example, and the element area becomes large. The width of the contact conductor 115 may be larger than 4L / 3. However, if the width of the contact conductor 115 in the longitudinal direction of the gate electrode is larger than 2L, the element area is significantly increased, which is not preferable. Alternatively, the width may be set to L, and L / 3 may be overlapped with the gate electrode 106, that is, the width of the contact conductor 115 in the longitudinal direction of the gate electrode may be designed to be L. In this case, even if the contact conductor 115 is displaced by about L / 3 in the direction of the element isolation region 102, the contact conductor 115 and the gate electrode 106 are in contact with each other on the side wall surface of the gate electrode. Can be maintained. This has also been confirmed by experiments.
[0047]
  Next, the source / drain conductor 155 formed in the source / drain regions 131 and 132 will be described with reference to FIG.
[0048]
  As shown in FIG. 1, the source / drain conductor 155 is formed from a position about 2 L / 3 away from the gate electrode 106 toward the element isolation region 102 above the surface where the shallow well region 104 and the gate insulating film 105 are in contact. It is formed so as to straddle the element isolation region 102 in the direction of the isolation region 102. The source / drain conductor 155 is thinner than the gate electrode 106. Therefore, since the source / drain conductor 155 is formed at a position sufficiently separated from the gate electrode 106 and the film thickness of the source / drain conductor 155 is thinner than that of the gate electrode 106, the source / drain conductor 155 and the gate electrode The facing area of 106 is small. Therefore, there is an effect that the capacity of the gate electrode 106 and the source / drain regions 131 and 132 is small.
[0049]
  In addition, since the distance between the source / drain conductor 155 and the upper wiring (not shown) is larger than the semiconductor device shown in FIG. 20 (Japanese Patent Laid-Open No. 2000-82815), the source / drain regions 131, There is an effect that the capacity of the 132 and the upper wiring is also small. In this embodiment, the case where the film thickness of the source / drain conductor 155 is thinner than that of the gate electrode 106 is described, but the present invention is not limited to this, and the film thickness of the source / drain conductor 155 is It doesn't matter if it's more. However, in this case, as compared with the case where the film thickness of the source / drain conductor 155 is thinner than that of the gate electrode 106, the capacitance combined with the gate electrode 106 and the source / drain regions 131 and 132, and the source / drain region The capacity of the 131 and 132 and the upper wiring is increased. However, as compared with the conventional example, the effect of reducing the capacity of the gate electrode 106 and the source / drain regions 131 and 132 can be maintained.
[0050]
  The source / drain conductor 155 is also formed on the element isolation region 102. Since it is not necessary to drop the contact hole 117 directly on the refractory silicide film 112 of the source / drain regions 131 and 132, the distance between the gate electrode 106 and the element isolation region can be reduced to reduce the junction capacitance. Further, since the source / drain conductor 155 is not restricted by the active regions of the source / drain regions 131 and 132 and can be freely laid out on the element isolation region 102, the degree of freedom in forming the contact hole 117 is increased. There is an effect that the degree of freedom of the upper layer wiring (not shown) is increased. This is an effect that cannot be realized in the semiconductor device shown in FIG. 20 (Japanese Patent Laid-Open No. 2000-82815) in which only a semiconductor film having a certain width can be formed from the gate electrode.
[0051]
  Here, an example of a preferable layout of the source / drain conductor 155 formed in the source / drain regions 131 and 132 shown in FIG. 1 will be described.
[0052]
  FIG. 13 is an enlarged cross-sectional view in the direction perpendicular to the longitudinal direction of the gate electrode, for explaining the positional relationship between the gate electrode 106, the source / drain conductor 155, and the element isolation region 102. Although FIG. 13 illustrates the source / drain region 132, the same applies to the source / drain region 131.
[0053]
  13A, the distance between the gate electrode end 124 and the element isolation region 102 end 125 is 4L / 3, and the distance (Sgppl) between the gate electrode end 124 and the end 123 of the source / drain conductor 155 is 2L /. This is a layout example when 3. First, since the source / drain conductor 155 and the refractory silicide film 112 in the source / drain region 132 are in contact with each other with a width of 2L / 3, the source / drain conductor 155 and the refractory silicide film have a sufficiently low contact resistance. 112 can be contacted. In addition, since the gate electrode 106 and the source / drain conductor 155 are separated from each other by about 2L / 3, the capacity of the gate electrode 106 and the source / drain region 132 can be reduced.
[0054]
  FIG. 13B shows a case where the position of the source / drain conductor 155 is shifted by about L / 3 toward the element isolation region 102. Thus, even if the position of the source / drain conductor 155 is shifted due to misalignment, the source / drain conductor 155 and the refractory silicide film 112 can be contacted with a sufficient width of L / 3, so that the contact resistance is sufficiently low. Can keep you.
[0055]
  Although not shown in the figure, when the position of the source / drain conductor 155 is shifted toward the gate electrode 106, the source / drain conductor 155 approaches the gate electrode 106, so there is a concern about an increase in capacitance. Since a sufficient distance of about L / 3 can be maintained, the capacity of the gate electrode 106 and the source / drain regions 131 and 132 is not increased.
[0056]
  As described above, in the semiconductor device according to the first embodiment, even if process fluctuation occurs, resistance and capacitance are not increased. In this embodiment, the distance (Sgppl) between the gate electrode 106 and the source / drain conductor 155 is 2L / 3, but this is only an example, and the distance may be set to L / 3 at the minimum. However, in this case, if the source / drain conductor 155 is displaced in the direction of the gate electrode 106 due to misalignment, the capacity of the gate electrode 106 and the source / drain regions 131 and 132 increases. However, instead, the distance between the gate electrode end 124 and the element isolation end 125 can be reduced by that amount (L / 3). For this reason, the source / drain junction capacitance can be reduced. Further, this distance may be larger than 2L / 3. In this case, since it is necessary to increase the distance between the gate electrode end 124 and the end 125 of the element isolation region 102 by the increased amount, the junction capacitance of the source / drain regions 131 and 132 increases. Implementation is possible if the increase is within an acceptable range.
[0057]
  In addition, as shown in FIG. 1A, when the channel width (gate width) in the longitudinal direction of the gate electrode is sufficiently larger than the contact hole 117, the source / drain conductivity stacked in the source / drain regions 131 and 132 is increased. The body 155 is divided into two or more places along the longitudinal direction of the gate electrode (three places in FIG. 1A). Therefore, since the source / drain conductors 155 can be laid out freely such as a place where a contact hole 117 with an upper wiring (not shown) is provided or a place used as a local interconnect described later, the degree of freedom in design Is significantly improved. Further, unlike the semiconductor device shown in FIG. 20 (Japanese Patent Laid-Open No. 2000-82815), the source / drain conductor 155 is not formed in an unnecessary region other than the active region of the transistor. Therefore, since the area of the source / drain conductor 155 that opposes the gate electrode 106 can be reduced, the capacity of the gate electrode 106 and the source / drain regions 131 and 132 can be reduced. Furthermore, since the area where the source / drain conductor 155 and the upper wiring (not shown) are opposed to each other in the vertical direction is reduced, the capacity of the source / drain regions 131 and 132 and the upper wiring can be reduced.
[0058]
  Although not shown, in the case of a transistor whose gate electrode width is not sufficiently large with respect to the contact hole 117, the source / drain conductor 155 may be formed only at one place. However, even in this case, the source / drain conductor 155 may be provided only in the region where the contact hole 117 is laid out. Therefore, regardless of the gate width, the semiconductor device shown in FIG. 20 (Japanese Patent Laid-Open No. 2000-82815) in which stacked semiconductor layers are always formed over the entire gate width in the longitudinal direction of the gate electrode cannot be realized. Thus, improvement in design freedom and reduction in capacitance between the gate electrode 106 and the source / drain regions 131 and 132 can be realized at the same time.
[0059]
  Next, the case where the contact hole 119 to the gate electrode 106 is formed on the contact conductor 115 will be described with reference to FIG.
[0060]
  2 (a) shows the planar layout, FIG. 2 (b) shows a cross section in the AA ′ direction in FIG. 2 (a), and FIG. 2 (c) shows a B- Sections in the B ′ direction are shown. In FIG. 2, the same components as those in FIG. 1 are denoted by the same reference numerals.
[0061]
  In this case, the connection between the gate electrode 106 and the upper wiring (not shown) and the connection region between the gate electrode 106 and the shallow well region 104 are formed on the same contact region 120. Accordingly, the region 180 indicated by a dotted line in the drawing is not necessary, so that the element area can be reduced and the degree of integration can be improved.
[0062]
  Next, a procedure for forming the semiconductor device shown in FIG. 1 according to the first embodiment will be described with reference to FIGS.
[0063]
  4 to 11, each partial view (a) corresponds to a planar layout, and each partial view (b) is a cross-sectional view taken along the section line AA ′ of the corresponding partial view (a). c) corresponds to a cross section taken along the section line BB 'in the corresponding partial drawing (a). 4 to 11, the same components as those in FIG. 1 are denoted by the same reference numerals.
[0064]
  First, as shown in FIG. 4, an element isolation region 102 is formed in a semiconductor substrate 101 by a known method. In the first embodiment, a trench having a depth of 400 to 700 nm is formed by using STI (Shallow Trench Isolation) technology, and an element isolation region 102 is formed by embedding an oxide film in the trench. However, the method of forming the element isolation region is not limited to this method, and any method can be used as long as the shallow well region 104 can be electrically isolated for each element.
[0065]
  Next, a deep well region 103 and a shallow well region 104 are formed. In this embodiment, in order to form the deep well region 103, when manufacturing an N-channel element, the adjacent side is 5 × 10 5 with energy of about 250 KeV to 350 KeV.¹²~ 5x10¹³/ Cm²About inject. When manufacturing a P-channel device, boron is 5 × 10 5 with energy of about 170 KeV to 230 KeV.¹²~ 5x10¹³/ Cm²About inject. When an N-channel device is formed to form the shallow well region 104, boron is produced at an energy of about 20 KeV to 90 KeV and 1 × 10 10.¹²~ 1x10¹⁴/ Cm²About inject. When a P-channel device is manufactured, the adjacent side is 1 × 10 5 with energy of about 50 KeV to 220 KeV.¹²~ 1x10¹⁴/ Cm²About inject.
[0066]
  Next, as shown in FIG. 5, after the gate insulating film 105 and the gate electrode 106 are sequentially formed by a normal method, a silicon oxide film having a thickness of 2 to 10 nm is formed on the side wall of the gate electrode by a thermal oxidation method (not shown). And an active region to be a source / drain. Next, after forming an LDD (Lightly Doped Drain) region 107 and a halo region (not shown) for suppressing the short channel effect, using the same method as in forming a conventional fine transistor, A gate sidewall insulating film 108 made of a silicon nitride film covering the sidewall of the gate electrode 106 is formed. The gate electrode sidewall insulating film 108 of this embodiment is formed of a silicon nitride film, but is not limited to this, and any silicon oxide film or insulating material may be used. Further, a silicon oxide film of 10 to 30 nm may be formed before forming the silicon nitride film. In this case, if the processing of the silicon nitride film is performed under conditions that have high selectivity with respect to the silicon oxide film, the processing of the silicon nitride film is completed on the silicon oxide film, so that damage during processing is applied to the silicon substrate There is an effect that it does not occur.
[0067]
  Next, as shown in FIG. 6, the resist 140 is patterned in order to remove the gate electrode 106 on the contact region 120 that connects the gate electrode 106 and the shallow well region 104 using a known lithography technique. Next, a part of the gate electrode 106 is etched using the resist 140 as a mask. Specifically, etching was performed using a helicon type RIE apparatus under a pressure of 0.4 Pa of a mixed gas of hydrogen bromide and oxygen.
[0068]
  Next, as shown in FIG. 7, after the resist 140 (shown in FIG. 6) is removed, the resist 145 is patterned using a well-known lithography technique, and then the gate electrode 106 and the shallow well region 104 are ohmically connected. For this, ion implantation 160 of the second conductivity type impurity is performed on the contact region 120. At this time, the resist 145 is patterned so that the ion implantation 160 of the second conductivity type impurity is not doped into the gate electrode 106. Specifically, as shown in FIG. 7C, when the distance between the end 121 of the resist 145 on the contact region 120 side and the end 122 of the gate electrode 106 on the contact region 120 side is L, the minimum processing dimension is L. Patterning is performed in a range of 0 to L / 3.
[0069]
  As described above, since the gate electrode 106 is not doped with the second conductivity type impurity, during the activation annealing, the impurity is a portion 106a (shown in FIG. 1) on the channel region 130 (shown in FIG. 1) of the gate electrode 106. Diffusion to the first conductivity type impurities. Therefore, the driving force of the transistor is not reduced. In addition, since the distance between the channel end 126 (shown in FIG. 9C) and the contact region 120 can be set small, the device can be miniaturized.
[0070]
  Next, as shown in FIG. 8, after removing the resist 145 (shown in FIG. 7), the resist 150 is patterned by using a well-known lithography technique to form the high concentration source / drain regions 131 and 132 and the gate electrode 106. In order to form the first impurity type impurity ion implantation 170 of the first conductivity type. In this embodiment, the gate electrode 106 and the source / drain regions 131 and 132 (shown in FIG. 1) are doped simultaneously. Here, the resist 150 is patterned so that the first conductivity type impurity ion implantation 170 is implanted only into the channel region 130. Specifically, in consideration of the diffusion of impurities implanted into the gate electrode 106 and the source / drain regions 131 and 132 in the lateral direction during activation annealing in a later step, the channel of the transistor with respect to the longitudinal direction of the gate electrode in advance. It is desirable that ion implantation is performed inwardly in the direction of the center by about 0.1 μm to 0.3 μm.
[0071]
  Therefore, since the portions 106b and 106c (shown in FIG. 1) which are not doped with both the donor and acceptor impurities are left at both ends of the gate electrode 106, the gate electrode 106 and the source / drain regions 131, Therefore, it is possible to reduce the capacity of the unit 132. Further, since the high melting point silicide film 112 (shown in FIG. 1) formed on the gate electrode end portions 106b and 106c in a later process eliminates the influence of impurities, the gate electrode 106 doped with impurities is used. A thick film can be formed as compared with the refractory silicide film 112 on a portion 106a of the film. Therefore, when the contact holes 117 and 118 (shown in FIG. 1) and the contact hole 133 (shown in FIG. 9) are formed, the refractory silicide film 112 is etched to form the upper wiring (not shown), the gate electrode 106, and the like. Can be prevented from increasing.
[0072]
  In this embodiment, in order to form a CMOS, when a donor impurity is implanted into the source / drain and gate electrode of the N channel type device, the gate electrode of the P channel type device is connected to the shallow well region having the N conductivity type. And a step of simultaneously performing donor impurity implantation into the contact region to be performed. Further, in the present embodiment, when acceptor impurities are implanted into the source / drain and gate electrodes of the P channel type element, the gate electrode of the N channel type element is connected to the shallow well region having the conductivity type of P type. The method includes a step of simultaneously performing acceptor impurity implantation into the contact region. Therefore, an ion implantation process for connecting the gate electrode and the shallow well region can be performed without adding a new process.
[0073]
  As for the ion implantation conditions, for N-channel transistors, arsenic ions are 2 × 10 5 with an energy of about 5 KeV to 50 KeV.¹⁵~ 5x10¹⁵/ Cm²The injection amount was about. As for the P-channel transistor, boron trifluoride ions are 2 × 10 2 with an energy of about 10 KeV to 30 KeV.¹⁵~ 5x10¹⁶/ Cm²The injection amount was about. Although not shown here, a screen oxide film of 5 to 30 nm may be formed on the entire surface before impurity implantation for the purpose of removing contamination during impurity implantation.
[0074]
  Next, as shown in FIG. 9, when the resist 150 (shown in FIG. 8) is removed and then an activation annealing process is performed, the implanted impurities are activated, and the contact region 120 is fully covered. A two conductivity type diffusion layer 111 is formed, and a first conductivity type diffusion layer (106 a, 131, 132) is formed in the gate electrode 106 and the source / drain regions 131, 132. As the activation annealing treatment, a rapid heating treatment was used at a temperature of 950 ° C. to 1100 ° C. In this embodiment, the activation annealing process is performed after the donor impurity implantation and the acceptor impurity implantation are performed. However, the present invention is not limited to this, and the junction depth of the source / drain regions 131 and 132 is to be finely adjusted. May be subjected to separate activation annealing treatments for the donor impurity and the acceptor impurity. Next, a refractory silicide film 112 is formed on the gate electrode 106, the active layers of the source / drain regions 131 and 132, and the contact region 120 by a known salicide process. As the high melting point material, titanium, cobalt, nickel, platinum, tantalum, or the like may be used.
[0075]
  Next, a silicon oxide film 114 and a silicon oxide film 114 are sequentially formed as a first interlayer insulating film by using a CVD method. Here, the thickness of the laminated film of the silicon nitride film 113 and the silicon oxide film 114 is set to be smaller than the thickness of the gate electrode 106. Next, the silicon oxide film 114 and silicon in a desired region where the contact conductor 115 (shown in FIG. 1) and the source / drain conductor 155 (shown in FIG. 1) are to be formed are formed using known lithography and processing techniques. When the nitride film 113 is removed, a contact hole 133 for burying the contact conductor 115 and a contact hole 134 for burying the source / drain conductor 155 are formed.
[0076]
  Here, the meaning of using the silicon nitride film 113 will be described.
[0077]
  The silicon nitride film 113 is used as a stopper when the silicon oxide film 114 is etched. When etching the silicon oxide film 114, a condition having a large selection ratio with respect to the underlying silicon nitride film 113 is used. When etching the silicon nitride film 113, a condition having a large selection ratio with respect to the silicon oxide film in the element isolation region Is used. By performing etching under such conditions, the contact conductor 115 and the source / drain conductor 155 are not etched without the silicon oxide film in the element isolation region 102 being etched and reduced, that is, without deteriorating element characteristics. The region for forming can be etched. When the silicon oxide film 114 is etched, a condition including a certain amount of overetching (specifically, about 30% of the etching amount) is generally taken into consideration in terms of film thickness variation and etching rate variation. Done under. Therefore, when the silicon nitride film 113 is not present, the silicon oxide film in the element isolation region made of the same material as the silicon oxide film 114 is significantly etched.
[0078]
  Thus, the silicon nitride film 113 has a function of preventing the silicon oxide film in the element isolation region from being etched. This is particularly effective when the first interlayer insulating film having a large overetching amount is thick. Although not shown, the contact holes 117 and 118 (shown in FIG. 1) protrude from the contact conductor 115 (shown in FIG. 1) and the source / drain conductor 155 (shown in FIG. 1). Even in this case, the etching of the contact holes 117 and 118 stops at the silicon nitride film 113 and the silicon oxide film in the element isolation region 102 is not etched. Therefore, it is possible to prevent deterioration of the characteristics of the element.
[0079]
  In the first embodiment, the silicon nitride film 113 is used as an etching stopper. However, when the film thickness of the silicon oxide film 114 is small, the overetch amount of the silicon oxide film 114, that is, the silicon oxide film in the element isolation region 102 is used. As long as the etching conditions of the silicon oxide film 114 can be set so that the etching amount is within an allowable range with respect to device characteristics, the silicon nitride film 113 may not be used.
[0080]
  Next, regions (contact holes 133 and 134) where the contact conductor 115 and the source / drain conductor 155 are formed will be described.
[0081]
  First, in the contact region 120, a region (contact hole 133) in which the contact conductor 115 for connecting the gate electrode 106 and the shallow well region 104 is formed will be described. As described above with reference to FIG. 12, the contact hole 133 is formed so as to straddle the gate electrode 106 and the contact region 120. Specifically, the contact hole 133 has a width (Wpl) of 4 L / 3 with respect to the longitudinal direction of the gate electrode, and the center of the contact hole 133 coincides with the gate electrode end 122. The width Wpl is preferably smaller than 2L. This is because if it is made too large, the element dimension in the longitudinal direction of the gate electrode becomes remarkably large. The width of the contact hole 133 in the direction perpendicular to the longitudinal direction of the gate electrode is preferably as large as the layout allows, but it is desirable that the contact hole 133 is designed to have a minimum processing dimension L for the purpose of obtaining a fine element.
[0082]
  On the other hand, the contact hole 134 formed in the source / drain regions 131 and 132 has a distance (Sgpl) between the gate electrode end 124 and the contact hole end 123 of 2/3 / L / L as shown in FIG. 3 from the position in the range 3 to the element isolation region 102.
[0083]
  The depth of the contact holes 133 and 134 (corresponding to the total film thickness of the silicon nitride film 113 and the silicon oxide film 114) is set to be smaller than the thickness of the gate electrode 106. Therefore, since the facing area between the gate electrode 106 and the source / drain conductor 155 is reduced, the capacitance between the gate electrode 106 and the source / drain electrode can be reduced.
[0084]
  Next, as shown in FIG. 10, after the conductor is formed, the contact conductor 115 and the source / drain conductor 155 are embedded in the contact holes 133 and 134 (shown in FIG. 9) by etching back, respectively. The In this embodiment, the contact conductor 115 and the source / drain conductor 155 are composed of a laminated film of a titanium film, a titanium nitride film, and a tungsten film. The titanium film and the titanium nitride film were formed by physical sputtering. The tungsten film was formed by a CVD method. A tungsten film formed by CVD is excellent in step coverage. For this reason, even if the high melting point silicide film 112 is disconnected in the contact region 120, the gate electrode 106 and the shallow well region 104 can be reliably connected by the tungsten film.
[0085]
  Both the contact conductor 115 and the source / drain conductor 155 are formed using an apparatus conventionally used in a production line. Therefore, it is not necessary to use a special process apparatus, and the cost does not increase. Here, the conductor is not limited to this, but it may be a refractory metal because a second interlayer insulating film may be formed in a later step and annealed for planarization. preferable.
[0086]
  Next, as shown in FIG. 11, after the second interlayer insulating film 116 is formed by a known method, contact holes 117 and 118 are opened at predetermined positions of the interlayer insulating film 116. After the contact process, the wiring process may be performed using a known method. When the contact hole 117 is formed on the source / drain regions 131 and 132, it is necessary to form the contact hole 117 directly on the refractory silicide film 112 which is an active region in the conventional example. However, in the present embodiment, the contact hole 117 may be formed on the conductor 115 formed on the source / drain regions 131 and 132 and the element isolation region 102 and on the element isolation region 102 side. The degree of freedom of wiring (not shown) formed thereon can be increased. Therefore, an integrated circuit with a small element area can be designed by laying out various contact conductors 115 and source / drain conductors 155 by the integrated circuit. Further, since the contact hole 117 does not need to be in direct contact with the refractory silicide film 112, the area of the source / drain active region can be reduced. Therefore, the junction capacitance of the source / drain regions 131 and 132 can be reduced.
[0087]
  In particular, since the DTMOS has the gate electrode 106 and the shallow well region 104 connected, the ratio of the junction capacitance to the total capacitance of the transistor is larger than that of a conventional MOS transistor in which the gate electrode and the well region are not connected. . For this reason, it is very important to reduce the junction capacitance. Further, since the source / drain conductor 155 is sufficiently separated from the gate electrode 106, the gate electrode 106 and the source / drain regions 131 and 132 are compared with the semiconductor device (Japanese Patent Laid-Open No. 2000-82815) shown in FIG. There is an effect that the capacity can be reduced.
[0088]
(Second Embodiment)
  The second embodiment provides an effect that the element area can be reduced when the semiconductor device of the first embodiment is adapted to a series transistor.
[0089]
  The configuration of the semiconductor device according to the second embodiment will be described with reference to FIG.
[0090]
  3A shows a cross-sectional view perpendicular to the longitudinal direction of the gate electrode of the semiconductor device of the present embodiment, and FIG. 3B shows the longitudinal direction of the gate electrode of the conventional semiconductor device. A cross-sectional view in the perpendicular direction is shown. In FIG. 3B, the same components as those in FIG. 19 are denoted by the same reference numerals.
[0091]
  First, in the conventional semiconductor device shown in FIG. 3B, the adjacent source / drain regions 307 and 307 are connected to each other by the contact plug 330 and the metal wiring 331. Therefore, as shown in FIG. 3B, the distance between the gate electrodes 306 of adjacent transistors needs to be 7L (= 3L + L + 3L).
[0092]
  However, in the semiconductor device of the present invention, as shown in FIG. 3A, the source / drain regions 131 and 132 of adjacent transistors are connected by a source / drain conductor 155. Therefore, the distance between the gate electrodes of adjacent transistors can be reduced to 11 L / 3 (= 4 L / 3 + L + 4 L / 3). For this reason, the area occupied by the element can be drastically reduced. In addition, since the upper wiring is not used to connect the source / drain regions 131 and 132 of the adjacent transistors, the degree of freedom of the upper wiring (not shown) can be greatly improved.
[0093]
(Third embodiment)
  The third embodiment provides a forming procedure in which the mask for forming a contact region for connecting the gate electrode and the shallow well is reduced as compared with the forming procedure of the semiconductor device of the first embodiment. is there.
[0094]
  A procedure for forming the semiconductor device according to the third embodiment will be described with reference to FIGS. 14 to 18, each partial view (a) corresponds to a planar layout, and each partial view (b) is a cross-sectional view taken along the section line AA ′ of the corresponding partial view (a). c) corresponds to a cross section taken along the section line BB 'in the corresponding partial drawing (a). Since the procedure before the formation of the gate electrode is the same as that in the first embodiment, it is omitted. 14 to 18, the same components as those in FIG. 1 are denoted by the same reference numerals.
[0095]
  First, although not shown, the element isolation region 102, the deep well region 103, and the shallow well region 104 are formed in the semiconductor substrate 101 in the same manner as the semiconductor device formation procedure of the first embodiment.
[0096]
  Next, as shown in FIG. 14, after the gate insulating film 105 and the gate electrode 106 are sequentially formed by a normal method, a silicon oxide film having a thickness of 2 to 10 nm is formed by a thermal oxidation method, although not shown. It is formed in the active region which becomes the side wall and the source / drain. At this time, the patterning of the gate electrode is performed so that the active layer of the contact region 120 is exposed, unlike the first embodiment. Next, the LDD region 107 and a halo region (not shown) for suppressing the short channel effect are formed using a method similar to that used for forming a conventional fine transistor, and then the sidewall of the gate electrode 106 is formed. Then, a gate sidewall insulating film 108 made of a silicon nitride film is formed.
[0097]
  Next, as shown in FIG. 15, as in the first embodiment, the second conductivity type diffusion layer 111 having a high impurity concentration for ohmically connecting the shallow well region 104 and the refractory silicide film 112, and the first The conductive type high concentration source / drain regions 131 and 132 and the gate electrode 106 are formed by ion-implanting each and then annealing. Next, a refractory silicide film 112 is formed on the gate electrode 106, the active layers of the source / drain regions 131 and 132, and the contact region 120 by a known salicide process. Next, a silicon oxide film 114 and a silicon oxide film 114 are sequentially formed as a first interlayer insulating film by using a CVD method. Next, the regions of the silicon oxide film 114 and the silicon nitride film 113 in the contact holes 134 and 133 in which the conductor is deposited are removed using a known lithography technique and processing technique.
[0098]
  Next, as shown in FIG. 16, after the conductor is deposited on the entire surface, the contact conductor 115 and the source / drain conductor 155 are etched so as to be embedded in the contact holes 133 and 134 (shown in FIG. 15), respectively. The contact conductor 115 and the source / drain conductor 155 are formed by adjusting the back conditions.
[0099]
  Next, as shown in FIG. 17, after forming a second interlayer insulating film 116 by a well-known method, contact holes 117 and 118 are opened at predetermined positions of the interlayer insulating film 116.
[0100]
  Next, as shown in FIG. 18, the contact metal plug 190 and the upper wiring 191 are formed to complete the semiconductor device of the third embodiment.
[0101]
  As described above, according to the formation procedure of the semiconductor device of the third embodiment, the semiconductor device of the present embodiment has a gate electrode sidewall insulating film at the gate electrode end on the contact region 120 side, as shown in FIG. Since 108 is formed, the element dimension in the longitudinal direction of the gate electrode is increased by the width of the gate electrode sidewall insulating film as compared with the semiconductor device of the first embodiment. Further, since the refractory silicide film 112 is insulated by the gate electrode sidewall insulating film, the refractory silicide film 112 cannot connect the gate electrode 106 and the shallow well region 104. However, in the third embodiment, a mask used in the step of forming the contact region 120 for connecting the gate electrode 106 and the shallow well region 104 (corresponding to FIG. 6 in the first embodiment) is not necessary. Therefore, the cost can be reduced.
[0102]
  Further, as described in the semiconductor device of the first embodiment, as shown in FIG. 21B, the connection between the gate electrode 106 and the shallow well region 104 can be made by using only the contact conductor 115 without using the upper wiring 191. It is realized by using. Therefore, as shown in FIG. 18, the upper wiring 191 can be freely laid out on the contact region 120 for other wiring. Therefore, the degree of freedom in designing the upper wiring can be improved, and the element can be miniaturized. In addition, since a refractory metal is used for the contact conductor 115, only one mask for forming the contact conductor 115 is added to the process of a transistor having a normal structure that is not a DTMOS, thereby deteriorating the production efficiency of the mass production line. The semiconductor device of the present invention can be formed without any problem. Therefore, it can be easily mounted on the same chip as a transistor having a normal structure. Therefore, a system LSI can be easily realized.
[0103]
【The invention's effect】
  As apparent from the above, according to the semiconductor device and the manufacturing method thereof of the present invention, the DTMOS transistor can be formed with good controllability by reliably connecting the gate electrode and the shallow well. Further, the design freedom of the upper wiring can be increased without increasing the element area, and the capacitance associated with the gate electrode and the source / drain region can be reduced.
[Brief description of the drawings]
FIGS. 1A, 1B and 1C are diagrams illustrating a semiconductor device according to a first embodiment of the present invention.
FIGS. 2A, 2B, and 2C are diagrams illustrating the semiconductor device. FIG.
FIGS. 3A and 3B are diagrams for explaining a semiconductor device according to a second embodiment of the present invention in comparison with a conventional example.
FIGS. 4A, 4B, and 4C are views for explaining a procedure for manufacturing the semiconductor device according to the first embodiment of the present invention.
FIGS. 5A, 5B, and 5C are diagrams illustrating a procedure for manufacturing the semiconductor device. FIG.
FIGS. 6A, 6B, and 6C are diagrams illustrating a procedure for manufacturing the semiconductor device.
FIGS. 7A, 7B, and 7C are diagrams illustrating a procedure for manufacturing the semiconductor device. FIG.
FIGS. 8A, 8B, and 8C are diagrams illustrating a procedure for manufacturing the semiconductor device.
FIGS. 9A, 9B, and 9C are diagrams illustrating a procedure for manufacturing the semiconductor device.
FIGS. 10A, 10B, and 10C are diagrams illustrating the semiconductor device and a procedure for manufacturing the semiconductor device. FIGS.
FIGS. 11A, 11B, and 11C are diagrams illustrating the semiconductor device and a procedure for manufacturing the semiconductor device. FIGS.
FIGS. 12A and 12B are diagrams for explaining a position where a conductor formed on a contact region in the semiconductor device is formed.
FIGS. 13A and 13B are diagrams illustrating positions where conductors formed on the source / drain regions in the semiconductor device are formed.
FIGS. 14A, 14B, and 14C are diagrams illustrating a semiconductor device according to a third embodiment of the present invention and a procedure for manufacturing the semiconductor device.
FIGS. 15A, 15B, and 15C are diagrams illustrating the semiconductor device and a procedure for manufacturing the semiconductor device. FIGS.
FIGS. 16A, 16B, and 16C are diagrams illustrating the semiconductor device and a procedure for manufacturing the semiconductor device. FIGS.
FIGS. 17A, 17B, and 17C are diagrams illustrating the semiconductor device and a procedure for manufacturing the semiconductor device.
FIGS. 18A, 18B, and 18C are diagrams illustrating the semiconductor device and a procedure for manufacturing the semiconductor device.
FIGS. 19A, 19B, and 19C are diagrams illustrating a conventional semiconductor device. FIGS.
20A and 20B are diagrams illustrating a conventional semiconductor device.
FIGS. 21A and 21B are diagrams for explaining a conventional problem.
[Explanation of symbols]
101 Silicon semiconductor substrate
102 Silicon oxide film
103 First conductivity type deep well
104 Shallow well of the second conductivity type
105 Gate insulation film
106 Gate electrode
107 LDD region
108,113 Silicon nitride film
110 High concentration layer of gate electrode doped in first conductivity type
111 High-concentration diffusion layer doped to second conductivity type
112 High melting point silicide film
113 Silicon nitride film
114 Silicon oxide film
115 Conductor
116 Interlayer insulation film
117,118,119 Contact hole
120 Contact region for connecting a gate electrode and a shallow well of the second conductivity type
130 channel region
131,132 Source / drain regions
140,145,150 resist
160 Second implantation type high concentration impurity ion implantation
170 Ion implantation of first conductivity type high concentration impurity

Claims (5)

A semiconductor substrate;
A first well type deep well region formed in the semiconductor substrate;
A second well-type shallow well region formed in the first well-type deep well region and separated by an element isolation region;
A gate insulating film formed on the second well-type shallow well region;
A gate electrode formed on the gate insulating film;
A contact region formed in the vicinity of an end of the gate electrode of the shallow well region of the second conductivity type;
A contact conductor formed to connect the gate electrode and the contact region across a step at the end of the gate electrode;
A source / drain formed on a region straddling the source / drain region of the shallow well region of the second conductivity type and the upper part of the element isolation region, and at a position away from the gate electrode above the semiconductor substrate surface With a conductor,
When the minimum processing dimension is L and the width of the contact conductor in the direction across the step of the gate electrode is Wpl,
4L / 3 ≤ Wpl ≤ 2L
While satisfying the conditions of
If the shortest distance between the gate electrode and the source / drain conductor is Sgppl,
L / 3 ≦ Sgppl ≦ 2L / 3
A semiconductor device characterized by satisfying the following condition . The semiconductor device according to claim 1 ,
A semiconductor device, wherein the source / drain conductor is thinner than the gate electrode. The semiconductor device according to claim 1 ,
The semiconductor device according to claim 1, wherein the source / drain conductors are formed in two or more locations in each of the source / drain regions. Forming a first conductivity type deep well region in a semiconductor substrate;
Forming an isolation region shallower than the deep well region of the first conductivity type so as to partition the surface of the semiconductor substrate;
Forming a shallow well region of a second conductivity type shallower than the element isolation region in a state partitioned by the element isolation region;
Sequentially forming a gate insulating film, a gate electrode extending in one direction, and a gate electrode side wall insulating film covering the side wall of the gate electrode on the shallow well region of the second conductivity type;
Removing the gate insulating film and part of the gate electrode on the second conductivity type shallow well region to form a contact region in the vicinity of the end of the gate electrode in the second conductivity type shallow well region; When,
Forming an interlayer insulating film over the entire surface of the substrate after forming the contact region;
Removing a region of the interlayer insulating film on a region straddling the step at the end of the gate electrode to form a first removal region;
Removing a region of the interlayer insulating film on a region straddling the source / drain region of the second conductivity type shallow well region and the element isolation region to form a second removal region;
And a step of embedding a conductor in the first removal region and the second removal region. The semiconductor device according to claim 4 ,
Sequentially forming a gate insulating film, a gate electrode extending in one direction, and a gate electrode side wall insulating film covering the side wall of the gate electrode on the shallow well region of the second conductivity type;
The gate insulating film and a part of the gate electrode on the second conductivity type shallow well region are removed to form a contact region for connecting the gate electrode and the second conductivity type shallow well. A method of manufacturing a semiconductor device, wherein the steps are performed simultaneously.

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