JP3910301B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a large-scale integrated semiconductor device and a manufacturing method thereof.
[0002]
[Prior art]
In order to realize a high-speed and high-performance semiconductor device, demands for miniaturization of individual semiconductor elements used in the semiconductor device and large-scale integration thereof are increasing over time. However, considering the miniaturization of MOSFETs, which are the main components of these semiconductor elements, this involves various difficulties.
[0003]
For example, the formation of element isolation to electrically insulate minute semiconductor elements must be achieved with a shorter distance for high density integration of elements. However, in the LOCOS method in which the surface of the semiconductor substrate to be isolated is thermally oxidized to form an element isolation oxide film, a Birds beak phenomenon occurs in which the periphery of the element isolation oxide film protrudes into the element region, reducing the effective element region. There is a problem that fine separation between elements cannot be performed.
[0004]
Therefore, a shallow trench having a depth required for element isolation is formed in the element isolation scheduled region, and then a silicon oxide film is formed in this groove by using chemical vapor deposition (CVD) or the like. Shallow Trench Isolation (STI) has been developed, in which an insulating material such as the above is formed to fill this groove, and further planarize the main surface of the semiconductor substrate to isolate the element.
[0005]
On the other hand, a short channel effect is known in which the threshold voltage decreases as the channel length (gate electrode length) of the MOSFET decreases. In this short channel effect, the threshold voltage greatly depends on the processing dimension of the gate electrode. Therefore, if the processing dimension is small, it is impossible to obtain an element having the intended characteristics even with a slight processing shift. This is extremely inconvenient for manufacturing a semiconductor circuit that requires a large number of uniform elements, for example, a dynamic random access memory (DRAM).
[0006]
Such a short channel effect is caused by the fact that the distortion of the electric field at the source and drain electrode portions of the MOSFET affects the channel portion as the channel length decreases. In order to suppress this effect, it is known that the impurity concentration in the channel portion may be increased. However, if the impurity concentration in the channel portion is increased, the electric capacity between the substrate, the source and the drain electrode increases, and Impedes high-speed operation. In order to solve such a problem, a technique (Silicon On Insulator, SOI) for forming a semiconductor element on a thin silicon layer formed on an insulating film has been developed.
[0007]
The short channel effect can also be avoided by bringing the junction position of the Pn-junction forming the source and drain closer to the semiconductor surface (that is, making the Pn-junction shallow). However, if the Pn− junction is made shallower, the resistance of the source and drain electrodes formed thereby increases, which impedes high-speed transmission of signals transmitted through the device. Furthermore, if the junction is shallow, if a contact for obtaining electrical contact is provided at this portion, the metallic material constituting the contact may diffuse downward and penetrate the junction, possibly inducing junction leakage. .
In order to deal with such problems, a semiconductor material is selectively formed on the surface portion of the semiconductor substrate where the source and drain electrodes are to be formed, and the surface of this region is the original semiconductor surface (surface on which the channel is formed). By moving further upward and forming the Pn-junction of the source and drain through this additional formed surface, the position of the junction is shallow with respect to the original semiconductor surface (surface on which the channel is formed), however, Thus, a method (Elevated source drain method) of ensuring the thickness of the electrode portion (diffusion layer thickness) for forming the source and drain has been used. .
[0008]
[Problems to be solved by the invention]
The above-described element isolation by STI and the elevated source drain structure have the following problems.
First, in an STI structure element, a silicon oxide film formed by CVD or the like is used for embedding a shallow trench. However, since its density is lower than that of the thermal oxide film used in LOCOS, this CVD insulating film is liable to undergo a volume change in the subsequent thermal process, and as a result, a large stress is concentrated on a part of the shallow trench, particularly on the bottom corner. To do. Due to the large stress remaining at the bottom corners, dislocations frequently occur, and when this crosses the pn junction formed in the vicinity thereof, there arises a problem that severe junction leakage occurs. When current leaks through the pn junction, the operation of the element is impaired, and in a storage element such as a DRAM, written information is lost, and the original function of the semiconductor device is lost.
[0009]
Next, in an Elevated Source Drain structure device, an epitaxial growth technique is used, but this method is very sensitive to a surface state where selective growth is performed. For example, a crystal defect with a disordered crystal structure remains in the source and drain regions due to a natural oxide film on the substrate surface immediately before growth or damage introduced during processing of the gate electrode. Such disorder of the crystal structure becomes a nucleus of dislocation generation, and there arises a problem that severe junction leakage occurs when the generated dislocation crosses the pn junction constituting the source and drain. When current leaks through the junction, the operation of the element is impaired, and in a storage element such as a DRAM, written information is lost, and the original function of the semiconductor device is lost.
[0010]
The present invention eliminates the disadvantages of the prior art as described above, suppresses the occurrence of dislocations from the shallow trench corner and the interface between the additionally formed silicon layer and the substrate, and improves the yield of the semiconductor device manufacturing process. An object of the present invention is to provide a semiconductor device with a reduced manufacturing cost and a manufacturing method thereof.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, the present invention selectively introduces oxygen atoms or nitrogen atoms only in the vicinity of sites where dislocations are likely to occur, such as the STI corner portion or the interface between the formed silicon layer and the substrate. Provided are a semiconductor device that suppresses generation and propagation thereof, and a manufacturing method thereof.
[0012]
That is, the present invention provides a semiconductor region, a shallow trench corner, a channel region present in the semiconductor region, a source and drain region present in the semiconductor region, and the source and drain regions in the semiconductor region. A pn junction surface to be formed, and a dislocation propagation blocking region present in the source or drain region between the shallow trench corner and the pn junction surface and containing oxygen or nitrogen at a higher concentration than the channel region. A semiconductor device is provided.
[0014]
In addition, the present invention provides that the shallow region of the source or drain region is implanted immediately after the shallow trench is formed by implanting oxygen or nitrogen atoms so as to have a specific depression angle with respect to the substrate perpendicular to the channel width direction of the element region. Provided is a method for manufacturing a semiconductor device, wherein oxygen atoms or nitrogen atoms are selectively introduced only into trench corners.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
The present invention is described in detail below.
According to the present invention, since oxygen atoms or nitrogen atoms are present in the vicinity of the dislocation generation region, oxygen or nitrogen atoms are actively incorporated into the dislocation nuclei and change the structure of the dislocation nuclei, thereby inhibiting dislocation movement. Therefore, by introducing oxygen or nitrogen atoms selectively only in the vicinity of sites where dislocations are likely to occur, such as STI corners and the interface between the formed silicon layer and the substrate, the generated dislocations do not move over a long distance. Stay in the vicinity where it occurred. Therefore, even if dislocation occurs, this does not cross the pn junction portion, so that the electrical characteristics of the device are not affected. In particular, since oxygen diffuses quickly in silicon, dislocation immobilization can be effectively achieved even in a low temperature thermal process.
[0017]
In addition, according to the present invention, oxygen atoms are selectively introduced while avoiding the pn junction portion, so that precipitates derived from oxygen atoms are not formed on the junction surface. For this reason, there is no electrical influence on the bonding of oxygen atoms. Therefore, even if there is a site where dislocations are likely to occur, it is possible to avoid the influence on the electrical characteristics of the element due to the transition without high-temperature heat treatment, improving the yield of the semiconductor device manufacturing process and reducing the manufacturing cost. A method for manufacturing a semiconductor device is achieved.
[0018]
Next, a process for manufacturing the STI-isolated trench type DRAM formed on the SOI wafer according to the present invention with high yield will be described.
First, as shown in FIG. 1, an n-type silicon semiconductor lower substrate 1100, a silicon oxide film layer 1102 formed on the n-type silicon semiconductor lower substrate, and an upper silicon layer 1101 formed on the silicon oxide film layer 1102 A substrate on which is formed is prepared. A pad silicon nitride film layer 1103 is formed on the substrate, and a trench 1201 is formed from the pad silicon nitride film layer 1103 and the upper silicon layer 1101 through the silicon oxide film layer 1102 to the lower silicon substrate 1100.
[0019]
The trench 1201 is formed by an RIE process, and forms a capacitor insulating film 1202 formed on the inner wall of the n-type silicon semiconductor lower substrate 1100 and a node filling the inside of the trench 1201 up to the surface of the upper silicon layer 1101 by a CVD process and a CMP process. An n-type polysilicon 1203 is formed to form a deep trench for deepening electric charges, Deep Trench (DT).
[0020]
Further, the oxygen concentration of the upper silicon layer 1101 is 10 by heat treatment during the wafer manufacturing process.¹⁶cm^-3It has fallen to the extent. The n-type polysilicon layer 1203, the insulating film 1202, and the n-type silicon semiconductor lower substrate 1100 constitute a DRAM charge storage capacitor.
[0021]
Next, as shown in FIG. 2, in order to achieve STI, an element region 1301 in which an access MOSFET is to be formed on the semiconductor main surface by an effective method among known techniques such as a Lithography process and an RIE process. Then, shallow trenches 1311, 1312 are formed surrounding the trench.
[0022]
Next, as shown in FIG. 3, ion implantation of oxygen atoms adjusted to have a specific depression angle with respect to the substrate perpendicular to the channel width direction (perpendicular to the paper surface) of the element region 1301 is performed. At this time, it is desirable to perform ion implantation from two directions a and b so that oxygen atoms are similarly implanted into the source 1302 and drain 1303 regions of the access MOSFET. In some cases, oxygen atoms may be implanted only into the drain 1303 region (side connected to the node polysilicon 1203, direction b).
At this time, the oxygen atom concentration is 1 × 10 at shallow trench corners 1321 and 1322.¹⁷cm^-3-1 x 10¹⁸cm^-3  It is desirable that the range is adjusted. In general, since the channel directions of the respective cells of the DRAM are parallel to each other, such oblique ion implantation can effectively introduce oxygen atoms only into the shallow trench corners 1321 and 1322 of the source 1302 and drain 1303 regions. .
[0023]
Further, since the upper surface of the element region 1301 is protected by the pad silicon nitride film layer 1103, oxygen atoms are not introduced into the channel region 1304. Therefore, by avoiding the high-temperature heat treatment, the influence of oxygen atoms does not reach the channel portion and is limited to the shallow trench corner portions 1321 and 1322 in the source 1302 and drain 1303 regions. Such a process can be performed without adding any new process such as a Lithography process other than ion implantation.
[0024]
Next, as shown in FIG. 4, the shallow trenches 1311 and 1312 are filled with an insulating material 1311.1332 such as a silicon oxide film by an effective method among known techniques such as a CVD method and a CMP method. The gate insulating film 1305 is planarized by using the pad silicon nitride film layer 1103 and the like, and the gate insulating film 1305 is formed by an effective method among known techniques such as thermal oxidation or CVD. Thereafter, the gate electrode 1306 is further effective from known techniques such as CVD and RIE, and the source electrode 1307 and drain electrode are further effective from known techniques such as ion implantation and RTA. 1308 is configured. The drain electrode and the n-type polysilicon layer 1203 are electrically connected to achieve a buried strap structure.
[0025]
Subsequently, after depositing a low dielectric constant insulating film as an interlayer film by, for example, a CVD method, a contact hole to the source electrode is formed by, for example, RIE technology, and a wiring material substance such as Al is further deposited. Then, a wiring is formed in a necessary shape using an RIE method or the like, and further, a trench type SOI-DRAM semiconductor device separated by STI is completed through a wiring process, a mounting process, and the like using a known technique.
[0026]
Although the above embodiment has been described by taking an SOI substrate as an example, it goes without saying that it can be applied to HAI substrates and Epi substrates. Instead of oxygen atoms, nitrogen atoms may be introduced. The same method can be applied when the element isolation is LOCOS.
[0027]
Next, a process of manufacturing a salicide COMS type Elevated source drain MOSFET structure having a local wiring between the source and drain electrodes of the present invention with high yield will be described.
[0028]
First, as shown in FIG. 5, a silicon semiconductor substrate 100, a region (p-well) 101 into which a p-type impurity is introduced, a region (n) into which an n-type impurity is introduced (n -well) 102, shallow trenches 111, 112, 113 formed on the surface thereof, and an insulating material such as a silicon oxide film 1200 that fills the substrate surface, and a gate insulating film 211 formed on the surface thereof. , 212 are prepared.
[0029]
The semiconductor substrate provided with this element isolation region is known in the Lithography process, RIE process, insulating film deposition by CVD (chemical vapor deposition) method, planarization by CMP (chemical mechanical polishing) method, ion implantation technique, etc. It can be achieved by an effective method of technology. In addition, these gate insulating films use an effective method of a known technique such as thermal nitridation or a JVD (Jet Vapor Deposition) method by forming a 50 angstrom thin silicon nitride film 1201 on the surface of the silicon substrate 100. Then, the portions other than those corresponding to 211, 212, 111, 112, and 113 are covered with a mask material using a Lithography method, for example, a thin silicon oxide film of 100 angstroms, and the exposed portions are heated with, for example, heated phosphoric acid. (H_Three PO_Four It can be achieved by exposing to a solution and selectively removing it, and further removing the thin oxide film as a mask material by exposing it to an HF solution. At this time, the end of the gate insulating film may be in a region corresponding to the gap between the gate electrode and the source and drain electrodes to be additionally formed thereafter. This is because the insulating film protruding from the gate electrode can be easily removed after forming the gate electrode and the source and drain additional electrodes. Therefore, the alignment accuracy of the lithography process necessary for forming the gate insulating film in advance is about the width of the source-drain and extension portions, and can be easily realized. Since the surface of the silicon substrate 100 forms a defect-free layer (DZ layer), the oxygen concentration is extremely low (10¹⁶cm^-3degree).
[0030]
Next, as shown in FIG. 6, a gate electrode constituent material 300 formed on one surface of the substrate, a region 301 into which an n-type impurity is introduced, and a region 302 into which a p-type impurity is introduced are included. Form. These gate electrode constituent materials 300 are formed on the surface of the silicon substrate 100 on the substrate, for example, by using an effective method of a known technique such as a CVD method. 2000 angstroms, and then a mask material such as a photo-resist is formed by the Lithography method, and n-type impurities and p-type impurities are selectively ion-implanted into the regions 301 and 302, respectively. it can. The energy for ion implantation is adjusted so that impurities are introduced into the polysilicon layer almost uniformly. Since the CVD method is used, the selectivity required for the epitaxial growth technique is not necessary. At this time, the amount of oxygen mixed in the polysilicon layer is minimized (10¹⁶cm^-3  (Following) For this reason, it becomes easy to form a uniform and uniform silicon layer, and there is no variation in the film thickness of the additional source and drain formation portions found in the epitaxial growth technique. As a result, when the junction for forming the source and drain is introduced from the additionally formed silicon surface to form the junction, the junction can be accurately formed at the target position.
[0031]
Next, as shown in FIG. 7, oxygen atoms are further introduced into the polysilicon upper layer portion 1000 using, for example, an ion implantation method. Alternatively, a polysilicon layer containing a large amount of oxygen may be further deposited. The introduction depth of the oxygen atoms is adjusted so that, after that, the heat treatment reaches the interface between the additional silicon layer and the substrate silicon, but the precipitation of oxygen atoms does not occur at the pn junction where p / n impurities are formed on the substrate. Since diffusion of oxygen atoms is faster than that of B and P, it is desirable to introduce oxygen only into the upper portion. As a result, oxygen atoms are introduced into the interface that can become the nucleus of the transition, and the occurrence and propagation of the transition are suppressed, and the pn junction is not affected by oxygen precipitation or the like. Such a process can be carried out without adding any new process such as a Lithography process other than ion implantation or CVD process.
[0032]
Next, as shown in FIG. 8, through the RIE process, gate electrodes 311 and 312 formed on the p-well, 101, n-well, and 102, and additionally formed on the source and drain regions, respectively. Silicon layers 411, 412 and 413 are formed. Since the gate layers 311, 312 and the silicon layers 411, 412 and 413 additionally formed on the source and drain regions can be formed at a time, the Elevated Source / Drain structure can be achieved. For this reason, it should be noted that the manufacturing cost can be reduced. At this time, the end of the gate insulating film may be in a region corresponding to the gaps 511, 512, 513, 514 between the gate electrodes 311, 312 and the additionally formed silicon layers 411, 412, 413. The additionally formed silicon layers 411, 412, and 413 extend to the element isolation regions 111, 112, and 113, and reduce the capacitance of the source and drain electrodes and the semiconductor substrate. Further, the additionally formed silicon layer 412 connects the p-well, 101, n-well, and 102 regions. As a result, not only the additional formation of the source and drain electrodes, but also a local inter-element wiring process can be simultaneously formed by this silicon layer. Therefore, a new local element wiring process is not required, and the manufacturing cost can be reduced.
[0033]
Thereafter, the substrate is heat-treated to diffuse impurities introduced into the silicon layers 411, 412, and 413 from the portion where the silicon layers 411, 412, 413 and the semiconductor substrate 100 are in contact with each other. Simultaneously with the formation of 611, 612, 613, and 614, the conductive impurities in the gate electrodes 311 and 312 and the silicon layers 411, 412, and 413 are activated. At this time, the diffusion process is adjusted so that oxygen atoms reach the additional silicon layer-substrate silicon interface but do not reach the pn junction surface. Oxygen atoms are introduced into the interface that can be the nucleus of the transition, suppressing the generation and propagation of the transition, and without affecting the pn junction. The oxygen concentration at this time is 1 × 10 at the additional silicon layer-substrate silicon interface.¹⁷cm-1 × 10¹⁸cm^-3If it is in the range, it is preferable.
[0034]
Next, as shown in FIG. 9, the gate insulating film remaining in the gaps 511, 512, 513, 514 is removed by, for example, a heated phosphoric acid (H 3 PO 4) solution, and further added to the gate electrode 311.312. N-type and p-type impurities are ion-implanted into the gaps 511, 512, and 513, 514, respectively, using the formed silicon layers 411, 412, 413 and the photo-resist formed by the lithography process as a mask. Further, for example, by subjecting this to a rapid raising / lowering heat treatment, the impurities are activated and source-drain extension portions 711, 712, 713, 714 are formed. Needless to say, the formation of the shallow source-drain extension can be achieved by an effective method of a known technique such as plasma immersion doping, gas impulse laser dopong, etc. in addition to the ion implantation technique.
[0035]
Next, as shown in FIG. 10, for example, a silicon oxide film is deposited by 2000 A by CVD, and then planarized by CMP to form gaps 511, 512, 513, and 514 with a low dielectric constant insulating film. Fill with 811,812,813,814. At this time, the heights of the electrodes of the gate electrodes 311 and 312 and the additionally formed silicon layers 411, 412 and 413 are uniform. Therefore, it is very easy to flatten the surface. Subsequently, a metal that selectively reacts with silicon, such as Co, is deposited on the entire surface by sputtering, and then subjected to a heat treatment, for example, a rapid thermal treatment (RTA) at 500 ° C. in a nitrogen atmosphere. By applying, silicidation is selectively advanced on the contact surfaces with silicon, that is, the gate electrodes 311 and 312 and the additionally formed silicon layers 411, 412 and 413, and the unreacted metal is converted into a solution such as HNO3. The silicide layers 901, 902, 903, 904, and 905 are formed on the gate, source, and drain in a self-aligned manner by processing and removing with the above. In this way, a salicide structure can be realized.
[0036]
Since the additionally formed source and drain electrodes are silicided, metal atoms diffuse in the source and drain and do not easily reach the junction. Therefore, junction leakage can be prevented. The additionally formed silicon layer 412 and silicide layer 903 form local inter-element wiring.
[0037]
Next, after depositing a low dielectric constant insulating film as an interlayer film by CVD or the like, contact holes to the source and drain electrodes are formed by, for example, RIE technology, and further, a wiring material substance such as Al is deposited and processed Further, a salicide CMOS type Elevated source drain MOSFET structure having STI isolation and local wiring is completed through a wiring process, a mounting process, and the like using a known technique.
[0038]
Although the introduction of oxygen atoms has been used as an example, the same effect can be obtained with nitrogen atoms as well. The same method can be applied when the element isolation is LOCOS. The nitrogen concentration at this time is 1 × 10¹⁵cm^-3-1 x 10¹⁶cm^-3If it is in the range, it is preferable.
[0039]
【The invention's effect】
According to the present invention, even if there is a site where a transition is likely to occur in the semiconductor element structure, a high-concentration oxygen region or a nitrogen region is formed between this portion and the pn junction surface and blocking this portion. This suppresses the propagation and propagation of dislocations and prevents the dislocations from crossing the pn junction. The oxygen concentration and nitrogen concentration at this time are 1 × 10 respectively.¹⁷cm^-3-1 x 10¹⁸cm^-3And 1 × 10¹⁵cm^-3-1 x 10¹⁶cm^-3If it is in the range, it is preferable. This achieves a semiconductor device manufacturing method that improves the yield of the semiconductor device manufacturing process and reduces the manufacturing cost.
[0040]
In particular, by selectively introducing oxygen atoms or nitrogen atoms into the shallow trench corners, even if stress remains in these areas, the oxygen or nitrogen atoms are actively incorporated into the transition nuclei and change the structure of the transition nuclei. To inhibit the movement of metastases. Thus, the generated transition remains in the vicinity of the generated distance without moving over a long distance. Even if the transition occurs, this does not cross the pn junction portion, so that the electrical characteristics are not affected.
[0041]
Further, since oxygen or nitrogen atoms are selectively introduced while avoiding the pn junction part, precipitates derived from oxygen atoms are not formed on the junction surface. For this reason, there is no electrical influence on the bonding of oxygen or nitrogen atoms.
[0042]
In addition, immediately after the shallow trench is formed, oxygen or nitrogen atoms can be effectively implanted by ion implantation of oxygen or nitrogen atoms adjusted to have a specific depression angle perpendicular to the channel width direction of the device region. In addition, oxygen atoms can be introduced only into the shallow trench corners of the source and drain regions. Further, since the upper surface of the element region is protected by the pad layer, oxygen or nitrogen atoms are not introduced into the channel region. Therefore, it can be performed without adding any new process such as a Lithography process other than ion implantation.
[0043]
An insulating film to be a gate insulating film is formed in advance in a region where a gate electrode is to be formed, and then a silicon layer is additionally formed over the entire surface, and oxygen or nitrogen atoms are introduced into the upper portion of the silicon layer. Then, the depth of introduction reaches the interface between the additional silicon layer and the substrate silicon in the subsequent thermal process, but precipitation of oxygen atoms or nitrogen atoms does not occur at the pn junction surface where p / n impurities form on the substrate. Adjust.
[0044]
As a result, oxygen or nitrogen atoms are introduced into the interface that can become the nucleus of the transition, and the occurrence and propagation of the transition are suppressed, and the pn junction is not affected. Therefore, the yield of the semiconductor device manufacturing process is improved and the manufacturing cost is reduced.
[0045]
Such a process can be carried out without adding any new process such as a Lithography process other than ion implantation or CVD process.
In addition, since a silicon layer to be additionally formed on the gate electrode and the source and drain regions can be formed at once by RIE (Reactive Ion Etching), a new process such as selective growth by an epitaxial growth technique is not required. Elevated Source / Drain structure can be achieved. For this reason, manufacturing cost can be reduced.
[0046]
In addition, according to the present invention, it is easy to form a uniform and uniform silicon layer, and there is no variation in the film thickness of the additional source and drain forming portions found in the epitaxial growth technique. As a result, when the junction for forming the source and drain is introduced from the additionally formed silicon surface to form the junction, the junction can be accurately formed at the target position.
[0047]
The additionally formed source and drain electrodes can be arbitrarily installed on the element isolation insulating film. For this reason, the formed source and drain electrodes on the semiconductor substrate are limited to a minimum area, and most of the source and drain electrodes are mounted on the element isolation insulating curtain, thereby reducing the capacitance of the source and drain electrodes and the semiconductor substrate. Is possible. For this reason, the device can be operated at high speed. This additional silicon layer does not necessarily correspond to one element, and may connect source and drain regions of a plurality of elements. Thereby, not only the additional formation of the source and drain electrodes, but also the local inter-element wiring can be formed simultaneously by this silicon layer. Therefore, a new local inter-element wiring process is not necessary, and the manufacturing cost can be reduced.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a process of manufacturing an STI-isolated trench type DRAM formed on an SOI wafer at a high yield.
FIG. 2 is a cross-sectional view of a process of manufacturing an STI-isolated trench type DRAM formed on an SOI wafer at a high yield.
FIG. 3 is a cross-sectional view of a process of manufacturing an STI-isolated trench type DRAM formed on an SOI wafer at a high yield.
FIG. 4 is a cross-sectional view of a process of manufacturing an STI-isolated trench type DRAM formed on an SOI wafer at a high yield.
FIG. 5 is a cross-sectional view of a process for manufacturing a salicide CMOS type Elevated source drain MOSFET structure having a local wiring between source and drain electrodes at a high yield.
FIG. 6 is a cross-sectional view of a process for manufacturing a salicide CMOS type Elevated source drain MOSFET structure having a local wiring between source and drain electrodes at a high yield.
FIG. 7 is a cross-sectional view of a process for manufacturing a salicide CMOS type Elevated source drain MOSFET structure having a local wiring between source and drain electrodes at a high yield.
FIG. 8 is a cross-sectional view of a process for manufacturing a salicide CMOS type Elevated source drain MOSFET structure having a local wiring between source and drain electrodes at a high yield.
FIG. 9 is a cross-sectional view of a process for manufacturing a salicide CMOS type Elevated source drain MOSFET structure having a local wiring between source and drain electrodes at a high yield.
FIG. 10 is a cross-sectional view of a process for manufacturing a salicide CMOS type Elevated source drain MOSFET structure having a local wiring between source and drain electrodes at a high yield.
[Explanation of symbols]
100 Semiconductor substrate
101 p-well region
102 n-well region
111, 112, 113 shallow trench isolation
200 element isolation insulating oxide film
201, 211, 212 Gate insulating nitride film
300 Polysilicon
301 n-type polysilicon region
302 p-type polysilicon region
311 n-type polysilicon gate electrode
312 p-type polysilicon gate electrode
411, 412, 413, polysilicon additional source drain electrode
511, 512, 513, 514 Interval formed between the gate electrode and the additional source / drain electrodes
611, 612, 613, 614 Source and drain diffusion layers
711, 712, 713, 714 Extended source and drain regions
811, 812, 813, 814 Interlayer insulating film
901, 902, 903, 904, 905 Silicide region
1000 High-concentration oxygen-containing region
1100 SOI wafer n-type silicon lower semiconductor substrate
1101 SOI wafer upper silicon layer
1102 SOI wafer insulating silicon oxide film layer
1103 Pad silicon nitride film
1201 Deep Trench for DRAM charge storage
1202 Node insulating film
1203 node n-type polysilicon electrode
1301 Element region for access transistor
1302 Access transistor source region
1303 Access transistor drain region
1304 Channel region for access transistor
1305 Gate insulating film for access transistor
1306 Gate electrode for access transistor
1307 Source electrode for access transistor
1308 Drain electrode for access transistor
1311, 1312 shallow trench for element isolation
1321 Source region into which oxygen atoms are introduced shallow trench corner
1322 Drain region into which oxygen atoms are introduced shallow trench corner
1331, 1332 CVD silicon oxide film

Claims (3)

A semiconductor region;
Shallow trench corners,
A channel region present in the semiconductor region;
Source and drain regions present in the semiconductor region ;
A pn junction surface forming the source and drain regions in the semiconductor region ;
A dislocation propagation blocking region which is present in the source or drain region between the shallow trench corner and the pn junction surface and contains oxygen or nitrogen at a higher concentration than the channel region. Semiconductor device.   The dislocation propagation blocking region has an oxygen concentration of 1 × 10 ¹⁷ cm ^-3 -1 x 10 ¹⁸ cm ^-3 Range or nitrogen concentration is 1 × 10 ¹⁵ cm ^-3 -1 x 10 ¹⁶ cm ^-3 2. The semiconductor device according to claim 1, wherein 3. The method of manufacturing a semiconductor device according to claim 1 , wherein after forming the shallow trench, oxygen or nitrogen atoms are implanted so as to have a specific depression angle with respect to the substrate perpendicular to the channel width direction of the element region. A method for manufacturing a semiconductor device, wherein oxygen atoms or nitrogen atoms are selectively introduced only into the corners of the shallow trench in the source or drain region.

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