JP4198401B2 - Field effect transistor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a large-scale integrated semiconductor device, particularly a high-speed fine semiconductor device having a silicided source and drain and an insulating film at the bottom of the element.Field effect transistor.
[0002]
[Prior art]
In order to realize a high-speed and high-performance semiconductor device, demands for miniaturization of individual semiconductor elements used in the semiconductor device and large-scale integration thereof are increasing over time. In particular, miniaturization of a field effect transistor (MOSFET) which is a main component of a semiconductor element is important.
[0003]
In the MOSFET, a so-called short channel effect occurs in which the threshold voltage decreases when the channel length is shortened by miniaturization. If the pn junctions of the source and drain regions are shallowed to avoid the influence of the short channel effect, the resistance of the source and drain regions increases, thereby hindering high-speed transmission of signals transmitted through the element. In addition, an insulator such as an oxide film is provided on the substrate, and a semiconductor element is processed and formed in a thin single crystal semiconductor layer (SOI: Silicon On Insulator) formed on the substrate. By defining the drain junction position, the short channel effect can be suppressed (FD-type SOI-MOSFET: Fully-Depleted SOI MOSFET). However, in this case as well, since the source and drain regions are formed with only a very thin silicon layer, the electrical resistance of this portion increases, and the high-speed transmission of the signal transmitted through the element remains unchanged.
[0004]
In order to reduce the resistance of the source and drain regions, there is a method in which the upper portions of the source and drain regions are combined (silicided) with a metal such as Co. However, when silicide is formed, metal atoms diffuse rapidly in silicon forming the source and drain regions, and reach a junction when a shallow junction is formed, resulting in junction leakage. In the case of SOI-MOSFET, the metal atoms destroy the junctions of the source / drain regions and the channel region, so that the normal operation of the device is impaired.
[0005]
The diffusion of this metal atom is extremely fast, and in the case of Co, it reaches a depth of 150 nm only by performing rapid heat treatment at 800 ° C. for 30 seconds for silicidation. Fig. 2 shows n with different junction depths.⁺The value of the junction leakage when Co silicide is formed to 35 nm on the / p junction is shown together with reference data of the junction not subjected to silicide. It can be seen that junction leakage has already occurred around a junction depth of 150 nm, which is much deeper than the silicide film. This is a result of Co atoms diffusing into the substrate.
[0006]
Thus, high-speed diffusion of metal atoms inevitably proceeds on the surface where the metal and silicon are in contact. Metal atoms that move rapidly in the silicon region form levels that mediate the generation of leaks in the silicon forbidden band. Naturally, if a level is formed at the source / drain junction, a leakage current is generated here. When a current leaks through the source / drain junction, the operation of the element is impaired, or in a storage element such as a DRAM, written information is lost, and the original function of the semiconductor device is lost. Even when a logic circuit is formed, specifications required for a semiconductor device such as an increase in standby power cannot be satisfied.
[0007]
In order to cope with such a problem, a semiconductor material is selectively formed on the surface of the semiconductor substrate where the source and drain regions are to be formed, and the surface of this region is changed to the original semiconductor surface (that is, the surface on which the channel is formed). 2) An ESD (Elevated source drain) structure has been used in which the source and drain pn junctions and the silicide layer are formed through the additionally formed surface.
[0008]
In this method, the pn junction positions of the source and drain to be finally formed must be adjusted with extremely high precision on the original semiconductor surface (that is, the surface on which the channel is formed) or slightly below this. However, the film thickness of the additionally formed silicon varies depending on the roughness of the substrate surface below it and the crystal structure. Further, the film quality (the presence or absence of defects) may vary depending on the surface shape. If the additionally formed silicon film thickness is non-uniform, it becomes extremely difficult to form the junction portion of the pn junction near the original semiconductor substrate surface (ie, the surface on which the channel is formed).
[0009]
Even when an ESD structure is used in the formation of the FD type SOI-MOSFET, if the film thickness and film quality of the additionally formed silicon layer are not uniform, even if additional sources and drains are formed, the thin film thickness and film quality The metal atoms are diffused in a projecting manner from the bad point and easily reach the source-drain / channel interface. As a result, junction leakage occurs. Furthermore, the diffusion of the metal in the crystal itself is very rapid, so that the additional silicon layer must be very thick, but it is almost impossible to uniformly grow very thick selective silicon, for example 150 nm. It is.
[0010]
In addition, when trying to achieve further miniaturization of the MOSFET, in addition to the generation of leakage current accompanying silicidation of the source and drain regions, an increase in contact resistance between the source and drain regions and the inter-element wiring is also a problem. It becomes. That is, as the device is miniaturized, the area of the source and drain regions also decreases, so the area of the interface between silicon and metal decreases, and the contact resistance between these materials is inversely proportional to the decrease in interface area. Increase in shape. Such an increase in contact resistance is a major issue that must be avoided to ensure high-speed operation of the device. However, at present, the salicide technique is used to convert all the upper portions of the source and drain regions into silicide layers, so that the contact area has already been maximized, and this contact resistance cannot be reduced any further.
[0011]
[Problems to be solved by the invention]
Conventionally, in order to keep the source and drain electrical resistance low while keeping the junction position of the source and drain regions shallow, it is necessary to silicidize it. It is difficult to keep the junction leakage caused by this low. In addition, when further miniaturization of the MOSFET is attempted, the interface area between the silicon region forming the source and drain and the wiring metal region (silicide region) is reduced, and the high-speed operation of the device is secured by increasing the contact resistance. It becomes difficult to do.
[0012]
  The present invention has been made in view of the above circumstances. The object of the present invention is to suppress junction leakage while keeping shallow source / drain junction positions in a structure in which silicide is formed on source / drain regions. Can also be kept low contact resistanceTo provide a field effect transistor.
[0013]
[Means for Solving the Problems]
(Constitution)
In order to solve the above problems, the present invention adopts the following configuration.
[0015]
  That is, the present inventionAn insulator, a first single crystal silicon layer selectively formed on the insulator and serving as a channel region, and a gate electrode formed on the first single crystal silicon layer via a gate insulating film And on the bottom and side surfaces of the groove provided in the insulator on both sides in the channel length direction of the first single crystal silicon layer, and the first single crystal is partially formed along the side surface of the groove. A second single crystal silicon layer which is in contact with the silicon layer and forms source and drain regions having p-type conductivity; and a silicide layer formed on a horizontal plane and a vertical plane of the second single crystal silicon layer; , Formed only in the silicide layer in the vicinity of the contact portion between the first single crystal silicon layer and the second single crystal silicon layer, and As and O are each 1 × 10 ¹⁹ cm ^-3 A field-effect transistor comprising: a diffusion suppression region that suppresses diffusion of metal atoms included in the silicide layer at the above concentrationIt is.
[0016]
Here, preferred embodiments of the present invention include the following.
(1) Diffusion suppression region has 10 As and O¹⁹cm^-3It is an area including the above density.
(2) The source and drain regions have p-type conductivity.
(3) Silicide layer is CoSi₂Be.
(4) The n-channel and p-channel MOSFETs having the above-described configuration are formed on the same substrate.
(5) An extension region is formed between the channel region and the source / drain regions.
[0017]
According to another aspect of the present invention, there is provided a method of manufacturing a field effect transistor having the above-described structure, the step of forming a gate electrode on a single-crystal first silicon layer on an edge via a gate insulating film; Removing the first silicon layer except for a portion to be a channel region, forming a groove by partially etching the insulator at both ends of the first silicon layer in the channel direction, and a bottom surface of the groove And a step of forming a single-crystal second silicon layer serving as a source and drain region on the side surface so as to be in contact with an end portion of the first silicon layer in the channel direction at a part of the side surface; Forming an amorphous region containing a predetermined amount or more of As and O in a portion of the layer located on the side surface of the groove on the first silicon layer side, and forming a silicide layer on the second silicon layer. That features To.
[0019]
(Function)
According to the present invention, grooves are formed in the SOI base insulator at both ends in the channel direction of the first silicon layer serving as the channel region, and the second silicon layers serving as the source and drain regions are formed on the bottom and side surfaces of the groove. As a result, the bottoms of the source and drain regions are positioned below the channel region, and the connection between the source and drain regions and the channel region has a vertical plane. In this case, the sum of the vertical plane of the source and drain regions and the horizontal plane is larger than the area of the region where the source and drain regions are projected onto the horizontal plane, and the silicon / silicide interface area increases, leading to a reduction in contact resistance. .
[0020]
Further, by forming a diffusion suppression region containing As and O in high concentration in the silicide layer in the vicinity of the source / drain regions and the channel region, diffusion of the metal in the silicide into the channel region can be suppressed. . As a result, it is possible to reduce junction leakage accompanying the formation of silicide.
[0021]
In addition, since the source and drain regions are additionally formed so as to bite into the insulator, the overlap between the gate electrode and the source and drain regions is minimized while ensuring the thickness of the source and drain regions regardless of the thickness of the SOI. Can be suppressed. As a result, electrical capacitive coupling between the gate electrode and the source / drain regions is reduced, and high-speed operation of the device can be ensured.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
The details of the present invention will be described below with reference to the illustrated embodiments.
[0023]
(First embodiment)
FIG. 1 is a sectional view showing an element structure of an SOI-MOSFET according to the first embodiment of the present invention. This embodiment is a salicide type SOI-MOSFET having a recessed S / D structure in which source and drain regions are digged into a BOX insulating film.
[0024]
An SOI substrate 100 is formed by forming a first single crystal silicon layer (SOI layer) 103 on the single crystal silicon substrate 101 via an insulating film 102, and a MOSFET is formed on the SOI substrate 100.
[0025]
A gate electrode 300 is formed on the silicon layer 103 with a gate insulating film 200 interposed therebetween, and sidewall insulating films 301 and 302 are formed on the sides of the gate electrode 300. The gate insulating film 200 and the silicon layer 103 are removed except for the gate portion including the sidewall insulating films 301 and 302. At both ends of the silicon layer 103 in the channel length direction, the insulating film 102 is etched to form grooves. A second single crystal silicon layer 600 is formed on the bottom and side surfaces of the groove, and the second silicon layer 600 is in contact with the first silicon layer 103 on the side surface of the groove. Thereby, the bottoms of the source region 601 and the drain region 602 of the SOI-MOSFET are provided so as to be positioned below the channel region 103, and the end of the channel region 103 and the source and drain regions 601 and 602 are vertical surfaces. It is connected.
[0026]
On the second silicon layer 600 to be the source and drain regions 601, 602, CoSi₂Layers 631 and 632 are formed. CoSi also on the gate electrode 300₂A layer 633 is formed. In the connection portions 611 and 612 between the source / drain regions 601 and 602 and the channel region 103, As and O are 10 in the silicide layers 631 and 632, respectively.¹⁹cm^-3The above-described diffusion suppression region is formed. In the figure, reference numeral 400 denotes an interlayer insulating film.
[0027]
With such a configuration, the following effects can be obtained.
[0028]
First, the sum of the vertical surfaces 611 and 612 of the source and drain regions 601 and 602 and the horizontal plane can be made larger than the area of the region obtained by projecting the source and drain regions 601 and 602 onto the horizontal plane. Further, CoSi is formed on the vertical and horizontal planes of the source / drain regions 601 and 602.₂By forming the layers 631 and 632, the silicon / silicide interface area can be increased more than the interface area achieved when the silicide layer is formed on the same plane. Therefore, the contact resistance of silicon / silicide can be reduced. Thereby, the high-speed operation | movement of an element is securable.
[0029]
Second, since the source and drain regions 601 and 602 are additionally formed so as to bite into the BOX insulating film 102, the gate and source regions 601 and 602 are sufficiently secured regardless of the thickness of the SOI, and the gates are formed. Overlap between the electrode 300 and the source / drain regions 601 and 602 can be minimized. As a result, electrical capacitive coupling between the gate electrode 300 and the source / drain regions 601 and 602 is reduced, and high-speed operation of the device can be ensured. Furthermore, it becomes easy to maintain the electrical insulation between the gate, the source and the drain during the salicide process.
[0030]
Third, since the source and drain regions 601 and 602 have vertical surfaces 611 and 612 in contact with the surface SOI layer forming the channel, As and O are self-aligned using oblique ion implantation. Can be selectively introduced into the vertical plane. As a result, it is possible to avoid an increase in contact resistance while suppressing the generation of leakage current accompanying silicidation. Therefore, standby power of the semiconductor circuit can be reduced, the memory element can avoid information loss, and high-speed operation of the element can be ensured.
[0031]
In order to further clarify the action pointed out in the third, the suppression of leakage current generation accompanying silicidation with As and O will be described in detail with reference to FIGS.
[0032]
FIG. 2 shows n with different junction depths.⁺/ P junction Junction leakage when Co silicide is formed to 35 nm_ROf the junction depth X together with reference data for the non-silicided junction._jIt is the figure shown as a function of. The applied voltage for junction leak measurement was 4V. As can be seen from this figure, CoSi₂When Co is formed on silicon, Co atoms diffuse at high speed in the silicon, resulting in a large junction leak. Prior to the silicidation reaction, the present inventors have confirmed that the occurrence of this leakage can be suppressed by performing ion implantation on the silicon surface immediately before depositing the metal.
[0033]
FIG. 3 shows that 35 nm CoSi is formed for each of the case where As ions are implanted through an oxide film prior to silicidation (a) and the case where Ge ions are implanted (b).₂Pn junction leakage current I at a junction depth of 100 nm after forming_RIs shown as a function of the injection volume Φ. In the figure, the leakage current when heat treatment is applied prior to Co deposition after ion implantation is also shown for reference (dotted line). It can be seen that heat treatment should not be applied after ion implantation in order to suppress leakage. This is because the amorphous layer generated by ion implantation disappears by heat treatment. Further, by comparing (a) and (b), it can be seen that the leakage current suppression capability greatly depends on the implanted ion species, and As is superior to Ge in leakage suppression capability by two orders of magnitude or more. In the case of As, the leakage current monotonously decreases with the injection amount, and 1 × 10¹⁴cm^-2Thus, the junction leak accompanying silicidation is almost eliminated.
[0034]
FIG. 4 shows an ion implantation amount of 1 × 10 when the ion implantation is performed via the oxide film and when the ion implantation is not performed via the oxide film.¹⁴cm^-2The leakage current (with a junction depth of 100 nm) is compared with the leakage current (reference) when no ion implantation is performed. In the case of Ge ion implantation, there is almost no difference in leakage current between the case of implantation through an oxide film and the case of implantation without an oxide film. However, in the case of As ion implantation, the leakage current is suppressed by about two orders of magnitude when the implantation is performed through the oxide film, compared with the case where the implantation is performed without the oxide film.
[0035]
Immediately before the silicidation metal deposition, As is ion-implanted through the oxide film, “knock-on” oxygen due to crystal defects and implanted ions ejecting oxygen in the oxide film is introduced to the surface of the source and drain regions. Is done. Crystal defects (and amorphous layers caused by crystal defects) modulate the reaction process of the subsequent silicidation process, and suppress the diffusion of silicidation metal into the silicon substrate (see the difference in the presence or absence of heat treatment in FIG. 3). ). Furthermore, as As and “knock-on” oxygen coexist, as shown in FIG. 4, the diffusion of silicided metal into the silicon substrate is further suppressed.
[0036]
FIG. 5 shows As ion implantation (injection amount 1 × 10¹⁴cm^-2) Through the oxide film and then CoSi₂The results of SIMS analysis of the distribution of As and O at the time of forming are shown. With the silicidation reaction, As and O are taken into the silicide layer and segregate preferably near the center of the silicide layer.¹⁹cm^-3It can be seen that a region including the above high concentration is formed and Co diffusion is suppressed.
[0037]
FIG. 6 shows the formed CoSi in the case where As ion implantation is performed through the oxide film (a) and in the case where the ion implantation is not performed through the oxide film (b).₂The contact resistance values between the p-type silicon diffusion layer and the p-type silicon diffusion layer are shown as a function of the amount of ion implantation for contacts with various aperture diameters. When As ions are implanted without an oxide film, the amount of implantation (1 × 10 6) that can suppress the generation of leakage current¹⁴cm^-2) Shows that the contact resistance greatly increases. On the other hand, when ion implantation is performed through an oxide film, the increase in contact resistance is significantly suppressed as compared with the case where implantation is performed without using an oxide film.
[0038]
As described above, As is ion-implanted through an oxide film before silicidation, a layer containing As and O is formed on the silicon surface, and then silicidation is performed to significantly suppress the generation of leakage current. In addition, the increase in contact resistance with the p-type silicon layer accompanying the introduction of As can be stopped by about 1.5 times.
[0039]
However, since the contact area is reduced with the miniaturization of the element, it is not preferable that the contact resistance is increased by As ion implantation in addition to this. Therefore, a layer containing As and O is selectively formed only in the source and drain portions adjacent to the surface SOI layer that forms a channel related to the occurrence of leakage. As a result, the occurrence of leaks in the vicinity of the junction between the source / drain regions and the channel region can be suppressed, and the increase in contact resistance can be suppressed without performing ion implantation in the other source / drain portions.
[0040]
In order to achieve this, as in the present embodiment, the BOX insulating film 102 is partially formed so that the source and drain regions 601 and 602 of the SOI-MOSFET are positioned below the bottom of the surface SOI layer 103. If the surface SOI layer 103 that forms the erosion and the connection portion between the source and drain regions 601 and 602 have a vertical surface, the vertical surface that is in contact with the surface SOI layer 103 that forms the channel. In addition, As and O can be selectively introduced in a self-aligned manner using oblique ion implantation. As a result, it is possible to avoid an increase in contact resistance while suppressing the generation of leakage current accompanying silicidation. Therefore, standby power of the semiconductor circuit can be reduced, the memory element can avoid information loss, and high-speed operation of the element can be ensured.
[0041]
(Second Embodiment)
7 to 8 are cross-sectional views showing manufacturing steps of the SOI-MOSFET according to the second embodiment of the present invention. The element structure is the same as that of the first embodiment, and is a manufacturing process of a salicide type SOI-MOSFET having a recessed S / D structure in which the source and drain regions have digged into the BOX insulating film.
[0042]
First, as shown in FIG. 7A, from a silicon oxide film (BOX) 102 formed on a single crystal silicon substrate 101 and an element forming single crystal silicon layer (SOI layer) 103 formed thereon. An SOI substrate 100 is prepared. Then, a gate insulating film 200 made of a silicon oxide film is formed on the surface of the SOI layer 103, and a gate electrode 300 made of polysilicon is further processed and formed thereon. Then, an oxide film 310 as a first insulating film and a nitride film 320 as a second insulating film are formed on the gate electrode 300. More specifically, after depositing a polysilicon film, an oxide film, and a nitride film on the gate insulating film 200, a resist is formed on the gate electrode pattern by photolithography, and the nitride film, oxide film, poly The silicon film is selectively etched into a gate pattern.
[0043]
Subsequently, using the gate electrode 300 as a mask, a conductive impurity, for example, B is introduced into the SOI layer 103 adjacent thereto to form source and drain extension regions.
[0044]
Next, as shown in FIG. 7B, gate sidewall insulating films 301 and 302 made of a silicon nitride film are formed on the left and right sides of the gate electrode 300, and at the same time, using this processing step, the known technique is effective. The gate oxide film 200 and the SOI layer 103 are removed using a method such as RIE (Reactive Ion Etching). As a result, only a portion (including source and drain extension regions) that forms a channel under the gate remains in the SOI layer 103.
[0045]
Next, as shown in FIG. 7C, an interlayer insulating film 400, for example, a silicon oxide film is formed on the structure of FIG. 7B by an effective method of known techniques such as CVD (Chemical Vapor Deposition). It deposits using the method etc., and this is planarized using the effective method of the well-known techniques, for example, CMP (Chemical Mechanical Polishing) method etc. Further, a resist mask 500 having an opening in an element formation scheduled region is formed using an effective method of known techniques, such as a photolithography method. This photolithography does not require precise alignment with the gate electrode.
[0046]
Next, as shown in FIG. 8D, using the resist mask 500 and simultaneously using the gate electrode portion as a mask, an effective method of a known technique such as the RIE method is used for the opening. The recesses 401 and 402 are formed on the left and right sides of the gate electrode by etching through the interlayer insulating film 400 and etching the upper portion of the BOX insulating film 102. Here, since the recesses 401 and 402 are formed in a self-aligning manner using the gate electrode portion as a mask, strict alignment accuracy is not required when the resist mask 500 is opened.
[0047]
Next, as shown in FIG. 8E, an amorphous silicon layer 600 is uniformly deposited on the surface of the substrate with the same thickness as the desired source and drain regions so as to cover the recesses 401 and 402. . The deposition of this silicon layer is within the scope of known techniques, for example SiH at 0.2 Torr, 400 ° C._FourIt can be easily formed by using a gas. SiH_FourB for gas₂H₆The amorphous silicon layer 600 may have the same conductivity as the source and drain extensions. Needless to say, conductive impurities such as B may be introduced by ion implantation.
[0048]
At this time, the SOI layer 103 forming the channel is connected to the silicon layer 600 at both ends 111 and 112. Therefore, by subsequently performing a heat treatment at 600 ° C. for 30 seconds in a nitrogen atmosphere, for example, the silicon at both ends 111 and 112 can be used as a seed to crystallize the adjacent alpha silicon layer. Here, the thicknesses of the source and drain regions are accurately defined by the silicon layer 600, and the variation in film thickness seen in the selective epitaxial growth method can be avoided.
[0049]
Next, as shown in FIG. 8F, an oxide film 700 is deposited on the entire surface with a film thickness of, for example, 20 nm using an effective method of known techniques, such as a CVD method. Next, after applying a resist to the entire surface, this is etched back by an effective method of known techniques, for example, an electron beam irradiation method so that the resists 501 and 502 remain only at the bottoms of the recesses 401 and 402. To. The etch back amount at this time is preferably adjusted so that the upper position of the resist is above the surface of the SOI layer 103 forming the channel.
[0050]
Next, as shown in FIG. 9G, the silicon oxide film 700 exposed on the resists 501 and 502 is selectively removed by immersing the resist in the HF solution, for example, using the resist as a mask. The silicon layer 600 is selectively removed using an effective method of known techniques, for example, an isotropic etching method such as a CDE (Chemical Dry Etching) method. At this time, the resists 501 and 502 at the bottom of the recesses 401 and 402 remain.
[0051]
By these processes, the silicon regions 601 and 602 that constitute the source and drain regions are electrically connected to the SOI layer 103 that forms the channel at the bottoms of the recesses 401 and 402, and the bottoms are below the 103. The BOX insulating film 102 can be partially eroded (recessed S / D structure). In addition, since the overlap with the gate electrode can be kept small while ensuring the desired thickness of the source and drain regions, electrical capacitive coupling between them is reduced, and the device can be operated at high speed.
[0052]
Further, the source / drain regions 601 and 602 can be formed in the recesses 401 and 402 formed in the gate electrode in a self-aligned manner. In addition, vertical surfaces 611 and 612 are formed at the connection between the SOI layer 103 forming the channel and the source / drain regions 601 and 602. Therefore, the sum of the vertical planes of the source / drain regions 601 and 602 and the horizontal planes 621 and 622 can be made larger than the area of the region where the source / drain regions 601 and 602 are projected onto the horizontal plane.
[0053]
Next, as shown in FIG. 9H, the upper portions of the resists 501 and 502 remaining at the bottoms of the recesses 401 and 402 are further retracted by an effective method of known techniques, for example, an electron beam irradiation method, The upper portions of the vertical surfaces 611 and 612 of the source / drain regions 601 and 602 are exposed. For example, the acceleration voltage is 50 KV and the injection amount is 2 × 10 6 over the remaining oxide film 700 obliquely from the exposed vertical surface.¹⁴cm^-2Ion implantation is performed under the following conditions. At the top of the exposed vertical surfaces 611 and 612, oxygen atoms in the silicon oxide film are "knocked-on" in a self-aligned manner and introduced simultaneously with As as an implantation element.
[0054]
As a result, crystal defects are generated on the upper surfaces of the vertical surfaces 611 and 612 and become amorphous. At this time, it is preferable that the range of the ion-implanted atoms is set to the thickness of the silicide layer formed thereon after that. In this manner, As and O can be simultaneously and easily introduced into the upper portions of the vertical surfaces 611 and 612 that are closest to the end portions 111 and 112 of the SOI layer 103 forming a channel in which leakage current is a concern. .
[0055]
In contrast, ion implantation is not performed on the horizontal planes 621 and 622 of the source and drain regions 601 and 602 protected by the resists 501 and 502. Needless to say, the vertical surfaces 611 and 612 containing As and O may be formed by implanting oxygen ions simultaneously with As ions. Here, the selective introduction of As and O into the vertical plane is easily achieved by only electron beam irradiation and ion implantation without requiring any photolithography with the formation of the recessed S / D. .
[0056]
Next, as shown in FIG. 9I, the resists 501 and 502, the remaining oxide film 700, and the first and second insulating films 310 and 320 on the gate electrode are removed. Here, the following should be noted. The layer containing As and O is introduced above the vertical surfaces 611 and 612 closest to the end portions 111 and 112 of the SOI layer 103 forming the channel. Therefore, as described in detail in the first embodiment, when the source and drain regions are silicided, these As and O can prevent the metal atoms from diffusing and reaching the SOI layer 103 forming a channel.
[0057]
As a result, no leakage current occurs. On the other hand, ion implantation is not performed on the horizontal planes 621 and 622 of the source and drain regions 601 and 602. Therefore, as pointed out in the first embodiment, an increase in contact resistance due to As ion implantation at this portion is avoided.
[0058]
Thereafter, Co is deposited on the entire surface of the semiconductor substrate to a thickness of, for example, 10 nm by an effective method of known techniques, for example, sputtering. Next, this semiconductor substrate is subjected to rapid thermal processing in nitrogen at, for example, 500 ° C. for 30 seconds, and a silicidation reaction is selectively advanced with silicon in direct contact with Co. Silicide regions are formed on the source 631, the gate 633, and the drain 632. In this case, the final thickness of the silicide layer is about 35 nm. Unreacted Co is selectively removed by immersing in a mixed solution of sulfuric acid and hydrogen peroxide. Further, rapid thermal processing is performed in nitrogen at, for example, 800 ° C. for 30 seconds to further reduce the electrical resistance of Co silicide. Thereby, the structure shown in FIG. 1 is obtained.
[0059]
Subsequently, using a known technique, a semiconductor device is completed through an interlayer film and formation of contacts to each electrode through the interlayer film, a wiring process, a mounting process, and the like. In this way, the generation of leakage current due to silicidation is suppressed, the contact resistance is kept low, the electric capacitive coupling with the gate electrode is reduced, and the recessed S / D structure in which the source and drain regions have digged into the BOX. The salicide type SOI-MOSFET is realized in a self-aligned manner with the gate electrode.
[0060]
As described above, according to the present embodiment, the source and drain regions 601 and 602 are formed by the silicon layer 600 deposited with the same thickness as the desired source and drain regions. The thickness is precisely defined, and the film thickness variation seen in the selective epitaxial growth method can be avoided.
[0061]
By using resist etchback, the source and drain regions 601 and 602 can be easily formed in the trenches 401 and 402 formed in the gate electrode in a self-aligned manner. Since the source / drain regions 601 and 602 have a horizontal plane and a vertical plane, it is possible to selectively introduce As and O into only the vertical plane in a self-aligning manner using oblique ion implantation. .
[0062]
By forming the diffusion suppression region containing As and O at the same time prior to the silicide, diffusion of metal atoms can be suppressed extremely effectively. Since the diffusion suppression region containing As and O is introduced at the upper part of the vertical surface closest to the end of the SOI layer forming the channel, a leakage current is generated when the source and drain electrodes are silicided. Can be prevented.
[0063]
Since ion implantation is not performed in the horizontal planes of the source and drain regions 601 and 602, an increase in contact resistance due to As ion implantation in this portion is avoided. As a result, it is possible to avoid an increase in contact resistance while suppressing the generation of leakage current accompanying silicidation. Therefore, standby power of the semiconductor circuit can be reduced, the memory element can avoid information loss, and high-speed operation of the element can be ensured.
[0064]
(Third embodiment)
10 and 11 are cross-sectional views showing a manufacturing process of an SOI-MOSFET according to the third embodiment of the present invention.
[0065]
In this embodiment, immediately before silicidation, a surface layer containing As and O is introduced only into a portion adjacent to the gate electrode, thereby suppressing the diffusion of Co atoms to the substrate and at least a part of the source and drain regions. In this case, a simple manufacturing process of a salicide MOSFET with reduced contact resistance is realized by not performing ion implantation immediately before silicidation.
[0066]
FIG. 10A shows a silicon substrate 101 formed by an effective method of a known technique, element isolation regions 121 and 122, a gate insulating film 200 formed on the surface of the silicon substrate, for example, a silicon oxide film, The gate electrode 300 formed thereon, for example, polysilicon is shown. On the left and right sides of the gate electrode, shallow diffusion layers 131 and 132 having a conductivity opposite to the substrate serving as the source and drain extension regions, for example, p-type conductivity, and the substrate opposite to the source and drain regions are provided. Diffusion layers 141 and 142 having conductivity, for example, p-type conductivity are formed. Further, gate sidewall insulating films 301 and 302, for example, silicon nitride films are formed on the left and right sides of the gate electrode 300.
[0067]
Next, as shown in FIG. 10B, a silicon oxide film 700 is deposited on the entire surface with a film thickness of, for example, 20 nm using an effective method of known techniques, such as a CVD method.
[0068]
Next, as shown in FIG. 10C, a resist mask 500 having openings in the source and drain regions is formed using an effective method of known techniques, such as a photolithography method. Subsequently, As is obliquely passed through the oxide film 700, for example, with an acceleration voltage of 50 KV and an injection amount of 2 × 10.¹⁴cm^-2Ion implantation is performed under the following conditions. At this time, the height and ion implantation angle of the resist 500 are such that both the resist and the gate electrode function as a mask, and ion implantation into the source and drain regions is performed only on a part 152 of the source and drain regions adjacent to the gate electrode. Adjust as follows. As a result, crystal defects are generated on the surface of the region 152 adjacent to the source and drain extension regions 132, and an amorphous layer containing As and O is generated. At this time, it is preferable that the range of the ion-implanted atoms is set to the thickness of the silicide layer formed thereon after that. As described above, As and O can be simultaneously and simply introduced into the regions adjacent to the source and drain extension regions where leakage current is a concern. In this case, ion implantation is not performed on at least a part of the source and drain regions.
[0069]
Similar oblique ion implantation is performed from the left and right sides, and the oxide film 700 is peeled off. As shown in FIG. 11D, regions adjacent to the source and drain extension regions 131 and 132 in which leakage current is a concern. On the surfaces of 151 and 152, an amorphous layer containing As and O is generated. Therefore, as explained in detail in the first embodiment, when the source and drain regions are silicided, it is possible to prevent the metal atoms from diffusing due to these As and O and reaching the shallow junction surface near the source and drain extensions. . As a result, no leakage current occurs. On the other hand, in the source and drain region portions (which are defined by the resist mask and the ion implantation angle and are formed at a distance of approximately the height of the gate electrode from the gate electrode) where the junction is deep and leakage is less likely to occur. In this case, unnecessary ion implantation is not performed. Therefore, as pointed out in the first embodiment, an increase in contact resistance due to As ion implantation at this portion is avoided.
[0070]
Next, as shown in FIG. 11E, Co is deposited on the entire surface of the semiconductor substrate to a thickness of, for example, 10 nm by an effective method of known techniques, for example, sputtering. Next, this semiconductor substrate is subjected to rapid thermal processing in nitrogen at, for example, 500 ° C. for 30 seconds, and a silicidation reaction is selectively advanced with silicon in direct contact with Co. Silicide regions are formed on the source 631, the gate 633, and the drain 632. In this case, the final thickness of the silicide layer is about 35 nm. Unreacted Co is selectively removed by immersing in a mixed solution of sulfuric acid and hydrogen peroxide. Further, rapid thermal processing is performed in nitrogen at, for example, 800 ° C. for 30 seconds to further reduce the electrical resistance of Co silicide.
[0071]
Thereafter, using a known technique, a semiconductor device is completed through formation of an interlayer film and contacts to each electrode through the interlayer film, a wiring process, a mounting process, and the like. In this way, a salicide MOSFET is realized in which the generation of leakage current associated with silicidation is suppressed and the contact resistance is kept low.
[0072]
As described above, according to the present embodiment, when the salicide MOSFET is formed, an amorphous material containing As and O only on the surfaces of the source and drain regions adjacent to the source and drain extension regions, where leakage current may be generated. By forming the layer, it is possible to prevent the occurrence of leakage current accompanying silicidation. At the same time, unnecessary ion implantation is not performed on the source and drain regions where the junction is deep and leakage is less likely to occur, thereby suppressing an increase in contact resistance due to As ion implantation.
[0073]
(Modification)
The present invention is not limited to the above-described embodiments. Although the embodiments have been described using a single MOSFET, it is needless to say that the above-described method can be similarly applied to a plurality of elements. Furthermore, it goes without saying that it can be selectively applied to a group of elements that form part of a semiconductor device, or can be applied to different conductive MOSFETs.
[0074]
The diffusion suppression region formed in the silicide may be any region that sufficiently suppresses the diffusion of Co in the silicide into the silicon layer, and the concentration of As and O required for this purpose is 1 × 10.¹⁹cm^-3That is all you need. Further, in order to form a diffusion suppression region of this concentration, the ion implantation amount of As implanted through the oxide film is 1 × 10.¹⁴cm^-2That is all you need. As for doping As and O, it is effective to ion-implant As through an oxide film. However, the present invention is not necessarily limited to this technique, and any technique that can simultaneously do As and O can be used.
[0075]
Further, the silicidation metal is not necessarily limited to Co, and Ti, Ni, or the like can be used instead. In other words, the present invention is effective when any metal material is formed on the source and drain, where the diffusion is reduced by the amorphization and the contact resistance is increased.
[0076]
In addition, various modifications can be made without departing from the scope of the present invention.
[0077]
【The invention's effect】
As described above in detail, according to the present invention, the bottoms of the source and drain regions are located below the channel region, and each connection portion between the channel region and the source and drain regions has a vertical plane. In a field effect transistor having a silicide layer on a region, by forming a high-concentration impurity region containing As and O in the silicide layer in the vicinity of the connection portion between the source and drain regions and the channel region, a shallow source, While maintaining the drain junction position, junction leakage can be kept low, and the contact resistance can be kept low.
[Brief description of the drawings]
FIG. 1 is a sectional view showing an element structure of an SOI-MOSFET according to a first embodiment.
FIG. 2 is a diagram showing the relationship between junction depth and junction leakage current with and without Co silicide.
FIG. 3 is a diagram showing the relationship between the dose of As and Ge and the junction leakage current.
FIG. 4 shows the leakage current when ion implantation is performed through an oxide film and when the ion implantation is not performed through comparison with the leakage current when ion implantation is not performed.
FIG. 5 is a diagram showing the result of SIMS analysis of the distribution of As and O in silicide and in silicon when silicide is formed after As ion implantation is performed through an oxide film.
FIG. 6 shows CoSi formed when As ion implantation is performed through an oxide film and when it is not performed through an oxide film.₂The figure which showed the value of contact resistance with a p-type silicon | silicone diffused layer as a function of the amount of ion implantation with respect to the contact of various opening diameters.
FIG. 7 is a cross-sectional view showing an SOI-MOSFET manufacturing process according to the second embodiment.
FIG. 8 is a cross-sectional view showing a manufacturing process of the SOI-MOSFET according to the second embodiment.
FIG. 9 is a cross-sectional view showing a manufacturing process of the SOI-MOSFET according to the second embodiment.
FIG. 10 is a cross-sectional view showing a manufacturing process of an SOI-MOSFET according to a third embodiment.
11 is a cross-sectional view showing a manufacturing step of the SOI-MOSFET according to the third embodiment. FIG.
[Explanation of symbols]
100 ... SOI substrate
101. Single crystal silicon substrate
102 ... Silicon oxide film (BOX insulating film)
103. Single crystal silicon layer (SOI layer)
111, 112 ... both ends of the SOI layer
121, 122 ... element isolation region
131, 132 ... Shallow diffusion layer serving as extension region
141, 142... Diffusion layers to be source and drain regions
151, 152 ... Amorphous layer containing As and O
200: Gate insulating film
300 ... Gate electrode
301, 302 ... Gate side wall insulating film
310: first insulating film on gate electrode
320 ... Second insulating film on the gate electrode
400 ... interlayer insulating film
401, 402 ... concave portion
500, 501, 502 ... resist mask
600 ... Amorphous silicon layer
601, 602... Source and drain regions
611, 612 ... vertical planes of the source and drain regions 601 and 602
621, 622 ... horizontal planes of the source and drain regions 601 and 602
631,632,633 ... CoSi₂layer
700 ... Silicon oxide film

Claims (2)

An insulator;
Selectively formed on the insulator, and the first single crystal silicon layer serving as a channel region,
A gate electrode formed on the first single crystal silicon layer via a gate insulating film;
Formed on the bottom and side surfaces of the groove provided in the insulator on both sides of the channel length direction of said first single crystal silicon layer, the first single crystal silicon layer in part along the sides of the groove A second single-crystal silicon layer that is in contact with and forms p-type conductivity source and drain regions;
A silicide layer formed on a horizontal plane and a vertical plane of the second single crystal silicon layer;
Wherein are only formed in the first said silicide layer contacting the vicinity of the single crystal silicon layer and the second single crystal silicon layer, the silicide includes As and O at each 1 × 10 ¹⁹ cm ^-3 or more concentrations A diffusion suppression region for suppressing diffusion of metal atoms constituting the layer;
A field effect transistor comprising: _2. The field effect transistor according to claim 1, wherein the silicide layer is CoSi2 .

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