JP3816746B2 - MOS field effect transistor and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a MOS field effect transistor (hereinafter abbreviated as MOSFET), and more particularly to a MOSFET having a silicide layer on a source / drain region and a method for manufacturing the same.
[0002]
[Prior art]
In recent years, in order to realize a high-speed and high-performance semiconductor device, demands for miniaturization and large-scale integration of individual semiconductor elements used for the semiconductor device are increasing. However, considering the miniaturization of MOSFETs, which are the main components of these semiconductor elements, various difficulties are associated with miniaturization and large-scale integration.
[0003]
For example, as the channel length of the MOSFET (that is, the length of the gate electrode) is reduced, a short channel effect in which the threshold voltage decreases occurs. If an element different from the threshold voltage intended at the time of designing a semiconductor circuit is formed, an element operation different from the design intention is caused and the function of the entire circuit is impaired. Further, since the threshold voltage depends on the processing dimension of the gate electrode, it is impossible to obtain an element having the desired characteristics even with a slight processing deviation, and a semiconductor circuit that requires a large number of uniform elements, such as a DRAM (Dynamic Random Access Memory) is extremely inconvenient.
[0004]
Such a short channel effect is caused by the fact that the distortion of the electric field at the source and drain portions of the MOSFET affects the vicinity of the center of the channel portion as the channel length is reduced. This effect can be avoided by bringing the position of the pn junction forming the source / drain region closer to the semiconductor surface, that is, by making the pn junction shallow. However, if the pn junction is simply shallow, the resistance of the source / drain region formed thereby increases, and high-speed transmission of signals transmitted through the element is hindered.
[0005]
In order to cope with this problem and reduce the resistance of the source and drain, a part of the upper part of the source / drain region is combined with a metal (silicide). As metal species for silicidation, elements such as Co, Ti, and Ni are used. Among these, Co is the metal species for silicidation that does not show an increase in electrical resistance (thin line effect) when it is formed into a thin line shape, maintains stability at high temperatures, and is compatible with miniaturized LSIs. However, when silicidation is performed, metal atoms diffuse rapidly in the silicon that forms the source / drain regions, and if a shallow pn junction is formed, it reaches the junction. For this reason, the leakage current of the junction portion is increased.
[0006]
The diffusion of this metal atom is extremely fast, and in the case of Co, it reaches a depth exceeding 100 nm only by performing a rapid heat treatment at 800 ° C. for 30 seconds for silicidation.
[0007]
Conventionally, in order to cope with such a problem, a semiconductor material is selectively formed on a surface portion of a semiconductor substrate where a source / drain region is to be formed, and the surface of this region is formed on the original semiconductor surface (that is, a channel is formed). The pn junction of the source / drain region and the silicide layer are formed through the additionally formed surface. As a result, the position of the junction is shallow with respect to the original semiconductor surface (that is, the surface where the channel is formed) and deep from the newly formed surface, and thus the thickness of the electrode portion forming the source / drain region (diffusion) A method employing a so-called E1evated Source Drain structure (hereinafter abbreviated as an ESD structure) that ensures the thickness of the layer has been used.
[0008]
Such selective silicon growth can be achieved using epitaxial growth techniques. However, in this method, the position of the pn junction of the source / drain region to be finally formed must be adjusted with extremely high accuracy on the original semiconductor surface or slightly below it. This is because when the junction is located above the surface (channel surface), the current driving capability of the MOSFET is significantly reduced. Moreover, if the junction is formed below the surface, a short channel effect will occur.
[0009]
By the way, the epitaxial growth technique is very sensitive to a surface state in which selective growth is performed. For example, the film thickness of silicon to be formed varies depending on the roughness of the substrate surface below it and the crystal structure. Further, the film quality (the presence or absence of defects) may vary depending on the surface shape. For example, the thickness and quality of the silicon layer formed on the source / drain regions differ depending on the element due to a natural oxide film on the substrate surface immediately before growth or damage introduced during processing of the gate electrode. There is a case.
[0010]
If the thickness of the additionally formed silicon film is not uniform, it becomes extremely difficult to form a junction portion of the pn junction near the original semiconductor substrate surface. This is because the impurities for forming the source / drain regions are introduced from the additionally formed silicon surface, so that the junction is formed at a certain position from this surface. If the film thickness is not uniform, the relative position of the original semiconductor surface from the additionally formed silicon surface becomes indefinite. Therefore, the position where the joint surface is to be formed is also indefinite.
[0011]
In addition, even when the additionally formed silicon film is non-uniform in quality, it is difficult to accurately match the junction portion of the pn junction with the target position below the original surface of the semiconductor substrate. Due to the difference in film quality (that is, the presence or absence of crystal defects), the impurity diffusion speed is modulated (Transient enhanced diffusion), and even if thermal diffusion of a predetermined impurity is performed to form a junction on the channel surface, This is because unexpected diffusion occurs and a uniform junction depth cannot be obtained.
[0012]
The same applies to the diffusion of metal atoms accompanying silicidation. If the film thickness and film quality are non-uniform, even if an additional silicon layer for silicidation is additionally formed on the source / drain regions, metal atoms will be diffused in a protruding manner from a thin film or a poor film quality. It easily reaches the joint surface. As a result, junction leakage occurs.
[0013]
Also, the diffusion of the metal in the crystal itself is very rapid. Therefore, the additional silicon layer to be formed must be very thick. However, for the reasons as described above, it is almost impossible to perform extremely thick selective silicon growth uniformly. Further, when the silicon layer to be additionally formed becomes thicker and almost equal to the height of the gate electrode, when the gate, source and drain are silicided at once (salicide process), electrical insulation between the gate, source and drain can be maintained. The drawback is that it becomes difficult.
[0014]
In addition, the selective silicon growth film is thinned in a region adjacent to the gate electrode. For this reason, the shortest distance from the metal-deposited layer to the bonding surface is determined by this portion, and the function of suppressing the junction leakage is limited no matter how thick the selected silicon growth film is.
[0015]
[Problems to be solved by the invention]
As described above, with the miniaturization of the MOS field effect transistor, it is necessary to provide a silicide layer in order to keep the junction position of the source / drain region shallow and to keep the electric resistance of the source / drain region low. However, it becomes difficult to keep the unavoidable high-speed diffusion of the metal atoms forming the silicide layer and the junction leakage caused by the diffusion. When realizing an ESD structure to eliminate this difficulty, the selective silicon growth layer must be formed thick enough to match the height of the gate electrode, and uniform and uniform film formation was extremely difficult. .
[0016]
The present invention has been made in consideration of the above-described circumstances. The object of the present invention is to provide a shallow source / drain region in a structure in which a silicide layer is provided in order to reduce the resistance of the source / drain region. An object of the present invention is to provide a MOS field-effect transistor that can sufficiently suppress junction leakage while maintaining the pn junction position and can reduce the thickness of a silicon layer formed on the source / drain regions, and a method for manufacturing the same.
[0017]
[Means for Solving the Problems]
(Constitution)
In order to solve the above problems, the present invention adopts the following configuration.
[0018]
That is, the present invention is a method for manufacturing a MOS field effect transistor having a silicide layer on top of a source / drain region formed on a surface portion of a silicon substrate with a gate electrode interposed therebetween, On the source / drain region, a film having an end portion separated from the gate electrode by a predetermined distance and selectively removable with respect to silicon, and an end portion partially protruding on the gate electrode side on the selectively removable film A step of forming a silicon layer for silicidation, a step of forming a sidewall insulating film on a side portion of the gate electrode so as to cover an end of the silicon layer for silicidation, and the selectively removable film By removing, a gap is formed between the source / drain regions and the silicon layer for silicidation. Forming, and For silicidation Forming a metal film on the silicon layer, siliciding the metal film, and filling the gap After the amorphous silicon layer is formed, the silicon layer is crystallized by heat treatment, Forming a connecting silicon layer.
[0019]
Here, preferred embodiments of the present invention include the following.
(1) Co was used as the metal film.
(2) A side wall insulating film is formed on the side of the gate electrode, and a silicidation silicon layer is formed so as to be held by the side wall insulating film.
(3) As a step of forming a silicidation silicon layer, a silicidation silicon layer is formed on a source / drain region via a TiN film, and then the TiN film is selectively removed.
[0020]
(4) As a step of forming a silicon layer for silicidation, after forming a TiN film on the source / drain region so that the end is separated from the gate electrode by a predetermined distance, the end is on the gate side on this TiN film. A silicon layer for silicidation is formed so as to partially protrude, and then a sidewall insulating film is formed on the side of the gate electrode so as to cover the end of the silicon layer for silicidation, and then the TiN film is selectively removed. To do.
(5) As a step of forming the connecting silicon layer, an amorphous silicon layer is formed in the gap by a CVD method, and then the silicon layer is crystallized by heat treatment.
[0021]
The present invention also includes a gate electrode formed on a silicon substrate via a gate insulating film, a source / drain region formed on the surface of the substrate across the gate electrode, and a side portion of the gate electrode. A sidewall insulating film; a first silicon layer formed on the source / drain region; a second silicon layer formed on the first silicon layer; and a second silicon layer formed on the second silicon layer. The second silicon layer is formed so that the end on the gate side penetrates into the side wall insulating film, and the silicide layer is formed from the upper surface of the second silicon layer by Co. And is formed by reacting with the second silicon layer. The portion of the sidewall insulating film The distance from the surface to the pn junction surface formed by the source / drain region is 150 nm or less, and the concentration of Co which is a silicide metal is 1 × 10 5 at the pn junction surface formed by the substrate and the source / drain region. ¹⁶ cm ^-3 It is characterized by the following.
[0022]
Here, preferred embodiments of the present invention include the following. That is, The first silicon layer is formed so as to partially extend on the element isolation region.
[0026]
In order to prove this, FIG. 2 shows SIMS measurement results showing Co atoms diffused in the substrate. 1 × 10 in this figure ¹⁶ cm ^-3 The value corresponds to the detection limit of SIMS. Thus, high-speed diffusion of metal atoms inevitably proceeds on the surface where the metal and silicon are in contact. When current leaks through the junction due to metal atoms that have penetrated deep into the substrate, the operation of the element is impaired, or information written in a memory element such as a DRAM is lost, which is the original function of the semiconductor device. Is lost.
[0027]
From the above results, the concentration of Co is sufficiently low (1 × 10 ¹⁶ cm ^-3 In the case of the following, since the junction leakage is extremely small, it can be seen that the leakage current can be suppressed by forming a pn junction at a depth of 150 nm or more from the substrate surface. However, as described above, the source / drain regions have to be formed shallowly in order to suppress the short channel effect of the MOSFET. Furthermore, in the ESD structure, if the selective silicon growth layer is formed to a thickness of 150 nm or more, leakage current can be suppressed. However, if such a thick growth layer is formed, uniform and uniform film formation becomes difficult. It becomes impossible to accurately align the pn junction of the drain region with the target position.
[0028]
Accordingly, the source / drain regions are formed by the shallow diffusion layer, and the thickness of the silicon layer formed on the source / drain regions is sufficiently thin (the distance from the silicon layer surface to the pn junction of the source / drain regions is 150 nm or less) And the Co concentration in the pn junction of the source / drain regions is 1 × 10 ¹⁶ cm ^-3 If the following can be set, all the above problems will be solved. For this reason, in the present invention, a silicon layer for silicidation is formed in a region where a silicide layer is to be formed via a gap from the source / drain region, and the silicon layer is not contacted with the source / drain region. By reacting with Co from the upper surface to form a silicide layer, diffusion due to silicidation of Co is prevented. Then, a silicide layer is connected to the source / drain region by forming a connection silicon layer in the gap.
[0029]
This idea can be applied not only to Co but also to other metals. In addition, the manufacturing method is not limited to this, and the thickness of the additionally formed silicon layer is 150 nm or less (more strictly speaking, the depth of the pn junction surface formed by the substrate and the source / drain regions and the thickness of the silicon layer). And the concentration of Co which is a silicide metal at the pn junction surface is 1 × 10 ¹⁶ cm ^-3 The following is sufficient.
[0030]
More specifically, the present invention relates to an element structure in which voids 701 and 702 are inserted below the silicon layers 521 and 522 to be silicided with metal (Co in the embodiment), as will be described later (FIG. 5F). Form. For this purpose, as is conventionally done, a silicidation reaction is advanced by depositing a metal film and performing a heat treatment. The diffusion of metal atoms is blocked by the gaps 701 and 702, and the metal atoms do not reach the pn junction surface formed in the substrate portion. Thereafter, an amorphous silicon layer containing conductive impurities is buried in the gaps 701 and 702 at low temperature, and electrical connection with the source / drain diffusion layers 111 and 112 is performed. This process is sufficiently cold so that metal atoms do not diffuse. Therefore, the junction leak accompanying this does not occur.
[0031]
Further, since metal atoms do not diffuse and reach the pn junction surface formed in the substrate portion, the film thickness of the silicon layer additionally formed in the source / drain regions is at least that of the silicon layer consumed by silicidation. The film thickness may be greater than that, and it is not necessary to increase the thickness unnecessarily in order to prevent diffusion of metal atoms. Furthermore, the junction depth of the extension portion of the source / drain region does not need to take into account junction leakage accompanying silicidation, and can be set to an arbitrary depth necessary for design. Further, the depth of the junction is kept constant regardless of the thickness of the additionally formed silicon layer. As a result, the bonding surface is accurately maintained at a desired target position under the surface of the silicon substrate (surface on which the channel is formed), so that the short channel effect due to the displacement of the bonding surface is prevented, and the threshold voltage is reduced. Controllability is maintained.
[0032]
Furthermore, a silicon layer additionally formed on the source / drain regions can be arbitrarily extended on the element isolation region. For this reason, the parasitic capacitance between the source / drain regions and the substrate can be reduced, and the portion extended at the same time can be used as a part of the local electric wiring. In addition, with this structure, it is possible to suppress the occurrence of junction leakage due to an abnormal silicidation reaction in the periphery of the element isolation. In addition, since the silicide layer has a free end and proceeds on a suitable silicon layer held in the air, it is possible to avoid the volume change caused by silicidation and the generation of stress due to this, and a new junction due to this. Leakage can be suppressed.
[0033]
In addition, this void can be filled with a semiconductor material containing a high concentration of impurities at low temperature after silicide formation. Therefore, diffusion of metal atoms is prevented, and at the same time, diffusion of impurities accompanying silicidation heat treatment can be avoided, and source / drain regions having a very steep impurity distribution can be formed.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
The details of the present invention will be described below with reference to the illustrated embodiments.
[0035]
FIG. 3 is a cross-sectional view showing an element structure of a MOSFET according to an embodiment of the present invention. This FET has a salicide type ESD structure in which Co atoms are prevented from diffusing into the substrate.
[0036]
In the figure, reference numeral 100 denotes a p-type silicon substrate, and element isolation regions 101 and 102 are formed so as to surround an element formation region on the substrate 100. In the element formation region surrounded by the element isolation regions 101 and 102, a gate electrode 300 made of polysilicon is formed through a gate insulating film 200 made of a silicon oxide film. On the surface layer of the substrate 100 with the gate electrode 300 interposed therebetween, an n type having a conductivity type opposite to that of the substrate ⁺ Type diffusion layers (source / drain regions) 111 and 112 are formed.
[0037]
A first silicon layer 900 (901, 902) for connection is formed on the source / drain regions 111, 112, respectively, and a second silicon layer 520 (521, 522) for silicidation is formed thereon. Is formed. The silicon layer 900 is formed apart from the gate electrode 300 on the gate side, and partially extends on the element isolation regions 101 and 102 on the side opposite to the gate electrode 300. The silicon layer 520 has an end protruding from the silicon layer 900 on the gate side, and is formed in a non-contact manner with the gate electrode 300. A silicon layer 520 (523) is formed on the gate electrode 300 through a conductive film 403 such as TiN.
[0038]
A silicide layer 800 (801, 802, 803) is formed on the silicon layer 520 by reacting with Co from the upper surface. The silicide layer 800 is formed so as to leave a part of the lower portion, not the entire silicon layer 520. Sidewall insulating films 600 (601 and 602) are formed on the side surfaces of the gate electrode 300. The sidewall insulating film 600 covers the gate side end portions of the silicon layers 521 and 522.
[0039]
Next, a method for manufacturing the MOSFET of this embodiment will be described based on the process cross-sectional views of FIGS. 4 and 5.
[0040]
First, as shown in FIG. 4A, a basic structure of a MOS transistor was created using a known manufacturing technique. That is, the element isolation regions 101 and 102 were etched so as to surround the element formation region of the silicon substrate 100, and then a silicon oxide film was embedded in the region. Subsequently, in the element formation region surrounded by the element isolation regions 101 and 102, a gate electrode 300 made of polysilicon is formed on the substrate surface via a gate insulating film 200 made of a silicon oxide film. In addition, diffusion layers 111 and 112 having a conductivity opposite to that of the substrate and forming part of the source / drain regions were formed.
[0041]
Next, as shown in FIG. 4B, a conductive material that can be selectively removed from silicon, such as a TiN film 400, is deposited on the entire surface of the substrate to a thickness of, for example, 10 nm using a sputtering method or the like. To deposit. Subsequently, a silicon layer 500, which is a semiconductor material in which additional source / drain regions are to be formed, is deposited on the entire surface with a film thickness of, for example, 40 nm using a CVD method or the like. The silicon layer 500 preferably contains the same conductive impurities as the diffusion layers 111 and 112 in advance. Of course, it is also possible to introduce conductive impurities after the silicon layer is formed.
[0042]
Next, this structure is exposed to a carbon-containing plasma, and carbon is selectively introduced into the horizontal surfaces 501, 502, and 503 of the silicon layer 500 as shown in FIG. The carbon-containing plasma can be generated in an effective manner within the known art. The source of carbon can be any source that can supply carbon into the plasma. For example, carbon-containing plasma is CF _Four , CHF _Three , CCl, CH _Four It can generate | occur | produce by supplying gas, such as, in plasma.
[0043]
In general, the plasma becomes positive with respect to surrounding materials in order to maintain the state. As a result, an electric field is generated from the plasma in a direction in which particles having a positive charge with respect to the surrounding substance are vertically incident. Therefore, the positively charged carbon particles in the plasma collide perpendicularly with the horizontal planes 501, 502, and 503 of the silicon layer 500. On the other hand, carbon particles are not injected into the vertical surfaces 511 and 512. Since the incident particles from the normally used RIE (Reactive Ion Etching) plasma are accelerated at 1 KV or less, the thickness of the carbon-containing silicon layer is only tens of angstroms. The carbon content of the carbon-containing silicon layer may be 1 atomic% or more.
[0044]
Then, as disclosed in US Pat. No. 6,051,509, when the carbon-containing silicon layer is thermally oxidized and the formed oxide film is immersed in a 200: 1 diluted HF solution, etching in the diluted HF solution is performed. The progress almost stops at a certain place (1-2 nm). Therefore, an oxide film can be selectively formed only on the horizontal planes 501, 502, and 503 of the silicon layer 500, and the vertical surfaces 511 and 512 can be exposed. The exposed silicon vertical surfaces 511 and 512 can be selectively removed using, for example, a CDE (Chemica 1 Dry Etching) method using an oxide film on the horizontal planes 501, 502, and 503 as a mask.
[0045]
Further, by immersing the vertical side portions 401 and 402 of the TiN film 400 exposed on the side portion of the gate electrode from which the silicon vertical surfaces 511 and 512 are selectively removed, for example, in a mixed solution of sulfuric acid and hydrogen peroxide solution, Further, it can be selectively removed. At this time, the time of immersion in the mixed solution is adjusted so that the TiN films on the gate side lower portions 301 and 302 of the silicon layer horizontal portions 501 and 502 are also slightly retracted. FIG. 4D shows a cross-sectional view after processing the semiconductor substrate of FIG. 4C based on the above description.
[0046]
Next, a silicon nitride film as an insulator film is deposited on the entire surface of the semiconductor substrate of FIG. At this time, silicon nitride films are also formed on the gate side lower portions 301 and 302 of the silicon layer horizontal portions 501 and 502. Next, gate sidewall insulating films 601 and 602 are formed by selectively anisotropically etching this in the vertical direction by the RIE method. At this time, the silicon nitride films on the gate side lower portions 301 and 302 of the silicon layer horizontal portions 501 and 502 remain, and the silicon layer horizontal portions 501 and 502 are supported. Further, a TiN film 403 is present on the gate electrode in a form of being enclosed in the gate sidewalls 601 and 602. FIG. 5E shows a cross-sectional view of the semiconductor substrate at this stage.
[0047]
Next, as shown in FIG. 5 (f), the silicon layer 501 and 502, which are additionally formed, except for necessary portions such as portions used for local electric wiring on the source and drain, are formed by, for example, lithography. Remove using RIE method. At this time, portions 521 and 522 (silicidation silicon layers) forming the source and drain of the remaining silicon layer cover the diffusion layers 111 and 112 and cover the element isolation regions 111 and 102. As a result, the parasitic capacitance between the source / drain and the substrate can be reduced.
[0048]
Thereafter, the semiconductor substrate is immersed in a mixed solution of sulfuric acid and hydrogen peroxide solution, and the remaining TiN film 400 is removed by isotropic etching without remaining. As a result, voids 701 and 702 are formed below the silicon portions 521 and 522 forming the source and drain, and these silicon portions 521 and 522 are held in the air by the gate sidewall insulating films 601 and 602.
[0049]
At this time, the insulating films forming the gate sidewall insulating films 601 and 602 exist between the silicon portions 521 and 522 forming the source and drain and the diffusion layers 111 and 112 in the gate side lower portions 301 and 302. This ensures the function of the source / drain extension of this part. In addition, part of the silicon portions 521 and 522 that have penetrated into the gate side wall insulating films 601 and 602 exerts the effect of the source and drain voltages on the source and drain extension portions through the insulating film, thereby suppressing depletion of these portions and electric resistance. In other words, it is expected to serve as an auxiliary gate electrode.
[0050]
On the other hand, the TiN film 403 on the gate electrode remains because it is sealed with the gate sidewall insulating films 601 and 602. Of course, after the TiN film 400 is formed and processed into an appropriate pattern, the silicon layer 500 is formed, and if the above procedure is performed, in addition to the gate sidewall insulating films 601 and 602, the silicon portions 521 and 522 are formed as elements. It goes without saying that it can have a support point directly on the separation.
[0051]
Next, Co is deposited on the entire surface of the semiconductor substrate to a thickness of 10 nm, for example, by sputtering or the like. At this time, it should be noted that the silicon layer portions 521 and 522 forming the source and drain are covered on the diffusion layers 111 and 112, and Co is not deposited.
[0052]
Next, this semiconductor substrate is subjected to rapid thermal processing in nitrogen at, for example, 500 ° C. for 30 seconds, and a silicidation reaction is selectively advanced with silicon in direct contact with Co. As a result, silicide regions are formed on the source 801, the gate 803, and the drain 802. In silicidation, it is desirable that the silicon portions 521 and 522 forming the source and drain are not consumed and the silicon portion remains at the bottom. In this case, the final thickness of the silicide layer is about 35 nm. Unreacted Co on the element isolation region is selectively removed by dipping in a mixed solution of sulfuric acid and hydrogen peroxide. Further, rapid thermal processing is performed in nitrogen at, for example, 800 ° C. for 30 seconds to further reduce the electrical resistance of Co silicide. FIG. 5G shows a cross-sectional view of the semiconductor substrate at this stage.
[0053]
Next, as shown in FIG. 5 (h), an amorphous silicon layer (for connection) is formed to fill the gaps 701 and 702 and to electrically connect the silicon portions 521 and 522 forming the source and drain and the diffusion layers 111 and 112, respectively. (Silicon layer) 900 is uniformly deposited on the surface of the substrate. The deposition of this amorphous silicon layer 900 is within the scope of known techniques, for example, SiH at 0.2 Torr, 400 ° C. _Four It can be easily formed by using a gas.
[0054]
Since the alpha silicon layer 900 is formed on the entire surface, it should be noted that the alpha silicon layers 901 and 902 are also formed below the silicon layer portions 521 and 522 so as to fill the gaps 701 and 702. It is. SiH _Four PH to gas _Three Or B ₂ H ₆ The amorphous silicon layer 900 has the same conductivity as the source and drain. Thereby, the electrical connection between the silicon layer portions 521 and 522 and the diffusion layers 111 and 112 is completed.
[0055]
Note also that TiN is already sealed between the gate electrode 300 and the silicide region 803 above this, so that the electrical connection has already been completed. Of course, TiN on the gate is removed, and gaps similar to 701 and 702 can be formed between the gate electrode 300 and the silicide region 803 thereon. In this case, it goes without saying that the gap is filled in this step and electrical connection is achieved.
[0056]
Thereafter, the amorphous silicon layer 900 on the substrate surface is removed by using an isotropic etching method such as a CDE method. The amorphous silicon layer 900 on the side of the gate electrode and the element isolation is removed, and at the same time, the silicide regions 801, 802, and 803 are exposed. Subsequently, for example, heat treatment is performed in a nitrogen atmosphere at 600 ° C. for 30 seconds to crystallize the amorphous silicon layers 901 and 902 using the silicon of the diffusion layers 111 and 112 as seeds. Thereby, the structure shown in FIG. 3 is completed. According to the experimental results of the present inventors, the diffusion distance of the leak source due to Co in this heat treatment is limited to 1 nm or less. Therefore, no leakage occurs from the shallow source / drain diffusion layers 111 and 112.
[0057]
In this way, the gate, source, and drain are silicided while providing the very shallow source / drain diffusion layers 111 and 112, and the diffusion of metal atoms is suppressed, so that the junction leakage is extremely low. . In addition, the source and drain lifting structure with the minimum height is possible, and part of the source and drain can be used as local electrical wiring on the element isolation, and at the same time, part of it is embedded in the gate sidewall. The completed MOSFET device is completed. Subsequently, using a known technique, the semiconductor device is completed through the formation of an interlayer insulating film and contacts to each electrode through the interlayer insulating film, as well as a wiring process and a mounting process.
[0058]
As described above, according to the present embodiment, the following effects can be obtained.
(1) As shown in FIGS. 5F and 5G, by taking an element structure in which voids 701 and 702 are inserted below additional silicon layers 521 and 522 formed on the source / drain regions 111 and 112, respectively. Even if a silicidation metal is deposited and heat-treated to advance the silicidation reaction as is conventionally done, metal atoms do not diffuse and reach the bonding surface formed in the substrate portion. Therefore, the junction leak accompanying this does not occur.
[0059]
(2) Further, since metal atoms do not diffuse and reach the bonding surface formed in the substrate portion, the film thicknesses of the additional silicon layers 521 and 522 to be the source and drain are at least consumed by silicidation. It is sufficient that the thickness is equal to or greater than the thickness of the silicon layer, and it is not necessary to increase the thickness unnecessarily in order to prevent diffusion of metal atoms.
[0060]
(3) Further, the junction depth of the extension portions of the source and drain can be set to an arbitrary depth necessary for design because it is not necessary to consider junction leakage accompanying silicidation. Further, the depth of the junction is kept constant regardless of the thickness of the silicon layers 521 and 522 to be additionally formed. As a result, the bonding surface is accurately maintained at a certain position below the surface of the silicon substrate (the surface on which the channel is formed), so that the short channel effect due to the displacement of the bonding surface is prevented and the threshold voltage is controlled Is preserved.
[0061]
(4) By extending the silicon layer to be the source and drain on the element isolation insulating film, the parasitic capacitance between the source and drain and the substrate can be reduced, and at the same time, it can be used as a part of local electrical wiring. Is possible.
[0062]
(5) In addition, with this structure, it is possible to suppress the occurrence of junction leakage due to abnormal silicidation reaction in the periphery of the element isolation. In addition, since silicidation proceeds with a good silicon layer that has a free end and is held in the air, it is possible to avoid volume changes due to silicidation and the generation of stress due to this, thereby creating a new junction. Leakage can be suppressed.
[0063]
(6) Further, after the silicide is formed, this void can be filled with a semiconductor material containing a high concentration of impurities at a low temperature, and the diffusion of impurities accompanying the silicidation heat treatment is avoided at the same time as the diffusion of metal atoms does not proceed. Sources and drains having a very steep impurity distribution can be formed.
[0064]
(7) If the TiN film is formed by selectively removing the TiN film by etching and the TiN film on the gate is sealed by the gate sidewall and left, the gate electrode and the additionally formed silicide region on the silicon The electrical connection is easily achieved.
[0065]
(8) In the lower part of the gate side part, the insulating film forming the gate side wall exists between the silicon part forming the source and drain and the shallow diffusion layer forming the source and drain extension part. The etched silicon portion exerts the source and drain voltage effects on the source and drain extension portions through the insulating film, and the depletion of this portion can be suppressed and the electric resistance can be reduced. In other words, the silicon portion that has penetrated into the gate side wall can serve as an auxiliary gate electrode.
[0066]
(Modification)
In addition, this invention is not limited to embodiment mentioned above. Although the embodiments have been described using a single MOSFET, the above method can be similarly applied to a plurality of elements, and can be selectively applied to an element group that forms a part of a semiconductor device. Needless to say, this is applicable. Furthermore, it is needless to say that the present invention can also be applied to a conductive MOSFET different from the embodiment.
[0067]
Further, the formation under the silicidation silicon layer is not necessarily limited to the TiN film, and a material that can be selectively peeled off from silicon, silicon oxide film, or silicon nitride film may be used. For example, a carbon film may be used instead of the TiN film, and the carbon film may be selectively peeled off by oxygen radicals in the step shown in FIG. Then, a silicon layer may be formed in the gap formed by removing the carbon film as described in FIG.
[0068]
Further, instead of the TiN film, it is also possible to use a conductive substance having a diffusion blocking ability such as WSi or TiSiN. In this case, the steps shown in FIG. 5G and the subsequent steps can be performed without forming the voids shown in FIG. 5F and leaving them on the gate, the source, and the drain.
[0069]
In addition, after the TiN film is processed into an appropriate shape, a silicon layer may be formed so that the additional silicon layer is held in the air even at a fulcrum other than the gate side wall. Further, it should be noted that the silicidation metal is not limited to Co, and the present technique is effective when any metal material is formed on the source and drain.
[0070]
In addition, various modifications can be made without departing from the scope of the present invention.
[0071]
【The invention's effect】
As described above in detail, according to the present invention, in a MOS field effect transistor having a silicided structure for reducing the resistance of the source / drain regions, the source / drain regions are formed in the regions where the silicide layers are to be formed. After forming a silicon layer for silicidation through a void, a metal film is formed on the silicon layer, and then heat treatment is performed to silicidize the metal film, and then a silicon layer for connection is formed so as to fill the void. By forming the junction, leakage of junction can be sufficiently suppressed while maintaining the shallow pn junction position of the source / drain region, and the thickness of the silicon layer formed on the source / drain region can be reduced.
[0072]
Further, according to the present invention, in a MOS field effect transistor having a silicidized structure for reducing the resistance of the source / drain region, the Co silicide layer is formed via the silicon layer formed on the source / drain region. In the formed structure, the distance from the surface of the silicon layer to the source / drain junction surface is 150 nm or less, and the Co concentration is 1 × 10 5 at the pn junction surface of the source / drain region. ¹⁶ cm ^-3 By making the following, junction leakage can be sufficiently suppressed.
[0073]
According to the present invention, in a MOS field effect transistor having a silicidized structure for reducing the resistance of the source / drain regions, the second silicon is disposed on the source / drain regions via the first silicon layer. Forming a layer, forming an end of the second silicon layer so as to enter the gate sidewall insulating film, and reacting the second silicon layer with a metal from its upper surface to form a silicide layer; The silicon part biting into the side wall serves as an auxiliary gate electrode, and the effect of the source and drain voltage is applied to the source and drain extension through the insulating film, and the depletion of this part is suppressed and the electric resistance is reduced. can get.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining the diffusion of Co into a silicon substrate by a silicidation process and showing the relationship between junction depth and leakage current.
FIG. 2 is a diagram for explaining the diffusion of Co into a silicon substrate by a silicidation process and showing the relationship between the depth from the substrate surface and the Co concentration.
FIG. 3 is a cross-sectional view showing a device structure of a MOSFET according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view showing the first half of the manufacturing process of the MOSFET of the embodiment;
FIG. 5 is a cross-sectional view showing the second half of the manufacturing process of the MOSFET of the embodiment;
[Explanation of symbols]
100: Silicon substrate
101, 102 ... element isolation region
111, 112 ... Source / drain diffusion layer region
200: Gate insulating film
300 ... Gate electrode
301, 302 ... Lower side of the gate
400 ... TiN film
401, 402: TiN film on the side of the gate electrode
403 ... TiN film remaining on the gate electrode
500... Silicon layer for forming lifted source / drain
501, 502, 503... Horizontal plane of the additional silicon layer introduced with carbon atoms
511, 512 ... vertical plane of the additional silicon layer into which no carbon atoms are introduced
521, 522 ... Silicidation silicon layer (second silicon layer)
601 602... Gate sidewall insulating film
701, 702 ... void
801, 802, 803 ... silicide layers
900 ... Amorphous silicon layer
901, 902 ... Connection silicon layer (first silicon layer)

Claims (6)

A method of manufacturing a MOS field effect transistor having a silicide layer on top of a source / drain region formed on a surface portion of a silicon substrate across a gate electrode,
On the source / drain region, a film having an end portion separated from the gate electrode by a predetermined distance and selectively removable with respect to silicon, and an end portion partially protruding on the gate electrode side on the selectively removable film Forming a silicidation silicon layer;
Forming a sidewall insulating film on the side of the gate electrode so as to cover the end of the silicidation silicon layer;
Forming a gap between the source / drain regions and the silicidation silicon layer by selectively removing the selectively removable film;
Forming a metal film on the silicidation silicon layer;
Siliciding the metal film;
Forming an amorphous silicon layer so as to fill the void, and then crystallizing the silicon layer by heat treatment to form a connection silicon layer;
A method of manufacturing a MOS field effect transistor comprising:   2. The method of manufacturing a MOS field effect transistor according to claim 1, wherein Co is used as the metal film.   2. The method of manufacturing a MOS field effect transistor according to claim 1, wherein TiN is used as the selectively removable film.   2. The method of manufacturing a MOS field effect transistor according to claim 1, wherein a CVD method is used as the step of forming an amorphous silicon layer in the gap. A gate electrode formed on the silicon substrate via a gate insulating film, a source / drain region formed on the substrate surface across the gate electrode, a sidewall insulating film formed on a side portion of the gate electrode, A first silicon layer formed on the source / drain region; a second silicon layer formed on the first silicon layer; a Co silicide layer formed on the second silicon layer; Comprising
The second silicon layer is formed such that an end on the gate side enters the sidewall insulating film, and the silicide layer is formed by reacting the second silicon layer with Co from the upper surface thereof,
The distance from the surface of the portion of the second silicon layer entering the sidewall insulating film to the pn junction surface formed by the source / drain region is 150 nm or less, and the pn junction formed by the substrate and the source / drain region On the surface, a MOS field effect transistor characterized in that the concentration of Co which is a silicide metal is 1 × 10 ¹⁶ cm ⁻³ or less. 6. The MOS field effect transistor according to claim 5, wherein the first silicon layer formed on the source / drain region is partially extended on the element isolation region.

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