JP2000182983A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress dislocation and its propagation by providing a dislocation propagating region contg. O or N at a higher concentration than that in a semiconductor region between a dislocation region existing in the semiconductor region and a p-n junction plane. SOLUTION: A substrate is heat treated to diffuse an impurity introduced in Si layers 411, 412, 413 into the substrate from parts where the Si layers 411, 412, 413 contact the semiconductor substrate 100, thereby forming four diffused layers and activating conductive impurities in gate electrodes 311, 312 and Si layers 411, 412, 413. At this time, the diffusion process is adjusted so that O atoms reach an additional Si layer-substrate Si interface but not reach a p-n junction plane. O atoms are introduced in an interface which may providing nuclei of dislocation, and the dislocation and its propagation are suppressed without influencing on the p-n junction. Instead of O atoms, N atoms may be introduced to obtain the same effect.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a large-scale integrated semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In order to realize a high-speed and high-performance semiconductor device, demands for miniaturization of individual semiconductor elements used in the semiconductor device and large-scale integration thereof are increasing with time. However, when miniaturization of MOSFET, which is a main component of these semiconductor elements, is considered, this involves various difficulties.

For example, formation of element isolation for electrically insulating fine semiconductor elements must be achieved by a shorter distance for high-density integration of elements. However, in the LOCOS method in which the surface of a semiconductor substrate to be isolated is thermally oxidized to form an element isolation oxide film, the periphery of the element isolation oxide film extends to the element region.
There is a problem that the k phenomenon occurs, the effective element area is reduced, and fine element isolation cannot be performed.

[0004] For this reason, a groove Shallowtrench having a depth required for element isolation is formed in an element isolation region, and thereafter, a chemical vapor deposition method is formed in the groove.
A technique for forming an insulating material such as a silicon oxide film using Deposition (CVD) or the like, filling the trenches, flattening the main surface of the semiconductor substrate, and isolating elements.
Rench Isolation (STI) has been developed.

On the other hand, there is known a short channel effect in which a threshold voltage decreases as a channel length (length of a gate electrode) of a MOSFET decreases. In this short channel effect,
Since the threshold voltage greatly depends on the processing size of the gate electrode, if the processing size is reduced, it becomes impossible to obtain an element having the intended characteristics even with a slight processing deviation. This is extremely inconvenient particularly in the manufacture of a semiconductor circuit requiring a large number of uniform elements, for example, a dynamic random access memory (DRAM).

[0006] Such a short channel effect is caused by MOSFE
This is because the distortion of the electric field in the source and drain electrode portions of T affects the channel portion as the channel length is reduced. To suppress this effect,
It is known that the impurity concentration in the channel portion may be increased. However, if the impurity concentration in the channel portion is increased, the electric capacity between the substrate and the source / drain electrodes is increased, and the high-speed operation of the device is hindered. In order to solve such a problem, a technology (Silicon On Insulator, SOI) for forming a semiconductor element on a thin silicon layer formed on an insulating film has been developed.

The short channel effect can also be avoided by bringing the junction of Pn-junction forming the source and drain closer to the semiconductor surface (ie, making the Pn-junction "shallow"). However, if the Pn- junction is simply made shallow, the resistance of the source and drain electrodes formed thereby increases, and the high-speed transmission of a signal transmitted through the element is hindered. Further, if the junction is shallow, if a contact for obtaining electrical contact is provided in this portion, the metal material constituting the contact diffuses downward and penetrates the junction, which may cause junction leakage. . In order to deal with such a problem, a semiconductor material is selectively formed on the surface of the semiconductor substrate where the source and drain electrodes are to be formed.
By moving the surface of this region above the original semiconductor surface (the surface on which the channel is formed) and forming a Pn-junction of the source and drain through the additional surface, the position of the junction is determined by the original semiconductor. Shallow to the surface (the surface where the channel is formed), but deep to the newly formed surface, thus the source,
Elevated sourcedrain method to secure the thickness of the electrode part forming the drain (thickness of the diffusion layer)
Has been used.

[0008]

There are the following problems in the above-described element isolation by STI and the elevated source drain structure. First, in the STI structure element, Shallo
A silicon oxide film formed by a CVD method or the like is used for filling the w trench. However, since the density is smaller than the thermal oxide film used in LOCOS, this CV
The D insulating film is liable to change its volume in the subsequent thermal process,
As a result, a large stress is concentrated on a part of the shallow trench, particularly on the corner of the bottom surface. Due to the large stress remaining at the corners of the bottom surface, dislocations are frequently generated, and there is a problem that severe junction leakage occurs when the dislocations cross the pn junction formed in the vicinity thereof. If a current leaks through the pn junction, there is a problem that the operation of the element is impaired, and in a storage element such as a DRAM, written information is lost, and the original function of the semiconductor device is lost.

Next, an epitaxial growth technique is used for an element having an elevated source drain structure, but this method is very sensitive to a surface state on which selective growth is performed.
For example, due to the natural oxide film on the substrate surface just before growth or the damage introduced during the processing of the gate electrode, the source,
Crystal defects having a disordered crystal structure remain in the drain region. Such a disorder of the crystal structure becomes a nucleus of the generation of dislocation, and there is a problem that when the generated dislocation crosses a pn junction constituting a source and a drain, severe junction leak occurs. When a current leaks through the junction, the operation of the element is impaired, and in a storage element such as a DRAM, written information is lost, and the original function of the semiconductor device is lost.

The present invention eliminates the above-mentioned disadvantages of the prior art, suppresses the occurrence of dislocations from the corners of the shallow trench and the interface between the additionally formed silicon layer and the substrate, and reduces the yield of the semiconductor device manufacturing process. It is an object of the present invention to provide a semiconductor device in which the manufacturing cost is reduced and a manufacturing method thereof is reduced.

[0011]

In order to achieve the above object, the present invention provides a method for selectively oxygenating only in the vicinity of a site where dislocation is likely to occur, such as an STI corner or an interface between a formed silicon layer and a substrate. Provided are a semiconductor device which suppresses generation and propagation of dislocations by introducing atoms and nitrogen atoms, and a method for manufacturing the same.

That is, the present invention provides a semiconductor region, a dislocation generation region existing in the semiconductor region, a pn junction surface existing in the semiconductor region, and a pn junction surface existing between the dislocation generation region and the pn junction surface. And a semiconductor device including a dislocation propagation region containing oxygen or nitrogen at a higher concentration than the semiconductor region.

The present invention also provides a semiconductor region, a corner portion of a shallow trench, a pn junction surface existing in the semiconductor region, and a semiconductor region existing between the corner portion of the shallow trench and the pn junction surface. And a dislocation propagation element region containing oxygen or nitrogen at a higher concentration.

Further, according to the present invention, immediately after the formation of the shallow trench, oxygen or nitrogen atoms are implanted so as to have a specific depression angle with respect to the substrate in a direction perpendicular to the channel width direction of the element region. A method for manufacturing a semiconductor device, wherein oxygen atoms or nitrogen atoms are selectively introduced only into the corners of the shallow trench.

Further, according to the present invention, an insulating film serving as a gate insulating film is formed in advance in a region where a gate electrode is to be formed, and thereafter, a silicon layer is additionally formed on the entire surface. Oxygen or nitrogen atoms are introduced, and the depth of the introduction is adjusted so that the oxygen atoms reach the interface between the additional silicon layer and the substrate silicon in the subsequent thermal process, but the deposition of oxygen or nitrogen atoms does not occur on the pn junction surface. There is provided a method of manufacturing a semiconductor device, characterized by adjusting.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail.
According to the present invention, since an oxygen atom or a nitrogen atom is present near the dislocation generation region, the oxygen or nitrogen atom is positively incorporated into the dislocation nucleus and changes the structure of the dislocation nucleus, thereby inhibiting dislocation movement. Therefore, by selectively introducing oxygen or nitrogen atoms only in the vicinity of a site where dislocation is likely to occur, such as an STI corner portion or an interface between the formed silicon layer and the substrate, the generated dislocation does not move over a long distance. Stay close to where it occurred. Therefore, even if dislocations are generated, they do not cross the pn junction, so that the electrical characteristics of the device are not affected. In particular, since oxygen rapidly diffuses in silicon, dislocation immobilization can be effectively achieved even in a low-temperature thermal process.

Further, according to the present invention, since oxygen atoms are selectively introduced avoiding the pn junction and the like, precipitates derived from oxygen atoms are not formed on the bonding surface. Therefore, there is no electric influence on the bonding of oxygen atoms. Therefore, even if there is a site where dislocations are likely to occur, it is possible to avoid the influence of the transition on the electrical characteristics of the element without high-temperature heat treatment, thereby improving the yield of the semiconductor device manufacturing process and reducing the manufacturing cost. A method of manufacturing a semiconductor device is achieved.

Next, a process of manufacturing a trench type DRAM with STI isolation formed on an SOI wafer according to the present invention at a high yield will be described. First, as shown in FIG.
N-type silicon semiconductor lower substrate 1100, silicon oxide film layer 11 formed on this n-type silicon semiconductor lower substrate
02. A substrate on which the upper silicon layer 1101 formed on the silicon oxide film layer 1102 is prepared. On this substrate, a pad silicon nitride film layer 1103 is formed, and a trench 1201 extending from the pad silicon nitride film layer 1103 and the upper silicon layer 1101 to the lower silicon substrate 1100 through the silicon oxide film layer 1102 is formed.

The trench 1201 is formed by an RIE process, and is formed by a CVD process and a CMP process. The capacitor insulating film 1202 formed on the inner wall of the n-type silicon semiconductor lower substrate 1100 and a node filling the inside of the trench 1201 to the surface of the upper silicon layer 1101. Is formed, and a deep trench (DT) for charge storage is formed.

The oxygen concentration of the upper silicon layer 1101 has dropped to about 10 ¹⁶ cm ^-3 due to the heat treatment during the wafer manufacturing process. n-type polysilicon layer 1203, insulating film 1
202, the n-type silicon semiconductor lower substrate 1100 is a DRAM
Is formed.

Next, as shown in FIG. 2, in order to achieve STI, a Lithography step and an RI
With an effective method among known techniques such as the E process,
Element region 130 where access MOSFET should be formed
1. Shallow trenches 1311 and 1312 surrounding this are formed.

Next, as shown in FIG.
Ion implantation of oxygen atoms adjusted so as to have a specific depression angle with respect to the substrate in a direction perpendicular to the channel width direction (perpendicular to the paper surface). At this time, the source 1 of the access MOSFET
It is preferable that ion implantation be performed in two directions a and b so that oxygen atoms are similarly implanted into the region 302 and the drain 1303 region. In some cases, oxygen atoms may be implanted only into the drain 1303 region (the side connected to the node polysilicon 1203, direction b). At this time, the oxygen atom concentration was 1 × 1 at the corners 1321 and 1322 of the shallow trench.
It is desirable that the adjustment be made in the range of 0 ¹⁷ cm ⁻³ −1 × 10 ¹⁸ cm ⁻³ . Generally, the channel direction of each cell of the DRAM is parallel to each other, and thus such oblique ion implantation can effectively introduce oxygen atoms only into the corner portions 1321 and 1322 of the shallow trenches in the source 1302 and drain 1303 regions. .

Since the upper surface of the element region 1301 is protected by the pad silicon nitride film layer 1103, oxygen atoms are not introduced into the channel region 1304. Therefore, by avoiding high-temperature heat treatment, the source 1302,
Shallow trench corner 132 of drain 1303 region
1,1322 only. Such a process can be performed without adding any new process such as a Lithography process other than ion implantation.

Next, as shown in FIG.
Shal with an effective method among known techniques such as P method
The low trenches 1311 and 1312 are filled with an insulating material 1311.1332 such as a silicon oxide film, and the surface thereof is flattened using a pad silicon nitride film layer 1103 or the like, and a known technique such as thermal oxidation or a CVD method is used. The gate insulating film 1305 is formed by an effective method. Thereafter, the gate electrode 1306 is formed by an effective method among known techniques such as a CVD method and an RIE method.
Further, the source electrode 1307 and the drain electrode 1308 are formed by an effective method among known techniques such as ion implantation and RTA. The drain electrode and the n-type polysilicon layer 1203 are electrically connected to each other.
Achieve structure.

Subsequently, after depositing a low dielectric constant insulating film as an interlayer film by, for example, a CVD method, a contact hole to a source electrode is formed by, for example, an RIE technique, and further, a wiring material such as Al is formed. The wiring is formed by using the RIE method or the like in a required shape, and a trench type SOI-DRAM semiconductor device with STI isolation is completed through a wiring process, a mounting process, and the like using a known technique. .

Although the above embodiment has been described using an SOI substrate as an example, it goes without saying that the present invention can be applied to an HAI substrate and an Epi substrate. A nitrogen atom may be introduced instead of an oxygen atom. A similar technique can be applied to the case where the element isolation is LOCOS.

Next, a salicide COMS type Elevat having a local wiring between the source and drain electrodes of the present invention.
ed source drain This shows a step of manufacturing a MOSFET structure with high yield.

First, as shown in FIG. 5, a silicon semiconductor substrate 100, a region (p-well) 101 formed in the silicon semiconductor substrate 100 and doped with a p-type impurity,
A region (n-well) 102 into which an n-type impurity is introduced, and a shallow trench 11 formed on the surface thereof
A substrate having an insulating material, such as a silicon oxide film 1200, and a gate insulating film 211, 212 formed on the surface thereof is prepared.

The semiconductor substrate provided with this element isolation region is:
Lithography process, RIE process, CVD (chemical va
Insulation film deposition by por deposition) and CM
It can be achieved by an effective method of a known technique such as flattening by P (chemical mechanical polishing), an ion implantation technique, and the like. Further, these gate insulating films are formed by thermally nitriding or thinning a 50 Å thin silicon nitride film 1201 on the surface of the silicon substrate 100.
After forming using an effective method of a known technique such as a (Jet Vapor Deposition) method, 211, 212, 111, 11
Parts other than the parts corresponding to 2,113 are covered with a mask material, for example, a thin silicon oxide film of 100 Å by using the Lithography method, and the exposed parts are exposed to, for example, a heated phosphoric acid (H ₃ PO ₄ ) solution. This can be achieved by selectively removing and further removing the thin oxide film serving as a mask material by exposing it to an HF solution. At this time, the end of the gate insulating film only needs to enter a region corresponding to a gap between the gate electrode and a source / drain electrode to be additionally formed thereafter. This is because the insulating film protruding from the gate electrode can be easily removed after the formation of the gate electrode and the additional source and drain electrodes. Therefore, the alignment accuracy of the lithography process necessary for forming the gate insulating film in advance is about the width of the source-drain, extension part,
Can be easily realized. The surface of the silicon substrate 100 has an extremely low oxygen concentration (about 10 ¹⁶ cm ⁻³ ) in order to form a defect-free layer (DZ layer).

Next, as shown in FIG. 6, a gate electrode constituting material 300 formed on one surface of the substrate, a region 301 into which an n-type impurity is introduced, and a p-type impurity are introduced. A region 302 is formed. These gate electrode constituent materials 300 are formed on the surface of the silicon substrate 100 by, for example, a polysilicon layer 300, using a known method such as a CVD method.
Is deposited, for example, in a thickness of 2,000 angstroms, and thereafter, a mask material, for example, a photo-resi
This can be achieved by forming st and selectively implanting n-type impurities and p-type impurities into the regions 301 and 302, respectively. The energy of the ion implantation is adjusted so that the impurity is substantially uniformly introduced into the polysilicon layer.
Since the CVD method is used, the selectivity required for the epitaxial growth technique is not required. At this time, the amount of oxygen mixed into the polysilicon layer is minimized (10 ¹⁶ cm ^−3).
Below). For this reason, it is easy to form a uniform silicon layer having a uniform thickness, and the variation in the thickness of the additional source and drain formation portions observed in the epitaxial growth technique is eliminated. Accordingly, when impurities to form the source and the drain are introduced from the additionally formed silicon surface to form a junction, a junction can be formed accurately at a target position.

Next, as shown in FIG.
Oxygen atoms are introduced into the polysilicon upper layer 1000 using, for example, an ion implantation method. Alternatively, a polysilicon layer containing a large amount of oxygen may be further deposited and formed. The introduction depth of oxygen atoms reaches the interface between the additional silicon layer and the substrate silicon by heat treatment, but is adjusted so that the deposition of oxygen atoms does not occur at the pn junction surface formed on the substrate. Since oxygen atoms diffuse faster than B and P, it is desirable to introduce oxygen only into the upper portion. As a result, oxygen atoms are introduced into the interface that can serve as a nucleus of the transition, thereby suppressing the occurrence and propagation of the transition, and does not affect the pn junction by oxygen precipitation or the like. In addition, such a process is not limited to ion implantation or a CVD process.
It can be performed without adding a new process such as an ography process.

Next, as shown in FIG. 8, after the RIE process, the gate electrodes 311 and 312 formed on the p-well, 101, n-well and 102 are added to the source and drain regions, respectively. Silicon layers 411, 41 formed
2,413 are formed. Since the silicon layers 411, 412, and 413 additionally formed on the gate electrodes 311 and 312 and the source and drain regions can be formed at one time, the Elevated Source / Drain structure can be achieved. Therefore, it should be noted that manufacturing costs can be reduced. At this time, the ends of the gate insulating film are connected to the gate electrodes 311 and 312 and the additionally formed silicon layer 411 and 312, respectively.
Gap 511, 512, 513, 51 with 412, 413
It suffices if it is in the area corresponding to 4. The additionally formed silicon layers 411, 412, and 413 correspond to the element isolation region 1
11, 112 and 113 to reduce the capacity of the source and drain electrodes and the semiconductor substrate. Further, the additionally formed silicon layer 412 has p-well, 101, n-
well and 102 regions are connected. Thus, not only the additional formation of the source and drain electrodes but also a local inter-element wiring step can be simultaneously formed by this silicon layer. Therefore, a new local element wiring step is not required, and the manufacturing cost can be reduced.

Thereafter, the substrate is subjected to a heat treatment, and the silicon layers 411, 412, 413 are removed from the portions where the silicon layers 411, 412, 413 are in contact with the semiconductor substrate 100.
Is diffused into the substrate to form a diffusion layer 611,
Simultaneously with the formation of 612, 613, 614, the gate electrodes 311, 312, silicon layers 411, 412, 413
Activate the conductive impurities therein. At this time, the diffusion process
It is adjusted so that oxygen atoms reach the additional silicon layer-substrate silicon interface, but do not reach the pn junction surface. Oxygen atoms are introduced into the interface that can be the nucleus of the transition, suppressing the occurrence and propagation of the transition, and does not affect the pn junction.
The oxygen concentration at this time is preferably within the range of 1 × 10 ¹⁷ cm −1 × 10 ¹⁸ cm ^{−3 at} the interface between the additional silicon layer and the silicon substrate.

Next, as shown in FIG.
The gate insulating film remaining on the 12, 513, 514 is removed by, for example, a heated phosphoric acid (H3 PO4) solution, and further, the gate electrodes 311.312 and the silicon layers 411, 412, 413 additionally formed, and lithogra
Using the photo-resist formed by the phy process as a mask,
The gaps 511, 512 and 513, 514 respectively
N-type and p-type impurities are ion-implanted. Further, for example, by performing a rapid rise and fall heat treatment on this, the impurities are activated,
Source-Drain Extension Department, 711, 712, 71
3,714 are formed. Shallow Source-Drain Extension
In addition to ion implantation technology, plasma immersion
Needless to say, it can be achieved by an effective method of a known technique such as doping, Gas imsersion laser dopong, or the like.

Next, as shown in FIG. 10, for example, a silicon oxide film is deposited at 2000 A by the CVD method, and thereafter, the gaps 511 and 5 are flattened by the CMP method.
12, 513, 514 are formed of low dielectric constant insulating films 811, 81.
2,813,814. At this time, the gate electrode 3
11, 312 and the additionally formed silicon layer 411,
The heights of the electrodes 412 and 413 are uniform. Therefore, it is very easy to flatten the surface. Subsequently, a metal selectively reacting with silicon, for example, Co, is deposited on the entire surface of the flattened surface by a sputtering method, and then subjected to a heat treatment, for example, a rapid heat treatment (R) at 500 ° C. in a nitrogen atmosphere.
TA), the silicidation is selectively advanced on the contact surface with silicon, that is, on the gate electrodes 311 and 312 and the additionally formed silicon layers 411, 412 and 413, and unreacted metal is removed. By treating and removing with a solution such as HNO3, silicide layers 901, 90
2, 903, 904, 905 are formed on the gate, source and drain in a self-aligned manner. Thus, a salicide structure can be realized.

Since the additionally formed source and drain electrodes are silicided, metal atoms diffuse in the source and drain and hardly reach the junction. For this reason,
Junction leakage can be prevented. In addition, the additionally formed silicon layer 412 and silicide layer 903 form local inter-element wiring.

Next, after depositing a low dielectric constant insulating film as an interlayer film by a CVD method or the like, contact holes to the source and drain electrodes are formed by, for example, RIE technology, and a wiring material such as Al is formed. Deposited, processed,
Further, using a known technique, a salicide CMOS type elevated source drain MOSFET structure having STI isolation and local wiring is completed through a wiring step, a mounting step, and the like.

Although the introduction of an oxygen atom has been used as an example,
Similar effects can be obtained with nitrogen atoms as well. A similar method can be applied to the case where the element isolation is LOCOS. The nitrogen concentration at this time is 1 × 10 ¹⁵ cm ⁻³ −1 × 10 ¹⁶
It is preferable to be within the range of cm ^-3 .

[0039]

According to the present invention, even if there is a site where a transition is likely to occur in the semiconductor device structure, a high-concentration oxygen region or nitrogen which is located between this portion and the pn junction surface and shuts off this region. By forming the region, the generation and propagation of dislocations are suppressed, and the dislocations are prevented from crossing the pn junction. The oxygen concentration and the nitrogen concentration at this time were 1 × 10
¹⁷ cm ^-3 -1 × 10 ¹⁸ cm ^-3 and 1 × 10 ¹⁵ cm ^-3 -1
It is preferable that the thickness be in the range of × 10 ¹⁶ cm ^-3 . Thus, a method of manufacturing a semiconductor device in which the yield of the semiconductor device manufacturing process is improved and the manufacturing cost is reduced is achieved.

In particular, by selectively introducing oxygen atoms or nitrogen atoms into the corners of the shallow trench, even if stress remains in this portion, oxygen or nitrogen atoms are positively incorporated into the transition nuclei, and It alters the structure and inhibits migration. Therefore, the generated transition stays in the vicinity where it occurred without moving over a long distance. Even if the transition occurs, it does not cross the pn junction, so that it does not affect the electrical characteristics.

Since oxygen or nitrogen atoms are selectively introduced avoiding the pn junction and the like, precipitates derived from oxygen atoms are not formed on the bonding surface. Therefore, there is no electric influence on the bonding of oxygen or nitrogen atoms.

Immediately after the formation of the shallow trench, oxygen or nitrogen atoms are implanted by ion implantation of oxygen or nitrogen atoms adjusted to have a specific depression angle with respect to the substrate in a direction perpendicular to the channel width direction of the element region. Thus, oxygen atoms can be effectively introduced only into the corners of the shallow trench in the source and drain regions. Further, since the upper surface of the element region is protected by the pad layer, oxygen or nitrogen atoms are not introduced into the channel region. Therefore, it can be performed without adding any new process such as a Lithography process other than ion implantation.

An insulating film serving as a gate insulating film is previously formed in a region where a gate electrode is to be formed, and thereafter, a silicon layer is additionally formed on the entire surface, and oxygen or nitrogen is formed on the silicon layer. The atoms are introduced and the depth of the introduction is reached in the subsequent thermal process to the additional silicon layer-substrate silicon interface, but the deposition of oxygen atoms or nitrogen atoms is p /
Adjust so that n impurities do not occur on the pn junction surface formed on the substrate.

As a result, oxygen or nitrogen atoms are introduced into the interface which can be the nucleus of the transition, thereby suppressing the occurrence and propagation of the transition, and without affecting the pn junction. Therefore, the yield of the semiconductor device manufacturing process is improved, and the manufacturing cost is reduced.

Such a step is performed by ion implantation or C
Other than the VD process, the process can be performed without adding any new processes such as a Lithography process. In addition, RIE (Re
active ion etching), a silicon layer to be additionally formed on the gate electrode and the source and drain regions can be formed at a time, so that the Elevated Source / Dr does not go through a new process such as selective growth by an epitaxial growth technique.
Ain structure can be achieved. Therefore, manufacturing costs can be reduced.

Further, according to the present invention, it is easy to form a uniform silicon layer having a uniform thickness, and the variation in the film thickness of the additional source and drain formation portions observed in the epitaxial growth technique is eliminated. Accordingly, when impurities to form the source and the drain are introduced from the additionally formed silicon surface to form a junction, a junction can be formed accurately at a target position.

The additionally formed source and drain electrodes can be arbitrarily placed on the element isolation insulating film. Therefore, the capacity of the source / drain electrodes and the semiconductor substrate is reduced by minimizing the area of the source / drain electrodes that can be formed on the semiconductor substrate and mounting most of them on the element isolation insulating screen. Becomes possible. Therefore, high-speed operation of the element is possible. The additional silicon layer does not necessarily have to correspond to one element, and may connect source and drain regions of a plurality of elements. As a result, not only the additional formation of the source and drain electrodes but also the local inter-element wiring can be simultaneously formed by this silicon layer. Therefore, a new local inter-element wiring step is not required, and the manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a process for manufacturing a trench DRAM with STI isolation formed on an SOI wafer at a high yield.

FIG. 2 is a cross-sectional view of a step of manufacturing a trench DRAM with STI isolation formed on an SOI wafer at a high yield.

FIG. 3 is a cross-sectional view of a step of manufacturing a trench DRAM with STI isolation formed on an SOI wafer at a high yield.

FIG. 4 is a cross-sectional view showing a step of manufacturing a trench DRAM with STI isolation formed on an SOI wafer at a high yield.

FIG. 5 is a salicide CMOS type elevated source drain MOS having local wiring between source and drain electrodes.
Sectional drawing of the process of manufacturing a FET structure with high yield.

FIG. 6 shows a salicide CMOS type elevated source drain MOS having local wiring between source and drain electrodes.
Sectional drawing of the process of manufacturing a FET structure with high yield.

FIG. 7 is a salicide CMOS type elevated source drain MOS having local wiring between source and drain electrodes.
Sectional drawing of the process of manufacturing a FET structure with high yield.

FIG. 8 shows a salicide CMOS type elevated source drain MOS having local wiring between source and drain electrodes.
Sectional drawing of the process of manufacturing a FET structure with high yield.

FIG. 9 shows a salicide CMOS type elevated source drain MOS having local wiring between source and drain electrodes.
Sectional drawing of the process of manufacturing a FET structure with high yield.

FIG. 10 shows a salicide CMOS type elevated source drain MO having local wiring between source and drain electrodes.
Sectional drawing of the process of manufacturing an SFET structure with a high yield.

[Explanation of symbols]

Reference Signs List 100 semiconductor substrate 101 p-well region 102 n-well region 111, 112, 113 shallow trench isolation 200 element isolation insulating oxide film 201, 211, 212 gate insulating nitride film 300 polysilicon 301 n-type polysilicon region 302 p-type polysilicon Region 311 n-type polysilicon gate electrode 312 p-type polysilicon gate electrode 411, 412, 413, polysilicon additional source / drain electrode 511, 512, 513, 514 Interval formed between gate electrode, additional source / drain electrode 611 , 612, 613, 614 Source / drain diffusion layers 711, 712, 713, 714 Extended source / drain regions 811, 812, 813, 814 Interlayer insulating films 901, 902, 903, 904, 905 Silicide region 1000 High concentration oxygen Existence area 1100 SOI wafer n-type silicon lower semiconductor substrate 1101 SOI wafer upper silicon layer 1102 SOI wafer insulating silicon oxide film layer 1103 pad silicon nitride film 1201 DRAM charge storage Deep Trench 1202 node insulating film 1203 node n-type polysilicon electrode 1301 access Element region for transistor 1302 Source region for access transistor 1303 Drain region for access transistor 1304 Channel region for access transistor 1305 Gate insulating film for access transistor 1306 Gate electrode for access transistor 1307 Source electrode for access transistor 1308 Drain electrode for access transistor 1311, 1312 Element isolation shallow trench 1321 Source region s into which oxygen atoms are introduced hallow t
Rench corner 1322 Shallow drain region into which oxygen atoms are introduced
trench corners 1331, 1332 CVD silicon oxide film

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 H01L 27/10 625A 21/336 671C 29/786 29/78 301R 301S 301Y 621 F Term (Reference) 5F032 AA35 CA03 CA17 CA20 DA60 5F040 DB03 DC01 EA08 EC01 EC07 EC13 EH02 EK01 EK05 EM10 FC11 FC15 FC19 5F048 AA04 AA07 AA09 AC03 BA01 BC01 BC05 BE03 BF04 BF05 BF06 BF07 BF15 BF16 AD03 GA03 AD03 GA03 AD04 HA10 JA02 JA32 NA01 NA02 PR12 PR21 PR34 PR37 PR40 5F110 AA06 AA16 BB04 BB06 DD05 GG02 GG39 HJ02 NN62 NN65 NN72

Claims (4)

[Claims] A semiconductor region; a dislocation generation region existing in the semiconductor region; a pn junction surface existing in the semiconductor region; and a dislocation generation region between the dislocation generation region and the pn junction surface; A semiconductor device comprising: a dislocation propagation blocking region containing oxygen or nitrogen at a higher concentration than a semiconductor region. 2. A semiconductor region, a corner of a shallow trench, a pn junction surface existing in the semiconductor region, and a region between the corner of the shallow trench and the pn junction surface which is higher than the semiconductor region. A dislocation propagation blocking region containing oxygen or nitrogen at a concentration. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the oxygen or nitrogen atoms are formed immediately after the formation of the shallow trench so as to have a specific depression angle with respect to the substrate in a direction perpendicular to the channel width direction of the element region. By performing the injection,
A method of manufacturing a semiconductor device, wherein oxygen atoms or nitrogen atoms are selectively introduced only into corners of the shallow trench in a source or drain region. 4. A method for manufacturing a semiconductor device according to claim 2, wherein an insulating film serving as a gate insulating film is formed in advance in a region where a gate electrode is to be formed, and thereafter, a silicon layer is formed on the entire surface. Additional formation, oxygen or nitrogen atoms are introduced into the upper part of this silicon layer, and the introduction depth is
A method of manufacturing a semiconductor device, characterized in that oxygen atoms reach the interface between the additional silicon layer and the substrate silicon in a subsequent heating step, but oxygen or nitrogen atoms are not deposited on the pn junction surface.