JP2007027502A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that relaxes a variation of semiconductor device current driving capability due to physical stress caused by an element separation film formed in a shallow trench isolation structure. <P>SOLUTION: This semiconductor device comprises a semiconductor substrate with a first area and a second area, a trench formed on the surface of the semiconductor substrate, an element separation isolating film buried in the trench and an active area formed on the surface of the semiconductor substrate and defined by the element separation insulating film. In this semiconductor device. The height of the element separation insulating film surface differs in the first and second areas, and the height of an element separation insulating film in either one of the areas is lower than that of the semiconductor substrate surface. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an STI structure as element isolation.

  Conventionally, in STI (shallow trench isolation), which is an element isolation technique, an oxide film is buried in the surface of a silicon substrate, and the depth of the silicon substrate surface and the buried oxide film is as small as possible. The structure is designed so that the direction (the thickness of the buried oxide film) is constant.

  When element isolation by such shallow trenches (hereinafter referred to as STI element isolation) is provided, stress (stress, hereinafter referred to as STI stress) from the buried oxide film is generated. It is known that the current drive capability Ids of the transistor is greatly influenced by this STI stress, and the influence degree becomes larger as the length LOD of the active region is shorter. Here, the length LOD of the active region is the length in the gate length direction.

  Further, it is known that when the active region length LOD is shortened, the current drive capability Ids of the PMOS transistor increases, but the current drive capability Ids of the NMOS transistor decreases. For example, it has been found that the current drive capability Ids of a PMOS transistor increases up to about 10% while the current drive capability Ids of an NMOS transistor decreases up to about 10%.

  Regarding the current drive capability Ids, it is known that the stress from the lateral direction (gate length direction) is more dominant in the transistor as the active region length LOD is shorter. On the other hand, there is a stress from the vertical direction (gate width direction), but there is almost no influence on the current drive capability Ids.

  By the way, the magnitude of such STI stress varies depending on the manufacturing method, but is determined when the STI element isolation structure is formed. However, the STI stress received from the buried oxide film is not controlled after the formation of the STI element isolation structure. That is, at present, no technology has been established for controlling the STI stress that affects the current drive capability Ids of peripheral transistors to mitigate fluctuations in the current drive capability caused by the STI stress.

  The present invention has been made in view of the above, and the fluctuation of the current drive capability of a semiconductor device due to physical stress caused by an element isolation film formed by a shallow trench isolation structure is mitigated. It is an object of the present invention to obtain a semiconductor device that can achieve matching of current drive capability and can exhibit the original current drive capability.

  In order to solve the above-described problems and achieve the object, a semiconductor device according to the present invention includes a semiconductor substrate having first and second regions, a groove formed in a surface layer of the semiconductor substrate, and a groove embedded in the groove. And an active region formed on the surface layer of the semiconductor substrate and defined by the element isolation insulating film, the height of the surface of the element isolation insulating film between the first region and the second region In contrast, the element isolation insulating film in any one of the regions is lower than the surface of the semiconductor substrate.

  According to the present invention, since the physical stress generated from the buried oxide film for STI element isolation can be released by recessing the surface of the buried oxide film for STI element isolation, the buried oxide film for STI element isolation can be released. The fluctuation of the current driving capability of the semiconductor device due to the physical stress generated from the above can be reduced, and the original current driving capability of the semiconductor device can be derived. Therefore, according to the present invention, the fluctuation of the current drive capability of the semiconductor device due to the physical stress generated from the buried oxide film isolated from the STI element is alleviated, and the consistency of the current drive capability can be obtained. There is an effect that a semiconductor device capable of exhibiting the ability can be obtained.

  Embodiments of a semiconductor device according to the present invention will be described below in detail with reference to the drawings. In addition, this invention is not limited to the following description, In the range which does not deviate from the summary of this invention, it can change suitably.

  First, the concept of the present invention will be described. FIG. 1 is a cross-sectional view for explaining the concept of the present invention. In order to compare the PMOS region and the NMOS region of a semiconductor device (transistor), a part of the PMOS region and a part of the NMOS region are shown side by side. It is sectional drawing in the gate length L direction. FIG. 2 is a top view of the periphery of the active region.

  As shown in FIG. 1, an STI element isolation 2 in which an oxide film is embedded as element isolation is formed at a predetermined position on the surface layer of a semiconductor substrate 1, and a region sandwiched between the STI element isolation 2 is defined as an active region 3. ing. Gate structures 5 each including a gate electrode 4 are formed on the active region 3. Here, since the components other than the above-described components are not directly related to the present invention, description and explanation in the drawings are omitted.

  In the case of the structure in which the STI element isolation 2 is provided as described above, the stress (stress) received from the buried oxide film of the STI element isolation 2 in the gate length L direction is applied to the active region 3 in the PMOS region as shown in FIGS. (Hereinafter referred to as STI stress) A occurs. Also, stress (hereinafter referred to as STI stress) B generated from the buried oxide film of the STI element isolation 2 is generated in the active region 3 of the NMOS region in the gate length L direction as shown in FIGS.

  The STI stresses A and B are compressive stresses when viewed from the active region 3. It is known that the current driving capability of a transistor is greatly influenced by this STI stress, and the influence degree becomes larger as the length LOD of the active region is shorter. Here, the length LOD of the active region is the length in the gate length direction. For example, the current drive capability Ids of the PMOS transistor increases by about 10% at the maximum, and the current drive capability Ids of the NMOS transistor decreases by about 10% at the maximum.

  Therefore, in the present invention, for example, as shown in FIG. 1, the surface of the STI element isolation 2 in the NMOS region is recessed. Thereby, the stress of the active region edge portion can be released (compression stress seen from the active region 3). As a result, the STI stress (STI stress B) in the NMOS region can be reduced. That is, the STI stress B is smaller than the STI stress A. The difference in the magnitudes of the STI stress A and B arrows in FIGS. 1 and 2 schematically shows the difference in the magnitude of the STI stress.

  Further, by reducing the STI stress B, it is possible to suppress a decrease in current driving capability due to the STI stress of the NMOS transistor. Therefore, according to the present invention, the fluctuation of the current driving capability of the transistor due to the physical stress generated from the buried oxide film of the STI element isolation 2 is alleviated, and the consistency of the current driving capability is obtained. An NMOS transistor capable of exhibiting the capability can be obtained.

  For reference, FIG. 3 shows a diagram corresponding to FIG. 1 in a conventional semiconductor device. As shown in FIG. 3, in the conventional semiconductor device, since the STI stress B in the active region 3 in the NMOS region is not suppressed, the STI stress B in the active region 3 in the NMOS region is reduced in the active region in the PMOS region. 3 and substantially the same size as the STI stress A in FIG. Therefore, the current driving capability Ids of the PMOS transistor is increased by about 10% at the maximum, and the current driving capability of the NMOS transistor is decreased from the original current driving capability.

Embodiment 1 FIG.
FIG. 4A is a cross-sectional view in the gate length L direction showing a part of the PMOS region and a part of the NMOS region of the semiconductor device (transistor) according to the first exemplary embodiment of the present invention. FIG. 4B is a diagram for explaining the gate structure of the semiconductor device according to the present embodiment. FIG. 5 is a top view of the semiconductor device (transistor) according to the first embodiment. In FIG. 5, only the active region, the STI element isolation region, and the gate electrode are shown.

  As shown in FIG. 4A, in the semiconductor device according to the present embodiment, between the STI element isolation 12 and the STI element isolation 12 which are element isolations for isolating each element on the surface layer of the semiconductor substrate 11. A source / drain diffusion layer 14 formed at a distance from each other so as to define a channel region in an active region 13 in which a transistor element is formed, and a surface layer portion of the source / drain diffusion layer 14 at a distance from each other And a silicide layer 15 formed with a gap therebetween.

  Further, on the source / drain diffusion layer 14 on the semiconductor substrate 1 and on the region sandwiched between the source / drain diffusion layers 10, as shown in FIG. A gate structure 21 having a stacked structure in which a gate electrode 19 including an insulating film 16, a polysilicon electrode 17, and a metal electrode 18 having a silicide layer formed on the surface of the polysilicon electrode is stacked in this order is formed.

  Further, a sidewall spacer 20 made of an insulating film such as a nitride film is formed on the outer side, that is, the side surface of the gate structure 21. A liner film 22 made of, for example, a nitride film is formed on the STI element isolation 12, the silicide layer 15, the sidewall spacer 20, and the gate electrode 19 so as to cover them.

  An interlayer insulating film 23 covering the gate structure 21 and the STI element isolation 12 is formed on the semiconductor substrate 11. In the interlayer insulating film 23, a contact 24 made of a conductive material and reaching the silicide layer 15 from the upper surface of the interlayer insulating film 23 and conducting to the source / drain diffusion layer 14 is formed. A wiring layer 25 is formed which is electrically connected to the contact 24.

  In the structure in which the STI element isolation 12 is provided as described above, the stress (STI) received from the buried oxide film of the STI element isolation 12 in the gate length L direction as shown in FIGS. Stress) C is generated. FIG. 7 is an enlarged view around the edge portion of the active region 13 in FIG. Similarly, stress (not shown) received from the buried oxide film of the STI element isolation 12 is generated in the active region 3 of the PMOS region in the gate length L direction. These STI stresses are compressive stresses when viewed from the active region 13.

  These STI stresses are compressive stresses when viewed from the active region 13, and the current drive capability of the transistor is greatly influenced by this STI stress, and the degree of influence increases as the length LOD of the active region decreases. Here, the length LOD of the active region is the length in the gate length direction. For example, the current driving capability Ids of the PMOS transistor increases due to the influence of the STI stress, and the current driving capability Ids of the NMOS transistor decreases due to the influence of the STI stress.

  In the semiconductor device according to the present embodiment configured as described above, the surface of the STI element isolation 12 in the NMOS region is recessed as shown in FIG. By recessing the surface of the STI element isolation 12 in the NMOS region, in the semiconductor device according to the present embodiment, stress at the edge of the active region 13 in the NMOS region is released (relaxation of compressive stress viewed from the active region 13). ) As a result, the STI stress (STI stress C) in the NMOS region is kept small. That is, in this semiconductor device, the STI stress C is smaller than the STI stress in the PMOS region. As a result, it is possible to alleviate the decrease in current driving capability caused by the STI stress of the NMOS transistor and to draw out the original current driving capability of the NMOS transistor.

  Further, in this semiconductor device, a liner film 22 having a force in a direction to cancel the STI stress B, that is, a tensile stress D viewed from the active region 13 is formed on and around the recessed STI element isolation 12 in the NMOS region. ing. By forming this liner film 22, in this semiconductor device, the STI stress (STI stress C) in the NMOS region is offset by the tensile stress D of the liner film 22, and the effect of releasing the STI stress is further improved. Therefore, the STI stress is further reduced. As a result, it is possible to further alleviate the decrease in the current driving capability due to the STI stress of the NMOS transistor and to draw out the original current driving capability of the NMOS transistor.

  As described above, in the semiconductor device according to the present embodiment, it is possible to suppress a decrease in current driving capability due to the STI stress of the NMOS transistor by significantly reducing the STI stress in the NMOS region. Therefore, in the semiconductor device according to the present embodiment, the fluctuation (current decrease) of the current drive capability of the NMOS transistor due to the physical stress generated from the buried oxide film of the STI element isolation 12 of the NMOS transistor is alleviated. As a result, an NMOS transistor capable of exhibiting the current driving capability can be obtained, so that a semiconductor device having a matching current driving capability with the PMOS transistor is realized.

  It should be noted that the effect of releasing the STI stress by recessing the surface of the STI element isolation 12 as described above can be controlled by the amount of recess in the surface of the STI element isolation. Similarly, the effect of releasing the STI stress by the liner film 22 can be controlled by controlling the material and film thickness of the liner film.

  Next, a method for manufacturing the semiconductor device according to the present embodiment shown in FIG. 4A will be described with reference to the drawings. 8 to 14 are cross-sectional views illustrating the manufacturing process of the semiconductor device according to the present embodiment. First, a semiconductor substrate 11 is prepared, and an STI element isolation 2 which is an element isolation for isolating each semiconductor element is selectively formed on the semiconductor substrate 11 by an STI (shallow trench isolation) process as shown in FIG. Then, the active region 13 is formed by ion implantation of impurities such as impurity threshold adjusting impurities for well formation in the PMOS region and the NMOS region in the region delimited by the STI element isolation 12. Note that the edge portion of the upper surface of the STI element isolation 12 is formed in a rounded state.

  Next, as shown in FIG. 9, a mask 31 is formed with a photoresist in the PMOS region, and hydrofluoric acid treatment is performed using the mask 31 to recess the surface of the STI element isolation 12 in the NMOS region. The recess amount F at this time is, for example, about several nm. By using the mask 31, the STI element isolation 12 in the PMOS region is not recessed, and only the STI element isolation 12 in the NMOS region can be recessed.

  Thereby, the stress at the edge of the active region 13 in the NMOS region can be released (relaxation of the compressive stress seen from the active region 13), and the STI stress (STI stress C) in the NMOS region as shown in FIG. It can be kept small. That is, the STI stress C can be made smaller than the STI stress in the PMOS region. As a result, it is possible to alleviate the decrease in current driving capability caused by the STI stress of the NMOS transistor and to draw out the original current driving capability of the NMOS transistor.

  Next, as shown in FIG. 11, a gate insulating film 16 made of an oxide film and a polysilicon electrode 17 made of polysilicon are formed on the semiconductor substrate 11 by a conventionally known method.

  Next, as shown in FIG. 11, a source / drain diffusion layer 14 and sidewall spacers 20 are formed by a conventionally known method, and a silicide layer 15 and a metal electrode 18 are further formed. As a result, a gate structure 21 having a stacked structure in which the gate electrode 19 including the metal electrode 18 whose surface layer of the polysilicon electrode is silicided is stacked in this order.

  Next, as shown in FIG. 12, the STI element isolation 12, the silicide layer 15, the sidewall spacer 20, and the gate electrode 19 are made of, for example, a nitride film so as to cover them, and force in a direction to cancel the STI stress C, that is, A liner film 22 having a tensile stress D viewed from the active region 13 is formed.

  By forming this liner film 22, the STI stress (STI stress C) in the NMOS region can be offset by the tensile stress D of the liner film 22, and the effect of releasing the STI stress can be further improved. C can be made even smaller. As a result, it is possible to further alleviate the decrease in the current driving capability due to the STI stress of the NMOS transistor and to draw out the original current driving capability of the NMOS transistor.

  Thereafter, an oxide film is deposited as the interlayer insulating film 23, and a contact hole reaching from the surface of the interlayer insulating film 23 to the silicide layer 15 is formed. Then, the contact hole is filled with a material containing at least a conductive material to form a contact 24 that is electrically connected to the silicide layer 15 (source / drain diffusion layer 14). Furthermore, by forming a wiring layer 25 that is electrically connected to the contact 24 on the interlayer insulating film 23, the semiconductor device according to the present embodiment shown in FIG. 4A can be manufactured.

  In the above description, the STI element isolation 12 in the NMOS region is recessed. However, in the present invention, the recess of the STI element isolation 12 is not limited to the NMOS region. That is, the STI element isolation 12 in the PMOS region can be recessed, and a liner film (in this case, having a stress in the compression direction) may be formed. In this case, for example, the STI stress (compressive stress) in the PMOS region STI element isolation 12 can be accelerated by the recess of the STI element isolation 12 and the formation of the liner film, and the current driving capability Ids can be increased. This is effective when the shape compression effect due to the liner film having a compressive stress surrounding the step of the recess exceeds the stress release effect.

Embodiment 2. FIG.
FIG. 13 is a top view schematically showing a configuration of a memory device (SRAM) unit in the semiconductor device according to the second embodiment of the present invention. In the memory device portion of this semiconductor device, a plurality of memory cells are formed by miniaturizing the design rule. Further, FIG. 14 shows a gate width W direction in which a part of the memory device part and a part of the logic part are shown side by side in order to compare the memory device part and the logic part of the semiconductor device according to the present embodiment (FIG. 14). 2 (see FIG. 2). Note that the structure of the transistor in the semiconductor device according to this embodiment is the same as the structure of the semiconductor device described in Embodiment 1 described above, and thus FIGS. For reference, description and explanation in the drawings are omitted.

  Conventionally, in a memory device in which a plurality of memory cells are formed by miniaturizing the design rule as described above, the gate width W (see FIG. 2) is shortened together with the length LOD of the active region. In the narrow channel effect, when the gate width W is shortened, the current driving capability Ids is extremely reduced as shown in FIG.

  However, in the memory device portion of the semiconductor device according to the present embodiment, the STI element isolation 12 is recessed as shown in FIG. As a result, the gate width W can be secured longer by “ΔW × 2” at both ends in the gate width W direction. Here, ΔW is a length that can be secured long at one end in the gate width W direction in the gate of the memory device portion.

  As a result, even in a memory device portion in which a plurality of memory cells (transistors) are formed by miniaturizing the design rule, the current driving ability Ids is reduced due to the gate width W being shortened due to the narrow channel effect as shown in FIG. And the original current driving capability Ids of the transistor can be extracted. Needless to say, the semiconductor device according to the present embodiment can also achieve the effects of the present invention described in the first embodiment.

  Although an example of the semiconductor device according to the present invention has been described above, the present invention is not limited to the above description, and can be appropriately changed without departing from the gist of the present invention. For example, the present invention can be applied to any product to which the STI element isolation technology can be applied, including a logic unit and an SRAM unit.

  As described above, the semiconductor device according to the present invention is useful for all semiconductor products using the STI element isolation technology, and is particularly suitable for SoC of the 65 nm generation and later.

FIG. 3 is a cross-sectional view in the gate length L direction showing a part of a PMOS region and a part of an NMOS region side by side in order to compare the PMOS region and the NMOS region of the semiconductor device according to the present invention. It is a top view of the active region periphery part of the semiconductor device concerning this invention. FIG. 7 is a cross-sectional view in the gate length L direction showing a part of a PMOS region and a part of an NMOS region side by side in order to compare a PMOS region and an NMOS region of a conventional semiconductor device. FIG. 3 is a cross-sectional view in the gate length L direction showing a part of a PMOS region and a part of an NMOS region of the semiconductor device according to the first exemplary embodiment of the present invention side by side; It is a figure explaining the gate structure of the semiconductor device concerning Embodiment 1 of this invention. 1 is a top view of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing for demonstrating the stress in an NMOS area | region. FIG. 7 is an enlarged view around an edge portion of an active region in FIG. 6. 6 is a cross-sectional view for explaining a manufacturing step of the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view for explaining a manufacturing step of the semiconductor device according to the first embodiment; FIG. It is sectional drawing for demonstrating the stress in an NMOS area | region. 6 is a cross-sectional view for explaining a manufacturing step of the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view for explaining a manufacturing step of the semiconductor device according to the first embodiment; FIG. FIG. 6 is a top view schematically showing a configuration of a memory device unit in a semiconductor device according to a second embodiment of the present invention. Sectional drawing in the gate width W direction which showed a part of memory device part and a part of logic part in order to compare the memory device part and logic part of the semiconductor device concerning Embodiment 2 of this invention side by side It is. It is a characteristic view showing the relationship between the gate width and the current drive capability in the narrow channel effect.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 STI element isolation | separation 3 Active region 4 Gate electrode 5 Gate structure 11 Semiconductor substrate 12 STI element isolation | separation 13 Active region 14 Source / drain diffused layer 15 Silicide layer 15
16 Gate insulating film 17 Polysilicon electrode 18 Metal electrode 19 Gate electrode 20 Sidewall spacer 21 Gate structure 22 Liner film 23 Interlayer insulating film 24 Contact 25 Wiring layer

Claims (4)

A semiconductor substrate having first and second regions;
A groove formed in a surface layer of the semiconductor substrate;
An element isolation insulating film embedded in the trench;
An active region formed on a surface layer of the semiconductor substrate and defined by the element isolation insulating film;
With
The height of the surface of the element isolation insulating film is different between the first region and the second region, and the height of the element isolation insulating film in one of the regions is lower than the surface of the semiconductor substrate. A semiconductor device. The semiconductor device according to claim 1, further comprising: a layer having a stress opposite to a direction of stress generated in the element isolation film, on the element isolation film. 2. The semiconductor device according to claim 1, wherein the semiconductor element includes an NMOS transistor and a PMOS transistor, and a surface of at least one of the element isolation insulating films is lower than a surface of the semiconductor substrate. A semiconductor device comprising a memory device region and a logic device region on a main surface of the semiconductor substrate,
The semiconductor device according to claim 1, wherein a surface of the element isolation film in the memory device region is lower than a surface of the semiconductor substrate.

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