JP2012199361A - Semiconductor integrated circuit device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve problems of low oxidation resistance and low wet etching resistance caused by use of a High-k insulation film and a metal electrode component as a gate stack material; the problems being caused because though it is important to reduce a distance between end parts of adjacent gates for microfabrication of a pattern, particularly in order to reduce a cell area of SRAM, it is hard in general to transfer a pattern in a single exposure by ArF in a 28 nm technology node, and accordingly, a microfabricated pattern is formed by repetition of exposure, etching, and the like a plurality of times.SOLUTION: According to the present invention, in patterning of a multilayer gate film having a high-k gate insulation film and a metal electrode film in a memory region, first, etching of a cutting region between adjacent gate electrodes is performed by using a first resist film, and after the unnecessary first resist film is removed, etching of a line-and-space pattern by using a second resist film is performed.

Description

  The present invention relates to a technique that is effective when applied to a processing technique for a gate electrode or the like in a method for manufacturing a semiconductor integrated circuit device (or a semiconductor device).

  In Japanese Patent Laid-Open No. 2002-175981 (Patent Document 1) or US Patent Publication No. 2002-59557 (Patent Document 2) corresponding thereto, patterning of a gate electrode such as an SRAM (Static Random Access Memory) is described. In order to avoid the rounding of the pattern corner portion, the resist mask patterning, the hard mask film patterning using the resist film, and the resist film removal process are repeated twice on the hard mask film to obtain a corner. A technique for obtaining a hard mask film pattern in which a portion does not round is disclosed.

  In Japanese Unexamined Patent Publication No. 2008-91824 (Patent Document 3) or US Pat. No. 7,462,566 (Patent Document 4) corresponding thereto, a line & space pattern is first used as a hard mask in patterning a gate electrode or the like. A technique is disclosed in which a first resist film is patterned, the resist film is removed, a fine pattern is baked on the second resist film, and a hard mask is processed using the new resist film. .

  Japanese Patent Application Laid-Open No. 2010-118599 (Patent Document 5) discloses an object for separating a gate abutting portion on a blocking separation region by first using a first resist film in patterning of a gate electrode or the like. A technique is disclosed in which etching of a target film is performed using a second resist film having a line and space pattern after etching the film and removing the resist.

JP 2002-175981 A US Patent Publication No. 2002-59557 JP 2008-91824 A US Pat. No. 7,462,566 JP 2010-118599 A

  In order to miniaturize the pattern, particularly to reduce the SRAM cell area, it is important to reduce the distance between the end portions of adjacent gates. However, in a 28 nm technology node, it is generally difficult to transfer a pattern by single exposure with ArF (wavelength 193 nm). Therefore, a fine pattern is usually formed by repeating multiple times of exposure, etching, etc., but the problem that the new resist film after etching of the line & space pattern does not become flat or the gate stack material Since a high-k insulating film and a metal electrode member are used, there are problems such as low oxidation resistance and low wet etch resistance.

  The present invention has been made to solve these problems.

  An object of the present invention is to provide a manufacturing process of a highly reliable semiconductor integrated circuit device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, according to one aspect of the present invention, in patterning a gate laminated film (including a dummy gate laminated film) having a high-k gate insulating film and a metal electrode film in the memory region, first, the first resist film is used. Then, after the first resist film that has become unnecessary is removed by performing etching of the region between the adjacent gate electrodes, the line and space pattern is etched using the second resist film.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, in patterning a gate stacked film (including a dummy gate stacked film) having a high-k gate insulating film and a metal electrode film in the memory region, first, a first resist film is used to cut a region between adjacent gate electrodes. After the first resist film that is no longer needed is removed by performing this etching, line & space pattern etching is performed using the second resist film, so that when the second resist film is formed The flatness of the resist upper surface can be improved.

1 is a wafer and chip top view for explaining an upper surface layout and the like of an SOC chip which is an example of a target device in a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present application; 1 is a top view of the memory region cutout portion R1 and the non-memory region cutout portion R2 in FIG. 1 for explaining an outline of a gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (cutting between adjacent gate electrodes). Region patterning resist film patterning completion). 1 is a top view of the memory region cutout portion R1 and the non-memory region cutout portion R2 in FIG. 1 for explaining an outline of a gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (cutting between adjacent gate electrodes). (When region etching is completed). FIG. 1 is a top view of a memory region cutout portion R1 and a non-memory region cutout portion R2 in FIG. 1 for explaining an outline of a gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (resist for gate electrode patterning). (When film patterning is completed). FIG. 1 is a top view of the memory region cutout portion R1 and the non-memory region cutout portion R2 in FIG. 1 for explaining the outline of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (the gate electrode film etching completion). Time). FIG. 2 is a device cross-sectional view (between adjacent gate electrodes) corresponding to the cross section A-B-C-D-E in FIG. 2 for explaining details of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application; When the resist film patterning for patterning the cutting region is completed). FIG. 3 is a device cross-sectional view (between adjacent gate electrodes) corresponding to the cross section A-B-C-D-E in FIG. 3 for explaining details of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application; (When the cut region etching is completed). 4 is a device cross-sectional view (for gate electrode patterning) corresponding to the cross section A-B-C-D-E in FIG. 4 for explaining details of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. At the completion of resist film patterning). Device sectional view corresponding to the A-B-C-D-E section of FIG. 5 for explaining details of the gate patterning process in the manufacturing method of the semiconductor integrated circuit device of the one embodiment of the present application (gate electrode film etching) When completed). The device of the YY 'cross section corresponding to the process flow of FIGS. 2-5 for demonstrating the detailed step of the gate patterning process in the manufacturing method of the semiconductor integrated circuit device of the said one Embodiment of this application of FIG. It is sectional drawing (at the time of completion of the resist film formation for cutting area patterning between adjacent gate electrodes). The device of the YY 'cross section corresponding to the process flow of FIGS. 2-5 for demonstrating the detailed step of the gate patterning process in the manufacturing method of the semiconductor integrated circuit device of the said one Embodiment of this application of FIG. It is sectional drawing (at the time of completion of upper layer film patterning of the multilayer resist film for patterning the cutting region between adjacent gate electrodes). The device of the YY 'cross section corresponding to the process flow of FIGS. 2-5 for demonstrating the detailed step of the gate patterning process in the manufacturing method of the semiconductor integrated circuit device of the said one Embodiment of this application of FIG. It is sectional drawing (at the time of completion of intermediate layer film etching of the multilayer resist film for patterning the cutting region between adjacent gate electrodes). The device of the YY 'cross section corresponding to the process flow of FIGS. 2-5 for demonstrating the detailed step of the gate patterning process in the manufacturing method of the semiconductor integrated circuit device of the said one Embodiment of this application of FIG. It is sectional drawing (at the time of completion of the lower layer film etching of the multilayer resist film for patterning the cutting area pattern between adjacent gate electrodes). The device of the YY 'cross section corresponding to the process flow of FIGS. 2-5 for demonstrating the detailed step of the gate patterning process in the manufacturing method of the semiconductor integrated circuit device of the said one Embodiment of this application of FIG. It is sectional drawing (at the time of completion of the shrink process for processing a gate electrode film etc.). The device of the YY 'cross section corresponding to the process flow of FIGS. 2-5 for demonstrating the detailed step of the gate patterning process in the manufacturing method of the semiconductor integrated circuit device of the said one Embodiment of this application of FIG. It is sectional drawing (at the time of completion of etching processes, such as a gate electrode film). The device of the YY 'cross section corresponding to the process flow of FIGS. 2-5 for demonstrating the detailed step of the gate patterning process in the manufacturing method of the semiconductor integrated circuit device of the said one Embodiment of this application of FIG. It is sectional drawing (at the time of completion of removal of the lower layer film etc. of the multilayer resist film for patterning the cutting area pattern between adjacent gate electrodes). The device of the YY 'cross section corresponding to the process flow of FIGS. 2-5 for demonstrating the detailed step of the gate patterning process in the manufacturing method of the semiconductor integrated circuit device of the said one Embodiment of this application of FIG. It is sectional drawing (at the time of completion of the resist film application | coating for gate electrode patterning). XX ′ cross-section and DE cross-section devices corresponding to the process flow of FIGS. 2 to 5 for explaining detailed steps of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. FIG. 18 is a cross-sectional view (same as FIG. 17, that is, when the gate electrode patterning resist film application is completed). XX ′ cross-section and DE cross-section devices corresponding to the process flow of FIGS. 2 to 5 for explaining detailed steps of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. It is sectional drawing (at the time of completion of development of the upper layer film of the multilayer resist film for gate electrode patterning). XX ′ cross-section and DE cross-section devices corresponding to the process flow of FIGS. 2 to 5 for explaining detailed steps of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. It is sectional drawing (at the time of completion of trimming of the upper layer film of the multilayer resist film for gate electrode patterning). XX ′ cross-section and DE cross-section devices corresponding to the process flow of FIGS. 2 to 5 for explaining detailed steps of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. It is sectional drawing (at the time of completion of etching of a gate electrode film etc.). XX ′ cross-section and DE cross-section devices corresponding to the process flow of FIGS. 2 to 5 for explaining detailed steps of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. It is sectional drawing (at the time of completion of removal of the lower layer film of the multilayer resist film for gate electrode patterning). FIG. 22 is a schematic device cross-sectional view of the non-memory region CMISFET pair cutout portion R3 of FIG. 1 for explaining the outline of the main process after gate processing in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (FIG. 22). The same, that is, when the removal of the lower layer film of the multilayer resist film for gate electrode patterning is completed). FIG. 1 is a schematic device cross-sectional view of the non-memory region CMISFET pair cutout portion R3 in FIG. 1 for explaining an outline of a main process after gate processing in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (offset spacer and When the extension area has been introduced). 1 is a schematic device cross-sectional view (side wall formation) of the non-memory region CMISFET pair cutout portion R3 of FIG. 1 for explaining an outline of main processes after gate processing in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. (When the insulating film formation is completed). 1 is a schematic device cross-sectional view (side wall formation) of the non-memory region CMISFET pair cutout portion R3 of FIG. 1 for explaining an outline of main processes after gate processing in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. When completed). FIG. 1 is a schematic device cross-sectional view (silicide layer formation) of the non-memory region CMISFET pair cutout portion R3 of FIG. 1 for explaining an outline of main processes after gate processing in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. When completed). 1 is a schematic device cross-sectional view of a non-memory region CMISFET pair cutout portion R3 in FIG. 1 for explaining an outline of main processes after gate processing in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (premetal insulating film) (When film formation is completed). Schematic device sectional view of non-memory region CMISFET pair cutout portion R3 in FIG. 1 for explaining an outline of main processes after gate processing in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (contact hole formation) When completed). FIG. 1 is a schematic device cross-sectional view of a non-memory region CMISFET pair cutout portion R3 in FIG. 1 for explaining an outline of a main process after gate processing in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (embedding a tungsten plug). When completed). 2 is a circuit diagram of an SRAM memory cell of an SOC chip, which is an example of a target device in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. FIG. FIG. 3 is a memory cell plane layout diagram showing an example of an actual plane layout of an SRAM memory cell of an SOC chip that is an example of a target device in the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application.

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) a step of preparing a semiconductor wafer having first and second main surfaces, the semiconductor wafer having a plurality of chip regions including a memory region and a non-memory region on the first main surface;
(B) forming a gate laminated film having a lower high-k gate insulating film and an upper gate metal electrode film on the first main surface of the semiconductor wafer;
(C) forming a first resist film for defining a cutting region between adjacent gate electrodes on the gate laminated film in the extending direction of the gate electrode in the memory region;
(D) forming a resist film opening corresponding to the cut region between the adjacent gate electrodes by performing patterning on the first resist film;
(E) performing the etching on the gate laminated film in a state where the patterned first resist film is present;
(F) a step of removing the first resist film after the step (e);
(G) After the step (f), a second resist film for defining a line and space pattern corresponding to the gate electrode in the memory region is formed on the first main surface of the semiconductor wafer. The step of:
(H) A step of patterning the second resist film;
(I) a step of performing etching on the gate laminated film in a state where the patterned second resist film is present;
(J) A step of removing the second resist film after the step (i).

  2. In the method for manufacturing a semiconductor integrated circuit device according to the item 1, there is no hard mask film between the first resist film, the second resist film, and the gate laminated film.

  3. In the method for manufacturing a semiconductor integrated circuit device according to the item 1 or 2, the second resist film in the step (g) may be used for defining a line and space pattern corresponding to the gate electrode in the non-memory region. is there.

  4). 4. The method of manufacturing a semiconductor integrated circuit device according to any one of items 1 to 3, wherein the adjacent gate electrode cutting region is in an element isolation region.

  5). 5. In the method for manufacturing a semiconductor integrated circuit device according to any one of items 1 to 4, the first resist film and the second resist film are each a multilayer resist film.

6). In the method for manufacturing a semiconductor integrated circuit device according to any one of 1 to 5, the step (e) includes the following substeps:
(E1) executing a process of reducing the opening of the resist film;
(E2) A step of performing anisotropic dry etching on the gate laminated film under the opening of the resist film after the step (e1).

7). In the method for manufacturing a semiconductor integrated circuit device according to any one of 1 to 6, the step (i) includes the following substeps:
(I1) executing a process of reducing the width of the patterned second resist film;
(I2) A step of performing anisotropic dry etching on a portion of the gate laminated film that is not covered with the second resist film after the step (i1).

  8). 8. In the method for manufacturing a semiconductor integrated circuit device according to any one of 1 to 7, the patterning in the steps (d) and (h) is performed by ArF lithography using 193 nm exposure light.

9. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first resist film and the second resist film have the following:
(X1) a lower resist film containing carbon as a main component;
(X2) an intermediate layer resist film containing silicon formed on the lower layer resist film as one of main components;
(X3) A photosensitive upper resist film formed on the intermediate resist film.

10. 10. The method for manufacturing a semiconductor integrated circuit device according to any one of 1 to 9, wherein the second resist film has the following:
(X1) a lower-layer-coated resist film containing carbon as a main component;
(X2) an intermediate layer resist film containing silicon formed on the lower layer resist film as one of main components;
(X3) A photosensitive upper resist film formed on the intermediate resist film.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Further, in the present application, the term “semiconductor device” or “semiconductor integrated circuit device” mainly refers to various types of transistors (active elements) alone, and resistors, capacitors, etc. as semiconductor chips (eg, single crystal). The one integrated on the silicon substrate). Here, as a representative of various transistors, a MISFET (Metal Insulator Semiconductor Effect Transistor) typified by a MOSFET (Metal Oxide Field Effect Transistor) can be exemplified. At this time, a typical integrated circuit configuration is a CMIS (Complementary Metal Insulator Semiconductor) integrated circuit represented by a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit in which an N-channel MISFET and a P-channel MISFET are combined. Can be illustrated.

  A semiconductor process of today's semiconductor integrated circuit device, that is, a LSI (Large Scale Integration) wafer process, is usually performed by carrying a silicon wafer as a raw material to a premetal process (an interlayer insulating film between the lower end of the M1 wiring layer and the gate electrode structure). Etc., contact hole formation, tungsten plug, embedding, etc.) (FEOL (Front End of Line) process) and M1 wiring layer formation, pad opening to the final passivation film on the aluminum-based pad electrode Can be roughly divided into BEOL (Back End of Line) processes up to the formation of the wafer (including the process in the wafer level package process).

  2. Similarly, in the description of the embodiment and the like, the material, composition, etc. may be referred to as “X consisting of A”, etc., except when clearly stated otherwise and clearly from the context, except for A It does not exclude what makes an element one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say. Similarly, “silicon oxide film”, “silicon oxide insulating film”, etc. are not only relatively pure undoped silicon oxide (FS), but also FSG (Fluorosilicate Glass), TEOS-based silicon oxide ( Thermal oxide films such as TEOS-based silicon oxide), SiOC (Silicon Oxicarbide) or Carbon-doped Silicon oxide or OSG (Organosilicate glass), PSG (Phosphorus Silicate Glass), BPSG (Borophosphosilicate Glass), CVD Oxide film, SOG (Spin ON Glass), nano-clustering silica (Nano-Clustering Silica: NCS) and other coating-type silicon oxide, silica-based low-k insulating film (porous insulating) Needless to say, a film) and a composite film with other silicon-based insulating films including these as main constituent elements are included.

  In addition to silicon oxide insulating films, silicon nitride insulating films that are commonly used in the semiconductor field include silicon nitride insulating films. Materials belonging to this system include SiN, SiCN, SiNH, SiCNH, and the like. Here, “silicon nitride” includes both SiN and SiNH unless otherwise specified. Similarly, “SiCN” includes both SiCN and SiCNH, unless otherwise specified.

  Note that SiC has similar properties to SiN, but SiON is often rather classified as a silicon oxide insulating film.

  The silicon nitride film is frequently used as an etch stop film in SAC (Self-Aligned Contact) technology, and is also used as a stress applying film (Stressor Film) in SMT (Stress Measurement Technique).

  Similarly, in the present application, the term “silicide” or “silicide layer” usually indicates nickel silicide or nickel platinum silicide, but includes alloys, mixed crystals, and the like whose main component is nickel monosilicide. In addition, the silicide is not limited to nickel silicide, nickel platinum silicide, or the like, but may be cobalt silicide, titanium silicide, tungsten silicide, or the like that has been proven in the past. In addition to the Ni (nickel) film, for example, a Ni-Pt alloy film (Ni and Pt alloy film), a Ni-V alloy film (Ni and V alloy film), A nickel alloy film such as a Ni—Pd alloy film (Ni—Pd alloy film), a Ni—Yb alloy film (Ni—Yb alloy film) or a Ni—Er alloy film (Ni—Er alloy film) is used. be able to. These silicides having nickel as a main metal element are collectively referred to as “nickel-based silicide”.

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5). “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor integrated circuit device (same as a semiconductor device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate and the like. Needless to say, a composite wafer such as a semiconductor layer is also included.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

1. Description of upper surface layout of SOC chip which is an example of target device in manufacturing method of semiconductor integrated circuit device of one embodiment of the present application (mainly FIG. 1)
In the following, an SOC chip will be specifically described as an example of the symmetric device of the present application, but it is needless to say that it may be a memory dedicated chip. In the following example, a 28 nm technology node generation product is mainly described as a specific example, but it goes without saying that it can be applied to other generations.

  FIG. 1 is a wafer and chip top view for explaining an upper surface layout and the like of an SOC chip which is an example of a target device in a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present application. Based on this, an upper surface layout and the like of an SOC chip as an example of a target device in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application will be described.

  As shown in FIG. 1, a device main surface 1a (first main surface) of a wafer 1 in the middle of a wafer process (here, a 300φ silicon single crystal wafer is described as an example, but the diameter may be 450φ or 200 phi). ) A large number of chip regions 2 are formed. The wafer 1 is provided with a notch 3 for discriminating its orientation.

  Next, details of the layout of each chip 2 (chip area) will be described. A large number of bonding pads 5 are provided in the peripheral portion 4 of the chip area 2, and a memory area 6 and a non-memory area 7 are provided in the internal area. Here, the memory area 6 is exemplified by an SRAM (Static Random Access Memory), but is not limited thereto, and may be a DRAM (Dynamic Random Access Memory) or a flash memory. Note that the “memory area” accurately refers to a memory cell area. Accordingly, many parts of the memory peripheral circuit belong to the non-memory area 7. Therefore, the non-memory area 7 includes a logic circuit, an analog circuit, and the like in addition to such a memory peripheral circuit.

2. Outline of gate patterning process in manufacturing method of semiconductor integrated circuit device according to one embodiment of the present application (mainly FIGS. 2 to 5 and FIGS. 6 to 9)
Here, in response to the description of the SRAM-embedded logic chip in section 1, the patterning (double patterning process) of the gate electrodes and the like in the memory region 6 and the non-memory region 7 (FIG. 1) will be described.

  2 is a top view of the memory region cutout portion R1 and the non-memory region cutout portion R2 of FIG. 1 (adjacent gates) for explaining the outline of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. (When the resist film patterning for patterning the inter-electrode cutting region is completed). 3 is a top view of the memory region cutout portion R1 and the non-memory region cutout portion R2 of FIG. 1 (adjacent gates) for explaining the outline of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. (When the inter-electrode cutting region etching is completed). 4 is a top view (gate electrode) of the memory region cutout portion R1 and the non-memory region cutout portion R2 of FIG. 1 for explaining the outline of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. Patterning resist film patterning is completed). FIG. 5 is a top view (gate electrode) of the memory region cutout portion R1 and the non-memory region cutout portion R2 of FIG. 1 for explaining the outline of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. When the film etching is completed). FIG. 6 is a device sectional view corresponding to the A-B-C-D-E section of FIG. 2 for explaining details of a gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. (When the resist film patterning for patterning the cut region between the gate electrodes is completed). FIG. 7 is a device sectional view corresponding to the A-B-C-D-E section of FIG. 3 for explaining the details of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present invention. (When the gate electrode cut region etching is completed). FIG. 8 is a device sectional view (gate) corresponding to the A-B-C-D-E section of FIG. 4 for explaining details of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. Electrode patterning resist film patterning completion). FIG. 9 is a device sectional view (gate) corresponding to the A-B-C-D-E section of FIG. 5 for explaining the details of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. Electrode electrode etching is completed). Based on these, the outline of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application will be described.

  First, the wafer 1 before processing the gate electrode film is prepared (see FIGS. 2 and 6). This is performed, for example, as follows. For example, a P-type silicon single crystal wafer 1 is prepared, and an element isolation region 9 such as STI (Shallow Trench Isolation) is formed on the device main surface 1a (the main surface opposite to the back surface 1b). Necessary impurity doped regions such as well regions are formed in the active region 8.

  Further, a High-k gate insulating film 16 (a gate insulating film including a High-k gate insulating film) is formed on almost the entire device main surface 1a (first main surface) of the wafer 1. Here, the “High-k gate insulating film” refers to a gate insulating film (a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a laminated film thereof) having a conventional silicon oxide film as a main film component. Is a gate insulating film having a high dielectric constant.

  Next, a lower layer film 14 b of a gate electrode film such as a titanium nitride film is formed on almost the entire surface of the high-k gate insulating film 16.

  Next, for example, a polysilicon film 14a (which may be an amorphous silicon film) is formed as an upper layer film of the gate electrode film on almost the entire surface of the titanium nitride film 14b.

  Next, a multilayer resist film 11 (first resist film) for patterning a cutting region between adjacent gate electrodes is formed on almost the entire surface of the polysilicon film 14a by coating or the like. The multilayer resist film 11 is made of a non-photosensitive silicon intermediate layer such as a carbon-based lower non-photosensitive film 11c (lower film) such as an SOC (Spin On Carbon) film or an Si-BARC (Silicon-Bottom Anti-Reflection Coating) film. It is composed of a film 11b (intermediate layer film), an organic upper photosensitive film 11a (upper layer film) such as an ArF chemically amplified resist film, and the like. The Si-BARC film contains silicon as one of main components (silicon content is, for example, about 15% to 45% by weight, and the same for the second resist film described below). Reflection by coating system or CVD It is a prevention film. The SOC film contains carbon as one of main components (the carbon content is, for example, about 80 to 90% by weight, and the same applies to the second resist film described below). The carbon-based film is a base film (a film having etching selectivity with respect to a silicon-based member).

  Next, as shown in FIGS. 2 and 6, exposure and development of the ArF chemically amplified resist film 11a are performed to form a resist film opening 12 corresponding to a cutting region between adjacent gate electrodes. The exposure with ArF excimer laser light (wavelength is 193 nm) is performed using, for example, an optical mask and an immersion reduction projection exposure apparatus (immersion scanner). Here, the width of the resist film opening 12 (equivalent to the length of the shorter side) is, for example, about 60 to 70 nm, which is about the same as the width of the element isolation region. The thickness is about 20 to 25 nm.

  Subsequently, the pattern of the ArF chemically amplified resist film 11a (upper layer film) of the multilayer resist film 11 is sequentially transferred to the Si-BARC film 11b (intermediate layer film) and the SOC film 11c (lower layer film) (for details, refer to section 3).

  Next, as shown in FIGS. 3 and 7, the gate electrode film 14 (polysilicon film 14a, titanium nitride film 14b) is formed by dry etching using the patterned resist film 11 for patterning a region between adjacent gate electrodes as a mask. Then, the high-k gate insulating film 16 is processed to open the cutting region 12 between adjacent gate electrodes.

  Next, as shown in FIGS. 4 and 8, similarly to the above, the gate electrode patterning multilayer resist film 15 (second resist) is formed on almost the entire device main surface 1a (first main surface) of the wafer 1. Film) is formed by coating or the like. The multilayer resist film 15 includes a carbon-based lower layer non-photosensitive film 15c (lower layer film) such as an SOC film, a silicon-based intermediate layer non-photosensitive film 15b (intermediate layer film) such as an Si-BARC film, and an ArF chemically amplified resist film. The organic upper layer photosensitive film 15a (upper layer film) and the like. Here, similarly to the above, exposure and development of the ArF chemically amplified resist film 15a are executed to form a resist film pattern 15a corresponding to the line and space pattern of the gate electrode. Exposure with ArF excimer laser light (wavelength is 193 nm) is performed using, for example, an optical mask and an immersion reduction projection exposure apparatus (immersion scanner), as before. Here, the width of the resist film pattern 15a corresponding to the line and space pattern of the gate electrode is about 45 nm at the beginning of patterning, but is set to about 30 nm by the trimming process described below. The carbon-based lower layer film in this step is preferably a coating-type planarizing film such as an SOC film from the viewpoint of planarization.

  Subsequently, the pattern of the ArF chemically amplified resist film 15a (upper layer film) of the multilayer resist film 15 is sequentially transferred to the Si-BARC film 15b (intermediate layer film) and the SOC film 15c (lower layer film). 3).

  Next, as shown in FIGS. 5 and 9, as a patterned gate electrode patterning multilayer resist film 15 (second resist film) mask, the gate electrode film 14 (polysilicon film 14a, titanium nitride) is formed by dry etching. Film 14b) and High-k gate insulating film 16 are processed to form gate electrode.

  In the above process, a recess portion 17 is formed on the upper surface of the element isolation region 9 by etching.

3. Detailed description of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (mainly FIGS. 10 to 17 and FIGS. 18 to 22).
FIG. 10 is a cross-sectional view taken along line YY ′ corresponding to the process flow of FIGS. 2 to 5 and D-E for explaining detailed steps of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. It is device sectional drawing of a cross section (at the time of completion of the resist film formation for cutting area patterning between adjacent gate electrodes). FIG. 11 is a cross-sectional view taken along line YY ′ corresponding to the process flow of FIGS. 2 to 5 and D-E for explaining detailed steps of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. FIG. 10 is a device cross-sectional view of the cross section (when the upper layer film patterning for patterning the cutting region pattern between adjacent gate electrodes is completed); FIG. 12 is a cross-sectional view taken along line YY ′ corresponding to the process flow of FIGS. 2 to 5 and D-E for explaining detailed steps of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. FIG. 10 is a device cross-sectional view of the cross section (when the intermediate layer film etching of the multilayer resist film for patterning the cutting region between adjacent gate electrodes is completed); FIG. 13 is a cross-sectional view taken along line YY ′ corresponding to the process flow of FIGS. 2 to 5 and DE for explaining the detailed steps of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. FIG. 10 is a device cross-sectional view of the cross section (when the etching of the lower layer film of the multilayer resist film for patterning the cutting region between adjacent gate electrodes is completed); FIG. 14 is a cross-sectional view taken along line YY ′ corresponding to the process flow of FIGS. 2 to 5 and D-E for explaining detailed steps of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. It is device sectional drawing of a cross section (at the time of completion of the shrink process for processing a gate electrode film etc.). FIG. 15 is a cross-sectional view taken along line YY ′ corresponding to the process flow of FIGS. 2 to 5 and D-E for explaining detailed steps of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. It is device sectional drawing of a cross section (at the time of the etching process completion of a gate electrode film etc.). FIG. 16 is a cross-sectional view taken along line YY ′ corresponding to the process flow of FIGS. 2 to 5 and DE for explaining the detailed steps of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. FIG. 10 is a device cross-sectional view of the cross section (when removal of the lower layer film and the like of the multilayer resist film for patterning the cutting region between adjacent gate electrodes is completed); FIG. 17 is a cross-sectional view taken along line YY ′ corresponding to the process flow of FIGS. 2 to 5 and D-E for explaining detailed steps of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. It is device sectional drawing of a cross section (at the time of completion of resist film application for gate electrode patterning). 18 is a cross-sectional view taken along the line XX ′ corresponding to the process flow of FIGS. 2 to 5 and D-E for explaining the detailed steps of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. FIG. 18 is a device cross-sectional view of the cross section (same as FIG. 17, that is, when the application of the resist film for gate electrode patterning is completed). FIG. 19 is a cross-sectional view taken along line XX ′ corresponding to the process flow of FIGS. 2 to 5 and D-E for explaining detailed steps of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. FIG. 4 is a cross-sectional device sectional view (when development of the upper layer film of the multilayer resist film for gate electrode patterning is completed). FIG. 20 is a cross-sectional view taken along the line XX ′ corresponding to the process flow of FIGS. 2 to 5 and D-E for explaining detailed steps of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. It is a device sectional view of a section (when trimming of the upper layer film of the multilayer resist film for gate electrode patterning is completed). FIG. 21 is a cross-sectional view taken along line XX ′ corresponding to the process flow of FIGS. 2 to 5 and D-E for explaining the detailed steps of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. It is device sectional drawing of a cross section (at the time of completion of etching of a gate electrode film etc.). FIG. 22 is a cross-sectional view taken along line XX ′ corresponding to the process flow of FIGS. 2 to 5 and D-E for explaining the detailed steps of the gate patterning process in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. It is device sectional drawing of a cross section (at the time of completion of removal of the lower layer film of the multilayer resist film for gate electrode patterning). Based on these, the details of the gate patterning process in the manufacturing method of the semiconductor integrated circuit device of the one embodiment of the present application will be described.

  As shown in FIG. 10, for example, a P-type silicon single crystal wafer 1 is prepared, and an element isolation region 9 such as STI is formed on the device main surface 1 a, followed by a well region or the like in the active region 8. The necessary impurity doped region is formed.

  Further, a High-k gate insulating film 16 (a gate insulating film including a High-k gate insulating film) is formed on almost the entire device main surface 1a (first main surface) of the wafer 1. An example of the high-k gate insulating film 16 is a hafnium oxide insulating film having a thickness of about 0.7 to 1.5 nm.

  Next, a lower layer film 14b of a gate electrode film such as a titanium nitride film (for example, about 10 nm thick) is formed on almost the entire surface of the high-k gate insulating film 16.

  Next, a polysilicon film 14a (which may be an amorphous silicon film) having a thickness of about 50 nm is formed as an upper layer film of the gate electrode film on almost the entire surface of the titanium nitride film 14b.

  Next, a multilayer resist film 11 (first resist film) for patterning a cutting region between adjacent gate electrodes is formed on almost the entire surface of the polysilicon film 14a by coating or the like. The multilayer resist film 11 is formed as follows, for example. That is, first, a carbon-based lower non-photosensitive film 11c (lower layer film) such as an SOC film is formed on almost the entire surface of the polysilicon film 14a by coating or the like (for example, a thickness of about 100 to 300 nm). Note that an amorphous carbon film by CVD (Chemical Vapor Deposition) or the like may be used. Subsequently, a silicon-based intermediate layer non-photosensitive film 11b (intermediate layer film) such as a Si-BARC film (for example, a thickness of about 10 to 100 nm) is formed on almost the entire surface of the SOC film 11c by coating or the like. Subsequently, an organic upper photosensitive film 11a (upper film) such as an ArF chemically amplified resist film is formed on almost the entire surface of the Si-BARC film 11b by coating or the like (for example, a thickness of about 50 to 180 nm).

  Next, as shown in FIG. 11, exposure and development of the ArF chemically amplified resist film 11a are performed to form a resist film opening 12 corresponding to the cutting region between adjacent gate electrodes. The exposure with ArF excimer laser light (wavelength is 193 nm) is performed using, for example, an optical mask and an immersion reduction projection exposure apparatus (immersion scanner).

Next, as shown in FIG. 12, using the patterned ArF chemically amplified resist film 11a as a mask, the ArF chemically amplified resist film is subjected to dry etching using, for example, a fluorocarbon-based gas (for example, CF ₄ ). The pattern of 11a is transferred to the Si-BARC film 11b.

Next, as shown in FIG. 13, with the patterned Si-BARC film 11b as a mask, the pattern of the Si-BARC film 11b is changed to the SOC film 11c by dry etching using, for example, an oxygen-based gas (for example, O ₂ ). Transcript to. At the same time, the remaining ArF chemically amplified resist film 11a is removed.

Next, as shown in FIG. 14, a pre-etching process (shrink process) is performed in a state where the wafer 1 is introduced into an etching chamber of a dry etching apparatus for etching the gate electrode 14, for example (a kind of dry etching). The upper surface of the polysilicon film 14a is slightly etched). That is, the shrink side wall 18 is formed on the side wall of the resist film opening 12. As the shrink processing conditions, gas atmosphere: for example, CHF ₃ (100 to 300 sccm) / O ₂ (10 to 50 sccm), RF power: for example, about 500 to 1000 watts, wafer bias: 100 to 300 volts, wafer stage temperature: 10 degrees Celsius From about 50 degrees.

Next, as shown in FIG. 15, by using the patterned SOC film 11c as a mask, by dry etching, a polysilicon film 14a (the etching gas is a halogen-based gas, specifically, for example, HBr), Titanium nitride film 14b (etching gas is halogen-based gas, specifically, for example, Cl ₂ / HBr), gate insulating film 16 (etching gas is halogen-based gas, specifically, for example, , BCl ₃ / Cl _2, etc.) sequentially, the shunted adjacent gate electrode cutting region 12 is formed. At the same time, the remaining Si-BARC film 11b is removed.

Next, as shown in FIG. 16, the SOC film 11c and the shrink side wall 18 are removed by ashing, wet cleaning, or the like. Examples of wet cleaning conditions include:
(1) First step: The chemical solution is dilute hydrochloric acid, the composition is, for example, a hydrogen chloride concentration of about 0.0418 mol%, and the treatment time is about 60 seconds at room temperature (15 to 25 degrees Celsius)
(2) Second step: The chemical solution is a mixed acid, the composition is, for example, a hydrogen chloride concentration of about 0.411 mol%, a hydrogen fluoride concentration of about 0.0106 mol%, and the treatment time is room temperature (15 to 25 degrees Celsius) ) About 60 seconds can be shown as a suitable example.

  Next, as shown in FIGS. 17 and 18, a gate electrode patterning multilayer resist film 15 (second resist film) is applied to almost the entire device main surface 1 a (first main surface) of the wafer 1. To form. The multilayer resist film 15 is formed as follows, for example. That is, first, a carbon-based lower non-photosensitive film 15c (lower film) such as an SOC film is formed on almost the entire surface of the wafer 1 on the device surface 1a (for example, a thickness of about 100 to 300 nm). Subsequently, a silicon intermediate layer non-photosensitive film 15b (intermediate layer film) such as a Si-BARC film is formed on almost the entire surface of the SOC film 15c by coating or the like (for example, a thickness of about 10 to 100 nm). Subsequently, an organic upper photosensitive film 15a (upper layer film) such as an ArF chemically amplified resist film is formed on almost the entire surface of the Si-BARC film 15b by coating or the like (for example, a thickness of about 50 to 180 nm).

  Next, as shown in FIG. 19, the ArF chemically amplified resist film 15a is exposed and developed to form a resist film pattern 15a corresponding to the line and space pattern of the gate electrode. Exposure with ArF excimer laser light (wavelength is 193 nm) is performed using, for example, an optical mask and an immersion reduction projection exposure apparatus (immersion scanner), as before.

Next, as shown in FIG. 20, a trimming process is performed on the patterned resist film pattern 15a so that the final width of the resist film pattern 15a is larger than the width 19 of the original resist film. Narrow. The trimming process is a process similar to dry etching, and is usually performed in the same apparatus or the same chamber as the subsequent etching process. As the atmosphere gas for the trimming process, for example, a Cl ₂ / O ₂ -based gas can be exemplified.

Next, as shown in FIG. 21, the trimmed resist film pattern 15a is sequentially applied to the Si-BARC film 15b (the etching atmosphere is, for example, a CF ₄ gas atmosphere) and the SOC film 15c (the etching atmosphere is the etching atmosphere). (For example, an O ₂ gas atmosphere) and using the patterned SOC film 15c as a mask, the polysilicon film 14a (the etching atmosphere is, for example, an SF ₆ / CF ₄ gas atmosphere) by dry etching as described above. ), A titanium nitride film 14b (etching atmosphere is, for example, an HBr / Cl ₂ -based gas atmosphere), and a gate insulating film 16 (etching atmosphere is, for example, a BCl ₃ / Cl ₂ -based gas atmosphere), and gate electrode lines that are trimmed sequentially An and space pattern is formed. At the same time, the remaining Si-BARC film 15b is removed.

Next, as shown in FIG. 22, the SOC film 15c is removed by ashing or the like and wet cleaning. Examples of wet cleaning conditions include:
(1) First step: The chemical solution is dilute hydrochloric acid, the composition is, for example, a hydrogen chloride concentration of about 0.0418 mol%, and the treatment time is about 60 seconds at room temperature (15 to 25 degrees Celsius)
(2) Second step: The chemical solution is a mixed acid, the composition is, for example, a hydrogen chloride concentration of about 0.411 mol%, a hydrogen fluoride concentration of about 0.0106 mol%, and the treatment time is room temperature (15 to 25 degrees Celsius) ) About 60 seconds can be shown as a suitable example.

4). Outline of main process after gate processing in manufacturing method of semiconductor integrated circuit device of one embodiment of the present application (mainly FIGS. 23 to 30)
FIG. 23 is a schematic device cross-sectional view of the non-memory region CMISFET pair cutout portion R3 of FIG. 1 for explaining an outline of main processes after gate processing in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. The same as FIG. 22, that is, when the removal of the lower layer film of the multilayer resist film for gate electrode patterning is completed). 24 is a schematic device cross-sectional view of the non-memory region CMISFET pair cutout portion R3 of FIG. 1 for explaining the outline of the main process after gate processing in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. Offset spacer and extension region introduction). 25 is a schematic device cross-sectional view of the non-memory region CMISFET pair cutout portion R3 of FIG. 1 for explaining the outline of the main process after gate processing in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present invention. (When the insulating film for forming the sidewall is formed). 26 is a schematic device cross-sectional view of the non-memory region CMISFET pair cutout portion R3 of FIG. 1 for explaining the outline of the main process after gate processing in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. Side wall formation). 27 is a schematic device cross-sectional view of the non-memory region CMISFET pair cutout portion R3 of FIG. 1 for explaining the outline of the main process after gate processing in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. When the silicide layer formation is completed). 28 is a schematic device cross-sectional view of the non-memory region CMISFET pair cutout portion R3 of FIG. 1 for explaining the outline of the main process after gate processing in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. When the premetal insulating film is formed). 29 is a schematic device cross-sectional view of the non-memory region CMISFET pair cutout portion R3 of FIG. 1 for explaining the outline of the main process after gate processing in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. Contact hole formation completed). 30 is a schematic device cross-sectional view of the non-memory region CMISFET pair cutout portion R3 of FIG. 1 for explaining the outline of the main process after gate processing in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. (When tungsten plug embedding is completed). Based on these, the outline of the main process after the gate processing in the manufacturing method of the semiconductor integrated circuit device according to the embodiment of the present application will be described.

  Based on FIG. 23 (same process steps as FIG. 9 and FIG. 22), the non-memory region CMISFET pair cut-out portion P channel device region R3p and non- FIG. A portion corresponding to the N channel device region R3n of the memory region CMISFET pair cutout portion will be described. As shown in FIG. 23, an N-well region 1n and a P-well region 1p are provided in the upper half of the P-type single crystal silicon substrate portion of the wafer 1.

  Next, as shown in FIG. 24, an offset spacer silicon nitride film 21 (for example, about 2 to 7 nm thick) is formed on almost the entire device surface 1a of the wafer 1 by, for example, CVD. Subsequently, the offset spacer silicon nitride film 21 is etched back by anisotropic dry etching to form the offset spacer 21.

Subsequently, a P-type extension region 22p (as an ion implantation condition, for example, ion species: BF ₂₎ is formed by ion implantation into the surface area of the device surface 1a of the wafer 1 in each of the P channel device region R3p and the N channel device region R3n. , implantation energy: 5 KeV from 1 KeV, dose: 1x10 ¹⁵ / cm ² from 8x10 ¹⁵ / cm ^2; ion species: C, implantation energy: 5 KeV from 1 KeV, dose: 4x10 ¹⁴ / cm ² from 9x10 ¹⁴ / ^cm 2) And N type extension region 22n (as ion implantation conditions, for example, ion species: As, implantation energy: 1 KeV to 10 KeV, dose amount: 1 × 10 ¹⁵ / cm ² to 9 × 10 ¹⁵ / cm ² ; ion species: C, implantation energy: 1 KeV Luo 5 KeV, dose: 4x10 ¹⁴ / cm ² from 9x10 ¹⁴ / cm ²⁾ to introduce.

  Next, as shown in FIG. 25, a sidewall silicon oxide film 23a (for example, a thickness of about 5 to 10 nm) is formed on almost the entire device surface 1a of the wafer 1 by, for example, CVD. Subsequently, a sidewall silicon nitride film 23b (for example, a thickness of about 20 to 30 nm) is formed on almost the entire surface of the sidewall silicon oxide film 23a by, for example, CVD.

Next, as shown in FIG. 26, the sidewall silicon oxide film 23a and the sidewall silicon nitride film 23b are etched back by anisotropic dry etching to form the silicon oxide film sidewall 23a and the silicon nitride film sidewall 23b. Form. Subsequently, a P-type high-concentration source / drain region 24p (as an ion implantation condition, for example, an ion species is formed by ion implantation on the device surface 1a surface region of the wafer 1 of each of the P-channel device region R3p and the N-channel device region R3n. : B, implantation energy: 0.5 KeV to 20 KeV, dose amount: 1 × 10 ¹⁵ / cm ² to 8 × 10 ¹⁵ / cm ² ) and N-type high-concentration source / drain region 24n (as ion implantation conditions, for example, ion species: As, Implantation energy: 2 KeV to 40 KeV, dose amount: 8 × 10 ¹⁴ / cm ² to 4 × 10 ¹⁵ / cm ² ; ion species: P, implantation energy: 10 KeV to 80 KeV, dose amount: 1 × 10 ¹³ / cm ² to 8 × 10 ¹³ / cm ² ) Introduce.

  Next, as shown in FIG. 27, a silicide layer 25 such as a nickel platinum silicide layer is formed on the gate electrode and the surface region of the source / drain region by a salicide process.

  Next, as shown in FIG. 28, a silicon nitride film (for example, a thickness of about 20 to 30 nm) is formed as a premetal lower layer insulating film 26a on almost the entire device surface 1a of the wafer 1 by, for example, plasma CVD. . Subsequently, a silicon oxide film (for example, a thickness of about 150 to 240 nm) is formed as a premetal upper-layer insulating film 26b on the substantially entire surface of the silicon nitride film 26a by, for example, plasma CVD.

  Next, as shown in FIG. 29, a contact hole forming resist film 27 is formed on the substantially entire surface of the silicon oxide film 26b by coating or the like. Subsequently, the resist film 27 is patterned by normal lithography (for example, ArF lithography). Using the patterned resist film 27 as a mask, contact holes 28 of the silicon oxide film 26b and the silicon nitride film 26a are sequentially opened by anisotropic dry etching. Thereafter, the resist film 27 that has become unnecessary is removed by ashing or the like.

  Next, as shown in FIG. 30, a tungsten plug 29 is embedded in the contact hole 28. Thereafter, as necessary, multilayer wiring is formed by a copper-based damascene method (embedded wiring method) or an aluminum-based normal wiring method (non-embedded wiring method).

5. Description of an SRAM memory cell of an SOC chip, which is an example of a target device in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application (mainly FIGS. 31 and 32)
Here, the six-transistor cell has been specifically described as an example, but the invention of the present application is not limited thereto, and it goes without saying that the invention can be applied to memory cells having other structures.

  FIG. 31 is a circuit diagram of an SRAM memory cell of an SOC chip which is an example of a target device in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. FIG. 32 is a memory cell plane layout diagram showing an example of an actual plane layout of an SRAM memory cell of an SOC chip which is an example of a target device in the method for manufacturing a semiconductor integrated circuit device according to the embodiment of the present application. Based on these, an SRAM memory cell of an SOC chip that is an example of a target device in the method of manufacturing a semiconductor integrated circuit device according to the embodiment of the present application will be described.

  As shown in FIG. 31, the SRAM memory cell MC is provided with a word line WL and a pair of bit lines BL and BLB that run orthogonal to each other, and an N-type storage transistor is located in the vicinity of the intersection. Q1, Q2, P-type storage transistors Q3, Q4, read transistors Q5, Q6, a power supply line Vdd for supplying power to them, a reference voltage line Vss, and the like are arranged.

  FIG. 32 shows the SRAM memory cell MC of FIG. 31 in an actual layout. As shown in FIG. 32, it can be seen that a large number of gate electrodes 14 running vertically are regularly cut by the cutting regions 12 between adjacent gate electrodes. Of the large number of contact portions 28, 30, the one shown in a horizontally long shape is a shared contact portion 30. Here, the contact portion 28 of the active region 8n of the N-channel device and the shared contact portion 30 of the active region 8p of the P-channel device are connected by the interconnect metal wiring IC.

6). Supplementary explanation and discussion on manufacturing method of semiconductor integrated circuit device according to one embodiment of the present application In the SRAM wide cell as shown in section 5, a longitudinal interval between adjacent gates, that is, adjacent gates Reducing the interelectrode cutting region 12 (see FIG. 2) is an important technical problem for reducing the cell area. However, in the 28 nm technology node (Technology Node) or later generations, since it is below the resolution limit, patterning of the gate electrode is performed once by photolithography (for example, exposure light having a wavelength of 193 nm and immersion reduced projection exposure). It is impossible to carry out with ArF lithography). In the 28 nm technology node or later generations, the gate stack structure includes a high-k gate insulating film and a metal-based gate, so that oxidation resistance and wet processing resistance are reduced. There is a tendency. In addition, because of the need to employ a multilayer resist process (45 nm technology node or later generations), there are problems inherent to the multilayer resist process.

  In order to solve the problem of the resolution limit, in this application, a multiple patterning process (Multiple Patterning Process) is adopted, in which the patterning of an etching mask film such as a resist film and the etching of a base film using the resist mask film are repeated multiple times. ing. However, a method of simply patterning the line-and-space pattern of the gate electrode (first lithography) and then patterning (second lithography) the adjacent gate electrode cutting region 12 (see FIG. 2) ( In the “L & S first method”, there is a problem that the resist film in the second lithography cannot secure flatness between the memory region 6 (pattern high density region) and the non-memory region 7 (pattern low density region). (See FIG. 1). Specifically, it is difficult to globally flatten with a lower layer film 15c (see FIG. 8) such as an SOC film.

  Therefore, in the examples shown in sections 2 to 4, first, the adjacent gate electrode cutting region 12 (see FIG. 2) is patterned (first lithography), and then the gate electrode line and space pattern is patterned (see FIG. 2). Second lithography) is performed (referred to as “L & S last method”). In this case, since the pattern density of the adjacent gate electrode cut region 12 (see FIG. 2) is generally low, the pattern density is unsatisfactory with the non-memory region 7 (pattern low density region). There is no balance.

  In the patterning of the adjacent gate electrode cut region 12 (see FIG. 2), when the shrink process (the process of reducing the area of the resist opening corresponding to the adjacent gate electrode cut region 12) is involved, the L & S first method is used. Since the unevenness of the ground is intense, the shrink shape becomes unstable depending on the ground. On the other hand, in the L & S last method, since the ground is flat, the shrink shape is stable.

  Further, in order to solve the problem of reduction in oxidation resistance and wet processing resistance, in addition to the L & S last method, the layout is made so that the adjacent gate electrode cut region 12 (see FIG. 2) is included in the element isolation region 9. It is effective (referred to as “a layout method in the gate edge element isolation region”). In the multiple patterning process, the removal of the resist film accompanied by ashing or wet chemical treatment is performed a plurality of times, so that excessive retraction of the gate insulating film and excessive oxidation of the metal-based gate electrode portion are likely to occur. However, in the layout method in the gate edge element isolation region, such multiple processing is performed not on the active region but mainly on the element isolation region 9 (see FIG. 2). The influence of can be reduced.

  In the L & S last method, it is effective to perform the patterning of the gate electrode in the non-memory region 7 simultaneously with the patterning of the line and space pattern of the gate electrode in the memory region 6. This is because the shrink process is a process for increasing the width of the resist covering portion and cannot be applied to the patterning of the line and space pattern of the gate electrode. In addition, by doing so, there is also an advantage that the trimming process can be applied to the patterning of the line and space patterns of the gate electrodes of the memory region 6 and the non-memory region 7 (regardless of the presence or absence of the shrink process).

  In the processes described in sections 2 to 4 and the like, basically, a hard mask (for example, SiN film) is not used, so that it is not necessary to remove the hard mask later, so that the entire process is simplified. Can do.

7). Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above embodiment, the gate first method has been mainly described as an example, but the present invention is not limited to this, and the dummy gate process in the gate last method is described. Needless to say, the present invention can also be applied to (Dummy Gate Process).

  In the above-described embodiment, a method not mainly using a hard mask has been specifically described as an example. However, the present invention is not limited thereto, and patterning of a cutting region between adjacent gate electrodes ( It goes without saying that a hard mask may be used for one or both of patterning and patterning of the line and space pattern of the gate electrode.

  Furthermore, in the above-described embodiment, an example in which an ordinary silicon-based (not silicon-based alloy) member is mainly used for the source / drain has been specifically described. However, the present invention is not limited thereto, and the source / drain is not limited thereto. Needless to say, the present invention can also be applied to those using silicon-based alloys (SiGe, SiC, etc.).

1 Wafer 1a Device main surface of wafer or chip (first main surface)
1b Back surface of wafer or chip 1n N well region 1p P well region 1s Semiconductor substrate region (P-type silicon single crystal substrate region)
2 Semiconductor chip or chip area 3 Notch 4 Chip peripheral part 5 Bonding pad 6 Memory area 7 Non-memory area 8 Active area 8n Active area of N channel device 8p Active area of P channel device 9 Element isolation area (STI)
11 A resist film for patterning a cutting region between adjacent gate electrodes (first resist film)
11a Upper layer film of the multilayer resist film for patterning the cutting region between adjacent gate electrodes 11b Intermediate layer film of the multilayer resist film for patterning the cutting region between adjacent gate electrodes 11c Lower layer film of the multilayer resist film for patterning the cutting region between adjacent gate electrodes 12 Cutting area (resist film opening corresponding to this)
14 Gate electrode (or gate electrode film)
14a Upper layer film of multilayer gate electrode (or gate electrode film) 14b Lower layer film of multilayer gate electrode (or gate electrode film) 15 Gate electrode patterning resist film (second resist film)
15a Upper layer film of the multilayer resist film for gate electrode patterning 15b Intermediate layer film of the multilayer resist film for gate electrode patterning 15c Lower layer film of the multilayer resist film for gate electrode patterning 16 Gate insulating film (gate insulating film having a High-k film)
17 Recessed part by etching 18 Side wall for shrink 19 Trimmed part (width of original resist film)
21 Offset spacer Silicon nitride film (offset spacer)
22n N-type extension region 22p P-type extension region 23a Side wall silicon oxide film (silicon oxide film side wall)
23b Side wall silicon nitride film (silicon nitride film side wall)
24n N-type high-concentration source / drain region 24p P-type high-concentration source / drain region 25 Silicide layer 26a Pre-metal lower layer insulation film 26b Pre-metal upper layer insulation film 27 Contact hole forming resist film 28 Normal contact hole (or contact portion)
29 Tungsten plug 30 Shared contact hole (or contact part)
BL, BLB Bit line IC Interconnect metal wiring MC Memory cell Q1, Q2 N-type memory transistor Q3, Q4 P-type memory transistor Q5, Q6 Read transistor R1 Memory area cutout part R2 Non-memory area cutout part R3 Non-memory area CMISFET pair cutout portion R3n Non-memory region CMISFET pair cutout portion N channel device region R3p Nonmemory region CMISFET pair cutout portion P channel device region Vdd Power supply line Vss Reference voltage line WL Word line

Claims (10)

A method of manufacturing a semiconductor integrated circuit device including the following steps:
(A) a step of preparing a semiconductor wafer having first and second main surfaces, the semiconductor wafer having a plurality of chip regions including a memory region and a non-memory region on the first main surface;
(B) forming a gate laminated film having a lower high-k gate insulating film and an upper gate metal electrode film on the first main surface of the semiconductor wafer;
(C) forming a first resist film for defining a cutting region between adjacent gate electrodes on the gate laminated film in the extending direction of the gate electrode in the memory region;
(D) forming a resist film opening corresponding to the cut region between the adjacent gate electrodes by performing patterning on the first resist film;
(E) performing the etching on the gate laminated film in a state where the patterned first resist film is present;
(F) a step of removing the first resist film after the step (e);
(G) After the step (f), a second resist film for defining a line and space pattern corresponding to the gate electrode in the memory region is formed on the first main surface of the semiconductor wafer. The step of:
(H) A step of patterning the second resist film;
(I) a step of performing etching on the gate laminated film in a state where the patterned second resist film is present;
(J) A step of removing the second resist film after the step (i).     In the method for manufacturing a semiconductor integrated circuit device according to the item 1, there is no hard mask film between the first resist film, the second resist film, and the gate laminated film.     In the method for manufacturing a semiconductor integrated circuit device according to the item 1, the second resist film in the step (g) is also for defining a line and space pattern corresponding to the gate electrode in the non-memory region.     In the method of manufacturing a semiconductor integrated circuit device according to the item 2, the cutting region between adjacent gate electrodes is in an element isolation region.     In the method for manufacturing a semiconductor integrated circuit device according to the item 2, each of the first resist film and the second resist film is a multilayer resist film. In the method of manufacturing a semiconductor integrated circuit device according to the item 5, the step (e) includes the following substeps:
(E1) executing a process of reducing the opening of the resist film;
(E2) A step of performing anisotropic dry etching on the gate laminated film under the opening of the resist film after the step (e1). In the method for manufacturing a semiconductor integrated circuit device according to the item 6, the step (i) includes the following substeps:
(I1) executing a process of reducing the width of the patterned second resist film;
(I2) A step of performing anisotropic dry etching on a portion of the gate laminated film that is not covered with the second resist film after the step (i1).     In the method for manufacturing a semiconductor integrated circuit device according to the item 1, the patterning in the steps (d) and (h) is performed by ArF lithography using 193 nm exposure light. In the method of manufacturing a semiconductor integrated circuit device according to the item 5, the first resist film and the second resist film have the following:
(X1) a lower resist film containing carbon as a main component;
(X2) an intermediate layer resist film containing silicon formed on the lower layer resist film as one of main components;
(X3) A photosensitive upper resist film formed on the intermediate resist film. In the method of manufacturing a semiconductor integrated circuit device according to the item 5, the second resist film has the following:
(X1) a lower-layer-coated resist film containing carbon as a main component;
(X2) an intermediate layer resist film containing silicon formed on the lower layer resist film as one of main components;
(X3) A photosensitive upper resist film formed on the intermediate resist film.

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