US20040164373A1 - Shallow trench isolation structure for strained Si on SiGe - Google Patents
Shallow trench isolation structure for strained Si on SiGe Download PDFInfo
- Publication number
- US20040164373A1 US20040164373A1 US10/374,866 US37486603A US2004164373A1 US 20040164373 A1 US20040164373 A1 US 20040164373A1 US 37486603 A US37486603 A US 37486603A US 2004164373 A1 US2004164373 A1 US 2004164373A1
- Authority
- US
- United States
- Prior art keywords
- trench
- layer
- liner
- sidewall
- top surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000002955 isolation Methods 0.000 title claims abstract description 35
- 229910000577 Silicon-germanium Inorganic materials 0.000 title abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims abstract description 31
- 230000000149 penetrating effect Effects 0.000 claims abstract description 5
- 239000012212 insulator Substances 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 7
- 238000000407 epitaxy Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 238000005520 cutting process Methods 0.000 claims description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 239000011800 void material Substances 0.000 claims description 2
- 229910052681 coesite Inorganic materials 0.000 claims 6
- 229910052906 cristobalite Inorganic materials 0.000 claims 6
- 239000000377 silicon dioxide Substances 0.000 claims 6
- 229910052682 stishovite Inorganic materials 0.000 claims 6
- 229910052905 tridymite Inorganic materials 0.000 claims 6
- 238000007254 oxidation reaction Methods 0.000 description 10
- 230000003647 oxidation Effects 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 230000037230 mobility Effects 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 208000032750 Device leakage Diseases 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
- H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
Definitions
- the present invention relates to the field of semiconductor devices in general.
- the invention relates to a shallow trench isolation structure, and method for fabricating such a structure, for MOSFET devices processed on substrates which comprise SiGe based material layers.
- the strained Si layer is typically formed by growing Si epitaxially over a relaxed graded SiGe (Ge stands for germanium) based layer as discussed in Materials Science and Engineering Reports R17, 105 (1996), by P. M. Mooney, and in U.S. Pat. No. 5,659,187 to LeGoues et al. titled: “Low Defect Density/arbitrary Lattice Constant Heteroepitaxial Layers” incorporated herein by reference.
- a heterostructure consisting of relaxed Si 0.7 Ge 0.3 capped with a thin (20 nm) strained Si layer has electron and hole mobilities over 80% higher than bulk Si. The higher mobility leads to faster switching speed, higher “on” current, and lower power dissipation.
- a MOSFET fabricated in tensile strained Si exhibits higher carrier mobilities than conventional MOSFET as it was shown for instance by K. Rim, et al. in “Enhanced performance in surface channel strained Si n and p MOSFETs”, Proceedings of the Twenty Sixth International Symposium on Compound Semiconductors Berlin, Germany 22-26 Aug. 1999. Fabrication of a tensilely strained Si layer is also taught in U.S.
- a possible solution to this problem would be to implement an STI process without a grown oxide liner.
- the oxide liner is a very important part of the isolation process. It serves to round the top corners of the trench, preventing high-field regions from forming between a polysilicon over layer and the substrate.
- the grown oxide liner also reduces the density of interface states at the STI edges that can cause carrier depletion in these regions.
- the liner also can prevent dopant diffusion into the STI trench, particularly if it is grown in the presence of nitrogen to form an oxy-nitride layer.
- the liner reduces stress and prevents defect injection into the substrate upon subsequent thermal processing. Therefore, without the grown liner oxide, an STI process would be difficult to implement in a manufacturing environment.
- One scheme consists of: a trench etched into a SiGe-containing substrate where the sidewalls of the trench are covered by a Si liner; a grown or deposited SiO 2 passivation layer; and an insulating material that fills the trench, and which is also planar with the wafer surface.
- the benefit of this structure is that it avoids thermal oxidation of SiGe on the walls of an etched trench by using a silicon liner that has vastly superior passivation properties compared to SiGe.
- This STI isolation scheme is described in U.S. Pat. Nos. 5,266,813 and 5,308,785 to Comfort et al. both titled: “Isolation technique for silicon germanium devices” and both incorporated herein by reference.
- the isolation structure is planar with the substrate top surface, when it would be desirable to have the insulating layer protrude above the surface to prevent non-uniform oxidation of the exposed Si liner, and to offset recessing of the isolation layers that can occur during subsequent processing.
- the thermal oxidation of the Si liner may be slower at the edge, possibly leading to enhanced breakdown of the gate oxide. This problem would be exacerbated if the dielectric in the trench were accidentally recessed, exposing the corner of the trench liner before growth of the gate oxide.
- the Si liner on the surface of the isolation structure is in a polycrystalline state, which is notoriously unsuitable for high performance devices.
- the polysilicon on the surface of the protruding insolation would also extend continuously from the source to the drain at the edge of the device, and could cause leakage between source and drain. In this prior art there is no suggestion how one could overcome the discussed difficulties.
- this invention discloses a structure, and a method of fabricating the same, which serves the isolation purposes without such problems.
- This result is obtained by using a key processing step, namely the selective epitaxial growth of the Si liner.
- Selective growth means that the Si deposits on the exposed crystalline Si or SiGe surfaces, but does not deposit on any other surface.
- Such selective epitaxial deposition techniques are widely practiced in the electronics processing arts. In this manner one can form a high-quality passivation layer, thereby eliminating problems associated with the oxidation of SiGe, and at the same time avoiding problems associated with an exposed polycrystalline Si layer on the protruding isolation structure.
- FIG. 1 shows schematic cross sectional views of embodiments of the isolation structure
- FIG. 2 shows a schematic cross sectional view of the isolation structure over a substrate comprising a buried insulator layer
- FIG. 3 shows a schematic cross sectional view of the of a MOSFET transistor utilizing the isolation scheme of the invention.
- FIG. 4 depicts a process sequence for making the isolation structure of the invention.
- FIG. 1 shows a schematic of embodiments of the isolation structure.
- FIG. 1A shows an embodiment where the Si liner does not reach up to the top of the surface of the wafer.
- FIG. 1B shows an embodiment where the Si liner does reach up to the top of the surface of the wafer.
- the two variations of the embodiment depends on the relative thickness of the Si liner 40 and the isolator layer 50 grown on the Si liner.
- the two embodiments of FIG. 1A and FIG. 1B are equally preferred and acceptable solutions to the objects of the invention.
- the embodiment comprises a SiGe based layer 10 .
- Layer 10 is on top of a support structure 70 , typically a Si wafer.
- the SiGe based layer is capped by a Si layer 20 , typically in a tensilely strained state.
- the top surface of the substrate 25 in this case is also the top surface 25 of the tensilely strained Si layer 20 .
- the support structure 70 , the SiGe based layer 10 , and the Si layer 20 together form the substrate.
- the substrate has a top surface 25 , which in FIG. 1A and FIG. 1B is the top surface of the Si layer 20 .
- a trench is extending downward from the top surface 25 penetrating into the SiGe based layer 10 , and passing through the Si layer 20 .
- the trench is filled with three materials: a Si liner 40 , an oxide (SiO 2 ) or oxy-nitride insulator liner 50 , and a oxide trench filling dielectric 60 .
- the trench filling dielectric 60 protrudes over the top 25 of the substrate. This protrusion of the trench filling dielectric 60 is a significant aspect of the present invention.
- the sidewall of the trench, which is formed inside the substrate, is covered by the Si liner 40 .
- the Si liner 40 covers all the surface of the SiGe based layer 10 which is on the trench sidewall. However, the Si liner 40 does not reach as high as the top edge of the trench, which edge is formed where the trench intersects the substrate top surface 25 .
- the Si liner 40 leaves uncovered a strip shaped surface 55 on the sidewall, where the strip shaped surface 55 runs along the sidewall edge. Because of this strip 55 the Si liner 40 only partially covers the surface of the Si layer 20 which is on the trench sidewall. In FIG. 1A the Si liner 40 does not break out to the top surface 25 anywhere. FIG. 1B is exactly as FIG. 1A with the exception that the Si liner 40 reaches higher than the substrate top surface 25 . This can happen because even for the case of selective epitaxy the thickness of the Si liner causes growth on the trench sidewall which reaches over the top surface 25 . However, the Si liner 40 is a monocrystalline material in its entirety, with no polycrystalline material composition.
- FIG. 1A and FIG. 1B are equally preferred and acceptable solutions to the objects of the invention in further figures only the embodiment where the Si liner 40 does not reach the top surface 25 will be shown. However, one skilled in the art would notice that where Si liner 40 reaches above the top surface of the substrate 25 is an equally acceptable embodiment.
- the invention assures that by using a Si liner 40 , Si is oxidized and not the sidewall surface of the SiGe based layer 10 , eliminating the Ge “snowplowing” effect. Furthermore, the Si liner 10 is a monocrystalline material in an epitaxial relationship with the sidewall, therefore enabling a high-quality oxide and good Si/SiO 2 interface quality to be obtained.
- the SiGe based layers are known in the art and can have a wide variety of compositions. Their purpose is to strain the overlaying Si layer, while maintaining a “device quality” material for the overlaying Si layer.
- the fabrication of such layers is described, for instance, in U.S. patent application Ser. No. 10/073,562, “Strained Si based layer made by UHV-CVD, and Devices Therein”, by J. Chu et al, filed Feb. 11, 2002, (Attorney Docket no.: YOR920010573US1).
- the composition of the SiGe based layer is typically SiGe, SiGeC, or even pure Ge, or a multi-layer structure consisting of one or more of the preceding list.
- the Si liner 40 in the trench is between about 1 nm and 50 nm thick; the strained Si layer 20 forming the top surface is between about 1 nm and 50 nm thick.; the SiGe based layer is between about 5 nm and 5 ⁇ m thick.; the insulator layer 50 grown on the Si liner 40 is between about 1 nm and 100 nm thick; the strip shaped surface on the sidewall below the edge of the top surface of the substrate, left uncovered by the Si liner 40 , is between about 1 nm and 50 nm wide; the trench dielectric 60 protrudes above the top surface of the substrate by about between 1 nm and 500 nm; the trench itself reaches a depth relative to the top surface of the substrate of about between 2 nm and 1 ⁇ m.
- FIG. 2 shows a schematic cross sectional view of the isolation structure over a substrate further comprising a buried insulator layer 80 .
- the substrate comprises the buried insulator layer 80 between the support 70 , typically Si, and the Siege based layer 10 .
- the buried insulator layer 80 is typically SiO 2 .
- the isolation structure is essentially the same as on bulk of FIG. 1, except that as the result of the selective deposition of the Si liner 40 , the Si liner 40 , and therefore the thermal SiO 2 layer 50 , are not found over the buried insulator layer 80 .
- FIG. 3 shows a schematic cross sectional view of the of a MOSFET transistor utilizing the isolation scheme of the invention.
- the MOSFET comprises a gate electrode 110 , separated from the strained Si layer 20 by an insulating gate dielectric 120 , which is typically SiO 2 .
- gate dielectric 120 typically SiO 2 .
- the source and drain regions 130 and 140 are implemented. In FIG. 3, as shown, it is not significant on which side of the gate is the source 130 , and on which side is the drain 140 .
- the remaining Si left over from the Si liner 40 after the thermal oxidation, is doped the same type as the source and drain regions and therefore becomes part of the source and drain regions 130 and 140 .
- the Si liner 40 is a monocrystalline material due to its selective deposition.
- the entire source/drain and gate regions are surrounded by the thermally-grown SiO 2 layer 50 , and the trench filling dielectric 60 .
- the MOSFET of FIG. 3 utilizes a buried SiO 2 layer 80 .
- One skilled in the art would notice that a similar device implementation could utilize a bulk substrate and isolation scheme shown in FIG. 1.
- a plurality of MOSFET devices shown schematically on FIG. 3 can form the basis of any system in need of MOSFET devices. In particular, for the case of digital processors such MOSFETs are typically wired into CMOS circuits, which then can form all the various logic circuits needed by the processors.
- FIG. 4 depicts a process sequence for making the isolation structure of the invention.
- One skilled in the art would notice that only the salient features of the process of one embodiment are being presented. Many further steps, all known in the electronics processing arts, may be needed to completely fabricate the isolation structure. Thus the presented steps should not be read in a way that is in any manner limiting.
- FIG. 4A shows the starting substrate comprising a relaxed Siege based layer 10 , with a strained Si layer 20 on top of it, and having a top surface 25 , same as the substrate top surface.
- the top surface 25 is then overlaid with a capping dielectric layer 30 , preferably silicon nitride to a thickness of between about 10 nm to 500 nm.
- This capping dielectric acts as a stopping layer for subsequent planarization steps.
- a thin etch protection SiO 2 layer 90 can be placed underneath dielectric capping layer 30 , to ensure that the substrate is not etched during the removal of layer 30 .
- a trench is etched, with the trench cutting through the capping dielectric layer 30 , and extending downward from the top surface of the substrate, which is the top surface of Si layer 20 .
- the trench next penetrates into the Siege based layer 10 .
- the trench has an auxiliary sidewall formed in the capping dielectric layer 30 , and has a sidewall formed in the substrate with crystalline layers 20 and 10 .
- the trench has a sidewall edge formed where the sidewall intersects the top surface of layer 20 .
- FIG. 4B a monocrystalline Si liner 40 is deposited by selective epitaxy over the sidewall, including a surface of the Siege based layer 10 on the sidewall.
- FIG. 4D depicts the state of the process after an insulator 50 is grown on the Si liner 40 , partially consuming the Si liner 40 . This consumption of the Si liner 40 is thinning the Si liner compared to as it was deposited on FIG. 4C. As shown in FIG.
- the insulator layer 50 removes the Si liner 40 in a strip shaped surface of the sidewall, where the strip 55 shaped surface runs along the sidewall edge.
- the Si liner does not reach up to the to surface 25 of the strained Si layer 20 .
- the layer inside the trench which intersects the top surface of the substrate is the grown insulator 50 .
- the thermally grown insulator 50 is typically a silicon-oxide or oxy-nitride. As shown in FIG. 1B, it is possible that the insulator 50 does not consume as much of the Si liner 40 that the liner would be below the top surface 25 .
- FIG. 1B it is possible that the insulator 50 does not consume as much of the Si liner 40 that the liner would be below the top surface 25 .
- a trench dielectric 60 is blanket deposited in a thickness that the trench dielectric 60 overfills the trench, beyond the top of the capping dielectric layer 30 . It is preferred that this trench dielectric consists essentially of SiO 2 .
- the next step is to polish the trench dielectric layer 60 until the capping dielectric 30 and the trench dielectric 60 form one common surface.
- the capping dielectric 30 acts as a stopping layer for the polishing step.
- FIG. 4G shows the step where the trench dielectric 60 is selectively etched down to a protruding level which is above the top surface of the strained Si layer 20 . This step is done typically by using a wet or dry selective etch.
- the trench is filled with a trench dielectric 60 to a protruding level which is above the substrate top surface.
- the capping dielectric 30 is removed, whereby the trench dielectric 60 remains protruding out of the trench to above the top surface of the Si layer 20 .
- the removal of the capping layer 30 is done selectively with 5 respect to the underlying Si layer 20 and trench dielectric 60 . If the optional thin SiO 2 layer 90 were used in the process, then it is removed after the removal of the capping dielectric 60 . Layer 90 would serve in a protective role making sure that the strained Si layer 20 is not etched during the removal of the capping dielectric layer 30 . With these etching steps the process is complete.
- the process illustrated in FIG. 4 was for an 10 embodiment with a bulk substrate, but one skilled in the art would notice that the process would be essentially identical for a substrate comprising a buried oxide layer 80 , as shown on FIG. 2.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Element Separation (AREA)
Abstract
Description
- The present invention relates to the field of semiconductor devices in general. In particular, the invention relates to a shallow trench isolation structure, and method for fabricating such a structure, for MOSFET devices processed on substrates which comprise SiGe based material layers.
- Today's integrated circuits include a vast number of devices. Smaller devices are key to enhance performance and to improve reliability. As MOSFET (Metal Oxide Semiconductor Field-Effect-Transistor, a name with historic connotations meaning in general an insulated gate Field-Effect-Transistor) devices are being scaled down, however, the technology becomes more complex and changes in device structures and new fabrication methods are needed to maintain the expected performance enhancement from one generation of devices to the next. In this regard the semiconductor that has progressed the farthest is the primary semiconducting material of microelectronics: silicon (Si).
- There is great difficulty in maintaining performance improvements in devices of deeply submicron generations. Several avenues are being explored for keeping device performance improvements on track. Among these is the use of tensilely strained Si as the basic semiconducting device material. The strained Si layer is typically formed by growing Si epitaxially over a relaxed graded SiGe (Ge stands for germanium) based layer as discussed in Materials Science and Engineering Reports R17, 105 (1996), by P. M. Mooney, and in U.S. Pat. No. 5,659,187 to LeGoues et al. titled: “Low Defect Density/arbitrary Lattice Constant Heteroepitaxial Layers” incorporated herein by reference. For instance, a heterostructure consisting of relaxed Si0.7Ge0.3 capped with a thin (20 nm) strained Si layer has electron and hole mobilities over 80% higher than bulk Si. The higher mobility leads to faster switching speed, higher “on” current, and lower power dissipation. A MOSFET fabricated in tensile strained Si exhibits higher carrier mobilities than conventional MOSFET as it was shown for instance by K. Rim, et al. in “Enhanced performance in surface channel strained Si n and p MOSFETs”, Proceedings of the Twenty Sixth International Symposium on Compound Semiconductors Berlin, Germany 22-26 Aug. 1999. Fabrication of a tensilely strained Si layer is also taught in U.S. patent application titled: “Strained Si based layer made by UHV-CVD, and Devices Therein”, by J. Chu et al, filed Feb. 11, 2002, Ser. No. 10/073562, (IBM Docket no.: YOR920010573US1) incorporated herein by reference.
- Innovations solving a problem, such as using SiGe as substrate material, often lead to unexpected complications. Such an unexpected difficulty arises in isolating devices when the substrate contains Ge. The two main device isolation schemes currently used in VLSI CMOS fabrication, local-oxidation of silicon (LOCOS) and shallow trench isolation (STI), both involve thermal oxidation of the substrate. However, thermal oxidation of SiGe based materials at high temperatures results in a high interface-state density, and defects caused by “snowplowing” of Ge. Therefore oxidation of SiGe based materials must be avoided in any isolation scheme.
- A possible solution to this problem would be to implement an STI process without a grown oxide liner. However, the oxide liner is a very important part of the isolation process. It serves to round the top corners of the trench, preventing high-field regions from forming between a polysilicon over layer and the substrate. The grown oxide liner also reduces the density of interface states at the STI edges that can cause carrier depletion in these regions. The liner also can prevent dopant diffusion into the STI trench, particularly if it is grown in the presence of nitrogen to form an oxy-nitride layer. Finally, the liner reduces stress and prevents defect injection into the substrate upon subsequent thermal processing. Therefore, without the grown liner oxide, an STI process would be difficult to implement in a manufacturing environment.
- Recognizing the problem, structures and methods were invented to avoid the oxidizing of Ge. One scheme consists of: a trench etched into a SiGe-containing substrate where the sidewalls of the trench are covered by a Si liner; a grown or deposited SiO2 passivation layer; and an insulating material that fills the trench, and which is also planar with the wafer surface. The benefit of this structure is that it avoids thermal oxidation of SiGe on the walls of an etched trench by using a silicon liner that has vastly superior passivation properties compared to SiGe. This STI isolation scheme is described in U.S. Pat. Nos. 5,266,813 and 5,308,785 to Comfort et al. both titled: “Isolation technique for silicon germanium devices” and both incorporated herein by reference.
- However, the use of this prior art has significant drawbacks. The isolation structure is planar with the substrate top surface, when it would be desirable to have the insulating layer protrude above the surface to prevent non-uniform oxidation of the exposed Si liner, and to offset recessing of the isolation layers that can occur during subsequent processing. The thermal oxidation of the Si liner may be slower at the edge, possibly leading to enhanced breakdown of the gate oxide. This problem would be exacerbated if the dielectric in the trench were accidentally recessed, exposing the corner of the trench liner before growth of the gate oxide. If one tried to correct for the planarity of the isolation structure and attempt to make it to protrude out of the substrate top surface, then having the Si liner surrounding high up the protruding isolation can cause severe device problems. The problem is that the Si liner on the surface of the isolation structure is in a polycrystalline state, which is notoriously unsuitable for high performance devices. In a MOSFET geometry, the polysilicon on the surface of the protruding insolation would also extend continuously from the source to the drain at the edge of the device, and could cause leakage between source and drain. In this prior art there is no suggestion how one could overcome the discussed difficulties.
- In view of the discussed problems, this invention discloses a structure, and a method of fabricating the same, which serves the isolation purposes without such problems. This result is obtained by using a key processing step, namely the selective epitaxial growth of the Si liner. Selective growth means that the Si deposits on the exposed crystalline Si or SiGe surfaces, but does not deposit on any other surface. Such selective epitaxial deposition techniques are widely practiced in the electronics processing arts. In this manner one can form a high-quality passivation layer, thereby eliminating problems associated with the oxidation of SiGe, and at the same time avoiding problems associated with an exposed polycrystalline Si layer on the protruding isolation structure.
- It is the object of the present invention to have an isolation that structure does not lead to device leakage or gate oxide breakdown.
- It is also an object of the present invention to teach a process for forming the isolation region that eliminates the requirement for precise planarization, and allows for flexibility in tailoring the height of the isolation region.
- It is a further object of the present invention to teach the structure of a shallow-trench isolation with an Si liner formed by selective growth and subsequent oxidation of Si in the trench.
- It is yet a further object of the present invention to teach devices, circuits, and processors fabricated with the invented isolation scheme.
- These and other features of the present invention will become apparent from the accompanying detailed description and drawings, wherein:
- FIG. 1 shows schematic cross sectional views of embodiments of the isolation structure;
- FIG. 2 shows a schematic cross sectional view of the isolation structure over a substrate comprising a buried insulator layer;
- FIG. 3 shows a schematic cross sectional view of the of a MOSFET transistor utilizing the isolation scheme of the invention; and
- FIG. 4 depicts a process sequence for making the isolation structure of the invention.
- FIG. 1 shows a schematic of embodiments of the isolation structure. FIG. 1A shows an embodiment where the Si liner does not reach up to the top of the surface of the wafer. FIG. 1B shows an embodiment where the Si liner does reach up to the top of the surface of the wafer. The two variations of the embodiment depends on the relative thickness of the
Si liner 40 and theisolator layer 50 grown on the Si liner. The two embodiments of FIG. 1A and FIG. 1B are equally preferred and acceptable solutions to the objects of the invention. In FIG. 1A, the embodiment comprises a SiGe basedlayer 10.Layer 10 is on top of asupport structure 70, typically a Si wafer. The SiGe based layer is capped by aSi layer 20, typically in a tensilely strained state. The top surface of thesubstrate 25, in this case is also thetop surface 25 of the tensilelystrained Si layer 20. Thesupport structure 70, the SiGe basedlayer 10, and theSi layer 20 together form the substrate. The substrate has atop surface 25, which in FIG. 1A and FIG. 1B is the top surface of theSi layer 20. A trench is extending downward from thetop surface 25 penetrating into the SiGe basedlayer 10, and passing through theSi layer 20. The trench is filled with three materials: aSi liner 40, an oxide (SiO2) or oxy-nitride insulator liner 50, and a oxidetrench filling dielectric 60. Thetrench filling dielectric 60 protrudes over the top 25 of the substrate. This protrusion of thetrench filling dielectric 60 is a significant aspect of the present invention. The sidewall of the trench, which is formed inside the substrate, is covered by theSi liner 40. TheSi liner 40 covers all the surface of the SiGe basedlayer 10 which is on the trench sidewall. However, theSi liner 40 does not reach as high as the top edge of the trench, which edge is formed where the trench intersects thesubstrate top surface 25. TheSi liner 40 leaves uncovered a strip shapedsurface 55 on the sidewall, where the strip shapedsurface 55 runs along the sidewall edge. Because of thisstrip 55 theSi liner 40 only partially covers the surface of theSi layer 20 which is on the trench sidewall. In FIG. 1A theSi liner 40 does not break out to thetop surface 25 anywhere. FIG. 1B is exactly as FIG. 1A with the exception that theSi liner 40 reaches higher than thesubstrate top surface 25. This can happen because even for the case of selective epitaxy the thickness of the Si liner causes growth on the trench sidewall which reaches over thetop surface 25. However, theSi liner 40 is a monocrystalline material in its entirety, with no polycrystalline material composition. Thus the problems in device fabrication due to polycrystalline Si reaching beyond thetop surface 25 are avoided because now theSi liner 40 does not cause gate oxide or source-to-drain leakage. Since the embodiments of FIG. 1A and FIG. 1B are equally preferred and acceptable solutions to the objects of the invention in further figures only the embodiment where theSi liner 40 does not reach thetop surface 25 will be shown. However, one skilled in the art would notice that whereSi liner 40 reaches above the top surface of thesubstrate 25 is an equally acceptable embodiment. - The invention assures that by using a
Si liner 40, Si is oxidized and not the sidewall surface of the SiGe basedlayer 10, eliminating the Ge “snowplowing” effect. Furthermore, theSi liner 10 is a monocrystalline material in an epitaxial relationship with the sidewall, therefore enabling a high-quality oxide and good Si/SiO2 interface quality to be obtained. - The SiGe based layers are known in the art and can have a wide variety of compositions. Their purpose is to strain the overlaying Si layer, while maintaining a “device quality” material for the overlaying Si layer. The fabrication of such layers is described, for instance, in U.S. patent application Ser. No. 10/073,562, “Strained Si based layer made by UHV-CVD, and Devices Therein”, by J. Chu et al, filed Feb. 11, 2002, (Attorney Docket no.: YOR920010573US1). The composition of the SiGe based layer is typically SiGe, SiGeC, or even pure Ge, or a multi-layer structure consisting of one or more of the preceding list.
- Dimensions of various layer thicknesses can vary significantly depending, for instance, on the type of circuits that are involved in the applications. Device technology with time is becoming more advanced along the general tendency of shrinking dimensions. Dimension values given here should not be read as restrictive, as one skilled in the art would recognize that several other dimensional variations might be possible, all the while maintaining the scope of the present invention. The
Si liner 40 in the trench is between about 1 nm and 50 nm thick; thestrained Si layer 20 forming the top surface is between about 1 nm and 50 nm thick.; the SiGe based layer is between about 5 nm and 5 μm thick.; theinsulator layer 50 grown on theSi liner 40 is between about 1 nm and 100 nm thick; the strip shaped surface on the sidewall below the edge of the top surface of the substrate, left uncovered by theSi liner 40, is between about 1 nm and 50 nm wide; thetrench dielectric 60 protrudes above the top surface of the substrate by about between 1 nm and 500 nm; the trench itself reaches a depth relative to the top surface of the substrate of about between 2 nm and 1 μm. - FIG. 2 shows a schematic cross sectional view of the isolation structure over a substrate further comprising a buried
insulator layer 80. Here, the substrate comprises the buriedinsulator layer 80 between thesupport 70, typically Si, and the Siege basedlayer 10. The buriedinsulator layer 80 is typically SiO2. The isolation structure is essentially the same as on bulk of FIG. 1, except that as the result of the selective deposition of theSi liner 40, theSi liner 40, and therefore the thermal SiO2 layer 50, are not found over the buriedinsulator layer 80. - FIG. 3 shows a schematic cross sectional view of the of a MOSFET transistor utilizing the isolation scheme of the invention. The MOSFET comprises a
gate electrode 110, separated from thestrained Si layer 20 by an insulatinggate dielectric 120, which is typically SiO2. On either side of thegate 110 the source and drainregions source 130, and on which side is thedrain 140. The remaining Si, left over from theSi liner 40 after the thermal oxidation, is doped the same type as the source and drain regions and therefore becomes part of the source and drainregions Si liner 40 is a monocrystalline material due to its selective deposition. The entire source/drain and gate regions are surrounded by the thermally-grown SiO2 layer 50, and thetrench filling dielectric 60. The MOSFET of FIG. 3 utilizes a buried SiO2 layer 80. One skilled in the art would notice that a similar device implementation could utilize a bulk substrate and isolation scheme shown in FIG. 1. A plurality of MOSFET devices shown schematically on FIG. 3 can form the basis of any system in need of MOSFET devices. In particular, for the case of digital processors such MOSFETs are typically wired into CMOS circuits, which then can form all the various logic circuits needed by the processors. - FIG. 4 depicts a process sequence for making the isolation structure of the invention. One skilled in the art would notice that only the salient features of the process of one embodiment are being presented. Many further steps, all known in the electronics processing arts, may be needed to completely fabricate the isolation structure. Thus the presented steps should not be read in a way that is in any manner limiting.
- FIG. 4A shows the starting substrate comprising a relaxed Siege based
layer 10, with astrained Si layer 20 on top of it, and having atop surface 25, same as the substrate top surface. Thetop surface 25 is then overlaid with a cappingdielectric layer 30, preferably silicon nitride to a thickness of between about 10 nm to 500 nm. This capping dielectric acts as a stopping layer for subsequent planarization steps. Optionally, a thin etch protection SiO2 layer 90 can be placed underneathdielectric capping layer 30, to ensure that the substrate is not etched during the removal oflayer 30. Then a trench is etched, with the trench cutting through the cappingdielectric layer 30, and extending downward from the top surface of the substrate, which is the top surface ofSi layer 20. The trench next penetrates into the Siege basedlayer 10. In this manner the trench has an auxiliary sidewall formed in the cappingdielectric layer 30, and has a sidewall formed in the substrate withcrystalline layers layer 20. The result of these steps is shown in FIG. 4B. Next, as shown in FIG. 4C, amonocrystalline Si liner 40 is deposited by selective epitaxy over the sidewall, including a surface of the Siege basedlayer 10 on the sidewall. The selective epitaxy leaves the auxiliary sidewall of the cappingdielectric layer 30 void of the Si liner grown in the trench. Preferred methods of depositing the single-crystal liner are rapid-thermal chemical vapor deposition and ultra-high-vacuum chemical vapor deposition. These, and other such methods are widely practiced in the electronics processing arts. FIG. 4D depicts the state of the process after aninsulator 50 is grown on theSi liner 40, partially consuming theSi liner 40. This consumption of theSi liner 40 is thinning the Si liner compared to as it was deposited on FIG. 4C. As shown in FIG. 4C and the following ones theinsulator layer 50 removes theSi liner 40 in a strip shaped surface of the sidewall, where thestrip 55 shaped surface runs along the sidewall edge. Here the Si liner does not reach up to the to surface 25 of thestrained Si layer 20. The layer inside the trench which intersects the top surface of the substrate is the growninsulator 50. The thermally growninsulator 50 is typically a silicon-oxide or oxy-nitride. As shown in FIG. 1B, it is possible that theinsulator 50 does not consume as much of theSi liner 40 that the liner would be below thetop surface 25. Next, as shown in FIG. 4E, atrench dielectric 60 is blanket deposited in a thickness that thetrench dielectric 60 overfills the trench, beyond the top of the cappingdielectric layer 30. It is preferred that this trench dielectric consists essentially of SiO2. As shown in FIG. 4F, the next step is to polish thetrench dielectric layer 60 until the cappingdielectric 30 and thetrench dielectric 60 form one common surface. The capping dielectric 30 acts as a stopping layer for the polishing step. FIG. 4G shows the step where thetrench dielectric 60 is selectively etched down to a protruding level which is above the top surface of thestrained Si layer 20. This step is done typically by using a wet or dry selective etch. In this manner the trench is filled with atrench dielectric 60 to a protruding level which is above the substrate top surface. Finally as shown in FIG. 4H, the cappingdielectric 30 is removed, whereby thetrench dielectric 60 remains protruding out of the trench to above the top surface of theSi layer 20. The removal of thecapping layer 30 is done selectively with 5 respect to theunderlying Si layer 20 andtrench dielectric 60. If the optional thin SiO2 layer 90 were used in the process, then it is removed after the removal of the cappingdielectric 60.Layer 90 would serve in a protective role making sure that thestrained Si layer 20 is not etched during the removal of the cappingdielectric layer 30. With these etching steps the process is complete. The process illustrated in FIG. 4 was for an 10 embodiment with a bulk substrate, but one skilled in the art would notice that the process would be essentially identical for a substrate comprising a buriedoxide layer 80, as shown on FIG. 2. - Many modifications and variations of the present invention are possible in light of the above teachings, and could be apparent for those skilled in the art. The scope of the invention is defined by the appended claims.
Claims (30)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/374,866 US20040164373A1 (en) | 2003-02-25 | 2003-02-25 | Shallow trench isolation structure for strained Si on SiGe |
TW093103893A TW200507169A (en) | 2003-02-25 | 2004-02-18 | Shallow trench isolation structure for strained Si on SiGe |
KR1020057013671A KR20050118162A (en) | 2003-02-25 | 2004-02-20 | Shallow trench isolation structure for strained si on sige |
PCT/US2004/005020 WO2004077509A2 (en) | 2003-02-25 | 2004-02-20 | SHALLOW TRENCH ISOLATION STRUCTURE FOR STRAINED Si ON SiGe |
US11/172,707 US7183175B2 (en) | 2003-02-25 | 2005-07-01 | Shallow trench isolation structure for strained Si on SiGe |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/374,866 US20040164373A1 (en) | 2003-02-25 | 2003-02-25 | Shallow trench isolation structure for strained Si on SiGe |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/172,707 Division US7183175B2 (en) | 2003-02-25 | 2005-07-01 | Shallow trench isolation structure for strained Si on SiGe |
Publications (1)
Publication Number | Publication Date |
---|---|
US20040164373A1 true US20040164373A1 (en) | 2004-08-26 |
Family
ID=32868962
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/374,866 Abandoned US20040164373A1 (en) | 2003-02-25 | 2003-02-25 | Shallow trench isolation structure for strained Si on SiGe |
US11/172,707 Expired - Fee Related US7183175B2 (en) | 2003-02-25 | 2005-07-01 | Shallow trench isolation structure for strained Si on SiGe |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/172,707 Expired - Fee Related US7183175B2 (en) | 2003-02-25 | 2005-07-01 | Shallow trench isolation structure for strained Si on SiGe |
Country Status (4)
Country | Link |
---|---|
US (2) | US20040164373A1 (en) |
KR (1) | KR20050118162A (en) |
TW (1) | TW200507169A (en) |
WO (1) | WO2004077509A2 (en) |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040256634A1 (en) * | 2003-06-13 | 2004-12-23 | Renesas Technology Corp. | Semiconductor device |
US20050023576A1 (en) * | 2003-07-31 | 2005-02-03 | Wen-Chin Lee | Semiconductor structure having a strained region and a method of fabricating same |
US20050032327A1 (en) * | 2002-07-03 | 2005-02-10 | Renesas Technology Corporation | Fabrication method and device structure of shallow trench insulation for silicon wafer containing silicon-germanium |
US20050282353A1 (en) * | 2004-06-17 | 2005-12-22 | Texas Instruments, Incorporated | Trench isolation structure and a method of manufacture therefor |
WO2006049848A2 (en) * | 2004-11-01 | 2006-05-11 | Advanced Micro Devices, Inc. | Method of forming isolation trench with spacer formation |
US20060208336A1 (en) * | 2003-09-08 | 2006-09-21 | Wen-Chin Lee | Semiconductor structure having a strained region and a method of fabricating same |
US20080078987A1 (en) * | 2006-09-29 | 2008-04-03 | Tokyo Electron Limited | UV-assisted dielectric formation for devices with strained germanium-containing layers |
US7439165B2 (en) | 2005-04-06 | 2008-10-21 | Agency For Sceince, Technology And Reasearch | Method of fabricating tensile strained layers and compressive strain layers for a CMOS device |
US20140151759A1 (en) * | 2012-12-03 | 2014-06-05 | Stmicroelectronics, Inc. | Facet-free strained silicon transistor |
US11282890B2 (en) * | 2020-01-21 | 2022-03-22 | Omnivision Technologies, Inc. | Shallow trench isolation (STI) structure for suppressing dark current and method of forming |
US11289530B2 (en) | 2020-01-21 | 2022-03-29 | Omnivision Technologies, Inc. | Shallow trench isolation (STI) structure for CMOS image sensor |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090096055A1 (en) * | 2007-10-16 | 2009-04-16 | Texas Instruments Incorporated | Method to form cmos circuits with sub 50nm sti structures using selective epitaxial silicon post sti etch |
US20090230438A1 (en) * | 2008-03-13 | 2009-09-17 | International Business Machines Corporation | Selective nitridation of trench isolation sidewall |
US20110140229A1 (en) * | 2009-12-16 | 2011-06-16 | Willy Rachmady | Techniques for forming shallow trench isolation |
WO2012141122A1 (en) * | 2011-04-14 | 2012-10-18 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device and method for manufacturing semiconductor integrated circuit device |
US9601594B2 (en) * | 2011-11-14 | 2017-03-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with enhanced strain |
US9209066B2 (en) | 2013-03-01 | 2015-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Isolation structure of semiconductor device |
CN111106057A (en) * | 2019-11-18 | 2020-05-05 | 华虹半导体(无锡)有限公司 | Method for manufacturing STI (shallow trench isolation) structure of flash memory device and flash memory device |
KR20220004899A (en) | 2020-07-03 | 2022-01-12 | 삼성전자주식회사 | Semiconductor devices and method of fabricating the same |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5212110A (en) * | 1992-05-26 | 1993-05-18 | Motorola, Inc. | Method for forming isolation regions in a semiconductor device |
US5266813A (en) * | 1992-01-24 | 1993-11-30 | International Business Machines Corporation | Isolation technique for silicon germanium devices |
US6482715B2 (en) * | 2000-12-16 | 2002-11-19 | Samsung Electronics Co., Ltd. | Method of forming shallow trench isolation layer in semiconductor device |
US6706581B1 (en) * | 2002-10-29 | 2004-03-16 | Taiwan Semiconductor Manufacturing Company | Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices |
US6727553B2 (en) * | 2001-08-27 | 2004-04-27 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device including SOI substrate |
US6730980B2 (en) * | 2000-08-28 | 2004-05-04 | Micron Technology, Inc. | Multi-trench region for accumulation of photo-generated charge in a CMOS imager |
US6730576B1 (en) * | 2002-12-31 | 2004-05-04 | Advanced Micro Devices, Inc. | Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6150212A (en) | 1999-07-22 | 2000-11-21 | International Business Machines Corporation | Shallow trench isolation method utilizing combination of spacer and fill |
JP2003031495A (en) * | 2001-07-12 | 2003-01-31 | Hitachi Ltd | Manufacturing method of semiconductor device substrate and semiconductor device |
JP4421811B2 (en) * | 2002-06-25 | 2010-02-24 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit device and manufacturing method thereof |
-
2003
- 2003-02-25 US US10/374,866 patent/US20040164373A1/en not_active Abandoned
-
2004
- 2004-02-18 TW TW093103893A patent/TW200507169A/en unknown
- 2004-02-20 KR KR1020057013671A patent/KR20050118162A/en not_active Application Discontinuation
- 2004-02-20 WO PCT/US2004/005020 patent/WO2004077509A2/en active Search and Examination
-
2005
- 2005-07-01 US US11/172,707 patent/US7183175B2/en not_active Expired - Fee Related
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5266813A (en) * | 1992-01-24 | 1993-11-30 | International Business Machines Corporation | Isolation technique for silicon germanium devices |
US5308785A (en) * | 1992-01-24 | 1994-05-03 | International Business Machines Corporation | Isolation technique for silicon germanium devices |
US5212110A (en) * | 1992-05-26 | 1993-05-18 | Motorola, Inc. | Method for forming isolation regions in a semiconductor device |
US6730980B2 (en) * | 2000-08-28 | 2004-05-04 | Micron Technology, Inc. | Multi-trench region for accumulation of photo-generated charge in a CMOS imager |
US6482715B2 (en) * | 2000-12-16 | 2002-11-19 | Samsung Electronics Co., Ltd. | Method of forming shallow trench isolation layer in semiconductor device |
US6727553B2 (en) * | 2001-08-27 | 2004-04-27 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device including SOI substrate |
US6706581B1 (en) * | 2002-10-29 | 2004-03-16 | Taiwan Semiconductor Manufacturing Company | Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices |
US6730576B1 (en) * | 2002-12-31 | 2004-05-04 | Advanced Micro Devices, Inc. | Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer |
Cited By (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050032327A1 (en) * | 2002-07-03 | 2005-02-10 | Renesas Technology Corporation | Fabrication method and device structure of shallow trench insulation for silicon wafer containing silicon-germanium |
US7029988B2 (en) * | 2002-07-03 | 2006-04-18 | Renesas Technology Corporation | Fabrication method and device structure of shallow trench insulation for silicon wafer containing silicon-germanium |
US20040256634A1 (en) * | 2003-06-13 | 2004-12-23 | Renesas Technology Corp. | Semiconductor device |
US7170109B2 (en) * | 2003-06-13 | 2007-01-30 | Renesas Technology Corp. | Heterojunction semiconductor device with element isolation structure |
US20050023576A1 (en) * | 2003-07-31 | 2005-02-03 | Wen-Chin Lee | Semiconductor structure having a strained region and a method of fabricating same |
US7045836B2 (en) * | 2003-07-31 | 2006-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure having a strained region and a method of fabricating same |
US20060208336A1 (en) * | 2003-09-08 | 2006-09-21 | Wen-Chin Lee | Semiconductor structure having a strained region and a method of fabricating same |
US7495267B2 (en) * | 2003-09-08 | 2009-02-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure having a strained region and a method of fabricating same |
US7371658B2 (en) * | 2004-06-17 | 2008-05-13 | Texas Instruments Incorporated | Trench isolation structure and a method of manufacture therefor |
US20050282353A1 (en) * | 2004-06-17 | 2005-12-22 | Texas Instruments, Incorporated | Trench isolation structure and a method of manufacture therefor |
WO2006049848A3 (en) * | 2004-11-01 | 2006-06-29 | Advanced Micro Devices Inc | Method of forming isolation trench with spacer formation |
US7144785B2 (en) | 2004-11-01 | 2006-12-05 | Advanced Micro Devices, Inc. | Method of forming isolation trench with spacer formation |
WO2006049848A2 (en) * | 2004-11-01 | 2006-05-11 | Advanced Micro Devices, Inc. | Method of forming isolation trench with spacer formation |
US7439165B2 (en) | 2005-04-06 | 2008-10-21 | Agency For Sceince, Technology And Reasearch | Method of fabricating tensile strained layers and compressive strain layers for a CMOS device |
US8168548B2 (en) * | 2006-09-29 | 2012-05-01 | Tokyo Electron Limited | UV-assisted dielectric formation for devices with strained germanium-containing layers |
US20080078987A1 (en) * | 2006-09-29 | 2008-04-03 | Tokyo Electron Limited | UV-assisted dielectric formation for devices with strained germanium-containing layers |
KR101307658B1 (en) | 2006-09-29 | 2013-09-12 | 도쿄엘렉트론가부시키가이샤 | Uv-assisted dielectric formation for devices with strained germanium-containing layers |
US20140151759A1 (en) * | 2012-12-03 | 2014-06-05 | Stmicroelectronics, Inc. | Facet-free strained silicon transistor |
US10134899B2 (en) | 2012-12-03 | 2018-11-20 | Stmicroelectronics, Inc. | Facet-free strained silicon transistor |
US10134895B2 (en) * | 2012-12-03 | 2018-11-20 | Stmicroelectronics, Inc. | Facet-free strained silicon transistor |
US11282890B2 (en) * | 2020-01-21 | 2022-03-22 | Omnivision Technologies, Inc. | Shallow trench isolation (STI) structure for suppressing dark current and method of forming |
US11289530B2 (en) | 2020-01-21 | 2022-03-29 | Omnivision Technologies, Inc. | Shallow trench isolation (STI) structure for CMOS image sensor |
US20220115434A1 (en) * | 2020-01-21 | 2022-04-14 | Omnivision Technologies, Inc. | Method of forming shallow trench isolation (sti) structure for suppressing dark current |
US11705475B2 (en) * | 2020-01-21 | 2023-07-18 | Omnivision Technologies, Inc. | Method of forming shallow trench isolation (STI) structure for suppressing dark current |
Also Published As
Publication number | Publication date |
---|---|
US20050260825A1 (en) | 2005-11-24 |
WO2004077509A3 (en) | 2004-10-21 |
US7183175B2 (en) | 2007-02-27 |
WO2004077509A2 (en) | 2004-09-10 |
KR20050118162A (en) | 2005-12-15 |
TW200507169A (en) | 2005-02-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7183175B2 (en) | Shallow trench isolation structure for strained Si on SiGe | |
US8703565B2 (en) | Bottom-notched SiGe FinFET formation using condensation | |
US8378414B2 (en) | Low leakage FINFETs | |
US7326634B2 (en) | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication | |
KR101115091B1 (en) | Semiconductor structure with different lattice constant materials and method for forming the same | |
KR101418615B1 (en) | Silicon carbide and related wide-bandgap transistors on semi insulating epitaxy | |
US6787423B1 (en) | Strained-silicon semiconductor device | |
US7732336B2 (en) | Shallow trench isolation process and structure with minimized strained silicon consumption | |
US20030049893A1 (en) | Method for isolating semiconductor devices | |
US7601568B2 (en) | MOS transistor and method for producing a MOS transistor structure | |
US20120273889A1 (en) | Shallow trench isolation for soi structures combining sidewall spacer and bottom liner | |
US7553713B2 (en) | Method of manufacturing semiconductor substrates and semiconductor devices | |
US20040016986A1 (en) | Field isolation structures and methods of forming field isolation structures | |
JP2007335801A (en) | Semiconductor device and method for manufacturing the same | |
CN100505275C (en) | Bipolar transistor and back-gated transistor structure and method | |
US20040038495A1 (en) | Method of providing a thick thermal oxide in trench isolation | |
US7153747B2 (en) | Method for making a transistor on a SiGe/SOI substrate | |
US6664165B2 (en) | Semiconductor device and fabrication method therefor | |
US11605649B2 (en) | Switches in bulk substrate | |
US20230369328A1 (en) | Semiconductor structure and method for forming same | |
WO2007116238A1 (en) | METHOD OF MANUFACTURING A GaN MOSFET | |
JPH11177082A (en) | Mis field-effect transistor and manufacture thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KOESTER, STEVEN J.;BEYER, KLAUS D.;HARGROVE, MICHAEL J.;AND OTHERS;REEL/FRAME:013816/0930;SIGNING DATES FROM 20030218 TO 20030220 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001 Effective date: 20150629 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001 Effective date: 20150910 |