JP2011151144A - Semiconductor device, manufacturing method thereof, and p-channel mos transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which dispenses with a patterning process of a lanthanum oxide film, relating to the semiconductor device in which a high-K gate insulating film is constituted by laminating a high-K dielectric film and a lanthanum oxide film, in an n-channel MOS transistor. <P>SOLUTION: The manufacturing method of a semiconductor device includes a step in which an oxide film 24 is formed on a high-K dielectric film 23 which is formed on an interface oxide film 22, a step for forming a nitride layer 25 at the high-K dielectric film, and a step in which the nitride layer and the oxide film are selectively removed from a first element region 21A to form a lanthanum oxide film 26 over first and second element regions 21B, a first lamination structure with the interface oxide film, high-K dielectric film, and lanthanum oxide film laminated thereon is formed in the first element region, and a second lamination structure with the interface oxide film, high-K dielectric film, oxide film, nitride layer, and lanthanum oxide film laminated thereon is formed in the second element region. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention generally relates to semiconductor devices, and more particularly, to a high-speed semiconductor device using a high-K dielectric film as a gate insulating film and a method for manufacturing the same.

  Conventionally, in a MOS transistor (metal oxide silicon field effect transistor) formed on a silicon substrate, a polysilicon gate electrode is formed on the silicon substrate via a gate insulating film made of a silicon thermal oxide film. A source region and a drain region are formed so as to be opposed to each other with a channel region formed with a predetermined gate length directly under the polysilicon gate electrode.

  In recent ultrahigh-speed MOS transistors, the operation speed is improved by shortening the gate length, and accordingly, the thickness of the gate insulating film is also reduced according to the scaling law. For example, in a MOS transistor having a gate length of 0.45 nm, when a silicon thermal oxide film is used as a gate insulating film, it is desirable to reduce the thickness of the gate insulating film to 1 nm or less. However, when the physical film thickness of the gate insulating film is reduced in this way, generation of a gate leakage current due to a tunnel current passing through the gate insulating film becomes a serious problem.

  In order to alleviate this problem, nitrogen atoms are introduced into the silicon thermal oxide film to increase the relative dielectric constant of the gate insulating film, while maintaining the physical film thickness to the extent that tunnel current does not flow. Attempts have also been made to reduce the EOT, which is called “electrical film thickness” or “converted film thickness”, and to reduce the gate length. However, while the relative dielectric constant of the silicon oxide film is 3.9 to 4.0, the relative dielectric constant of the SiN film is only about 7 to 8, and the gate length can be further increased by using the SiON film having this intermediate composition. There is a clear limit to addressing this shortening.

On the other hand, a metal oxide insulating film such as HfO ₂ or ZrO ₂ has a very large relative dielectric constant of 20 to 30, and is generally called a high-K dielectric film. Therefore, by using such a high-K dielectric film as a gate insulating film, the gate leakage current due to the tunnel effect can be effectively obtained even in a MOS transistor having a shorter gate length, for example, a gate length of 32 nm, 16 nm, or 8 nm. Is expected to be suppressed.

  However, in a MOS transistor having a structure in which a polysilicon gate electrode is formed on a gate insulating film made of such a high-K dielectric film, the threshold value is fixed at a deep level whether it is a p-channel MOS transistor or an n-channel MOS transistor. The so-called Fermi level pinning problem, and the SO (Surface Optical) phonon oscillation induced in the high-K dielectric film where polarization easily occurs, constitutes an inversion channel in the channel region of the transistor. A problem known as phonon scattering, which causes a scattering by combining with, causing a decrease in carrier mobility.

  On the other hand, in a so-called metal gate technology in which a person skilled in the art generally uses a metal called “metal” or a conductive metal nitride for a gate electrode, the gate electrode does not have a problem of depletion, and high-K By combining a metal gate electrode made of the metal with a so-called high-K gate insulating film made of a dielectric film, it is expected that a MOS transistor characterized by a large drain current and operating at high speed can be obtained. .

2008-205012

Kita, K., et al. Technical report of IEICE. SDM 108 (407) pp.5-8, 20090119

  However, even in the metal gate technology, when a high-K dielectric film is directly formed on a silicon substrate as a gate insulating film, it is caused by lattice vibration in a high-K dielectric film such as surface roughness scattering or hafnium oxide (HfOx). Since phonon scattering occurs and the mobility of carriers transported in the channel decreases, the silicon oxide film is usually formed between the silicon substrate and the high-K dielectric film by thermal oxidation or radical oxidation. It has been proposed to form an interfacial oxide film.

  However, in a MOS transistor having a gate insulating film having a structure in which such a silicon oxide film and a high-K dielectric film are laminated, oxygen atoms between the silicon oxide film and the high-K dielectric film are not affected. Substantial charges are generated in the form of electric dipoles due to the number density difference (Non-Patent Document 1), and in particular, in the case of an n-channel MOS transistor, there arises a problem that the threshold value becomes deep. As a result, even if a high-K dielectric film is used, the desired transistor operation speed cannot be improved.

Therefore, for an n-channel MOS transistor, a lanthanum oxide (La ₂ O ₃ ) film is formed on a high-K dielectric film made of a hafnium oxide film, and is formed at the interface between the hafnium oxide film and the silicon oxide film therebelow. In addition to canceling out the effect of electric dipoles generated in an undesired direction, a technique for freely controlling the threshold value of an n-channel MOS transistor by controlling the amount of La diffused into the hafnium oxide film has been proposed. Yes.

As for the p-channel MOS transistor, it is desirable to further increase the effect of the electric dipole generated at the interface between the hafnium oxide film and the silicon oxide film. Therefore, an aluminum oxide (Al ₂ O ₃ ) film is formed on the hafnium oxide film. A technique has been proposed in which the threshold value of the p-channel MOS transistor is freely controlled by forming and controlling the amount of Al diffusion into the hafnium oxide film.

  1A to 1F are diagrams illustrating a process according to the related art of the present invention.

  Referring to FIG. 1A, an element region 11A for an n-channel MOS transistor and an element region 11B for a p-channel MOS transistor are formed in a silicon substrate 11, and the silicon substrate is formed in any element region. A high-K dielectric film 13 made of, for example, hafnium oxide is formed on the substrate 11 via an interface oxide film 12 made of a silicon thermal oxide film or a radical oxide film.

  Next, as shown in FIG. 1B, an aluminum oxide film 14A is formed on both the element region 11A and the element region 11B in the structure of FIG. 1A, and then the aluminum oxide film 14A is formed on the element region 11B as shown in FIG. 1C. It is selectively removed from the element region 11A by wet or dry etching.

Further, as shown in FIG. 1D, a lanthanum oxide (La ₂ O ₃ ) film 14B is formed on both the element region 11A and the element region 11B in the structure of FIG. 1C, and then, as shown in FIG. The lanthanum film 14B is selectively removed from the element region 11B by wet etching.

Further, as shown in FIG. 1F, the structure of FIG. 1E is heat-treated, and in the element region 11A, oxygen atoms are diffused from the hafnium oxide film 13 to the lanthanum oxide film 14B and the interface oxide film 12 as indicated by arrows. In 11B, oxygen atoms are diffused from the aluminum oxide film 14A to the hafnium oxide film 13 and from the hafnium oxide film 13 to the interface oxide film 12 as indicated by arrows. Such movement of oxygen atoms occurs from the higher number density of oxygen atoms to the lower one (Non-patent Document 1), where positive charges are present in the portions where oxygen vacancies are generated, Negative charges are generated in pairs and an electric dipole is formed. In the system shown in FIGS. 1A to 1F, the number density of oxygen atoms increases in the order of lanthanum oxide film, hafnium oxide constituting the interface oxide film, silicon oxide film, and aluminum oxide film (La ₂ O ₃ <HfO ₂ < SiO ₂ <Al ₂ O ₃ ). The high-K dielectric film 13 and the lanthanum oxide film 14B formed in this way, and the high-K dielectric film 13 and the aluminum oxide film 14A are respectively the gate insulating film 15A and the p-channel MOS of the n-channel MOS transistor. A gate insulating film 15B of the transistor is formed.

  As shown in FIG. 1E, the direction of the electric dipole formed at the interface between the high-K dielectric film 13 and the lanthanum oxide film 14B is at the interface between the high-K dielectric film 13 and the silicon oxide film 12. The lanthanum oxide film 14B is generated at the interface between the high-K dielectric film 13 and the interface oxide film 12 in the channel region in the element region 11A of the n-channel MOS transistor. This not only cancels the adjustment effect of the threshold voltage by the electric dipole, but also acts to produce the effect of the electric dipole in the opposite direction.

  At that time, in the element region 11A of the n-channel MOS transistor, La atoms in the lanthanum oxide film 14B diffuse to the interface between the hafnium oxide film 13 and the interfacial oxide film 12, and the interfacial oxide film 12 passes from the hafnium oxide film 13. By bonding with oxygen atoms diffused into lanthanum oxide, lanthanum oxide having a low number density of oxygen atoms is formed. As a result, excess oxygen atoms at the interface between the hafnium oxide film and the interfacial oxide film 12 are fixed in the form of lanthanum oxide, and the occurrence of undesired electric dipoles at the interface is reduced.

  On the other hand, in the element region 11B, the direction of the electric dipole formed at the interface between the high-K dielectric film 13 and the aluminum oxide film 14A is the interface between the high-K dielectric film 13 and the silicon oxide film 12. The aluminum oxide film 14A is formed at the interface between the high-K dielectric film 13 and the interface oxide film 12 in the channel region in the element region 11B of the p-channel MOS transistor. This acts to enhance the threshold voltage adjustment effect of the p-channel MOS transistor by the electric dipole.

  In the element region 11B, Al in the aluminum oxide film 14A diffuses to the interface between the hafnium oxide film 13 and the interface oxide film 12, thereby forming aluminum oxide having a high number density of oxygen atoms. Thus, the aluminum oxide formed at the interface between the hafnium oxide film 13 and the interface oxide film 12 releases oxygen to the interface oxide film 12, and the interface region oxide with the high-K dielectric film 13 in the element region 11B. The electric dipole generated at the interface of the film 12 acts to enhance the threshold voltage adjustment effect.

  However, in the process of FIGS. 1A to 1F, the lanthanum oxide film 14B is selectively etched in the process of FIG. 1E. However, since the lanthanum oxide film 14B has water absorption, for example, an etching residue is generated in the subsequent patterning process. Various problems occur, such as the aggregation of the lanthanum oxide film 14B where the La concentration is high and the La concentration is high, while the La portion is low and the La distribution is locally non-uniform. . In the lanthanum oxide film 14B in which aggregation occurs, the film thickness may vary by several microns. In the selective etching process, a cleaning process is generally indispensable for both dry etching and wet etching, and contact with water cannot be avoided.

  If the selective etching step of FIG. 1E is omitted, the lanthanum oxide film 14B remains on the aluminum oxide film 14A in the state of FIG. 1F. As a result, La atoms and Al atoms together with the high-K dielectric film are left. 13 diffuses toward the interface between the interfacial oxide film 12 and acts to reduce the threshold voltage adjustment effect of the p-channel MOS transistor due to the dipole at the interface.

  According to one aspect, a semiconductor device includes: a silicon substrate in which a first element region for an n-channel MOS transistor and a second element region for a p-channel MOS transistor are defined by an element isolation region; A first metal gate electrode formed on the silicon substrate via a first gate insulating film in one element region; and a second gate insulating film on the silicon substrate in the second element region. In the first element region, the n-type first electrode is opposed to the silicon substrate in the first element region with a first channel region directly below the first metal gate electrode interposed therebetween. The source and drain regions of the semiconductor device are opposed to each other in the second element region in the silicon substrate with a second channel region directly under the second metal gate electrode interposed therebetween. A second source and drain region of the mold, wherein the first gate insulating film is formed on the surface of the silicon substrate, and the first insulating film is formed on the first insulating film. A second insulating film having a dielectric constant higher than that of the first insulating film; and a first lanthanum oxide film formed on the second insulating film, wherein the second gate insulating film includes the silicon A third insulating film formed on the surface of the substrate; a fourth insulating film having a higher dielectric constant than the third insulating film formed on the third insulating film; and the fourth insulating film. And an oxide film made of aluminum oxide or titanium dioxide formed on the oxide film and a second lanthanum oxide film formed on the oxide film, and the gap between the oxide film and the second lanthanum oxide film. A layer containing nitrogen is interposed.

  According to another aspect, a method of manufacturing a semiconductor device includes a first method of covering a first element region and a second element region on a silicon substrate having first and second element regions defined by an element isolation region. A step of forming an insulating film, and a second dielectric constant higher than that of the first insulating film over the first and second element regions and covering the first insulating film on the silicon substrate. A step of forming an insulating film, a step of forming an oxide film made of aluminum oxide or titanium dioxide on the silicon substrate over the first and second element regions and covering the second insulating film; Nitriding the surface of the second insulating film over the first and second element regions to form a nitride layer; selectively forming the nitride layer and the oxide film from the first element region; To remove the first element region And exposing the second insulating film, over the first and second element regions on the silicon substrate, covering the second insulating film in the first element region, and In the second element region, a lanthanum oxide film is formed to cover the nitride layer, and in the first element region, the first insulating film, the second insulating film, and the lanthanum oxide film are stacked. In the second element region, the first insulating film, the second insulating film, the oxide film, the nitride layer, and the lanthanum oxide film are stacked in the second element region. Forming a stacked structure; forming a metal or conductive metal nitride layer as a metal gate electrode layer on the silicon substrate, covering the lanthanum oxide film over the first and second element regions; ,including.

  According to another aspect, a p-channel MOS transistor includes a silicon substrate, a metal gate electrode formed on the silicon substrate via a gate insulating film, and a channel region immediately below the metal gate electrode in the silicon substrate. And p-type source and drain regions facing each other, wherein the gate insulating film is formed on the silicon substrate surface and the first insulating film is formed on the first insulating film. A second insulating film having a dielectric constant higher than that of the first insulating film; an oxide film made of aluminum oxide or titanium dioxide formed on the second insulating film; and an oxide formed on the oxide film A layer containing nitrogen is interposed between the oxide film and the lanthanum oxide film.

  According to the first and second aspects, when manufacturing a semiconductor device, a nitride layer is interposed between the oxide film made of aluminum oxide or titanium dioxide and the lanthanum oxide film in the second element region. Therefore, when forming the lanthanum oxide film, La is prevented from diffusing into the oxide film in the second gate insulating film or the second stacked structure, and in the first element region, Induces a dipole of a desired polarity at the interface between the silicon substrate and the first gate insulating film or first laminated structure, while the silicon substrate and the second gate insulation are in the second element region. In the metal gate MOS transistor using a high-K dielectric film, a dipole having a desired reverse polarity can be induced at the interface with the film or the second laminated structure. , It is possible to align in both the threshold characteristic of the p-channel MOS transistors and n-channel MOS.

It is sectional drawing (the 1) explaining the manufacturing process of the conventional semiconductor device. It is sectional drawing (the 2) explaining the manufacturing process of the conventional semiconductor device. It is sectional drawing (the 3) explaining the manufacturing process of the conventional semiconductor device. It is sectional drawing (the 4) explaining the manufacturing process of the conventional semiconductor device. It is sectional drawing (the 5) explaining the manufacturing process of the conventional semiconductor device. It is sectional drawing (the 6) explaining the manufacturing process of the conventional semiconductor device. It is sectional drawing which shows the structure of the semiconductor device by one Embodiment. FIG. 3 is a sectional view (No. 1) for explaining a manufacturing step of the semiconductor device of FIG. 2; FIG. 3 is a sectional view (No. 2) for explaining a manufacturing step of the semiconductor device of FIG. 2; FIG. 3 is a sectional view (No. 3) for explaining the manufacturing process of the semiconductor device of FIG. 2; FIG. 4 is a sectional view (No. 4) for explaining the manufacturing step of the semiconductor device of FIG. 2; FIG. 6 is a sectional view (No. 5) for explaining the manufacturing step of the semiconductor device of FIG. 2; FIG. 6 is a sectional view (No. 6) for explaining the manufacturing step of the semiconductor device of FIG. 2; FIG. 7 is a sectional view (No. 7) for explaining a manufacturing step of the semiconductor device of FIG. 2; FIG. 8 is a cross-sectional view (No. 8) for explaining the manufacturing step of the semiconductor device of FIG. 2; FIG. 9 is a sectional view (No. 9) for explaining the manufacturing step of the semiconductor device of FIG. 2; FIG. 10 is a sectional view (No. 10) for explaining the manufacturing process of the semiconductor device of FIG. 2; FIG. 11 is a cross-sectional view (No. 11) illustrating the manufacturing process of the semiconductor device of FIG. 2; FIG. 13 is a cross-sectional view (No. 12) for explaining the manufacturing process of the semiconductor device of FIG. 2;

  FIG. 2 is a cross-sectional view showing a configuration of a semiconductor device according to a preferred embodiment.

  Referring to FIG. 2, an element region 21A for an n-channel MOS transistor and an element region 21B for a p-channel MOS transistor are defined on a p-type silicon substrate 21 by an STI-type element isolation region 21I. A p-type well 21PW is formed in the element region 21A.

In the element region 21A, an interface oxide film 22a made of a thermal oxide film having a thickness of 1 nm or less, for example, 0.7 nm is formed on the silicon substrate 21, and the film thickness is formed on the interface oxide film 22a. Is a hafnium oxide (HfO ₂ ) film 23 a having a thickness of 1.0 nm to 2.0 nm, preferably 1.5 nm, and a lanthanum oxide (La ₂ O ₃ ) having a thickness of 0.3 nm to 0.8 nm, preferably 0.5 nm. The film 26a is sequentially stacked to form the first gate insulating film 22A.

In still the device region 21A, on the first gate insulating film 22A, sequentially laminated metal gate electrode 23A of the polysilicon film 28a doped with metal film 27a and the n-type composed of TiN is in the gate length L _A Is formed.

On the other hand, in the element region 21B, an interfacial oxide film 22b made of a thermal oxide film having a thickness of 1 nm or less, for example, 0.7 nm is formed on the silicon substrate 21 in the same manner as the interfacial oxide film 22a. A hafnium oxide (HfO ₂ ) film 23b having a thickness of 1.0 nm to 2.0 nm, preferably 1.5 nm, and a thickness of 0.3 nm to 0.8 nm, preferably 0.5 nm are formed on the interface oxide film 22b. The aluminum oxide (Al ₂ O ₃ ) film 24b and the lanthanum oxide film 26b having a film thickness of 0.3 nm to 0.8 nm, preferably 0.5 nm are sequentially stacked to form the second gate insulating film 22B. Yes. At this time, in this embodiment, the film thickness is 0.2 nm or more and less than 0.5 nm between the aluminum oxide film 24b and the lanthanum oxide film 26b, that is, the film thickness is larger than the film thickness of the aluminum oxide film 24b. A small aluminum nitride (AlN) layer 25b is interposed, and the aluminum nitride layer 25b serves as a barrier film that prevents diffusion of lanthanum (La) from the lanthanum oxide film 26b to the aluminum oxide film 24b and further to the hafnium oxide film 23b. Function. As will be described later, the aluminum nitride layer 25b is formed by nitriding the surface portion of the aluminum oxide film 24b. Accordingly, the film thickness of the aluminum oxide film 24b is actually the same as that described above. From this value, the thickness is reduced by the thickness of the aluminum nitride layer 25b.

Further, in the element region 21B, a metal gate electrode 23B in which a metal film 27b made of TiN and a p-type doped polysilicon film 28b are sequentially stacked on the second gate insulating film 22B has a gate length L _B It is formed with.

  Here, the metal films 27a and 27b are not limited to TiN, and refractory metals such as TaN, TaSiN, W, and WN or conductive nitrides thereof can be used.

  In the silicon substrate 21, n-type source extension regions 21a and drain extension regions are provided on both sides of the channel region 23CA immediately below the metal gate electrode 23A in the element region 21A so as to face each other across the channel region 23CA. In addition, a p-type source extension region 21c and a drain extension region 21d are formed on both sides of the channel region 23CB immediately below the metal gate electrode 23B in the element region 21B so as to face each other across the channel region 23CB. Has been.

Further, sidewall insulating films 23A ₁ and 21A ₂ are formed on the opposite sidewall surfaces of the gate electrode 23A, and the sidewall insulation is seen in the silicon substrate 21 when viewed from the channel region 21CA in the element region 21A. An n + -type source region 21e and a drain region 21f are formed outside the films 23A ₁ and 23A ₂ , respectively.

Similarly, sidewall insulating films 23B ₁ and 21B ₂ are formed on the opposite sidewall surfaces of the gate electrode 23B, and the sidewalls of the element region 21B as viewed from the channel region 21CB are formed in the silicon substrate 21. A p + -type source region 21g and a drain region 21h are formed outside the insulating films 23B ₁ and 23B ₂ , respectively.

  As a result, the element region 21A has an n-channel MOS transistor having a metal gate electrode 23A and a gate insulating film 22A, and the element region 21B has a p-channel MOS transistor having a metal gate electrode 23B and a gate insulating film 22B. It is formed.

In the case where the gate insulating film 22A is formed by stacking the interface oxide film 22a having a thickness of 0.7 nm, the hafnium oxide film 23a having a thickness of 1.5 nm, and the lanthanum oxide film 26a having a thickness of 0.5 nm. The equivalent film thickness EOT of the gate insulating film 22A is about 1.07 nm. Further, the gate insulating film 22B is formed in such a manner that the interface oxide film 22b having a film thickness of 0.7 nm, the hafnium oxide film 23b having a film thickness of 1.5 nm, the aluminum oxide film 25b having a film thickness of 0.5 nm, and the film thickness being 0. In the case where the gate insulating film 22B is composed of a stack of .2 nm aluminum nitride film 25b and 0.5 nm thick lanthanum oxide film 26b, the EOT of the gate insulating film 22B is 1.287 nm. However, in this calculation, the relative dielectric constant of the interface oxide films 22a and 22b is 3.9, the relative dielectric constant of HfO ₂ constituting the high-K dielectric films 23a and 23b is 20, and the relative dielectric constant of the lanthanum oxide films 26a and 26b. The dielectric constant is 25, the relative dielectric constant of the aluminum oxide film 24b is 16, and the relative dielectric constant of the aluminum nitride film 25b is 9.

  As described above, in this embodiment, the converted film thickness EOT of the gate insulating films 22A and 22B is 1.0 to 1.1 nm, and the physical film thicknesses are 2.7 nm for the n channel and 3.2 nm for the p channel, respectively. Therefore, an increase in gate leakage current can be suppressed. The same applies when the gate length is shorter than 45 nm.

  A method for manufacturing the semiconductor device of FIG. 2 will be described below.

  Referring to FIG. 3A, element regions 21A and 21B are defined by an element isolation region 21I on the silicon substrate 21, and a p-type well 21PW is formed in the element region 21A. In the step of FIG. 3A, the silicon oxide film 22 to be the interface oxide films 22a and 22b is further formed on the silicon substrate 21A for 7 seconds to 8 in a dry oxygen atmosphere at 900 ° C. and an oxygen partial pressure of 1320 Pa (10 Torr), for example. By performing the thermal oxidation treatment step for 2 seconds, the film is formed to a thickness of 1 nm or less, for example, 0.7 nm.

Next, in the step shown in FIG. 3B, the HfO ₂ film 23 to be the high-K dielectric films 23a and 23b is formed on the silicon oxide film 22 by, for example, 1.5 nm by ALD (atomic layer deposition) method or MOCVD method. It is formed in a film thickness. The HfO ₂ film 23 is formed by the ALD method by using a CVD apparatus and purging with hafnium chloride (HfCl ₄ ) and water vapor (H ₂ O) between 300 ° C. and 350 ° C., for example, 320 ° C. It can be performed by repeatedly supplying alternately while sandwiching. At that time, zirconium chloride (ZrCl ₄ ) can be added to the hafnium chloride. In this case, a (Hf, Zr) O ₂ film is obtained as the high-K dielectric film 23. However, in this case, it is preferable to control so that the ratio of zirconium to the whole of hafnium (Hf) and zirconium (Zr) does not exceed 30%.

Next, in the step of FIG. 3C, an aluminum oxide film as the oxide film 24 on the HfO ₂ film 23, by an ALD method or the MOCVD method as in the case of the HfO ₂ film 23, for example, a film thickness of 0.5nm It is formed. When the aluminum oxide film 24 is formed by the ALD method, a CVD apparatus is used, and at a temperature of 200 ° C. to 300 ° C., for example, 250 ° C., Al (CH ₃ ) ₃ (trimethylammonium) and H ₂ O are interposed. It can be performed by repeatedly supplying them alternately with a purge step in between.

Next, in the step of FIG. 3D, the structure of FIG. 3C is introduced into a remote plasma nitriding apparatus, and plasma is excited at a power of 1500 to 2000 W in a helium (He) atmosphere at a temperature of 400 ° C. or lower, and nitrogen gas is supplied. For example, the surface portion of the aluminum oxide film 24 is nitrided by nitrogen radicals by flowing at a flow rate of 30 sccm to 100 sccm for 10 seconds to 20 seconds, and an aluminum nitride (AlN) layer having a thickness of 0.2 nm or more and less than 0.5 nm. 25 is formed. However, the nitridation process of the aluminum oxide film 24 is not limited to the remote plasma nitridation process, and any process may be used as long as nitrogen radicals can be efficiently generated at a low temperature. For example, the nitriding process can be performed using a downflow plasma processing apparatus. In this case, the downflow plasma processing apparatus is operated at room temperature, and flash lamp heating or laser scan heating is performed for about 1 millisecond. In this case, it is preferable to use light having a wavelength shorter than 1100 nm, which is shorter than the fundamental absorption edge wavelength of silicon. In any case, it is possible to nitride only the surface portion of the aluminum oxide film 24 while suppressing the diffusion of La from the lanthanum oxide film 26. As the nitriding gas, nitrogen monoxide (NO), nitrous oxide (N ₂ O), ammonia (NH ₃ ), or the like can be used in addition to nitrogen.

  3E, a hard mask film M1 made of, for example, an amorphous silicon film is formed on the aluminum nitride layer 25 by a sputtering method or a CVD method to a thickness of about 0.5 nm, and the element region 21B is formed as a resist pattern. In the state protected by R1, as shown in FIG. 3F, the hard mask film M1 is removed from the element region 21A by dry etching. Further, the remaining aluminum nitride layer 25 and aluminum oxide film 24 are also removed by dry etching to expose the hafnium oxide film 23 in the element region 21A.

  Further, in the step of FIG. 3F, after the hafnium oxide film 24 is exposed in the element region 21A, the resist pattern R1 is removed using a stripping solution in the element region 21B. At this time, the aluminum nitride film 25 is protected by the hard mask film M1 in the element region 21B and does not come into contact with the stripping solution.

  Further, the hard mask film M1 is selectively removed in the element region 21B by wet etching using TMAH (tetramethylammonium hydroxide) as an etchant, and the aluminum nitride layer 25 is exposed in the element region 21B. The aluminum nitride layer 25 is resistant to TMAH. Since hafnium oxide is resistant to TMAH, the hafnium oxide film 23 exposed in the element region 21A is not eroded or removed in this step.

Next, in the step of FIG. 3G, the exposed hafnium oxide film 23 is covered in the element region 21A and the exposed aluminum nitride film 25 is covered in the element region 21B on the structure of FIG. 3F. In addition, the lanthanum oxide film 26 is formed by the ALD method using La (thd) ₃ as a source gas, for example, in a CVD apparatus at a substrate temperature of 150 ° C. to 250 ° C., preferably 200 ° C., with the source gas La (thd) By repeatedly supplying the gas ₃ and the gas alternately while interposing the purge process therebetween, the film is formed to a thickness of 0.5 nm, for example.

  Thereafter, the structure of FIG. 3G thus obtained is introduced into the sputtering apparatus, and in the step of FIG. 3H, the TiN film 27 corresponding to the gate electrodes 23A and 23B has a thickness of, for example, 7.5 nm to 12.5 nm. Preferably, a polysilicon film 28 is formed to a thickness of 10 nm, and a polysilicon silicon film 28 is formed thereon, for example, to a thickness of 30 nm to 70 nm, preferably 50 nm.

  The TiN film 27 and the polysilicon film 28 thus formed, and the silicon oxide film 22, the hafnium oxide film 23, the aluminum oxide film 24, the aluminum nitride film 25, and the lanthanum oxide film 26 thereunder are formed as shown in FIG. 3I. In the element region 21A, a gate insulating film 22A composed of a stack of the interfacial oxide film 22a, hafnium oxide film 23a, and lanthanum oxide film 26a is a metal gate electrode formed of a stack of TiN film 27a and polysilicon film 28a. In addition, in the element region 21B, a gate insulating film 22B made of a laminate of the interfacial oxide film 22b, the hafnium oxide film 23b, the aluminum oxide film 24b, the aluminum nitride layer 25, and the lanthanum oxide film 26b is formed in the element region 21B. Lamination of 27b and polysilicon film 28b It is formed under the Li Cheng metal gate electrode 23B.

  Further, in the step of FIG. 3J, an n-type impurity element such as phosphorus (P) or arsenic (As) is ion-implanted into the silicon substrate 21 in the element region 21A using the metal gate electrode 23A as a mask to form an n-type source. Extension regions 21a and drain extension regions 21b are formed. In the step of FIG. 3J, a p-type impurity element such as boron (B) is ion-implanted into the silicon substrate 21 in the element region 21B using the metal gate electrode 23B as a mask, and a p-type source extension region 21c and A drain extension region 21d is formed.

Furthermore the sidewall insulating films 24A _1, 24A ₂ to the metal gate electrode 23A in the step of FIG. 3K, also forming a sidewall insulating film 24B _1, 24B ₂ on the metal gate electrode 23B, arsenic or phosphorus in the device region 21A N-type impurity elements such as boron with the metal gate electrode 23A and sidewall insulating films 24A ₁ and 24A ₂ as masks, and p-type impurity elements such as boron in the element region 21B with the metal gate electrode 23B and sidewall insulation. Using the films 24B ₁ and 24B ₂ as masks, as described above with reference to FIG. 2, in the element region 21A in the silicon substrate 21, the side wall insulating film as viewed from the channel region 21CA. outside of 23A ₁ and 23A _2, the n + -type source region 21e and the drain region 21f Also in the device region 21B, the outer sides of the sidewall insulation films 23B ₁ and 23B ₂ when viewed from the channel region 21Cb, to form p + -type source region 21g and the drain region 21h, respectively.

  In the step of FIG. 3K, the polysilicon film 28a constituting the metal gate electrode 23A becomes n + type as the n + type source and drain regions 21e and 21f are doped, and the polysilicon film 28b constituting the metal gate electrode 23B. Is doped p + type with doping of the p + type source and drain regions 21g and 21h. However, in this embodiment, the adjustment of the threshold voltage in the n-channel MOS transistor and the p-channel MOS transistor has already been completed by the laminated structure of the gate insulating films 22A and 22B. It is not necessary to dope the polysilicon film constituting part of the gate to n-type and the polysilicon film constituting part of the metal gate of the p-channel MOS transistor to p-type, and these polysilicon films are identical. The conductivity type may be doped.

  3L, an interlayer insulating film 29 is formed on the silicon substrate 21. In the interlayer insulating film 29, the source region 21e and the drain region 21f of the n-channel MOS transistor and the source of the p-channel MOS transistor are formed. Via plugs 29A to 29D are formed corresponding to the region 21g and the drain region 21h, respectively. In FIG. 3L, each of the via plugs 29A to 29D includes a metal plug 29a such as tungsten (W) and a Ti or TiN barrier film 29b covering the metal plug 29a.

In this embodiment, the aluminum oxide film 24 can be replaced with a titanium oxide (TiO ₂ ) film. In this case, a titanium nitride (TiN) layer is formed in place of the aluminum nitride layer 25. For example, when the titanium nitride film is formed with a thickness of 0.3 nm and the titanium nitride layer is formed with a thickness of 0.2 nm, the relative dielectric constant of titanium oxide is 50 and the relative dielectric constant of titanium nitride is 30. The gate insulating film 22B has an EOT of 1.0224.

As mentioned above, although this invention was described about preferable embodiment, this invention is not limited to this specific embodiment, A various deformation | transformation and change are possible within the summary described in the claim.
(Appendix 1)
A silicon substrate in which a first element region for an n-channel MOS transistor and a second element region for a p-channel MOS transistor are defined by an element isolation region;
A first metal gate electrode formed on the silicon substrate via a first gate insulating film in the first element region;
A second metal gate electrode formed on the silicon substrate via a second gate insulating film in the second element region;
N-type first source and drain regions opposed to each other across the first channel region directly below the first metal gate electrode in the silicon substrate in the first element region;
P-type second source and drain regions opposed to each other across the second channel region directly below the second metal gate electrode in the silicon substrate in the second element region;
Including
The first gate insulating film includes a first insulating film formed on the surface of the silicon substrate and a second dielectric constant higher than that of the first insulating film formed on the first insulating film. And a first lanthanum oxide film formed on the second insulating film,
The second gate insulating film includes a third insulating film formed on the surface of the silicon substrate and a fourth dielectric constant higher than that of the third insulating film formed on the third insulating film. An insulating film, an oxide film made of aluminum oxide or titanium dioxide formed on the fourth insulating film, and a second lanthanum oxide film formed on the oxide film,
A semiconductor device, wherein a layer containing nitrogen is interposed between the oxide film and the second lanthanum oxide film.
(Appendix 2)
2. The semiconductor device according to claim 1, wherein the layer containing nitrogen is an aluminum nitride layer or a titanium nitride layer having a thickness of 0.2 nm or more and less than 0.5 nm formed on the oxide film surface.
(Appendix 3)
The semiconductor device according to appendix 1 or 2, wherein the first insulating film and the third insulating film are silicon oxide films having a thickness of 1 nm or less.
(Appendix 4)
4. The semiconductor device according to claim 1, wherein the second insulating film and the fourth insulating film are made of hafnium oxide or hafnium zirconium oxide.
(Appendix 5)
5. The semiconductor device according to claim 1, wherein the first and second metal gate electrodes are made of a titanium nitride film and a polysilicon film formed on the titanium nitride film. 6. .
(Appendix 6)
Forming a first insulating film on the silicon substrate in which the first and second element regions are defined by the element isolation region, covering the first and second element regions;
Forming a second insulating film having a dielectric constant higher than that of the first insulating film on the silicon substrate so as to cover the first insulating film over the first and second element regions;
Forming an oxide film made of aluminum oxide or titanium dioxide on the silicon substrate so as to cover the second insulating film over the first and second element regions;
Nitriding the surface of the second insulating film over the first and second element regions to form a nitride layer;
Selectively removing the nitride layer and the oxide film from the first element region and exposing the second insulating film in the first element region;
Over the silicon substrate, over the first and second element regions, the first element region covers the second insulating film, and the second element region covers the nitride layer. Then, a lanthanum oxide film is formed, and in the first element region, a first stacked structure in which the first insulating film, the second insulating film, and the lanthanum oxide film are stacked, and the second Forming a second stacked structure in which the first insulating film, the second insulating film, the oxide film, the nitride layer, and the lanthanum oxide film are stacked in the element region;
Forming a metal or conductive metal nitride layer as a metal gate electrode layer on the silicon substrate so as to cover the lanthanum oxide film over the first and second element regions;
A method for manufacturing a semiconductor device, comprising:
(Appendix 7)
The method of manufacturing a semiconductor device according to appendix 6, wherein the nitride layer forming step is performed such that substantial diffusion of La from the lanthanum oxide film to the oxide layer does not occur.
(Appendix 8)
The method of manufacturing a semiconductor device according to appendix 6 or 7, wherein the nitride layer forming step is performed such that the thickness of the nitride layer is not less than 0.2 nm and less than 0.5 nm.
(Appendix 9)
The semiconductor device according to any one of appendices 6 to 8, wherein the nitride layer forming step is performed using a remote plasma processing apparatus at a temperature of 400 ° C. or lower for 10 seconds to 20 seconds. Manufacturing method.
(Appendix 10)
The semiconductor device according to any one of appendices 6 to 8, wherein the nitride layer forming step is performed by performing a heat treatment for 1 millisecond or less in a downflow plasma processing apparatus. Manufacturing method.
(Appendix 11)
The step of selectively removing the nitride layer and the oxide film from the first element region is performed by forming an amorphous silicon film as a hard mask film on the nitride layer in the second element region. And the step of selectively removing the nitride layer and the oxide film from the first element region is selective to the amorphous silicon film with respect to the nitride layer in the second element region. The manufacturing method of the semiconductor device as described in any one of the additional remarks 6-10 characterized by including the process to remove.
(Appendix 12)
The method of manufacturing a semiconductor device according to claim 11, wherein the step of selectively removing the amorphous silicon film from the nitride layer is performed using tetramethylammonium hydroxide as an etchant.
(Appendix 13)
A silicon substrate;
A metal gate electrode formed on the silicon substrate via a gate insulating film;
P-type source and drain regions opposed to each other across the channel region directly below the metal gate electrode in the silicon substrate;
Including
The gate insulating film includes a first insulating film formed on the surface of the silicon substrate and a second insulating film having a dielectric constant higher than that of the first insulating film formed on the first insulating film. And an oxide film made of aluminum oxide or titanium dioxide formed on the second insulating film, and a lanthanum oxide film formed on the oxide film,
A p-channel MOS transistor, wherein a layer containing nitrogen is interposed between the oxide film and the lanthanum oxide film.

11, 21 Silicon substrate 12, 22, 22a, 22b Interfacial oxide film 13, 23, 23a, 23b high-K dielectric film 14A, 24, 24b Aluminum oxide film 14B, 26, 26a Lanthanum oxide film 21A, 21B Element region 21CA , 21Cb channel region 21I isolation region 21PW well 21a, 21b, 21c, 21d diffusion regions 22A, 22B a gate insulating film 23A, 23B the metal gate electrode _{24A 1, 24A 2, 24B 1} , 24B 2 sidewall insulating films 25,25b nitride Layer 27, 27a, 27b Metal film 28, 28a, 28b Polysilicon film 29 Interlayer insulating film 29A-29D Via plug 29a W plug 29b Barrier film M1 Hard mask film

Claims (7)

A silicon substrate in which a first element region for an n-channel MOS transistor and a second element region for a p-channel MOS transistor are defined by an element isolation region;
A first metal gate electrode formed on the silicon substrate via a first gate insulating film in the first element region;
A second metal gate electrode formed on the silicon substrate via a second gate insulating film in the second element region;
N-type first source and drain regions opposed to each other across the first channel region directly below the first metal gate electrode in the silicon substrate in the first element region;
P-type second source and drain regions opposed to each other across the second channel region directly below the second metal gate electrode in the silicon substrate in the second element region;
Including
The first gate insulating film includes a first insulating film formed on the surface of the silicon substrate and a second dielectric constant higher than that of the first insulating film formed on the first insulating film. And a first lanthanum oxide film formed on the second insulating film,
The second gate insulating film includes a third insulating film formed on the surface of the silicon substrate and a fourth dielectric constant higher than that of the third insulating film formed on the third insulating film. An insulating film, an oxide film made of aluminum oxide or titanium dioxide formed on the fourth insulating film, and a second lanthanum oxide film formed on the oxide film,
A semiconductor device, wherein a layer containing nitrogen is interposed between the oxide film and the second lanthanum oxide film.   2. The semiconductor device according to claim 1, wherein the layer containing nitrogen is an aluminum nitride film or a titanium nitride film having a thickness of 0.2 nm or more and less than 0.5 nm formed on the surface of the oxide film. Forming a first insulating film on the silicon substrate in which the first and second element regions are defined by the element isolation region, covering the first and second element regions;
Forming a second insulating film having a dielectric constant higher than that of the first insulating film on the silicon substrate so as to cover the first insulating film over the first and second element regions;
Forming an oxide film made of aluminum oxide or titanium dioxide on the silicon substrate so as to cover the second insulating film over the first and second element regions;
Nitriding the surface of the second insulating film over the first and second element regions to form a nitride layer;
Selectively removing the nitride layer and the oxide film from the first element region and exposing the second insulating film in the first element region;
Over the silicon substrate, over the first and second element regions, the first element region covers the second insulating film, and the second element region covers the nitride layer. Then, a lanthanum oxide film is formed, and in the first element region, a first stacked structure in which the first insulating film, the second insulating film, and the lanthanum oxide film are stacked, and the second Forming a second stacked structure in which the first insulating film, the second insulating film, the oxide film, the nitride layer, and the lanthanum oxide film are stacked in the element region;
Forming a metal or conductive metal nitride layer as a metal gate electrode layer on the silicon substrate so as to cover the lanthanum oxide film over the first and second element regions;
A method for manufacturing a semiconductor device, comprising:   4. The method of manufacturing a semiconductor device according to claim 3, wherein the nitride layer forming step is executed so that substantial diffusion of La from the lanthanum oxide film to the oxide layer does not occur.   5. The method of manufacturing a semiconductor device according to claim 3, wherein the nitride layer forming step is performed such that the thickness of the nitride layer is not less than 0.2 nm and less than 0.5 nm. .   The step of selectively removing the nitride layer and the oxide film from the first element region is performed by forming an amorphous silicon film as a hard mask film on the nitride layer in the second element region. And the step of selectively removing the nitride layer and the oxide film from the first element region is selective to the amorphous silicon film with respect to the nitride layer in the second element region. 6. The method for manufacturing a semiconductor device according to claim 3, further comprising a step of removing the semiconductor device. A silicon substrate;
A metal gate electrode formed on the silicon substrate via a gate insulating film;
P-type source and drain regions opposed to each other across the channel region directly below the metal gate electrode in the silicon substrate;
Including
The gate insulating film includes a first insulating film formed on the surface of the silicon substrate and a second insulating film having a dielectric constant higher than that of the first insulating film formed on the first insulating film. And an oxide film made of aluminum oxide or titanium dioxide formed on the second insulating film, and a lanthanum oxide film formed on the oxide film,
A p-channel MOS transistor, wherein a layer containing nitrogen is interposed between the oxide film and the lanthanum oxide film.