JP2011103329A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has improved characteristics of both a p-type MIS transistor and an n-type MIS transistor without employing a dual metal gate process. <P>SOLUTION: The semiconductor device includes: a first interfacial silicon oxide film 105 formed in order on a p-type semiconductor region 10A, and a first gate insulating film 106A and a first gate electrode 119A including aluminum; a second interfacial silicon oxide film 105 formed in order on an n-type semiconductor region 10B; and a second gate insulating film 106B and a second gate electrode 119A including an element having effect of lowering an effective work function. Here, the concentration of aluminum of an upper part of the first gate insulating film 106A is 1×10<SP>20</SP>/cm<SP>3</SP>or more. The concentration of aluminum of an upper part of the first gate insulating film 106B is 1×10<SP>19</SP>/cm<SP>3</SP>or less. The difference in film thickness between the first interfacial silicon oxide film 105 and second interfacial silicon oxide film 105 is ≤0.2 nm. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device including a complementary transistor and a manufacturing method thereof.

  In order to reduce power consumption and improve performance in a 32 nm generation complementary metal insulating semiconductor (CMIS), it is required to further reduce the thickness of the gate insulating film. If the gate insulating film made of a conventional silicon oxide film-based material is further thinned, the increase in leakage current exceeds the allowable range. Therefore, the use of a high dielectric constant film (high-k film) having a higher relative dielectric constant than that of a conventional silicon oxide film-based material as a gate insulating film has been studied. A hafnium (Hf) -based insulating film has a thermal stability of 1000 ° C. or higher and a relative dielectric constant of 13 or higher, and thus is considered promising as a candidate for a high dielectric constant film. However, in the case of using a hafnium silicate (HfSiOx) film or a hafnium oxide (HfOx) film as the gate insulating film and using polysilicon as the gate electrode, an increase in equivalent oxide thickness (EOT) due to depletion and a Fermi level The increase in threshold voltage due to pinning cannot be ignored. This becomes a significant problem particularly in the p-type MIS transistor.

  For this reason, utilization of the metal gate electrode which used the metal instead of the polysilicon as a gate electrode is examined. When a metal gate is applied for bulk CMIS, a metal having an effective work function (eWF) near the conduction band of silicon (Si) is used for the n-type MIS transistor, and a valence band of Si is used for the p-type MIS transistor. A metal having a nearby eWF may be used. Specifically, it is preferable to use a metal having an eWF of 4.8 eV or more for the p-type MIS transistor and a metal having an eWF of 4.3 eV or less for the n-type MIS transistor.

From the relationship between the metal material and eWF, a metal material such as titanium (Ti), molybdenum (Mo) or tantalum (Ta) is promising in the case of an n-type MIS transistor, and platinum (Pt) in the case of a p-type MIS transistor. ), Metal materials such as ruthenium oxide (RuO ₂ ) or titanium nitride (TiN) are promising. Therefore, when forming a CMIS transistor, a dual metal gate process may be constructed using these materials. However, Pt, RuO _{2 and the} like that are promising as gate electrodes of p-type MIS transistors are very difficult to process. Materials such as Ti, Mo, and Ta, which are promising as gate electrodes for n-type MIS transistors, are not easily processed and have problems such as instability at high heat loads. For this reason, the construction of a dual metal gate process is not easy.

  Therefore, a method has been proposed in which a metal gate electrode made of titanium nitride (TiN) or the like is used for both the p-type MIS transistor and the n-type MIS transistor. For example, an eWF suitable for an n-type MIS transistor is realized by inserting a cap film made of a metal such as lanthanum (La), yttrium (Y), or magnesium (Mg) between a metal gate electrode and a gate insulating film. be able to. Further, an eWF suitable for a p-type MIS transistor can be realized by inserting a cap film made of aluminum oxide (AlOx) between a metal gate electrode and a gate insulating film (see, for example, Patent Document 1). ).

JP 2007-329237 A

  However, the present inventors have found that the following problems occur when an eWF suitable for a p-type MIS transistor is realized using an AlOx film as a cap film.

  First, it has been found that when an AlOx film is inserted between a gate electrode and a gate insulating film, EOT increases and the gate capacity decreases. When an AlOx film having a low relative dielectric constant is formed on a high dielectric constant film, the high dielectric constant film has a relatively low dielectric constant. Further, it has been clarified that the excess oxygen component in the AlOx film diffuses into the high dielectric constant film, so that a reoxidation increase of the interface layer occurs in the subsequent heat treatment, and the EOT increases.

  In order to suppress the increase in EOT, it is conceivable to reduce the physical film thickness of the high dielectric constant film by the amount of insertion of AlOx. However, if high dielectric constant films having different thicknesses are formed in the p-type MIS transistor formation region and the n-type MIS transistor formation region, the number of steps increases and the manufacturing cost increases.

Furthermore, the inventors of the present application have revealed that when an AlOx film is used as a cap film, the characteristics of the n-type MIS transistor may be deteriorated. When an AlOx film is used as a cap film of a p-type MIS transistor, it is usually necessary to selectively remove the AlOx film formed on the high dielectric constant film in the n-type MIS transistor formation region. As a method for selectively removing the AlOx film without damaging the high dielectric constant film, a hydrochloric acid-hydrogen peroxide type cleaning is known. However, if an AlOx film is formed on a high dielectric constant film, it cannot be sufficiently removed with hydrochloric acid or hydrochloric acid-hydrogen peroxide type chemicals.
The reason is considered to be that the AlOx film is chemically stable and has removal resistance against these agents. In addition, the chemical removability may be lowered due to the chemical stability improvement due to the reaction and combination of AlOx and the high dielectric constant film. The physical analysis reveals that AlOx on the high dielectric constant film easily reacts with the high dielectric constant film and that Al diffuses into the high dielectric constant film to form a bond between Hf and Al. ing. This suggests that Al bonded to Hf is chemically stable and cannot be removed by these agents.

  For this reason, Al remains in the formation region of the n-type MIS transistor, the eWF of the n-type MIS transistor shifts, and the threshold voltage increases. Further, if the amount of LaOx introduced is increased in order to suppress the influence of remaining Al, the mobility on the N channel side and the gate capacity are reduced due to excessive La. Of course, it is possible to form the LaOx film first, but in that case, the removability of the LaOx film on the P channel becomes a problem as well as the removability of Al. As a result, the characteristics of the p-type MIS transistor are deteriorated, which is not a fundamental solution.

  An object of the present application is to solve the above-described problem and to realize a semiconductor device in which characteristics of both the p-type MIS transistor and the n-type MIS transistor are improved without using a dual metal gate process.

  In order to achieve the above object, according to the present invention, a semiconductor device is configured to adjust the effective work function of a p-type MIS transistor by using a cap film made of aluminum and a diffusion prevention film made of aluminum nitride.

Specifically, a semiconductor device according to the present invention includes a semiconductor substrate having a p-type semiconductor region and an n-type semiconductor region, a first interface layer formed on the p-type semiconductor region, and a first interface layer. A first gate insulating film including aluminum, a first gate electrode formed on the first gate insulating film, and a second interface layer formed on the n-type semiconductor region A second gate insulating film formed on the second interface layer and containing an element having an effect of reducing an effective work function, and a second gate electrode formed on the second gate insulating film The aluminum concentration in the upper part of the first gate insulating film is 1 × 10 ²⁰ / cm ³ or more, and the aluminum concentration in the upper part of the second gate insulating film is 1 × 10 ¹⁹ / cm ^3. The thickness of the first interface silicon oxide film and the second field The difference from the thickness of the planar silicon oxide film is 0.2 nm or less.

The semiconductor device of the present invention is 1 × 10 ²⁰ / cm ³ or more, the aluminum concentration in the upper part of the second gate insulating film is 1 × 10 ¹⁹ / cm ³ or less, and the first interfacial silicon oxide film The difference between this film thickness and the film thickness of the second interface silicon oxide film is 0.2 nm or less. For this reason, eWF suitable for the p-type MIS transistor can be realized, and EOT can be suppressed small. In addition, since Al is hardly contained in the gate insulating film of the n-type MIS transistor, the concentration of the element having the effect of reducing the effective work function in the second gate insulating film can be kept low. Therefore, the mobility and driving force of the n-type MIS transistor can be improved.

  In the semiconductor device of the present invention, the concentration of aluminum in the upper portion of the first gate insulating film may be higher than the concentration of aluminum in the lower portion of the first gate insulating film.

  The semiconductor device of the present invention may further include a first cap film made of aluminum and formed between the first gate insulating film and the first gate electrode.

The semiconductor device of the present invention may further include a diffusion prevention film made of aluminum nitride formed between the first gate insulating film and the first gate electrode. With such a configuration, Al can be efficiently diffused in the high dielectric constant film.
For the first gate electrode and the second gate electrode, a film formed of titanium nitride, tantalum nitride, tantalum silicon nitride, titanium aluminum nitride, or hafnium nitride can be used.

  In the semiconductor device of the present invention, a film containing lanthanum, yttrium, magnesium, or gadolinium can be used for the second gate insulating film.

  In the semiconductor device of the present invention, the second gate insulating film may contain lanthanum, and the lanthanum concentration at the interface between the second interface silicon oxide film and the semiconductor substrate may be 1.5 atomic% or less.

  In the semiconductor device of the present invention, the high dielectric constant film can be a film containing hafnium or a film containing zirconium.

  The semiconductor device of the present invention further includes an interlayer insulating film formed on the semiconductor substrate, and the interlayer insulating film has a first opening exposing the p-type semiconductor region and a second opening exposing the n-type semiconductor region. The first gate insulating film is formed so as to cover a side surface of the first opening and a portion exposed from the first opening of the p-type semiconductor region, and the second gate insulating film. The film may be formed so as to cover the side surface of the second opening and the portion exposed from the second opening of the n-type semiconductor region. With such a structure, since the source and drain can be formed before the gate insulating film, the heat treatment step after forming the gate insulating film can be reduced.

  A method for manufacturing a semiconductor device according to the present invention includes an interface silicon oxide film, a high dielectric constant film, a first cap film made of aluminum, and aluminum nitride on a semiconductor substrate having a p-type semiconductor region and an n-type semiconductor region. A step (a) for sequentially forming a diffusion prevention film and a hard mask, and a portion formed on the n-type semiconductor region in the first cap film, the diffusion prevention film and the hard mask after the step (a). A step (b) of removing, a step (c) of forming a second cap film containing an element having an effect of reducing the effective work function on the semiconductor substrate after the step (b), and a step (c) A step (d) of performing a heat treatment later, a step (e) of forming an electrode film on the semiconductor substrate after the step (d), and an electrode film, a high dielectric constant after the step (e). Membrane and interfacial silicon The first interface silicon oxide film, the first gate insulating film, and the first gate electrode are formed on the n-type semiconductor region by patterning the oxide film, and the second interface is formed on the p-type semiconductor region. A step (f) of forming a silicon oxide film, a first gate insulating film, and a second gate electrode.

  In the method of manufacturing a semiconductor device according to the present invention, a diffusion prevention film made of AlN is formed on a first cap film made of Al. For this reason, Al diffusion to the hard mask can be suppressed, and Al can be efficiently diffused into the high dielectric constant film. Further, since the first cap film is made of Al, it is possible to suppress an increase in the thickness of the interface silicon oxide film and to keep EOT small. Furthermore, since Al is easy to remove, Al remaining in the n-type semiconductor region can be reduced. Thereby, the concentration of the element having the effect of reducing the effective work function in the second gate insulating film can be kept low. Therefore, the effect of improving the mobility and driving force of the n-type MIS transistor can also be obtained.

In the method of manufacturing a semiconductor device of the present invention, the aluminum concentration on the first gate insulating film is 1 × 10 ²⁰ / cm ³ or more, and the aluminum concentration on the second gate insulating film is 1 × 10 ¹⁹ / cm ³ or less, and the difference between the thickness of the first interface silicon oxide film and the thickness of the second interface silicon oxide film may be 0.2 m or less.

  The method for manufacturing a semiconductor device of the present invention further includes an aluminum diffusion step (f) for diffusing aluminum contained in the first cap film after the step (b) and before the step (e). May be.

  The semiconductor device manufacturing method of the present invention may further include a step (h) of removing the second cap film after the step (d) and before the step (e).

  The semiconductor device manufacturing method of the present invention may further include a step (i) of removing the hard mask in the p-type semiconductor region after the step (h) and before the step (e).

  The semiconductor device manufacturing method of the present invention may further include a step (j) of removing the diffusion barrier film in the p-type semiconductor region after the step (i) and before the step (e). Good.

  In the method for manufacturing a semiconductor device of the present invention, a film containing lanthanum, yttrium, magnesium, or gadolinium can be used for the second cap film.

  In the method for manufacturing a semiconductor device of the present invention, the second cap film contains lanthanum, and heat treatment may be performed at a temperature of 800 ° C. or lower in the step (d).

  In the method for manufacturing a semiconductor device of the present invention, a film containing hafnium or a film containing zirconium can be used as the high dielectric constant film.

  In the method for manufacturing a semiconductor device of the present invention, a step of forming a p-type source / drain diffusion layer in the p-type semiconductor region and an n-type source / drain diffusion layer in the n-type semiconductor region (step (a)). i) and an interlayer having a first opening exposing the p-type semiconductor region and a second opening exposing the n-type semiconductor region after step (i) and before step (a) A step (j) of forming an insulating film, and in the step (a), the high dielectric constant film is formed from the side surfaces of the first opening and the second opening and the first opening of the p-type semiconductor region. You may form so that the exposed part and the part exposed from the 2nd opening part of the n-type semiconductor region may be covered.

  According to the semiconductor device and the method for manufacturing the semiconductor device of the present invention, a semiconductor device in which the characteristics of both the p-type MIS transistor and the n-type MIS transistor are improved can be realized without using a dual metal gate process.

It is sectional drawing which shows the semiconductor device for evaluation. It is a characteristic view which shows the relationship between the capacity | capacitance of the semiconductor device for evaluation, and a voltage. It is a characteristic view which shows the relationship between the film thickness of a cap film | membrane, and EOT. (A)-(c) is a cross section of the semiconductor device for evaluation, (a) shows the cross section on the P channel side when the cap film is an AlOx film, and (b) shows the P when the cap film is an Al film. A cross section on the channel side is shown, and (c) shows a cross section on the N channel side. It is a characteristic view showing the relationship between the treatment time with hydrochloric acid and the remaining amount of the cap film. It is a characteristic view which shows the result of having measured the aluminum density | concentration contained in a high dielectric constant film after removing a cap film | membrane. It is a characteristic view showing the relationship between the film thickness of the cap film and the eWF of the n-type MIS transistor. (A)-(c) is the result of having measured Al diffusion in a TiN film | membrane, (a) shows the distribution before heat processing, (b) shows the distribution after heat processing at 800 degreeC, (c ) Shows the distribution after heat treatment at 800 ° C. when a diffusion barrier film made of AlN is formed. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. FIG. 6 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment in the order of steps. FIG. 6 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment in the order of steps. FIG. 6 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment in the order of steps. FIG. 6 is a characteristic diagram showing a vertical distribution of Al in a p-type MIS transistor. It is a characteristic view which shows distribution of EOT and eWF in a p-type MIS transistor. It is a characteristic view which shows the relationship between the heat processing temperature in an n-type MIS transistor, eWF, and EOT. It is a characteristic view which shows distribution of the depth direction of La in an n-type MIS transistor. It is a characteristic view which shows the relationship between the heat processing temperature in a p-type MIS transistor, eWF, and EOT. It is sectional drawing which shows the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment to process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment to process order. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment to process order.

  First, the principle for realizing an effective work function (eWF) suitable for a p-type MIS transistor while suppressing an increase in equivalent oxide thickness (EOT) of the p-type MIS transistor will be described.

FIG. 1 shows a cross-sectional configuration of the evaluation semiconductor device. The evaluation semiconductor device is a metal-insulating film-semiconductor (MIS) capacitor sequentially formed on a semiconductor substrate 301 which is a silicon substrate, and includes an interface silicon oxide film 302, a high dielectric constant film 303, a cap film 304, and An electrode film 305 is provided. The interface silicon oxide film 302 is a SiO ₂ film having a thickness of about 1.2 nm. The high dielectric constant film 303 is a nitrogen-containing hafnium silicate (HfSiON) film having a thickness of 1.5 nm. The electrode film 305 is a TiN film having a thickness of 15 nm.

  FIG. 2 shows the capacitance-voltage (CV) characteristics of the semiconductor device for evaluation. In FIG. 2, the frequency of the applied voltage is 100 kHz. When an AlOx film or an Al film having a thickness of 0.5 nm was provided as the cap film 304, the flat band voltage (Vfb) shifted in the positive direction as compared with the case where no cap film was formed. This indicates that eWF is increased by providing the cap film 304 made of an AlOx film or an Al film. When the film thickness was the same, the increase amount of eWF was larger in the AlOx film than in the Al film.

  On the other hand, as shown in FIG. 2, when the cap film 304 is an AlOx film, the storage capacity is reduced as compared with the case where the cap film is not formed. This indicates that EOT is increasing. On the other hand, when the cap film 304 is an Al film, the storage capacity is almost the same as when the cap film is not formed.

  FIG. 3 shows the relationship between the thickness of the cap film and the amount of increase in EOT. In the case of the AlOx film, the amount of increase in EOT increased as the film thickness increased. However, in the case of the Al film, the EOT value was almost constant even when the film thickness was increased.

  4A to 4C schematically show the results of observing the cross section of the semiconductor device for evaluation with a transmission electron microscope (TEM). (A) shows the case where an AlOx film having a film thickness of 0.5 nm is used for the cap film, and (b) shows the case where an Al film having a film thickness of 0.5 nm is used for the cap film. Further, (c) shows a cross section on the N channel side. As shown in FIG. 4, it is clear that the thickness of the interfacial silicon oxide film is thinner when the cap film is an Al film than when the cap film is an AlOx film. This is because when the cap film is an AlOx film, excess oxygen diffuses into the high dielectric constant film and the interfacial silicon oxide film immediately after the cap film is deposited or in the heat treatment step after the deposition, so that the interfacial silicon oxide film is It shows that the film is increased. On the other hand, in the case of an Al film, surplus oxygen does not diffuse, so that an increase in the interface silicon oxide film can be suppressed. Compared with the cross section of the N channel shown in FIG. 4C, it can be seen that the film thickness of the interface silicon oxide film on the N channel side is almost the same as that when the cap film is Al. On the other hand, when AlOx was used for the cap film, it was found that the thickness of the interface silicon oxide film was 0.2 nm or more thicker than that of the interface silicon oxide film on the N channel side.

  Unlike the AlOx film that is an oxide film, the Al film that is a metal film can be easily dissolved and removed with dilute hydrochloric acid. FIG. 5 shows the relationship between the treatment time with dilute hydrochloric acid and the remaining amount of the Al-based cap film formed on the high dielectric constant film. The film thickness of the cap film is a value obtained by X-ray photoelectron spectroscopy (XPS) measurement. As shown in FIG. 5, in the case of an Al film, the cap film can be almost completely removed by performing the treatment for several tens of seconds. However, in the case of the AlOx film, even if the treatment was continued for about 1000 seconds, the result was that the AlOx film was saturated with the remaining AlOx film of about 0.1 nm.

FIG. 6 illustrates the distribution in the depth direction of the Al amount remaining in the high dielectric constant film after removing the cap film made of Al or AlOx in the N channel region. First, an interfacial silicon oxide film made of SiO ₂ , a high dielectric constant film made of HfSiON, and a cap film were formed on a Si substrate, and then the cap film was removed with dilute hydrochloric acid to form an electrode film made of TiN. In FIG. 6, the case where the cap film is an AlOx film having a thickness of 0.5 nm is indicated by a broken line, and the case where the cap film is an Al film having a thickness of 1.0 nm is indicated by a solid line. A secondary ion mass spectrometry (SIMS) method from the backside was used for the measurement of the residual amount of Al. As shown in FIG. 6, when the cap film is an AlOx film, even if hydrochloric acid-based Al removal cleaning is performed, the interface between the high dielectric constant film and the TiN film is about 2 × 10 ²⁰ atoms / cm ³ . Al remains. On the other hand, when the cap film was an Al film, the residual amount of Al in the bulk of the high dielectric constant film after the hydrochloric acid-based Al removal cleaning was 1 × 10 ¹⁹ atoms / cm ³ or less.

  If Al diffuses into the gate insulating film of the n-type MIS transistor, the effect of La or the like that shifts eWF to the lower side may be hindered. FIG. 7 shows the relationship between the film thickness of the LaOx film and eWF when the LaOx film is deposited on the high dielectric constant film after the cap film is removed and an electrode film made of TiN is formed. Whether the cap film is an AlOx film or an Al film, eWF tends to decrease as the thickness of the LaOx film increases. However, this is because increasing the thickness of the LaOx film increases the amount of La diffused into the high dielectric constant film. When the cap film was an AlOx film, eWF was about 0.15 eV to 0.2 eV higher than when the cap film was an Al film. Therefore, when the cap film is an Al film, the concentration of La necessary for realizing the same eWF can be made lower than when the cap film is an AlOx film. If the La concentration in the gate insulating film can be reduced, there is an advantage that the mobility of carriers on the N channel side increases and the current driving capability of the transistor can be improved.

  By using an Al film instead of the AlOx film, an increase in EOT of the p-type MIS transistor can be suppressed and the current driving capability of the n-type MIS transistor can be improved. However, in order to realize an eWF equivalent to the AlOx film, it is necessary to make the thickness of the Al film thicker than that of the AlOx film. The reason why the thickness of the Al film needs to be increased is considered to be that the Al film is more easily diffused into the TiN film than the AlOx film. That is, when an Al film is used, Al diffuses not only in the high dielectric constant film but also in the TiN film. For this reason, it is considered that the Al concentration in the high dielectric constant film decreases and the shift amount of eWF becomes small.

  Increasing the thickness of the Al film has little effect on EOT. For this reason, with respect to EOT, there is no major problem even if Al diffuses into the TiN film. However, the diffusion of Al into the TiN film is not always constant in the plane due to the annealing characteristics. For this reason, the residual film thickness of Al after removal of the hard mask may vary, and the eWF may vary. Therefore, it is necessary to suppress the diffusion of Al into the TiN film.

  In order to suppress the diffusion of Al into the TiN film, a diffusion prevention film may be formed between the Al film and the TiN film. The diffusion prevention film may be a chemically stable film, but in order to form a complementary transistor, it needs to be a film that can be easily removed. For this reason, it is preferable to use an aluminum nitride (AlN) film as the diffusion preventing film.

  FIGS. 8A to 8C show the profiles of Ti and Al at the interface between the TiN film and the Al film. (A) shows the profile immediately after laminating the Al film on the TiN film, (b) shows the profile after the heat treatment at 800 ° C., and (c) shows between the TiN film and the Al film. The profile after performing the heat processing of 800 degreeC in the case of inserting an AlN film into is shown. As shown in FIG. 8B, when there is no AlN film, Al is diffused deeply in the TiN film after the heat treatment. However, when an AlN film is inserted as shown in FIG. 8C, the diffusion of Al into the TiN film is suppressed even after heat treatment.

  In the case where a p-type MIS transistor and an n-type MIS transistor are formed to form a complementary MIS transistor, the first cap film having an effect of increasing the eWF of the p-type MIS transistor is formed and then made of TiN or the like. It is common to form a hard mask. The hard mask is formed to prevent La or the like contained in the second cap film having the effect of reducing the eWF of the n-type MIS transistor from diffusing into the gate insulating film of the p-type MIS transistor. For this reason, after diffusing the second cap film, at least a part of the hard mask is generally removed. Also, all the hard mask is removed. Since the etching rate differs between the Al film and the AlN film, the etching can be easily stopped at the interface between the Al film and the AlN film. Therefore, when the diffusion prevention film made of AlN is formed between the first cap film made of Al and the hard mask made of TiN, there is also an advantage that the hard mask can be easily removed.

  Thus, by using an Al film instead of the AlOx film as the cap film of the p-type MIS transistor and further providing a diffusion prevention film made of AlN, the eWF can be increased without increasing the EOT of the p-type MIS transistor. Can do. Further, by preventing the diffusion of Al into TiN, it is possible to suppress variations in the Al diffusion amount and the Al residual amount after removal of the hard mask. Thereby, the dispersion | variation in eWF shift amount can be suppressed. Furthermore, the remaining amount of Al in the high dielectric constant film of the n-type MIS transistor can be greatly reduced as compared with the case where AlOx is used as a conventional cap film. As a result, it is possible to suppress the deterioration of the n-type MIS transistor characteristics. Below, it demonstrates still in detail using embodiment.

(First embodiment)
FIG. 9 shows a cross-sectional configuration of the semiconductor device according to the first embodiment. A semiconductor substrate 101 such as a silicon (Si) substrate is formed with a p-type semiconductor region 10A where a p-type MIS transistor is formed and an n-type semiconductor region 10B where an n-type MIS transistor is formed. The p-type semiconductor region 10 </ b> A has an n-well 103 separated by the element isolation region 102, and the n-type semiconductor region 10 </ b> B has a p-well 104 separated by the element isolation region 102. The element isolation region 102 may be a local oxidation of silicon (LOCOS) method or a shallow trench isolation (STI) method.

A p-type gate stack is formed on the n-well 103. The p-type gate stack is formed by sequentially forming an interface silicon oxide film 105 made of a silicon oxide film (SiO ₂ film) or a silicon oxynitride film (SiON film), etc., and a first gate insulating film 106A which is a high dielectric constant film. A first cap film 107 that is an Al film, a diffusion prevention film 117 that is an AlN film, and a first gate electrode 119A. An n-type gate stack is formed on the p-well 104. The n-type gate stack includes an interfacial silicon oxide film 105, a second gate insulating film 106B that is a high dielectric constant film containing an element such as La, and a second gate electrode 119B, which are sequentially formed. .

The high dielectric constant film is an insulating film or zirconium oxide (ZrO) containing Hf and O, such as a hafnium silicate (HfSiO) film, a hafnium nitride silicate (HfSiON) film, a hafnium oxide (HfO) film, or a hafnium zirconate (HfZrO) film. Any insulating film containing zirconium may be used. The first gate insulating film 106A contains Al having an effect of increasing eWF, and the surface density of Al in the upper portion of the first gate insulating film 106A is 1 × 10 ¹⁵ cm ⁻² or more. The second gate insulating film 106B does not substantially contain Al, and the surface density of Al in the upper part of the second gate insulating film 106B is 1 × 10 ¹² cm ⁻² or less. Further, the second gate insulating film 106B contains La having an effect of reducing eWF. On the other hand, La is not substantially contained in the first gate insulating film 106A. Note that the second gate insulating film 106B may contain magnesium (Mg), yttrium (Y), magnesium (Mg), gadolinium (Gd), or the like instead of La.

  The first gate electrode 119A is a laminated film of a hard mask 108 made of TiN, a first electrode film 110 made of TiN, and a second electrode film 111 made of polysilicon, and is a second gate electrode 119B. Is a laminated film of a first electrode film 110 made of TiN and a second electrode film 111 made of polysilicon. Since the first gate electrode 119A includes the hard mask 108, it is thicker than the second gate electrode 119B. For this reason, eWF can be made larger. However, the first gate electrode 119A may not include the hard mask 108. The hard mask 108 and the first electrode film 110 are made of titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum carbide (TaC), or hafnium nitride (HfN) instead of TiN. It may be.

  The configuration in which the p-type gate stack includes the diffusion prevention film 117 and the first cap film 107 is shown. However, the diffusion prevention film 117 may be removed. In addition, the first cap film 107 may be diffused and integrated with the first gate insulating film 106A. The n-type gate stack may have a second cap film containing an element having an effect of reducing eWF.

  Sidewalls 113 are formed on the side surfaces of the p-type gate stack and the n-type gate stack. A p-type extension diffusion layer 115A is formed on both sides of the p-type gate stack in the n-well 103, and a p-type source / drain diffusion layer 116A is formed on the outer side of the p-type extension diffusion layer 115A. An n-type extension diffusion layer 115B is formed on both sides of the n-type gate stack in the p-well 104, and an n-type source / drain diffusion layer 116B is formed on the outer side of the n-type extension diffusion layer 115B. A silicide layer 114 is formed on the first gate electrode 119A, the second gate electrode 119B, the p-type source / drain diffusion layer 116A, and the n-type source / drain diffusion layer 116B. An interlayer insulating film 121 is formed so as to cover the p-type gate stack and the n-type gate stack, and a contact plug 122 connected to the silicide layer 114 is formed in the interlayer insulating film 121.

  10 to 12 show the semiconductor device manufacturing method according to the first embodiment in the order of steps. First, as shown in FIG. 10A, a p-type semiconductor region 10A for forming a p-type MIS transistor and an n-type semiconductor region 10B for forming an n-type MIS transistor which are separated from each other by an element isolation region 102 on a semiconductor substrate 101. Form. The semiconductor substrate 101 may be a Si substrate, for example. An n-well 103 is formed in the p-type semiconductor region 10A, and a p-well 104 is formed in the n-type semiconductor region 10B. The element isolation region 102 may be formed by a local oxidation of silicon (LOCOS) method or a shallow trench isolation (STI) method.

Next, as shown in FIG. 10B, an interfacial silicon oxide film 105 is formed on the entire surface of the semiconductor substrate 101. The interface silicon oxide film 105 may be a silicon oxide film (SiO ₂ film) or a silicon oxynitride film (SiON film). Specifically, a chemical oxide film with an optical film thickness of about 0.5 nm and a radical oxide film with a film thickness of about 0.5 nm to 1.5 nm may be used. The chemical oxide film may be formed by treating the semiconductor substrate 101 with a mixed solution of hydrochloric acid and hydrogen peroxide. The radical oxide film may be formed by performing heat treatment at about 600 ° C. to 850 ° C. in an H ₂ and N ₂ O mixed gas atmosphere.

Subsequently, a high dielectric constant film 106 is formed on the interfacial silicon oxide film 105. The high dielectric constant film 106 may be an Hf-based insulating film such as an HfSiO film, an HfSiON film, an HfO film, or HfZrO. The high dielectric constant film 106 may be formed by, for example, an atomic layer deposition method (ALD method). In this case, an inorganic material such as HfCl ₄ (hafnium tetrachloride) or an organic material containing Hf such as Hf [N (C ₂ H ₅ ) CH ₃ ] ₄ (tetrakis (ethylmethylamino) hafnium) and SiH ₄ A gas containing Si such as Si or an organic material containing Si such as SiH [N (CH ₃ ) ₂ ] ₃ (tris (dimethylamino) silane) may be used as a raw material. Oxygen (O ₂ ), ozone (O ₃ ), water vapor (H ₂ O) or the like is used while alternately depositing for a short time at a film forming temperature of about 300 ° C. to 600 ° C. and purging surplus raw materials. It only has to be oxidized.

The film thickness of the high dielectric constant film 106 should be about 2 nm to 3.5 nm in combination with the radical oxide film when the EOT is intended to be in the range of about 1.0 nm to 1.5 nm. Good. The high dielectric constant film 106 may be a zirconium-based film such as zirconium oxide (ZrO) in addition to the Hf-based film. In the case of a Zr-based film, inorganic raw material ZrCl ₄ (zirconium tetrachloride) or organic raw material Zr [N (C ₂ H ₅ ) CH ₃ ] ₄ (tetrakis (ethylmethylamino) zirconium) May be formed by the same film formation method as that for the Hf-based film, or Zr may be introduced.

  Subsequently, in order to prevent the high dielectric constant film 106 from being crystallized, the high dielectric constant film 106 may be subjected to plasma nitriding treatment. When the amount of nitrogen introduced in the plasma nitriding process is too large, the BTI characteristics may be deteriorated together with the deterioration of the transistor interface characteristics. In addition, since the nitrogen element has a positive fixed charge in the high dielectric constant film and the work function is lowered when the amount of introduced nitrogen is increased, the amount of introduced nitrogen is preferably about 10 atomic% or less.

  Thereafter, the high dielectric constant film 106 can be heat-treated in an oxygen or nitrogen atmosphere. Thereby, impurities in the high dielectric constant film 106 can be removed and defects can be repaired. In addition, adhesion with the interface silicon oxide film 105 can be improved.

  Subsequently, a first cap film 107 made of aluminum (Al) is formed on the high dielectric constant film 106. The first cap film 107 may be formed by a physical vapor deposition (PVD) method. Specifically, the film formation is performed using an aluminum target by sputtering discharge in a rare gas atmosphere so that the physical film thickness is about 0.3 nm to 2 nm. Subsequently, a diffusion prevention film 117 made of aluminum nitride (AlN) is formed. The thickness of the diffusion preventing film 117 may be about 1 nm to 5 nm. When forming the diffusion prevention film 117, it is possible to form it by a PVD method using an Al target in a nitrogen atmosphere. Thereafter, a hard mask 108 made of TiN is formed. The thickness of the formed hard mask 108 may be determined according to the second cap film diffusion penetration depth. In the case where the second cap film is made of LaOx, the diffusion penetration depth of La is about 4 nm, so that it may be about 6 nm to 15 nm.

  The first cap film 107, the diffusion preventing film 117, and the hard mask 108 are preferably formed successively by the PVD method. If the atmosphere is released before the hard mask 108 is formed, the oxidation of Al proceeds, and there is a possibility that the EOT and eWF of the p-type MIS transistor vary. In addition, the removability of Al is lowered, and the characteristics of the n-type MIS transistor may be deteriorated. Instead of the PVD method, an ALD method or a chemical vapor deposition (CVD) method may be used. By using the ALD method, not only the controllability of the film thickness and the impurity content can be improved, but also advantages such as the low temperature of the process can be obtained.

  Next, as shown in FIG. 10C, the portions formed in the n-type semiconductor region 10B in the hard mask 108, the diffusion prevention film 117, and the first cap film 107 are selectively selected using lithography and etching techniques. To remove. The etching conditions are set so that the high dielectric constant film 106 is not damaged. Specifically, hydrochloric acid, a mixed solution of hydrochloric acid and hydrogen peroxide solution (HPM), or a mixed solution of sulfuric acid and hydrogen peroxide solution (SPM) may be used. In the case of hydrochloric acid, the concentration may be about 1/100 to 1/1000. In the case of HPM or SPM, the concentration may be about 1/100 to 1/1000. Since the Al film has better removability than the AlOx film and can reduce the cleaning load, it has an advantage that damage to the high dielectric constant film 106 can be further reduced.

  Note that the plasma nitridation process for the high dielectric constant film 106 described above can be performed at this stage. When nitrogen is mixed on the P channel side, deterioration of interface characteristics and BIT characteristics is induced. However, at this stage, since the P channel side is masked by TiN / AlN, mixing of nitrogen into the P channel side can be prevented, and only the N channel can be selectively nitrided.

  Next, as shown in FIG. 10D, a second cap film 109 containing La is formed. The second cap film may be formed using a sputtering method or an ALD method. In the case of using the sputtering method, a La film can be formed by using a target made of lanthanum and forming by direct current discharge using Ar gas. A lanthanum oxide (LaOx) film can be formed by reactive sputtering using oxygen gas. The LaOx film may be formed by RF sputtering using a target made of LaOx. Alternatively, after vaporizing and depositing an organic material containing La, a purge process, an oxidation process, and an organic substance removal process may be sequentially performed to form a LaOx film by a so-called ALD method.

  Hereinafter, specific conditions when a LaOx film is formed as the second cap film 109 using RF sputtering will be described. In order to suppress damage to the high dielectric constant film, it is preferable that the RF power is about 300 W to 800 W, the discharge pressure is about 0.1 Torr, and the self-bias voltage is about 100 V. Thereby, the film formation rate can be controlled to about 40 seconds to 100 seconds per 1 nm. In this way, the second cap film 109 having a thickness of about 0.1 nm to 2 nm is formed.

  Thereafter, a heat treatment is performed to form a La diffusion high dielectric constant film 106b in which La contained in the second cap film 109 is diffused in the n-type semiconductor region 10B. In the p-type semiconductor region 10A, La diffuses into the hard mask 108 to form a La diffusion region 108a. The heat treatment may be performed at a temperature of about 600 ° C. to 850 ° C. in a nitrogen atmosphere. The heat treatment time depends on the atmospheric pressure and the heat treatment method, but is about 5 to 120 seconds when using the rapid heat treatment method at normal pressure, and about 1 minute to 10 minutes when using the resistance heater under reduced pressure. If it exists, it has been confirmed that the characteristics are not deteriorated.

  As shown in FIG. 11A, the unreacted second cap film 109 remaining on the high dielectric constant film 106 and the hard mask 108 is removed. Although the unreacted second cap film 109 need not be removed, removing the unreacted second cap film 109 reduces the breakdown voltage and reliability due to excessive La in the n-type MIS transistor. Can be suppressed. In addition, in the p-type transistor, device delay due to an etch stop during gate etching and an increase in interface resistance can be suppressed.

  When the unreacted second cap film 109 is removed by cleaning, it is performed under conditions that do not damage the high dielectric constant film 106 in the n-type semiconductor region 10B. Specifically, hydrochloric acid, hydrogen peroxide hydrochloride (HPM), or hydrogen peroxide sulfate (SPM) may be used. In the case of hydrochloric acid, the concentration may be about 1/100 to 1/1000. In the case of HPM or SPM, the concentration may be about 1/100 to 1/1000.

  It is also preferable to remove the La diffusion region 108a formed on the hard mask 108. When the second cap film 109 is made of LaOx, the La diffusion region 108a absorbs oxygen. For this reason, when the second cap film 109 is left, it becomes a supply source of oxygen, which may cause an interface thickening or the like in a later process. It has been clarified that the diffusion length of La into the hard mask 108 depends on the heat treatment temperature, and is about 3 nm at 800 ° C. Therefore, when removing the second cap film 109, it is preferable to remove the surface of the hard mask 108 by 3 nm or more, and it is more preferable to remove about 5 nm including overetching. Further, the hard mask 108 may be completely removed. However, if the hard mask 108 is left and used as a part of the gate electrode of the p-type MIS transistor, there is a difference between the thickness of the gate electrode of the p-type MIS transistor and the thickness of the gate electrode of the n-type MIS transistor. EWF can be controlled.

  Further, when the hard mask 108 is completely removed, there is no problem even if a part of the diffusion prevention film 117 is removed. Further, the diffusion preventing film 117 may be completely removed. However, when the diffusion prevention film 117 is completely removed, it is preferable that the first cap film 107 is sufficiently diffused into the high dielectric constant film before the diffusion prevention film 117 is removed.

  Next, as shown in FIG. 11B, a first electrode film 110 made of TiN is formed on the entire surface of the semiconductor substrate 101. The first electrode film 110 may be formed by a PVD method, a CVD method, or an ALD method. The film thickness of the first electrode film 110 affects the work function of the gate electrode. Therefore, the thickness of the first electrode film 110 may be about 4 nm to 20 nm.

Next, as shown in FIG. 11B, a second electrode film 111 made of polysilicon doped with phosphorus having a thickness of 80 nm to 150 nm is deposited. The concentration of phosphorus may be about 1 × 10 ¹⁴ to 2 × 10 ¹⁵ / cm ² . Alternatively, arsenic or the like may be implanted after the non-doped polysilicon film is formed.

  Next, as shown in FIG. 12A, the second electrode film 111, the first electrode film 110, the hard mask 108, and the high dielectric constant film are formed in the p-type semiconductor region 10A by using lithography and etching techniques. 106 and the interfacial silicon oxide film 105 are etched to form a p-type gate stack. The p-type gate stack includes a first gate electrode 119A including a second electrode film 111, a first electrode film 110, and a hard mask 108, and a first gate insulating film 106A made of a high dielectric constant film in which Al is diffused. And have. In the n-type semiconductor region 10B, the second electrode film 111, the first electrode film 110, the La diffusion high dielectric constant film 106b, and the interface silicon oxide film 105 are etched to form an n-type gate stack. The n-type gate stack includes a second gate electrode 119B including the second electrode film 111 and the first electrode film 110, and a second gate insulating film 106B made of a high dielectric constant film in which La is diffused.

  Next, as shown in FIG. 12B, a p-type extension diffusion layer 115A and an n-type extension diffusion layer 115B having relatively shallow junction depths are formed in the n-well 103 and the p-well 104, respectively, by a known method. . Subsequently, sidewalls 113 are formed on the side surfaces of the p-type gate stack and the n-type gate stack. Thereafter, a p-type source / drain diffusion layer 116A and an n-type source / drain diffusion layer 116B having junction depths deeper than the extension diffusion layer are formed in the n-well 103 and the p-well 104, respectively. Further, a silicide layer 114 is formed.

Next, as shown in FIG. 12C, an interlayer insulating film 121 made of, for example, a SiO ₂ film is formed on the semiconductor substrate 101 so as to cover the p-type gate stack and the n-type gate stack by a known method. Form. Subsequently, a contact plug 122 made of tungsten or the like that reaches the silicide layer 114 through the interlayer insulating film 121 is formed. Thereafter, wiring or the like (not shown) is formed as necessary.

  In the present embodiment, there is no particular heat treatment step for diffusing the first cap film 107 made of Al. However, diffusion of the first cap film 107 occurs in the heat treatment step for diffusing the second cap film 109 and the subsequent heat treatment step. In addition to these heat treatment steps, an Al diffusion step may be provided. When the Al diffusion step is not performed, as shown by a broken line in FIG. 13, a portion having a high Al concentration is formed on the high dielectric constant film. On the other hand, by performing the Al diffusion step, as indicated by a solid line in FIG. 13, the diffusion of Al into the high dielectric constant film is promoted, and the Al concentration in the high dielectric constant film becomes more uniform. By sufficiently diffusing Al in the high dielectric constant film and forming a strong bond between Al and Hf, the effect of increasing the eWF becomes larger, and the gate leakage current (Jg) can be reduced, or TDDB (Time Dependent Dielectric Breakdown) and the like can be improved.

  The heat treatment that is the Al diffusion step may be performed any time after the first cap film 107 is formed and before the gate stack is formed. However, the removability of the first cap film 107 may decrease in the n-type semiconductor region 10B due to the heat treatment. For this reason, it is preferable to perform the Al diffusion step after removing the first cap film 107 in the n-type semiconductor region 10B. Further, an Al diffusion step may be performed after heat treatment for diffusing the second cap film 109 or after removing the hard mask 108 after that. However, if the Al diffusion step is performed after removing the diffusion preventing film 117, Al may be diffused into the first electrode film made of TiN. Therefore, it is preferable to perform an Al diffusion step before removing the diffusion prevention film 117.

  After Al in the first cap film diffuses into the high dielectric constant film and Hf and Al are combined, Al hardly diffuses into the TiN film. Therefore, if the heat treatment for diffusing the second cap film 109 is performed, there is no problem even if the diffusion prevention film 117 is removed.

  The Al diffusion step is preferably performed in an inert gas atmosphere in order to suppress Al oxidation. The treatment temperature may be 800 ° C. or higher. However, if the temperature is too high, oxidation and crystallization of the high dielectric constant film proceed, and therefore it is preferably 1000 ° C. or lower.

  FIG. 14 shows the distribution of EOT and eWF when the first cap film is an Al film with a thickness of 1 nm and when the first cap film is an AlOx film with a thickness of 0.5 nm. When an Al film having a thickness of 1 nm is used as the first cap film, EOT is reduced without lowering the eWF of the p-type MIS transistor as compared with the case of using an AlOx film having a thickness of 0.5 nm. The thickness can be reduced by about 0.2 nm. Further, the difference from EOT when the cap film is not formed is 0.2 nm or less. Therefore, the difference between the EOT of the second gate insulating film of the n-type MIS transistor and the first gate insulating film of the p-type MIS transistor and EOT is 0.2 nm or less.

  In addition, when the first cap film is an Al film, the temperature of the heat treatment for thermally diffusing LaOx, which is the material of the second cap film, into the gate insulating film can be lowered. FIG. 15 shows the relationship between the temperature of the heat treatment for diffusing the second cap film and the eWF and EOT of the n-type MIS transistor. As shown in FIG. 15, the higher the heat treatment temperature, the lower the eWF value. The value of eWF of the n-type MIS transistor may be about 4.1 eV. When the first cap film is an AlOx film, the removability with a hydrochloric acid-based solution is inferior, so that Al remains in the high dielectric constant film. Therefore, in order to cancel the influence of the remaining Al on the eWF and obtain the necessary eWF, it is necessary to perform a heat treatment at a high temperature of about 850 ° C. to increase the amount of La diffusion. However, when the first cap film is an Al film, the heat treatment temperature can be lowered to 700 ° C. to 750 ° C. as shown in FIG. As shown in FIG. 15, in the case where the first cap film is an Al film, unlike the case of the AlOx film, the lower the heat treatment temperature, the smaller the EOT can be obtained. Further, by reducing the heat treatment temperature, when the heat treatment temperature is lowered as shown in FIG. 16, the concentration of La in the vicinity of the interface with the semiconductor substrate can be lowered, and the interface characteristics can be improved. . As the interface characteristics are improved, the mobility and current driving capability of the n-type MIS transistor can be further improved. In the n-type MIS transistor, the La concentration at the interface between the interfacial silicon oxide film and the semiconductor substrate is preferably about 1.5 atomic% or less.

  Further, it is possible to further improve the characteristics of the p-type MIS transistor by lowering the temperature of the heat treatment for diffusing the second cap film. FIG. 17 shows the relationship between the temperature of the heat treatment for diffusing the second cap film and the eWF and EOT of the p-type MIS transistor. When the first cap film is an Al film, the EOT can be reduced without degrading the eWF of the p-type MIS transistor even if the temperature of the heat treatment for diffusing the second cap film is lowered. .

  The second cap film only needs to contain an element having an effect of reducing the eWF of the nMIS transistor, and may be another lanthanoid such as gadolinium (Gd) or an oxide film thereof instead of La. Alternatively, yttrium (Y), magnesium (Mg), or an oxide film thereof may be used.

  The first electrode film may be titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum carbide (TaC), or hafnium nitride (HfN) instead of TiN.

(Second Embodiment)
FIG. 18 shows a cross-sectional configuration of the semiconductor device according to the second embodiment. In FIG. 18, the same components as those of FIG.

  The semiconductor device of the present embodiment includes a p-type MIS transistor having a three-dimensional first gate insulating film 106A and a first gate electrode 119A embedded in an opening formed in an interlayer insulating film, and a three-dimensional first. An n-type MIS transistor having two gate insulating films 106B and a second gate electrode 119B.

  With such a structure, the gate insulating film can be formed after the impurity diffusion layer such as the source / drain diffusion layer is formed. Therefore, the process of applying heat to the gate insulating film can be reduced, so that the high dielectric constant film and the gate electrode material are mixed in the subsequent thermal process, the interface layer is increased, and the Al profile and La in the high dielectric constant film are increased. It is possible to suppress deterioration of characteristics due to the broadening of the profile.

In FIG. 18, a surface protective film 131 made of SiO ₂ is formed between the sidewall 113 and the semiconductor substrate 101. An etching stopper film 135 made of SiO ₂ is formed between the interlayer insulating film 136 made of SiN, the sidewall 113 and the semiconductor substrate 101.

  19 to 21 show the method of manufacturing the semiconductor device according to the second embodiment in the order of steps. First, as shown in FIG. 19A, a semiconductor substrate 101 having a p-type semiconductor region 10A for forming a p-type MIS transistor and an n-type semiconductor region 10B for forming an n-type MIS transistor is connected to each other by an element isolation region 102. Separated n-well 103 and p-well 104 are formed.

Subsequently, a surface protective film 131 made of a SiO ₂ film having a thickness of about 5 nm is formed on the entire surface of the semiconductor substrate 101. A dummy gate 132 made of a polysilicon film or an amorphous silicon film having a thickness of about 100 nm is formed on the surface protective film 131. The thickness of the dummy gate 132 may be determined in consideration of the heights of the p-type gate electrode and the n-type gate electrode to be formed later. A p-type extension diffusion layer 115A is formed in the n-well 103 and an n-type extension diffusion layer 115B is formed in the p-well 104 by a self-alignment process using the dummy gate 132 as a mask. Note that a so-called halo layer may be formed by performing ion implantation in the counter (reverse polarity) direction in a self-aligned manner with respect to the dummy gate 132.

Next, as shown in FIG. 19B, a low-temperature deposited silicon nitride film (SiN film) having a thickness of about 8 nm to 20 nm is formed on the entire surface of the semiconductor substrate 101. Subsequently, etch back is performed to form a sidewall 113 of the p-type gate electrode and a sidewall 113 of the n-type gate electrode. Subsequently, ions are implanted into the n-well 103 by a self-alignment process using the dummy gate 132 and the sidewall 113 as a mask, and a heat treatment is performed to form a p-type source / drain diffusion layer 116A. Similarly, an n-type source / drain diffusion layer 116B is formed by performing ion implantation into the p-well 104 by a self-alignment process using the dummy gate 132 and the sidewall 113 as a mask, and further performing heat treatment. Subsequently, after removing portions of the surface protective film 131 formed on the p-type source / drain diffusion layer 116A and the n-type source / drain diffusion layer 116B, an etching stopper film 135 made of an SiO ₂ film or the like is formed. Further, an interlayer insulating film 136 made of a SiN film is formed.

  Next, as shown in FIG. 19C, the interlayer insulating film 136 is polished by chemical mechanical polishing (CMP) until the etching stopper film 135 is exposed. Thereafter, the etching stopper film 135 and the dummy gate 132 are removed by reactive ion etching (RIE) or the like to form an opening 136a. At this time, the surface protective film 131 is also removed, and the n-well 103 and the p-well 104 are exposed.

  Next, as shown in FIG. 20A, an interfacial silicon oxide film 105 is formed at a portion exposed from the opening 136a of the semiconductor substrate 101 by low-temperature oxidation, and then a high dielectric constant film 106 is formed by an ALD method or the like. Form. Thereafter, plasma nitridation may be performed on the high dielectric constant film 106 as in the first embodiment. Subsequently, a first cap film 107 made of Al is formed on the high dielectric constant film 106, and a diffusion prevention film 117 made of AlN is formed on the first cap film 107. Further, a hard mask 108 made of TiN is formed on the diffusion preventing film 117.

  Next, as shown in FIG. 20B, a resist mask 138 covering the p-type semiconductor region 10A is formed using a known lithography technique. Subsequently, using the resist mask 138 as an etching mask, the hard mask 108, the diffusion preventing film 117, and the first cap film 107 are selectively removed by etching. The etching conditions are set so that the high dielectric constant film 106 is not damaged. Wet etching using dilute hydrochloric acid, hydrochloric acid hydrogen peroxide (HPM), sulfuric acid hydrogen peroxide (SPM) or the like is preferable.

  Next, as shown in FIG. 20C, the resist mask 138 is removed. Thereafter, as described in the first embodiment, plasma nitridation can be performed. Subsequently, a second cap film 109 containing an element having an effect of reducing eWF such as a LaO film is formed. Subsequently, heat treatment for diffusing the second cap film 109 is performed. The heat treatment may be performed at a temperature of about 600 ° C to 850 ° C. However, as described in the first embodiment, the heat treatment temperature is preferably low. As a result, the portion of the high dielectric constant film 106 formed in the n-type semiconductor region 10B becomes the La diffusion high dielectric constant film 106b. In addition, an La diffusion region 108 a containing La is formed on the hard mask 108.

  Next, as shown in FIG. 21A, the unreacted second cap film 109 and La diffusion region 108a are removed by etching. The removal of the second cap film 109 and the La diffusion region 108a is set so as not to damage the high dielectric constant film 106. Wet etching using dilute hydrochloric acid, HPM or SPM is preferred.

  When removing the La diffusion region 108a, at least a part of the hard mask 108 other than the La diffusion region 108a may be removed. When the hard mask 108 is completely removed, at least a part of the diffusion prevention film 117 may be removed. However, when the diffusion prevention film 117 is completely removed, it is preferable that the first cap film 107 is sufficiently diffused into the high dielectric constant film 106 before the diffusion prevention film 117 is removed.

Next, as shown in FIG. 21B, a first electrode film 110 made of a TiN film having a thickness of about 10 nm to 20 nm is formed. The first electrode film 110 may be formed by an ALD method using titanium chloride (TiCl ₄ ) and ammonia (NH ₃ ). The film formation temperature may be about 400 ° C. to 600 ° C. The first electrode film 110 also functions as a metal barrier film for the side wall of the gate electrode. For this reason, it is generally preferable to form a film by an ALD method having a high step coverage. However, since the aspect ratio is not large, it can be formed by sputtering.

  Next, a second electrode film 139 made of tungsten (W), copper (Cu), an alloy containing these, or the like is formed so as to fill the opening. For the formation of the second electrode film 139, an ALD method, a CVD method, a PVD method, a plating method, or the like may be used. Subsequently, sintering may be performed at a temperature of about 350 ° C. to 500 ° C. in a hydrogen atmosphere. After that, the second electrode film 139, the first electrode film 110, the diffusion prevention film 117, the first cap film 107, and the high dielectric constant film 106 are formed using the interlayer insulating film 121 as a stopper by using a CMP method or the like. Etc., the part formed outside the opening is removed. As a result, a p-type MIS transistor having the first gate insulating film 106A and the first gate electrode 119A made of a high dielectric constant film in which Al is diffused is formed in the p-type semiconductor region 10A. In the n-type semiconductor region 10B, an n-type MIS transistor having a second gate insulating film 106B and a second gate electrode 119B made of a high dielectric constant film in which La is diffused is formed. Thereafter, contacts and wirings may be formed as necessary.

    The second cap film only needs to contain an element having an effect of reducing the eWF of the nMIS transistor, and may be another lanthanoid such as gadolinium (Gd) or an oxide film thereof instead of La. Alternatively, yttrium (Y), magnesium (Mg), or an oxide film thereof may be used.

  The first electrode film may be titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum carbide (TaC), or hafnium nitride (HfN) instead of TiN.

  INDUSTRIAL APPLICABILITY The semiconductor device and the method for manufacturing the semiconductor device according to the present invention can improve the characteristics of both the p-type MIS transistor and the n-type MIS transistor, and are useful as a semiconductor device having a complementary MIS transistor and a method for manufacturing the semiconductor device. It is.

10A p-type semiconductor region 10B n-type semiconductor region 101 semiconductor substrate 102 element isolation region 103 n well 104 p well 105 interface silicon oxide film 106 high dielectric constant film 106A first gate insulating film 106B second gate insulating film 106b La diffusion High dielectric constant film 107 First cap film 108 Hard mask 108a La diffusion region 109 Second cap film 110 First electrode film 111 Second electrode film 113 Side wall 114 Silicide layer 115A p-type extension diffusion layer 115B n-type Extension diffusion layer 116A p-type source / drain diffusion layer 116B n-type source / drain diffusion layer 117 Diffusion prevention film 119A First gate electrode 119B Second gate electrode 121 Interlayer insulation film 122 Contact plug 131 Surface protection film 132 Dummy gate 1 5 etching stopper film 136 interlayer insulating film 136a opening 138 resist mask 139 second electrode layer 301 semiconductor substrate 302 surface silicon oxide film 303 high dielectric constant film 304 cap film 305 electrode film

Claims (19)

a semiconductor substrate having a p-type semiconductor region and an n-type semiconductor region;
A first interfacial silicon oxide film formed on the p-type semiconductor region;
A first gate insulating film formed on the first interfacial silicon oxide film and containing aluminum;
A first gate electrode formed on the first gate insulating film;
A second interfacial silicon oxide film formed on the n-type semiconductor region;
A second gate insulating film formed on the second interfacial silicon oxide film and including an element having an effect of reducing an effective work function;
A second gate electrode formed on the second gate insulating film,
The aluminum concentration in the upper part of the first gate insulating film is 1 × 10 ²⁰ / cm ³ or more,
The aluminum concentration in the upper part of the second gate insulating film is 1 × 10 ¹⁹ / cm ³ or less,
The difference between the film thickness of the first interface silicon oxide film and the film thickness of the second interface silicon oxide film is 0.2 nm or less.   2. The semiconductor device according to claim 1, wherein the concentration of aluminum in the upper portion of the first gate insulating film is higher than the concentration of aluminum in the lower portion of the first gate insulating film.   The semiconductor device according to claim 1, further comprising a first cap film made of aluminum formed between the first gate insulating film and the first gate electrode.   The diffusion prevention film made of aluminum nitride formed between the first gate insulating film and the first gate electrode is further provided. Semiconductor device.   The first gate electrode and the second gate electrode each include a film made of titanium nitride, tantalum nitride, tantalum silicon nitride, titanium aluminum nitride, or hafnium nitride. The semiconductor device according to item.   The semiconductor device according to claim 1, wherein the second gate insulating film contains lanthanum, yttrium, magnesium, or gadolinium. The second gate insulating film includes lanthanum,
The semiconductor device according to claim 6, wherein a concentration of lanthanum at an interface between the second interface silicon oxide film and the semiconductor substrate is 1.5 atomic% or less.   The semiconductor device according to claim 1, wherein the high dielectric constant film is a film containing hafnium or a film containing zirconium. Further comprising an interlayer insulating film formed on the semiconductor substrate,
The interlayer insulating film has a first opening that exposes the p-type semiconductor region, and a second opening that exposes the n-type semiconductor region,
The first gate insulating film is formed so as to cover a side surface of the first opening and a portion exposed from the first opening of the p-type semiconductor region,
2. The second gate insulating film is formed to cover a side surface of the second opening and a portion exposed from the second opening of the n-type semiconductor region. The semiconductor device of any one of -8. An interfacial silicon oxide film, a high dielectric constant film, a first cap film made of aluminum, a diffusion barrier film made of aluminum nitride, and a hard mask are sequentially formed on a semiconductor substrate having a p-type semiconductor region and an n-type semiconductor region. Step (a);
After the step (a), a step (b) of removing a portion formed on the n-type semiconductor region in the first cap film, the diffusion prevention film, and the hard mask;
A step (c) of forming a second cap film containing an element having an effect of reducing an effective work function on the semiconductor substrate after the step (b);
A step (d) of performing a heat treatment after the step (c);
A step (e) of forming an electrode film on the semiconductor substrate after the step (d);
After the step (e), the electrode film, the high dielectric constant film, and the interfacial silicon oxide film are patterned to form a first interfacial silicon oxide film and a first gate insulation on the n-type semiconductor region. Forming a film and a first gate electrode, and forming a second interface silicon oxide film, a first gate insulating film, and a second gate electrode on the p-type semiconductor region (f). A method for manufacturing a semiconductor device, comprising: The aluminum concentration in the upper part of the first gate insulating film is 1 × 10 ²⁰ / cm ³ or more,
The aluminum concentration in the upper part of the second gate insulating film is 1 × 10 ¹⁹ / cm ³ or less,
11. The method of manufacturing a semiconductor device according to claim 10, wherein the difference between the film thickness of the first interface silicon oxide film and the film thickness of the second interface silicon oxide film is 0.2 nm or less.   An aluminum diffusion step (f) for diffusing aluminum contained in the first cap film is further provided after the step (b) and before the step (e). Item 11. A method for manufacturing a semiconductor device according to Item 10.   13. The method according to claim 10, further comprising a step (h) of removing the second cap film after the step (d) and before the step (e). A method for manufacturing a semiconductor device according to claim 1.   14. The method according to claim 13, further comprising a step (i) of removing the hard mask in the p-type semiconductor region after the step (h) and before the step (e). The manufacturing method of the semiconductor device of description.   The method further comprises a step (j) of removing the diffusion barrier film in the p-type semiconductor region after the step (i) and before the step (e). 14. A method for manufacturing a semiconductor device according to 14.   16. The method of manufacturing a semiconductor device according to claim 10, wherein the second cap film contains lanthanum, yttrium, magnesium, or gadolinium. The second cap film includes lanthanum,
The method of manufacturing a semiconductor device according to claim 16, wherein in the step (d), heat treatment is performed at a temperature of 800 ° C. or lower.   The method for manufacturing a semiconductor device according to claim 10, wherein the high dielectric constant film is a film containing hafnium or a film containing zirconium. (I) forming a p-type source / drain diffusion layer in the p-type semiconductor region and forming an n-type source / drain diffusion layer in the n-type semiconductor region before the step (a);
Interlayer insulation having a first opening exposing the p-type semiconductor region and a second opening exposing the n-type semiconductor region after the step (i) and before the step (a). And (j) forming a film,
In the step (a), the high dielectric constant film is exposed to side surfaces of the first opening and the second opening, a portion of the p-type semiconductor region exposed from the first opening, and the n-type semiconductor region. The method of manufacturing a semiconductor device according to claim 10, wherein the semiconductor device is formed so as to cover a portion exposed from the second opening.

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