JP2006086511A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress an increase of a threshold voltage in a semiconductor device including a gate insulating film made of a high dielectric constant film and a gate electrode made of a polycrystal silicon film containing P-type impurities. <P>SOLUTION: A P-type MOSFET120 includes a semiconductor substrate (N well 102b), a gate insulating film formed on the semiconductor substrate and made of a high dielectric constant film 108 including a silicate compound containing a first element selected from a group consisting of Hf, Zr, and lanthanoid, and N; a gate electrode formed on the gate insulating film and made of a polycrystal silicon film 114 containing P-type impurities; and a stopper oxide film 110 formed between the gate insulating film and the gate electrode, whereby a reaction of the first element and the polycrystal silicon film 114 is stopped, and having a specific dielectric constant of 8 or more. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device including a gate insulating film made of a high dielectric constant film and a gate electrode made of a polycrystalline silicon film containing a P-type impurity.

  In recent years, use of a high dielectric constant film called a high-k film as a constituent material of a semiconductor device has begun to be studied. By using a high dielectric constant film as the gate insulating film of the MOSFET, even if the physical thickness of the gate insulating film is increased to some extent, the equivalent silicon oxide film thickness is reduced and is physically and structurally stable. A gate insulating film can be realized. For this reason, the MOS capacitance can be increased to improve the MOSFET characteristics, and the gate leakage current can be reduced as compared with the case where a conventional silicon oxide film is used.

In Patent Document 1, in a semiconductor device having at least a part of a structure in which an electrode made of Si or SiGe is formed on Si via a dielectric film, the derivative film is formed from the Si side from the first amorphous state. A semiconductor device characterized by comprising a quality oxide film, a crystalline oxide film, and a second amorphous oxide film is described. Here, it is described that the crystalline oxide film is formed by stacking one or more of ZrO ₂ , HfO ₂ , TiO ₂ , Ta ₂ O ₅ , BST, STO, and PZT. Further, it is described that the first amorphous oxide is a metal oxide containing SiO ₂ or Al ₂ O ₃ , and the second amorphous oxide is a metal oxide containing Al ₂ O _3. ing.

In Patent Document 1, when Si or SiGe is used as a gate electrode, if Si or SiGe is directly formed on a crystalline oxide film such as ZrO ₂ , the reducing atmosphere during the film formation acts on the grain boundaries of ZrO ₂ to form ZrO _{2. 2} has been partially reduced, resulting in an increase in leakage current. In Patent Document 1, in order to solve this problem, the amorphous metal oxide film such as _Al 2 _{O 3} formed on the ZrO _2, ZrO ₂ is directly in a reducing atmosphere at the time of Si or SiGe electrode formed It prevents contact and solves the above problems.

Non-Patent Document 4 discloses a structure in which an Al ₂ O ₃ cap layer is formed on Hf silicate.

By the way, it has been reported that the addition of nitrogen such as Hf silicate and Zr silicate makes an amorphous film made of these materials amorphous (for example, Non-Patent Document 1). When an amorphous film is used as the high dielectric constant film, there is no grain boundary as described above. Therefore, even if Si or SiGe is formed on the upper layer, the high dielectric constant film is formed by the reducing atmosphere during film formation. The phenomenon that the material to be reduced is reduced can be prevented. When using a high dielectric constant film made of such a material, the high dielectric constant film itself is amorphous, so it is necessary to further form an amorphous metal oxide film as described above on the high dielectric constant film. Will disappear.
JP 2002-314072 A Special table 2003-514382 gazette Masahiro Koike et al, “Effect on Hf-N Bond on Properties of Thermally Stable Amorphous HfSiON and Applicability of this Material to Sub-50nm Technology Node LSIs”, 2003 IEEE, 0-7803-7873-3 / 03 C. Hobbs et al, “Fermi Level Pinning at the PolySi / Metal Oxide Interface”, 2003 Symposium on VLSI Technology Digest of Technical Papers, 4-89114-035-6 / 03 GD Wilk et al, “High-k gate dielectrics: Current status and materials properties considerations”, Journal of Applied Physics Volume 89, Number 10, pp5243-5275, 2001 E. Cartier et al, “Systematic study of pFET Vt with Hf-based gate stacks with poly-Si and FUSI gates”, 2004 Symposium on VLSI Technology Digest o Technical Papers, pp44-45, 2004

However, in recent years, when a high dielectric constant material such as an HfSiON film is used as the gate insulating film, the threshold voltage Vth of the P-type MOSFET is significantly higher than when using SiO ₂ as the gate insulating film, It has been found that there is a new problem that the on-current is reduced. Recent research has shown that when the gate insulating film is composed of a high dielectric constant film and the gate electrode is composed of polycrystalline silicon, a phenomenon called Fermi Level Pinning occurs ( Non-patent document 2). Fermi level pinning is a level in which the metal constituting the high dielectric constant film diffuses into the polycrystalline silicon constituting the gate electrode in the vicinity of the gate insulating film side interface in the gate electrode, and is based on the bond between silicon and the above metal. It is thought to be caused by the formation of

  When the metal constituting the high dielectric constant film diffuses into the polycrystalline silicon of the gate electrode of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a depletion layer is generated in the polycrystalline silicon in the vicinity of the interface with the gate insulating film. Due to the influence of the depletion layer, a sufficient electric field is not applied to the gate insulating film even when a gate voltage is applied, and it is difficult to induce carriers in the channel region. As a result, there has been a problem that the threshold voltage increases and the variation of the threshold voltage increases.

  Such Fermi level pinning tends to occur particularly when Zr and Hf are used for the high dielectric constant film and a gate electrode made of polycrystalline silicon containing P-type impurities is used.

  The present invention has been made in view of such circumstances, and in a semiconductor device including a gate insulating film made of a high dielectric constant film and a gate electrode made of a polycrystalline silicon film containing a P-type impurity, It aims at providing the technique which suppresses the increase in a threshold voltage.

  In the process of studying countermeasures against the above-described problems, the present inventor has developed that the metal constituting the high dielectric constant film is polycrystalline between the high dielectric constant film and the gate electrode constituted by the polycrystalline silicon film. It was thought that the formation of a depletion layer in polycrystalline silicon can be suppressed by forming a film that prevents diffusion into silicon, and various materials suitable as a blocking film were studied.

  As a result, the present inventor uses an oxide film having a certain degree of blocking function and a large relative dielectric constant as the blocking film, so that the effect of lowering the EOT (equivalent oxide film thickness) is reduced without impairing the effect. The inventors have found that the metal constituting the dielectric film can be prevented from diffusing into the polycrystalline silicon, and have arrived at the present invention described below.

  According to the present invention, a semiconductor substrate, a first element selected from the group consisting of any one of Hf, Zr, and a lanthanoid element formed on the semiconductor substrate, and a high silicate compound including N are included. A gate insulating film made of a dielectric film, a gate electrode formed on the gate insulating film and made of a polycrystalline silicon film containing a P-type impurity, and formed between the gate insulating film and the gate electrode In addition, there is provided a semiconductor device characterized in that the reaction between the first element and the polycrystalline silicon film is inhibited, and a blocking oxide film having a relative dielectric constant of 8 or more is included.

  Here, the semiconductor device can be a P-type MOSFET. Further, the semiconductor device can be a CMOS (Complementary Metal Oxide Semiconductor) device including a P-type MOSFET and an N-type MOSFET. Lanthanoid elements include La (lanthanum), Ce (cerium), Pr (praseodymium), Nd (neodymium), Pm (promethium), Sm (samarium), Eu (europium), Gd (gadolinium), Tb (terbium), Dy. (Dysprosium), Ho (holmium), Er (erbium), Tm (thulium), Yb (ytterbium), Lu (lutetium).

  In the semiconductor device of the present invention, the high dielectric constant film can be amorphous. As described above, by adding nitrogen to the high dielectric constant film Hf silicate, Zr silicate, or the like, the high dielectric constant film made of these materials can be made amorphous. Thereby, the heat resistance of the high dielectric constant film can be improved and the leakage current can be suppressed.

Non-Patent Document 2 reports that Fermi level pinning occurs when a high dielectric constant film such as HfO ₂ is provided in contact with polycrystalline silicon. In particular, in the P-type MOSFET, the influence of the threshold voltage due to the influence of such Fermi level pinning becomes large.

  However, in the present invention, since the blocking oxide film is formed between the high dielectric constant film and the polycrystalline silicon film, the amount of diffusion of the metal constituting the high dielectric constant film into the polycrystalline silicon is reduced. Generation of a depletion layer in crystalline silicon can be suppressed. Thereby, the occurrence of Fermi level pinning can be reduced, an increase in the threshold voltage of the semiconductor device can be suppressed, and variations in the threshold voltage can be reduced.

  Further, since the oxide film having a relative dielectric constant of 8 or more is used as the blocking oxide film, the blocking oxide film can be formed without impairing the effect of lowering the EOT due to the use of the high dielectric constant film as the gate insulating film. Oxidation does not reduce the relative permittivity.

  In the semiconductor device of the present invention, the blocking oxide film can include an oxide of a second element selected from the group consisting of Al and Y.

Such a second element can be favorably used as a material for the blocking oxide film because it does not adversely react with the polycrystalline silicon film even when it is in contact with the polycrystalline silicon film. The blocking oxide film can be, for example, Al ₂ O ₃ (relative dielectric constant of about 8 to 10), Y ₂ O ₃ (relative dielectric constant of about 15), or a nitride thereof. Since these materials are amorphous, when the amorphous material as described above is used as the high dielectric constant film, the effect of suppressing the leakage current can be further enhanced.
In addition, by making the high dielectric constant film amorphous and the blocking oxide film amorphous, metal atoms in the high dielectric constant film are likely to occur when the high dielectric constant film is polycrystalline, through the grain boundary. Since the phenomenon of diffusion into the blocking oxide film can be suppressed, the blocking ability of metal atoms can be further increased.

  In the semiconductor device of the present invention, the blocking oxide film can be made of a material having a negative fixed charge.

  According to the present invention, a semiconductor substrate, a first element selected from the group consisting of any one of Hf, Zr, and a lanthanoid element formed on the semiconductor substrate, and a high silicate compound including N are included. A gate insulating film made of a dielectric film, a gate electrode formed on the gate insulating film and made of a polycrystalline silicon film containing a P-type impurity, and formed between the gate insulating film and the gate electrode In addition, a semiconductor device is provided that includes a blocking oxide film that is made of a material having a negative fixed charge and that has a relative dielectric constant of 8 or more.

  FIG. 4 is a schematic diagram showing an interface state when HfSiON is used as the high dielectric constant film and a polycrystalline silicon film containing a P-type impurity is formed in contact with the high dielectric constant film. FIG. 4B is an enlarged view of FIG. Here, Hf in the gate insulating film constituted by the high dielectric constant film reacts with Si in the gate electrode constituted by the polycrystalline silicon film to form an Hf-Si bond, and this bond generates an interface trap. is doing. Holes in the polycrystalline silicon film containing P-type impurities are trapped in this interface trap, positive interface trap charges are generated, and Vfb (flat band voltage) and Vth (threshold voltage) shift in the negative direction.

  As described above, by providing a blocking oxide film between the high dielectric constant film and the polycrystalline silicon film, the reaction between the first element and the polycrystalline silicon film can be blocked, and the amount of interface charge can be reduced. Can be reduced. Thereby, generation | occurrence | production of a depletion layer can be suppressed and generation | occurrence | production of Fermi level pinning can be reduced. Further, by forming the high dielectric constant film from a material having a negative fixed charge, it is possible to cancel the positive interface trap charge. Thereby, an increase in the threshold voltage of the semiconductor device can be more effectively suppressed, and variations can be reduced.

The Al ₂ O ₃ described above is also known to have a negative fixed charge (for example, Non-Patent Document 3, Patent Document 2 and the like), and it is more effective when the blocking oxide film is made of Al ₂ O _3. The effect of Fermi level pinning can be reduced.

  In the semiconductor device of the present invention, the ratio of the second element in the blocking oxide film to the first element in the gate insulating film can be 0.15 or more (molar ratio). Thereby, the barrier property of the blocking oxide film can be ensured.

  In the semiconductor device of the present invention, the ratio of the second element in the blocking oxide film to the first element in the gate insulating film can be 2 or less (molar ratio). Thereby, it is possible to secure the effect of lowering EOT due to the use of the high dielectric constant film as the gate insulating film. Further, even when an N-type MOSFET including a gate electrode composed of a polycrystalline silicon film containing a P-type impurity is formed at the same time as a P-type MOSFET including a gate electrode composed of a polycrystalline silicon film containing a P-type impurity, An increase in the threshold voltage of the P-type MOSFET can be suppressed without impairing the characteristics of the N-type MOSFET.

  In the semiconductor device of the present invention, the high dielectric constant film can be made of HfSiON. When the high dielectric constant film contains Hf, the influence of Fermi level pinning as described above becomes large. However, according to the present invention, since the blocking oxide film is provided between the high dielectric constant film and the polycrystalline silicon film, even when Hf is used as the material of the high dielectric constant film, the influence of phenyl level pinning Can be reduced. The high dielectric constant film can also be made of ZrSiON or lanthanoid nitride silicate.

  The semiconductor device of the present invention can further include a silicon oxide film provided between the semiconductor substrate and the gate insulating film. This silicon oxide film can also contain nitrogen.

  By providing the silicon oxide film between the semiconductor substrate and the high dielectric constant film, the metal in the high dielectric constant film can be prevented from diffusing into the semiconductor substrate.

  A semiconductor device according to the present invention is a high dielectric constant film formed on a semiconductor substrate and including a silicate compound including a first element selected from the group consisting of any of Hf, Zr, and a lanthanoid element, and N A second gate electrode formed of a polycrystalline silicon film containing an N-type impurity and in contact with a high dielectric constant film of the second gate insulating film; , May further be included.

  The semiconductor device of the present invention can be a CMOS device including an N-type MOSFET and a P-type MOSFET. Here, the P-type MOSFET can have a configuration in which a blocking oxide film is provided between the high dielectric constant film and the polycrystalline silicon film, and the N-type MOSFET has a high level without providing a blocking oxide film. A structure in which a polycrystalline silicon film is directly disposed on the dielectric constant film can be employed. Thereby, an increase in threshold voltage can be suppressed in the P-type MOSFET, and the characteristics of the N-type MOSFET 118 can be kept good.

  According to the present invention, an increase in threshold voltage can be suppressed in a semiconductor device including a gate insulating film formed of a high dielectric constant film and a gate electrode formed of a polycrystalline silicon film containing a P-type impurity. it can.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

  FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device 100 in the present embodiment. In the present embodiment, semiconductor device 100 includes a P-type MOSFET 120.

  The semiconductor device 100 includes a silicon substrate 102 provided with an N well 102b having an N type conductivity type, a pair of impurity diffusion regions 122 formed in the N well 102b, and a channel region (non-conducting region) provided therebetween. A silicon oxide film 106 formed on the channel region; a high dielectric constant film 108 formed on the silicon oxide film 106; a blocking oxide film 110 formed on the high dielectric constant film 108; Polycrystalline silicon film 114 formed on oxide film 110 and sidewall insulating film 116 are included. The silicon oxide film 106 and the high dielectric constant film 108 constitute a gate insulating film, and the polycrystalline silicon film 114 forms a gate electrode. The polycrystalline silicon film 114 is doped with a P-type impurity such as B (boron). The P-type MOSFET 120 is configured by the above elements.

  The high dielectric constant film 108 is a film having a relative dielectric constant higher than that of silicon oxide, and a so-called high-k film can be used. The high dielectric constant film 108 can be made of a material having a relative dielectric constant of 10 or more. Specifically, the high dielectric constant film 108 can be a silicate film containing one or more elements selected from the group consisting of Hf, Zr, and a lanthanoid element, and N (nitrogen). By using such a material, the relative dielectric constant of the high dielectric constant film 108 can be increased and good heat resistance can be imparted. Therefore, it can contribute to size reduction and reliability improvement of the MOSFET.

  Here, the content of nitrogen in the high dielectric constant film 108 with respect to all elements constituting the high dielectric constant film 108 can be set to 5 atomic% or more. As a result, the high dielectric constant film 108 can be made amorphous, and leakage current can be suppressed. Further, the content of nitrogen in the high dielectric constant film 108 with respect to all elements constituting the high dielectric constant film 108 can be set to 20 atomic% or less. Thereby, the interface characteristics can be kept good.

The blocking oxide film 110 has a function of blocking the metal element contained in the high dielectric constant film 108 from diffusing into the polycrystalline silicon film 114. Further, the blocking oxide film 110 can be an oxide film made of a material having a relative dielectric constant of 8 or more. Specifically, the blocking oxide film 110 may include an oxide or oxynitride of an element selected from the group consisting of Al and Y. The blocking oxide film 110 can be, for example, an Al ₂ O ₃ film or a Y ₂ O ₃ film. Films made of these materials have a high relative dielectric constant and are oxidized, so that the film quality is not changed by oxidation and the relative dielectric constant does not decrease. Therefore, the metal element contained in the high dielectric constant film 108 diffuses into the polycrystalline silicon film 114 without impairing the effect of lowering the EOT by using the high dielectric constant film 108 as described above as the gate insulating film. Can be prevented. In addition, since these materials are amorphous, when an amorphous material is used as the high dielectric constant film 108, the effect of suppressing leakage current can be further enhanced. Further, as the blocking oxide film 110, a film containing nitrogen can be used. When a film containing nitrogen is used as the blocking oxide film 110, the ability to block the diffusion of metal atoms can be further enhanced. In this case, the content of nitrogen in the blocking oxide film 110 with respect to all elements constituting the blocking oxide film 110 in the blocking oxide film 110 can be set to 5 atomic% or more.

  The thickness of the blocking oxide film 110 can be set to 0.2 nm or more, for example. Thereby, the function of preventing the metal element contained in the high dielectric constant film 108 from diffusing into the polycrystalline silicon film 114 can be made sufficient. Further, the thickness of the blocking oxide film 110 can be set to 1 nm or less, for example. Thus, the metal element contained in the high dielectric constant film 108 diffuses into the polycrystalline silicon film 114 without impairing the effect of lowering the EOT due to the use of the high dielectric constant film 108 as described above as the gate insulating film. It is possible to ensure the function of preventing the failure. Here, the term “film thickness” simply refers to the film thickness in the stacking direction.

  The blocking oxide film 110 can be made of a material having a negative fixed charge. As described above with reference to FIG. 4, when the metal element in the high dielectric constant film 108 diffuses into the polycrystalline silicon film 114, a bond between the metal element and Si in the polycrystalline silicon film 114 is formed. This bond generates an interface trap, and holes in the polycrystalline silicon film containing the P-type impurity are captured by the interface trap, and a positive interface charge is generated. When the blocking oxide film 110 has a negative fixed charge, the negative fixed charge can cancel the positive interface charge, and the increase in the threshold voltage of the P-type MOSFET 120 can be more effectively suppressed. .

Al ₂ O ₃ is known to have a negative fixed charge, and by using Al ₂ O ₃ as the blocking oxide film 110, the metal element contained in the above-described high dielectric constant film 108 is a polycrystalline silicon film. Along with the function of preventing diffusion to 114, it is also possible to cancel the positive interface charge, and the rise in the threshold voltage of the P-type MOSFET 120 can be more effectively suppressed.

  When a material including the above-described element is used as the material constituting the high dielectric constant film 108, the P-type MOSFET 120 may have a problem that the threshold voltage increases due to the influence of Fermi level pinning. According to the configuration of semiconductor device 100 in the present embodiment, since blocking oxide film 110 is provided between high dielectric constant film 108 and polycrystalline silicon film 114 of P-type MOSFET 120, the influence of Fermi level pinning is reduced. be able to.

  2 and 3 are process cross-sectional views showing an example of a manufacturing procedure of the semiconductor device 100 having the configuration shown in FIG. Here, a procedure for manufacturing a CMOS device by simultaneously forming an N-type MOSFET 118 together with a P-type MOSFET 120 will be described.

  First, after forming an element isolation region (STI) 104 by STI (Shallow Trench Isolation) on a silicon substrate 102 by a known technique, P-type impurities are ion-implanted, and P-wells 102a and N-type impurities are ion-implanted. N wells 102b are respectively formed (FIG. 2A). The element isolation region 104 may be formed by another known method such as a LOCOS method. The element isolation region 104 separates the P well 102a and the N well 102b.

  Subsequently, channel regions are respectively formed in the P well 102a and the N well 102b by a known technique. A punch-through stopper region can also be formed by ion implantation of N-type impurities and P-type impurities below the channel regions of the P well 102a and the N well 102b. By forming such a punch-through stopper region, the short channel effect can be suppressed.

  Subsequently, a silicon oxide film 106 (for example, a film thickness of about 1 nm to 2 nm) is formed on the surface of the silicon substrate 102 (FIG. 2B). The silicon oxide film 106 can be formed, for example, by thermally oxidizing the surface of the silicon substrate 102. As conditions for thermal oxidation, for example, a processing temperature of 900 ° C. and a processing time of about 40 seconds to 50 seconds can be used.

Subsequently, a high dielectric constant film 108 (for example, a film thickness of about 2 nm) is formed on the silicon oxide film 106 (FIG. 2C). The high dielectric constant film 108 can be formed by a CVD method, an ALD method (atomic layer deposition method), a sputtering method, or the like. In the present embodiment, HfSiON is employed as the high dielectric constant film 108. This film formation is first performed using an organic hafnium source gas, an oxidizing gas, and a silicon-containing gas. Here, for example, oxygen can be used as the oxidizing gas, and monosilane (SiH ₄ ) can be used as the silicon-containing gas. Thereby, hafnium silicate (HfSiO) is formed.

  Thereafter, annealing is performed using a nitrogen-containing gas such as ammonia. The conditions are a processing temperature of 900 to 1000 ° C. and a processing time of 40 seconds. By performing annealing, nitrogen is introduced into the hafnium silicate and the high dielectric constant film 108 is made amorphous. Nitrogen can also be introduced by nitrogen plasma treatment. Also, HfSiON can be manufactured by introducing nitrogen when forming the high dielectric constant film 108 such as during sputtering. Furthermore, HfSiON can also be manufactured by performing an oxidation process after forming HfSiN by reactive sputtering.

Subsequently, a blocking oxide film 110 (for example, a film thickness of about 0.7 nm) is formed on the high dielectric constant film 108 (FIG. 2D). The blocking oxide film 110 can be formed by CVD, ALD, or sputtering. In the present embodiment, Al ₂ O ₃ is employed as the blocking oxide film 110. This film formation is performed by an ALD method using Al (CH ₃ ) ₃ and an oxidizing gas such as O ₃ or H ₂ O as raw materials.

  Here, in the blocking oxide film 110, the ratio of Al or Y contained in the blocking oxide film 110 to Hf, Zr, and lanthanoid elements contained in the high dielectric constant film 108 is 0.15 or more, more preferably 0. .5 or more (molar ratio). Thereby, the barrier property of the blocking oxide film 110 can be ensured. Further, in the blocking oxide film 110, the ratio of Al or Y contained in the blocking oxide film 110 to Hf, Zr, and lanthanoid elements contained in the high dielectric constant film 108 is 2 or less (molar ratio). can do. Thereby, the characteristics of the N-type MOSFET 118 can also be kept good.

Also, if a blocking oxide layer 110 using _{Al 2 O 3, Al 2 O} 3 may be nitrided. By using a nitrided oxide film obtained by nitriding Al ₂ O ₃ , the reliability can be further improved without increasing the EOT and the threshold voltage.

  Thereafter, a polycrystalline silicon film 114 is formed on the blocking oxide film 110 (FIG. 3E). Next, N-type impurities are ion-implanted into the polycrystalline silicon film 114 formed on the P well 102a, and P-type impurities are ion-implanted into the polycrystalline silicon film 114 formed on the N well 102b.

  Subsequently, the silicon oxide film 106, the high dielectric constant film 108, the blocking oxide film 110, and the polycrystalline silicon film 114 are selectively dry etched and processed into the shape of the gate electrode (FIG. 3F). Next, a sidewall insulating film 115 is formed on the sidewalls of the silicon oxide film 106, the high dielectric constant film 108, the blocking oxide film 110, and the polycrystalline silicon film 114 on the P well 102a. Further, a sidewall insulating film 116 is formed on the sidewalls of the silicon oxide film 106, the high dielectric constant film 108, the blocking oxide film 110, and the polycrystalline silicon film 114 on the N well 102b. The sidewall insulating film 115 and the sidewall insulating film 116 can be formed by anisotropic etching using, for example, a fluorocarbon gas.

  Subsequently, source / drain extension regions, which are electrical connection portions between the channel region and an impurity diffusion region described later, are formed on the surfaces of the P well 102a and the N well 102b, respectively.

  Next, impurity diffusion regions 121 are formed on the P well 102a by doping the surface layer of the P well 102a with N-type impurities such as P and As using the gate electrode and the sidewall insulating film 115 as a mask. On the N well 102b, using the gate electrode and the sidewall insulating film 116 as a mask, the surface layer of the N well 102b is doped with a P-type impurity such as B or Al to form an impurity diffusion region 122 (FIG. 3G). ). Thereby, a source region and a drain region are formed. Thereafter, the impurity is activated by performing a heat treatment, for example, at about 1000 ° C. in a non-oxidizing atmosphere. Through the above process, the semiconductor device 100 which is a CMOS device having the N-type MOSFET 118 and the P-type MOSFET 120 is formed.

  As shown in the present embodiment, by nitriding the high dielectric constant film 108, it is possible to prevent crystallization from occurring even if high-temperature heat treatment is performed in activation after ion implantation. The high dielectric constant film 108 can be kept in an amorphous state. As described above, when the blocking oxide film 110 is formed on the high dielectric constant film 108 by keeping the high dielectric constant film 108 in an amorphous state, the high dielectric constant film 108 is made of metal compared to the case where the high dielectric constant film 108 is polycrystalline. The ability to prevent diffusion of atoms can be increased. In particular, by using the amorphous high dielectric constant film 108 and the amorphous blocking oxide film 110, the ability of preventing diffusion of metal atoms can be further enhanced.

  As described above, according to the semiconductor device 100 in the present embodiment, since the blocking oxide film 110 is provided between the high dielectric constant film 108 and the polycrystalline silicon film 114 of the P-type MOSFET 120, the influence of Fermi level pinning. Can be reduced. Thereby, an increase in the threshold voltage of the P-type MOSFET 120 can be suppressed, and variations in the threshold voltage can be reduced.

(Example 1)
In the P-type MOSFET 120 having the same configuration as shown in FIG. 1, as a blocking film provided between the high dielectric constant film 108 and the polycrystalline silicon film 114, (i) a SiO ₂ film, (ii) a SiN film, ( iii) Regarding the Al ₂ O ₃ film, whether or not the metal constituting the high dielectric constant film has a function of preventing the metal from diffusing into the polycrystalline silicon (hereinafter referred to as “blocking function”) was examined.

The results are shown below.
(I) SiO ₂ : In order to satisfy the blocking function to a certain degree of effectiveness, the film thickness of the SiO ₂ film must be considerably increased, and since the relative dielectric constant of the SiO ₂ film is low, it is high as a gate insulating film. It has been found that the effect of lowering the EOT (SiO ₂ equivalent film thickness) due to the use of the dielectric constant film is impaired.

(Ii) SiN film: There was a blocking function to some extent. However, SiN film is higher relative dielectric constant than SiO ₂ film, when in contact with the high dielectric constant film, is oxidized by oxygen contained therein, it becomes a SiO ₂ film. For this reason, it has been found that the relative dielectric constant is lowered during operation, and the effect of lowering EOT due to the use of a high dielectric constant film as the gate insulating film is impaired.

(Iii) Al ₂ O ₃ film: The relative dielectric constant was high and the blocking function was larger than that of the SiO ₂ film. For this reason, even when the film thickness satisfies the blocking function to a certain degree of effectiveness, the effect of lowering EOT due to the use of the high dielectric constant film as the gate insulating film is not impaired.

(Example 2)
A P-type MOSFET 120 having the same configuration as that shown in FIG. 1 was manufactured. Here, the sidewall insulating film 116 was not formed.
A silicon oxide film 106 with a thickness of about 1.0-2.0 nm was formed on the silicon substrate 102, and a HfSiO film was formed thereon with a thickness of about 1-2.5 nm by CVD. Subsequently, this structure was plasma-nitrided to form an HfSiON film (high dielectric constant film 108). Next, an Al ₂ O ₃ film (blocking oxide film 110) was formed on the high dielectric constant film 108. A polysilicon layer (polycrystalline silicon film 114) was grown on the blocking oxide film 110, and a gate electrode was formed by patterning. Subsequently, ion implantation was performed to form a source and a drain (impurity diffusion region 122). Thereafter, the activation process was annealed at about 1000 ° C. to form a transistor structure.
Here, a transistor structure in which the film thickness of the Al ₂ O ₃ film (blocking oxide film 110) was 2 mm, 4 mm, or 8 mm was created.

(Comparative Example 1: Ref. 1)
A silicon oxide film was formed on a silicon substrate, a polysilicon layer was grown thereon, and patterning was performed to form a gate electrode. Subsequently, ion implantation was performed to form a source and a drain. Thereafter, the activation process was annealed at about 1000 ° C. to form a transistor structure.

(Comparative Example 2: Ref. 2)
A silicon oxide film having a thickness of about 1.6 to 2.5 nm was formed on a silicon substrate, and a HfSiO film was formed thereon by a CVD method to a thickness of about 1 to 2.5 nm. Subsequently, this structure was plasma-nitrided to form an HfSiON film. Next, a polysilicon layer was grown thereon and patterned to form a gate electrode. Subsequently, ion implantation was performed to form a source and a drain. Thereafter, the activation process was annealed at about 1000 ° C. to form a transistor structure.

(Comparative Example 3)
A silicon oxide film having a thickness of about 1.6 to 2.5 nm was formed on a silicon substrate, and a HfSiO film was formed thereon by a CVD method to a thickness of about 1 to 2.5 nm. Thereafter, an Al ₂ O ₃ film was formed thereon without performing plasma nitridation. A polysilicon layer was grown on the Al ₂ O ₃ film and patterned to form a gate electrode. Subsequently, ion implantation was performed to form a source and a drain. Thereafter, the activation process was annealed at about 1000 ° C. to form a transistor structure.

FIG. 5 shows the relationship between the threshold voltage Vth and the Al ₂ O ₃ film thickness in the transistor structure created in Example 2.
Here, by introducing the Al ₂ O ₃ film into the transistor structure, the threshold voltage Vth increases as compared with the structure in which the Al ₂ O ₃ film of Comparative Example 2 is not introduced, and the Al ₂ O ₃ film By setting the film thickness to 2 mm, the minimum increase of 100 mV necessary for improving the transistor characteristics could be achieved. As the Al ₂ O ₃ film thickness increased, Vth increased.

FIG. 6 shows the relationship between the EOT and the Al ₂ O ₃ film thickness in the transistor structure created in Example 2.
The EOT increased as the thickness of the Al ₂ O ₃ film increased. When the thickness of the Al ₂ O ₃ film reached 8 mm, EOT increased by 2 mm (0.2 nm). Therefore, if the film thickness of Al ₂ O ₃ is thicker than this, the effect of using the high dielectric constant film is offset.

From the above results, an excellent transistor can be provided by improving the transistor characteristics and reducing EOT in the range of Al ₂ O ₃ film thickness of 2 to 8 mm (molar ratio: 0.16 to 1.6). It was shown that.

In the HfSiO film of Comparative Example 3, the long-term reliability life did not reach 10 years. This is presumably because the HfSiO film contains a crystalline part and this part becomes a leak path.
On the other hand, it was confirmed that the long-term reliability life of the HfSiON film of Example 2 was 10 years or longer. The HfSiON film of Example 2 was confirmed to exist in an amorphous state even after the activation treatment after the formation of the source and drain. This is considered to have improved reliability.

  The embodiments and examples of the present invention have been described above with reference to the drawings. However, these are examples of the present invention, and various configurations other than the above can be adopted.

  In the above example, the N-type MOSFET 118 also includes the blocking oxide film 110, but the N-type MOSFET 118 can be configured not to include the blocking oxide film 110. Thereby, in the P-type MOSFET 120, by providing the blocking oxide film 110, an increase in threshold voltage can be suppressed, and the characteristics of the N-type MOSFET 118 can be kept good.

1 is a cross-sectional view illustrating an example of a structure of a semiconductor device in an embodiment. It is process sectional drawing which shows an example of the manufacturing procedure of the semiconductor device in embodiment. It is process sectional drawing which shows an example of the manufacturing procedure of the semiconductor device in embodiment. FIG. 5 is a schematic diagram showing a state of an interface when HfSiON is used as a high dielectric constant film and a polycrystalline silicon film containing a P-type impurity is formed in contact with the high dielectric constant film. In transistor structure created in Example 2 is a diagram showing the relationship between the threshold voltage Vth and the Al ₂ O ₃ film thickness. 6 is a diagram showing the relationship between EOT and Al ₂ O ₃ film thickness in the transistor structure created in Example 2. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor device 102 Silicon substrate 102a P well 102b N well 104 Element isolation region 106 Silicon oxide film 108 High dielectric constant film 110 Blocking oxide film 114 Polycrystalline silicon film 116 Side wall insulating film 118 N-type MOSFET
120 P-type MOSFET
121 Impurity diffusion region 122 Impurity diffusion region

Claims (12)

A semiconductor substrate;
Gate insulation formed on the semiconductor substrate and formed of a high dielectric constant film including a silicate compound including a first element selected from the group consisting of any one of Hf, Zr, and a lanthanoid element, and N A membrane,
A gate electrode formed on the gate insulating film and made of a polycrystalline silicon film containing a P-type impurity;
A blocking oxide film formed between the gate insulating film and the gate electrode, blocking reaction between the first element and the polycrystalline silicon film, and having a relative dielectric constant of 8 or more;
A semiconductor device comprising: The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the blocking oxide film includes an oxide of a second element selected from the group consisting of Al and Y. The semiconductor device according to claim 1,
The semiconductor device, wherein the blocking oxide film is made of a material having a negative fixed charge. A semiconductor substrate;
Gate insulation formed on the semiconductor substrate and formed of a high dielectric constant film including a silicate compound including a first element selected from the group consisting of any one of Hf, Zr, and a lanthanoid element, and N A membrane,
A gate electrode formed on the gate insulating film and made of a polycrystalline silicon film containing a P-type impurity;
A blocking oxide film formed between the gate insulating film and the gate electrode, made of a material having a negative fixed charge, and having a relative dielectric constant of 8 or more;
A semiconductor device comprising: The semiconductor device according to claim 1,
The semiconductor device, wherein the blocking oxide film is made of Al ₂ O ₃ . The semiconductor device according to claim 5,
_{2. The} semiconductor device according to claim 1, wherein the blocking oxide film is made of a nitrided oxide film obtained by nitriding Al ₂ O ₃ . The semiconductor device according to claim 1,
A ratio of the second element in the blocking oxide film to the first element in the gate insulating film is 0.15 or more (molar ratio). The semiconductor device according to claim 1,
A semiconductor device, wherein a nitrogen content in the high dielectric constant film with respect to all elements constituting the high dielectric constant film in the gate insulating film is 5 atomic% or more. The semiconductor device according to claim 1,
The semiconductor device, wherein the high dielectric constant film is amorphous. The semiconductor device according to claim 1,
The semiconductor device, wherein the high dielectric constant film is made of HfSiON. The semiconductor device according to claim 1,
The semiconductor device further comprising a silicon oxide film provided between the semiconductor substrate and the gate insulating film. The semiconductor device according to claim 1,
A second dielectric layer formed on the semiconductor substrate and formed of a high dielectric constant film including a silicate compound including a first element selected from the group consisting of any one of Hf, Zr, and a lanthanoid element, and N. Gate insulating film of
A second gate electrode formed of a polycrystalline silicon film containing an N-type impurity and formed in contact with the high dielectric constant film of the second gate insulating film;
A semiconductor device further comprising:

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