CN105448684B - The method for forming grid - Google Patents
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- CN105448684B CN105448684B CN201410265004.2A CN201410265004A CN105448684B CN 105448684 B CN105448684 B CN 105448684B CN 201410265004 A CN201410265004 A CN 201410265004A CN 105448684 B CN105448684 B CN 105448684B
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Abstract
The present invention provides a kind of method for forming grid, including：Substrate is provided, makes substrate that there is first area and second area；Form pseudo- grid and interlayer dielectric layer；Form sacrifice layer；The pseudo- grid positioned at first area are removed, to form the first opening in the interlayer dielectric layer of first area；The first metal layer is being formed in the inter-level dielectric layer surface of the sacrificial layer surface of second area, first area and the first opening；Part the first metal layer and partial sacrificial layer are removed by cmp to form first grid.The beneficial effects of the present invention are, the pseudo- grid in second area are not exposed out during cmp, reduce the problem of cmp excessively removes the pseudo- grid in second area and forms depression, so as to which the surface of pseudo- grid and interlayer dielectric layer composition is more smooth, highly more consistent, the bridge joint problem that may occur when being subsequently formed grid is so advantageously reduced.
Description
Technical field
The present invention relates to field of semiconductor manufacture, and in particular to a kind of method for forming grid.
Background technology
CMOS (Complementary Metal Oxide Semiconductor, CMOS)
It is the elementary cell in modem logic circuit, includes PMOS and nmos device.
The PMOS and nmos device are by grid (Gate), p-type or N-type source region in the substrate of grid both sides
(Source) area or drain region (Drain) area and the passage (Channel) between source region and drain region are formed.
With the development of semiconductor technology, start to gradually adopt rear grid technique (gate-last) to form half in the prior art
The grid of conductor device, this technique are typically initially formed pseudo- grid (dummy gate), then form source region and drain region, then coating
Between dielectric layer, and remove pseudo- grid and be open with being formed in interlayer dielectric layer, then with constitutive promoter to form metal level.In shape
Into, it is necessary to remove unnecessary metal by flatening process, retain after metal level the metal that is located in the opening using as
The grid of semiconductor devices.
It is widely used at present during cmp (Chemical Mechanical Polishing, CMP) technique
One of flatening process.This technique is to reach one of method of global planarizartion, especially as the reduction of characteristic size, chemistry
The application of mechanical lapping is more extensive.For example, in the above-mentioned latter in grid technique, chemical machine can be used after forming metal level
Tool grinding removes unwanted partial metal layers.
But there is the problem of easily being bridged between other devices in the transistor formed in rear grid technique.
The content of the invention
The present invention is solved the problems, such as to be to provide a kind of method for forming grid, easily occurred with reducing grid with other devices
The problem of bridge joint.
To solve the above problems, the present invention provides a kind of method for forming grid, including：
Substrate is provided, the substrate has the secondth area for being used for first area and the second device for forming the first device
Domain；
Pseudo- grid are formed respectively on the substrate of the first area and second area；
Form interlayer dielectric layer on the substrate of the first area and second area, and make the surfaces of the pseudo- grid with
The surface of the interlayer dielectric layer flushes；
Sacrifice layer is formed on the pseudo- grid positioned at the interlayer dielectric layer of second area and positioned at second area；
The pseudo- grid positioned at first area are removed, to form the first opening in the interlayer dielectric layer of first area；
Formed in the inter-level dielectric layer surface of the sacrificial layer surface of second area, first area and the first opening
The first metal layer；
Part the first metal layer is removed by cmp, the first metal layer conduct in the described first opening
First grid；
After the first grid is formed, the sacrifice layer is removed.
Optionally, the step of forming sacrifice layer includes：Form the sacrifice layer of oxide or nitride material.
Optionally, the step of forming sacrifice layer includes：Form the sacrifice higher compared to the interlayer dielectric layer consistency
Layer.
Optionally, the step of forming sacrifice layer includes：Form sacrifice layer of the thickness in the range of 30~80 angstroms.
Optionally, the step of cmp includes：The grinding rate of the sacrifice layer is less than the first metal layer
Grinding rate.
Optionally, the step of cmp includes：The grinding rate of the sacrifice layer is no more than the first metal layer
/ 20th of grinding rate.
Optionally, after the step of forming sacrifice layer, remove before the step of pseudo- grid of first area, in addition to：
Hard mask is formed in the sacrificial layer surface；Remove the hard mask positioned at first area；
Remove includes positioned at the step of pseudo- grid of first area：Using remaining hard mask as etching mask, etching removes institute
Rheme is in the pseudo- grid of first area.
Optionally, the step of forming hard mask includes, and forms the hard mask of titanium nitride material.
Optionally, the step of forming hard mask includes, and forms hard mask of the thickness in the range of 50~100 angstroms.
Optionally, remove includes positioned at the step of hard mask of first area, and position is removed by the way of plasma etching
Hard mask in first area.
Optionally, the step of forming the first metal layer includes, and forms the first metal layer of aluminum.
Optionally, the step of forming the first metal layer also includes, before the first metal layer of aluminum is formed, described
Workfunction layers are formed in the bottom of first opening and side wall.
Optionally, include form pseudo- grid respectively on the substrate of the first area and second area the step of, formed
The pseudo- grid of polycrystalline silicon material.
Optionally, after the step of forming first grid, in addition to：
Remaining sacrifice layer is removed to expose the pseudo- grid being located in second area；
The pseudo- grid being located in second area are removed to be open to form second in the interlayer dielectric layer in second area；
In the described second opening and inter-level dielectric layer surface forms second metal layer；
By cmp to remove the second metal layer of inter-level dielectric layer surface, in the described second opening
Second metal layer is as second grid.
Optionally, the first area is used to form PMOS, and the second area is used to form NMOS；Or described
One region is used to form NMOS, and the second area is used to form PMOS.
Optionally, the step of removing part the first metal layer by cmp also includes：Part removes described sacrificial
Domestic animal layer.
Compared with prior art, technical scheme has advantages below：
Before the first metal layer is formed, formed in the interlayer dielectric layer positioned at second area and pseudo- grid surface sacrificial
Domestic animal layer, so when carrying out cmp to the first metal layer, cmp can be made not contact positioned at lining
Pseudo- grid in the second area of bottom, it can so reduce cmp and excessively remove the pseudo- grid in second area and form depression
The problem of, so as to which the surface of pseudo- grid and interlayer dielectric layer composition is more smooth, highly more consistent, after so advantageously reducing
Continue the bridge joint problem that may occur when forming grid.
Brief description of the drawings
Fig. 1 is the structural representation of cmos device in the prior art；
Fig. 2 to Figure 10 is the structural representation of each step in method one embodiment of the invention for forming grid.
Embodiment
In order to solve the problems, such as that transistor easily bridges between other devices, each step of grid technique after analysis,
When removing unwanted partial metal layers using cmp (Chemical Mechanical Polishing, CMP),
Because (quilt) grinding rate (RR) between different materials there may be larger difference, this can cause after chemical mechanical polishing,
Difference in height be present between different materials, so as to cause bridge joint the problem of.
Specifically, need to form the grid of PMOS and nmos device respectively with reference to figure 1, manufacture cmos device.To be initially formed
Exemplified by metal gates 3 in PMOS device, when forming the metal gates 3 of PMOS device by cmp, now
Pseudo- grid 4 to be removed are remained as in nmos device.
Although under normal conditions, to the cmp that the metal gates 3 of PMOS device are carried out detect it is described
Stop during interlayer dielectric layer 2, but metal gates are ground because cmp is significantly faster than that to the grinding rate of pseudo- grid 4
Speed is ground, therefore the speed that the pseudo- grid 4 in nmos device are removed will be significantly faster than that in PMOS device that metal gates 3 are gone
The speed removed, so cause the part interlayer dielectric layer 2 around the pseudo- grid 4 and pseudo- grid of nmos device surface easily produce it is recessed
Fall into, that is to say, that now the surface topography (topography) in the cmos device compares out-of-flatness, PMOS device region with
The difference in height increased between nmos device region be present.
When this difference in height can cause to be formed metal in the nmos device, because nmos device surface is less than PMOS devices
The surface in part region, the cmp carried out to nmos device metal level easily stop at the of a relatively high PMOS devices in surface
Part surface, the metal material in depression in nmos device region can not be ground to.These remaining metal materials are likely to
The metal gates of nmos device and the other devices of surrounding are caused to produce bridge joint phenomenon.
Therefore, in order to solve the above problems, the present invention provides a kind of method for forming grid, comprises the following steps：
Substrate is provided, makes the substrate that there is the secondth area for being used for first area and the second device for forming the first device
Domain；Pseudo- grid are formed respectively on the substrate of the first area and second area；In the first area and second area
Substrate on form interlayer dielectric layer, and the surface of the pseudo- grid is flushed with the surface of the interlayer dielectric layer；Positioned at
The interlayer dielectric layer in two regions and form sacrifice layer on the pseudo- grid of second area；The pseudo- grid positioned at first area are removed,
To form the first opening in the interlayer dielectric layer of first area；In sacrificial layer surface positioned at second area, first area
The first metal layer is formed in inter-level dielectric layer surface and the first opening；Part the first metal layer is removed by cmp
And partial sacrificial layer, the first metal layer in the described first opening is as first grid.
By above-mentioned steps, before the first metal layer is formed, in the interlayer dielectric layer positioned at second area and
Pseudo- grid surface forms sacrifice layer, so when carrying out cmp to the first metal layer, can grind chemical machinery
Mill does not contact the pseudo- grid in substrate second area, can so reduce cmp and excessively remove in second area
Pseudo- grid and the problem of form depression, so as to which surface that pseudo- grid and interlayer dielectric layer are formed is more smooth, highly more consistent, this
Sample advantageously reduces the bridge joint problem that may occur when being subsequently formed grid.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Referring to figs. 2 to the structural representation of each step in the embodiment of method one that Figure 10 is present invention formation grid.Need
It is noted that in order that accompanying drawing is more clear and succinct, only figure 2 illustrates substrate, Fig. 3 then eliminates institute into Figure 10
Substrate is stated, the present invention should not be limited with this.
With reference first to Fig. 2, there is provided substrate 10, wherein, the substrate 10 includes being used for the first area for forming the first device,
And for forming the second area of the second device.
In the present embodiment, the substrate 10 can be silicon substrate either silicon-on-insulator, but the present invention to this simultaneously
Do not limit.
The first area is the PMOS area for forming PMOS device, and accordingly, the second area is for shape
Into the NMOS area of nmos device.
It should be noted that in other embodiments of the invention, the first area can also be used to form NMOS
The NMOS area of device, the corresponding second area be the PMOS area for forming PMOS device, it is of the invention to this not
Limit.
In the present embodiment, side wall 120,220 and gate dielectric layer 210 and silicon are also formed with around the pseudo- grid 200
The structures such as compound layer 110.But these structures are this area common structure, the present invention is not repeated this, while is not also made
Any restriction.
Please continue to refer to Fig. 2, pseudo- grid 200 are formed respectively on the substrate of described NMOS area and PMOS area.
Specifically, the pseudo- grid 200 are used as material using polysilicon (poly), but the present invention is not limited equally this
It is fixed.
After this, interlayer dielectric layer 100 is formed on the substrate 10, and make the surfaces of the pseudo- grid 200 with it is described
The surface of interlayer dielectric layer 100 is flush, and (referred to pseudo- grid 200 are suitable with the height of the interlayer dielectric layer 100, can be with endless
It is complete consistent), that is to say, that pseudo- grid 200 expose from the interlayer dielectric layer 100.
In the present embodiment, can use for the sacrifice layer, removal rate is more in cmp
High material forms the interlayer dielectric layer 100, that is to say, that the removal rate of the sacrifice layer formed in subsequent step is more
It is low, and the removal rate of interlayer dielectric layer 100 is higher.
The reason for being chosen to remove speed relatively higher interlayer dielectric layer 100 is, subsequently through cmp
During removing the first metal layer being located in first area (for PMOS area in the present embodiment), in cmp
When drawing to an end, the interlayer dielectric layer 100 in PMOS area can expose, and now, speed be removed for interlayer dielectric layer 100
The lower sacrifice layer of rate advantageously ensures that sacrifice layer will not be completely removed in itself, and then plays nmos area below protection sacrifice layer
The effect that pseudo- grid in domain do not expose.
Specifically, the present embodiment can be used for the sacrifice layer, the lower material of consistency forms described
Interlayer dielectric layer 100.For example, the earth silicon material that some consistency are relatively low, with realize it is above-mentioned make sacrifice layer be not easy by
The purpose removed completely.But the present invention to this and is not construed as limiting.
With continued reference to Fig. 3, in the interlayer dielectric layer of the first area and second area and positioned at second area
Sacrifice layer 310 is sequentially formed on pseudo- grid, the sacrifice layer 310 is used to protect pseudo- grid in follow-up cmp step
200。
Specifically, the present embodiment is initially formed the first grid in first area, that is to say, that the sacrifice layer 310 is used
In in cmp to form the first grid during make positioned at second area (to be nmos device in the present embodiment
Region) in pseudo- grid 200 be not exposed during cmp.
Further, the grinding rate of sacrifice layer 310 is less than the grinding rate of the first metal layer, so subsequently leading to
When crossing cmp and forming the first grid, grinding is easier to stop on the sacrifice layer 310, that is to say, that
The sacrifice layer 310 is set to be not easy to be completely removed as far as possible, so that being located at second area (being NMOS area in the present embodiment)
In pseudo- grid 200 be not exposed.
Specifically, can make the grinding rate of sacrifice layer 310 for the grinding rate of the first metal layer 1/20th or
Person is lower, so further advantageously ensures that sacrifice layer 310 will not be removed when grinding the first metal layer.
In the present embodiment, the sacrifice layer 310 can be the sacrifice layer of oxide or nitride material, for example, described
Sacrifice layer 310 can be silica or silicon nitride.The grinding rate of the sacrifice layer 310 of this material is less than the first metal layer
Grinding rate, also, the sacrifice layer 310 of this material and interlayer dielectric layer 100 material (in the present embodiment for consistency compared with
Low earth silicon material) it is closer to, be advantageous to the progress of follow-up cmp step.The specific material present invention
Do not limit, can be selected according to actual conditions.
As it was noted above, the sacrifice layer 310 can use the material higher compared to the consistency of interlayer dielectric layer 100.Cause
The higher sacrifice layer 310 of density means that grinding rate is relatively low relative to interlayer dielectric layer 100, so in follow-up chemical machinery
In the step of grinding, the sacrifice layer 310 is not easily removed, and further ensures the pseudo- grid 200 in second area in chemistry
Do not expose in mechanical polishing step.
In practical operation, the higher sacrifice layer of described consistency can be formed by way of chemical vapor deposition
310, specifically, pre-reaction material when can be by changing chemical vapor deposition adjusts the cause of the sacrifice layer 310 of formation
Density.
On the one hand, if the thickness of sacrifice layer 310 is too small, it is difficult to ensure that the pseudo- grid 200 in NMOS area do not reveal, so as to nothing
Method plays a good protection；On the other hand, if the thickness of the sacrifice layer 310 is excessive, subsequently need to remove the sacrifice
It is cumbersome when layer 310 is further to remove the pseudo- grid 200 in NMOS area, or easily cause NMOS area and PMOS area
The excessive progress for influenceing follow-up cmp of difference in height.Therefore, in the present embodiment, the sacrifice layer to be formed can be made
310 thickness is in the range of 30~80 angstroms.
Used it should be understood that this numerical value is only the present embodiment, during practical operation, the sacrifice layer 310
Thickness should be adjusted according to actual conditions, and the present invention is not limited this.
In the present embodiment, hard mask 320 is also formed with the sacrifice layer 310, the hard mask 320 is used for rear
When continuous etching is located at the pseudo- grid 200 in first area, protection is located at the impregnable etching mask of sacrifice layer in second area.
In the present embodiment, the hard mask 320 is formed as material using titanium nitride but the present invention is not limited this,
Other materials can also be as the material of the hard mask 320 such as tantalum nitride.
Further, in order that the hard mask 320 formed plays a part of above-mentioned etching mask enough, while it is unlikely to again
It is blocked up and influence whole manufacturing process, in the present embodiment, form hard mask 320 of the thickness in the range of 50~100 angstroms.
With reference to figure 4, the photoresist 50 with figure is formed in the hard mask 320 positioned at second area, then with
The photoresist 50 of figure is etching mask, the hard mask 320 being located in first area and sacrifice layer 310 is removed, by first
Pseudo- grid 200 in region expose.
Specifically, in the present embodiment, the hard mask 320 and sacrificial can be removed by the way of plasma etching
Domestic animal layer 310.For example, first using fluorine-containing or chloride gas come the hard mask 320 of etch nitride titanium material, then using fluorine-containing
Gas etching sacrifice layer 310.
During practical operation, etching can be adjusted according to actual conditions and sacrifice layer 310, the specific material of hard mask 320
Method and etching agent, the present invention are not limited this.
With reference to figure 5, using remaining photoresist 50 and hard mask 320 as etching mask, remove and be located in first area
Pseudo- grid 200, and then in the interlayer dielectric layer 100 in first area formed first opening 201.First opening
201 are used to fill metal level in subsequent steps to form first grid.
It should be noted that during the first area puppet grid 200 are etched, the photoresist 50 has been possible to
It is complete to remove, after photoresist 50 is removed, etching mask of the hard mask 320 as second area.Situation about being shown in Fig. 5
Situation about not being completely removed for the photoresist, now the etching mask of second area is still photoresist 50.
In the present embodiment, it is further comprising the steps of before the first metal layer is subsequently formed：
Work-function layer (not shown) is formed in the first opening 201 of formation, the work-function layer is whole for adjusting
The work function size of individual PMOS device.
It should be understood that whether the present invention is for necessarily be formed the work-function layer and do not limit.Meanwhile work(
Function layer sheet is as prior art, and the present invention is not repeated this, while also the material to work-function layer, forming method etc. are not made
Limit.
With reference to figure 6, in the first opening 201, photoresist 50 and first area, the interlayer dielectric layer 100 of second area
Upper covering the first metal layer 401, the first metal layer 401 are used for the first grid for forming first area PMOS device.
In the present embodiment, the first metal layer 401 is aluminum metal layer.But the present invention is not limited this, for example,
Other metals such as tungsten are also used as the material of the first metal layer 401.
With reference to figure 7, by cmp to remove part the first metal layer 401, retain in the first opening
The first metal layer, to form the first grid 400 in PMOS device region.
In the present embodiment, after the first grid 400 is formed, the sacrifice layer 310 is partially removed, still, this
Invent the pseudo- grid 200 for being intended to not allow in second area to expose, do not limited for whether the sacrifice layer 310 is partially removed,
In other embodiments of the invention, the sacrifice layer 310 is also possible to not be removed, or the amount being removed can be neglected substantially
Disregard.
Because the material of the material and the interlayer dielectric layer 100 of the sacrifice layer 310 is closer to, and sacrifice layer 310
Thickness it is also relatively small (in the present embodiment be 30~80 angstroms), so, during cmp, the chemical machine
Tool grinding can with the sacrifice layer 310 be polish stop layer in the nmos device region formed with sacrifice layer 310, and not have
Have in the PMOS device region of sacrifice layer 310 with interlayer dielectric layer 100 for polish stop layer.
During cmp, due to having the stop of the sacrifice layer 310, the cmp of this step
The pseudo- grid 200 in second area can't be contacted, so avoiding the part of pseudo- grid 200 and surrounding in the prior art as best one can
The problem of interlayer dielectric layer 100 is excessively removed.
After this, it is necessary to remove the pseudo- grid in nmos device region, the present embodiment removes the puppet in nmos device region
Before grid, in addition to remaining sacrifice layer 310 is removed to expose the pseudo- grid 200 being located in second area.Due to the present embodiment
In the thickness of sacrifice layer 310 in the range of 30~80 angstroms, sacrifice layer 310 is unlikely to blocked up, and then does not interfere with this step substantially
Rapid progress.
Specifically, in the present embodiment, remaining sacrifice layer 310 can be performed etching using fluorine-containing gas, still
The present invention is to this and is not construed as limiting.
With reference to figure 8, the pseudo- grid 200 being located in second area are removed, with the interlayer dielectric layer 100 in second area
Form the second opening 202.Second opening 202 is used for the second grid for forming nmos device.
With reference to figure 9, in the described second opening 202 and in the first area and the inter-level dielectric of second area
100 surface of layer form second metal layer 402.
In the present embodiment, the second metal layer 402 can use and the identical aluminium conduct of the first metal layer 401
Material.But likewise, the present invention is not limited this.
With reference to figure 10, by cmp to remove part second metal layer 402, retain positioned at the second opening 202
In second metal layer 402, with formed be located at second area in second grid 403.Now, this step chemical mechanical lapping can
Stop grinding during detecting the material of interlayer dielectric layer 100 in milling apparatus.I other words this step chemical mechanical polishing step
Polish stop layer is used as using the interlayer dielectric layer 100.
Because the interlayer dielectric layer 100 in first area and second area is mutually flush substantially, so positioned at the
The second metal layer material on the surface of interlayer dielectric layer 100 can be more thoroughly milled away in two regions, will not be occurred substantially
Cause metal material to remove halfway problem because the surface of interlayer dielectric layer 100 carries depression in the prior art, and then also solve
Determine because of the bridge joint problem that the surface of interlayer dielectric layer 100 carries the metal material of residual and may trigger.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (16)
- A kind of 1. method for forming grid, it is characterised in that including：Substrate is provided, the substrate has the second area for being used for first area and the second device for forming the first device；Pseudo- grid are formed respectively on the substrate of the first area and second area；Form interlayer dielectric layer on the substrate of the first area and second area, and make the surfaces of the pseudo- grid with it is described The surface of interlayer dielectric layer flushes；Sacrifice layer is formed on the pseudo- grid positioned at the interlayer dielectric layer of second area and positioned at second area；The pseudo- grid positioned at first area are removed, to form the first opening in the interlayer dielectric layer of first area；First is being formed in the inter-level dielectric layer surface of the sacrificial layer surface of second area, first area and the first opening Metal level；Part the first metal layer is removed by cmp, the first metal layer in the described first opening is as first Grid；After the first grid is formed, the sacrifice layer is removed.
- 2. the method for grid is formed as claimed in claim 1, it is characterised in that the step of forming sacrifice layer includes：Form oxygen The sacrifice layer of compound or nitride material.
- 3. the method for grid is formed as claimed in claim 1, it is characterised in that the step of forming sacrifice layer includes：Form phase The sacrifice layer higher compared with the interlayer dielectric layer consistency.
- 4. the method for grid is formed as claimed in claim 1, it is characterised in that the step of forming sacrifice layer includes：Formed thick The sacrifice layer spent in the range of 30~80 angstroms.
- 5. the method for grid is formed as claimed in claim 1, it is characterised in that include the step of cmp：It is described The grinding rate of sacrifice layer is less than the grinding rate of the first metal layer.
- 6. the method for grid is formed as claimed in claim 1, it is characterised in that include the step of cmp：It is described / 20th of the grinding rate of sacrifice layer no more than the grinding rate of the first metal layer.
- 7. the method for grid is formed as claimed in claim 1, it is characterised in thatAfter the step of forming sacrifice layer, remove before the step of pseudo- grid of first area, in addition to：Hard mask is formed in the sacrificial layer surface；Remove the hard mask positioned at first area；Remove includes positioned at the step of pseudo- grid of first area：Using remaining hard mask as etching mask, etching removes institute's rheme Pseudo- grid in first area.
- 8. the method for grid is formed as claimed in claim 7, it is characterised in that the step of forming hard mask includes, and forms nitrogen Change the hard mask of titanium material.
- 9. the method for grid is formed as claimed in claim 7 or 8, it is characterised in that the step of forming hard mask includes, and is formed Hard mask of the thickness in the range of 50~100 angstroms.
- 10. the method for grid is formed as claimed in claim 7 or 8, it is characterised in that remove the hard mask positioned at first area The step of include, the hard mask positioned at first area is removed by the way of plasma etching.
- 11. the method for grid is formed as claimed in claim 1, it is characterised in that the step of forming the first metal layer includes, shape Into the first metal layer of aluminum.
- 12. the method for grid is formed as claimed in claim 11, it is characterised in that the step of forming the first metal layer is also wrapped Include, before the first metal layer of aluminum is formed, workfunction layers are formed on the bottom of the described first opening and side wall.
- 13. the method for grid is formed as claimed in claim 1, it is characterised in that in the first area and second area Substrate on the step of forming pseudo- grid respectively include, form the pseudo- grid of polycrystalline silicon material.
- 14. the method for grid is formed as claimed in claim 1, it is characterised in that after the step of forming first grid, also wrap Include：Remaining sacrifice layer is removed to expose the pseudo- grid being located in second area；The pseudo- grid being located in second area are removed to be open to form second in the interlayer dielectric layer in second area；In the described second opening and inter-level dielectric layer surface forms second metal layer；By cmp to remove the second metal layer of inter-level dielectric layer surface, second in the described second opening Metal level is as second grid.
- 15. the method for grid is formed as claimed in claim 1, it is characterised in that the first area is used to form PMOS, institute Second area is stated to be used to form NMOS；Or the first area is used to form NMOS, the second area is used to be formed PMOS。
- 16. the method for grid is formed as claimed in claim 1, it is characterised in thatThe step of removing part the first metal layer by cmp also includes：Part removes the sacrifice layer.
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| CN111900088B (en) * | 2019-05-05 | 2024-03-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
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| CN101714527A (en) * | 2008-10-06 | 2010-05-26 | 台湾积体电路制造股份有限公司 | Method for manufacturing semiconductor element |
| CN102969237A (en) * | 2011-08-31 | 2013-03-13 | 中芯国际集成电路制造(上海)有限公司 | Method for forming grid electrode and method for flattening interlayer medium layer |
| CN103094082A (en) * | 2011-10-31 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Method to manufacture semi-conductor device |
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