CN109767987A - A kind of post tensioned unbonded prestressed concrete forming method - Google Patents
A kind of post tensioned unbonded prestressed concrete forming method Download PDFInfo
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- CN109767987A CN109767987A CN201910078653.4A CN201910078653A CN109767987A CN 109767987 A CN109767987 A CN 109767987A CN 201910078653 A CN201910078653 A CN 201910078653A CN 109767987 A CN109767987 A CN 109767987A
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Abstract
The present invention provides a kind of post tensioned unbonded prestressed concrete forming method, grid is formed on the substrate and covers the interlayer dielectric layer of grid, anti-reflecting layer is coated in inter-level dielectric layer surface, and until etching anti-reflecting layer to the interlayer dielectric layer for exposing top portions of gates, the interlayer dielectric layer thickness for being etched to top portions of gates to interlayer dielectric layer is suitable with the thickness of dielectric layers on source-drain electrode, removes anti-reflecting layer later；Until carrying out being ground to top portions of gates exposing to interlayer dielectric layer again；Etching grid forms gate recess, deposits gate dielectric layer and filling metal gate material in groove later, and grind the metal gates for forming surfacing.The present invention is by only performing etching the dielectric layer on top portions of gates, reduce the difference in height of dielectric layer and dielectric layer on source-drain electrode on top portions of gates, after chemical mechanical grinding, improve the flatness in silicon wafer, reduce aluminium remaining risk on dielectric layer, while also reducing milling time and reducing grinding consumptive material and using.
Description
Technical field
The present invention relates to a kind of semiconductor processing technologies, more particularly to a kind of post tensioned unbonded prestressed concrete forming method.
Background technique
For post tensioned unbonded prestressed concrete (gate last) technique, wherein the exploitation of chemical-mechanical planarization (CMP) technique is by industry
Think most challenging.In conventional post tensioned unbonded prestressed concrete (gate last) technique, need to use CMP process by polysilicon gate
Silica separation layer and nitride spacer at the top of (poly gate) are ground off, and stop grinding after exposing the top of polysilicon gate
Mill, this step CMP process are known as opening the CMP (Poly opening nitride polish CMP) at the top of polysilicon gate, letter
Claim POP CMP；Polysilicon gate is then removed, different metal layers is filled into the groove left, then carry out one or more steps
The chemically mechanical polishing of metal layer, this single metal layer chemically-mechanicapolish polish (metal gate CMP) technique, only leave in groove
Metal, to finally obtain the metal-gate structures of high k dielectric constant.
Fig. 1 to Fig. 2 is the schematic diagram of POP CMP process in the prior art, and Fig. 3 to Fig. 4 is metal in the prior art
The schematic diagram of layer chemically mechanical polishing (metal gate CMP) technique.As depicted in figs. 1 and 2, polycrystalline is formed in substrate 10
Si-gate 11, polysilicon gate 11 is successively covered by nitride spacer 12 and silica separation layer 13, and in Fig. 2, POP CMP is specific
Including two step CMP process, the first step is the CMP of silica separation layer 13, to expose the silicon nitride isolation at 11 top of polysilicon gate
Layer, second step is the CMP of nitride spacer 12, to expose polysilicon gate 11.Above-mentioned two steps CMP process grinds chip interior
Mill uniformity (in die uniformity) suffers from very high requirement, wherein to the CMP of silica separation layer
Lapping uniformity control it is the most key.
However problem is, since the density of polysilicon gate 11 is larger, and the substrate before silicon oxide deposition separation layer 13
There are the drop of grid height, about 1000A to 1800A to then result in polysilicon gate 11 after silica separation layer 13 deposits on surface
The thickness drop h of the silica separation layer 13 of top and source-drain area is even more up to 1000A to 4000A.Using conventional oxygen
SiClx CMP process can not usually effectively eliminate this biggish thickness drop, can be genetic to always with the progress of process of lapping
The grinding technics of silica separation layer 13 terminates, as shown in Fig. 2, this drop causes remaining oxidation between polysilicon gate 11
Pit 14 is formed in silicon separation layer 13, is difficult to repair the CMP of next step nitride spacer 12, and due to material
Select the difference of ratio, it is also possible to which the pit 14 of this silica separation layer 13 is further amplified.As shown in Figure 3 and Figure 4, oxygen
It is also filled with metal material in SiClx separation layer pit 14, in subsequent chemical metal layer mechanical polishing process, can directly be given
The technique causes huge obstacle, the adjustment space of the huge compression technique, as shown in figure 4, the metal between easily causing grid
Residual, leads to shorted devices.
It is, therefore, desirable to provide a kind of method solves the above problems.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of post tensioned unbonded prestressed concrete forming methods, use
Metal residual between solving the problem of grid in the prior art leads to shorted devices.
In order to achieve the above objects and other related objects, the present invention provides a kind of post tensioned unbonded prestressed concrete forming method, provides a substrate,
The substrate is equipped with source-drain electrode, and the source-drain electrode is equipped with dielectric layer, and this method at least includes the following steps: Step 1:
The interlayer dielectric layer of grid and the covering grid is formed on the substrate；Step 2: on the surface of the interlayer dielectric layer
It is coated with anti-reflecting layer, and until etching the anti-reflecting layer to the interlayer dielectric layer for exposing the top portions of gates；Step 3: to institute
It states interlayer dielectric layer to perform etching, the interlayer dielectric layer thickness and the medium on the source-drain electrode for being etched to the top portions of gates
Thickness degree is suitable, removes the anti-reflecting layer later；Step 4: grinding to the interlayer dielectric layer, it is ground to the grid
Until exposing at the top of pole；Step 5: performing etching to the grid, gate recess is formed；Step 6: to the gate recess
Deposit one layer of gate dielectric layer, metal material filled to groove again later, the metal material cover the interlayer dielectric layer and
The groove upper surface；Step 7: forming metal after removing the interlayer dielectric layer and the metal material of the groove upper surface
The upper surface that material and the interlayer dielectric layer flush.
Preferably, the grid formed over the substrate in step 1 is the multiple grids being spaced apart from each other.
Preferably, grid described in step 1 is dummy gate layer stack structure, including polysilicon gate and covers the polysilicon
The upper surface of grid and the separation layer of side wall.
Preferably, the separation layer is nitride spacer.
Preferably, the grinding that the top portions of gates is exposed in step 4 includes removing the nitridation of the polysilicon gate upper surface
Silicon separation layer, until exposing the polysilicon gate.
Preferably, the grid is performed etching including removing the polysilicon gate completely and retaining described more in step 5
The nitride spacer of crystal silicon grid side wall.
Preferably, interlayer dielectric layer described in step 1 is silica separation layer.
Preferably, the silica separation layer is formed using the method for chemical vapor deposition.
It preferably, is aluminium to the metal material of gate recess deposition in step 6.
It preferably, is chemical and mechanical grinding method to the grinding method that the gate dielectric layer carries out in step 7.
Preferably, the anti-reflecting layer material in step 2 is organic antireflective coating.
Preferably, the interlayer dielectric layer in step 3 is with a thickness of 4000A-6000A.
Preferably, the thickness of top portions of gates interlayer dielectric layer described in step 3 and the thickness of dielectric layers phase on the source-drain electrode
Difference is no more than 150A.
Preferably, the material of the gate dielectric layer in step 7 is silica and work function material titanium and nitridation
Titanium.
Preferably, it carries out gate dielectric layer silica with rapid thermal oxidation mode to be deposited, with atomic layer deposition side
Formula deposits work function material.
As described above, post tensioned unbonded prestressed concrete forming method of the invention, has the advantages that the post tensioned unbonded prestressed concrete side of being formed of the invention
Method reduces dielectric layer and dielectric layer on source-drain electrode on top portions of gates by only performing etching to the dielectric layer on top portions of gates
Difference in height improves the flatness in silicon wafer after chemical mechanical grinding, reduces aluminium remaining risk on dielectric layer,
Milling time is also reduced simultaneously and reduces grinding consumptive material uses.
Detailed description of the invention
Fig. 1 and Fig. 2 is shown as POP CMP process schematic diagram in the prior art；
Fig. 3 and Fig. 4 is shown as chemical metal layer mechanical polishing process schematic diagram in the prior art；
Fig. 5 is shown as that the structural schematic diagram of the interlayer dielectric layer of grid and covering grid is formed on the substrate in the present invention；
Fig. 6 is shown as the structural schematic diagram that the surface in the present invention in interlayer dielectric layer is coated with after anti-reflecting layer；
Fig. 7 is shown as etching the structural representation of the anti-reflecting layer to the interlayer dielectric layer for exposing top portions of gates in the present invention
Figure；
Fig. 8 is shown as being etched on the interlayer dielectric layer thickness and source-drain electrode of top portions of gates interlayer dielectric layer in the present invention
The comparable structural schematic diagram of thickness of dielectric layers；
Fig. 9 is shown as the structural schematic diagram after the structure removal anti-reflecting layer of Fig. 8；
Figure 10 is shown as the structural schematic diagram that etching grid in the present invention forms gate recess；
Figure 11 is shown as depositing gate recess in the present invention structural schematic diagram after gate dielectric layer and metal material；
Figure 12 is shown as the metal gates that the present invention is formed.
Figure 13 is shown as the flow chart of post tensioned unbonded prestressed concrete forming method of the invention.
Component label instructions
11 polysilicon gates
12 nitride spacers
13 interlayer dielectric layers
14 anti-reflecting layers
15 metal materials
16 gate dielectric layers
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also be by addition different specific
Embodiment is embodied or practiced, and the various details in this specification can also not carried on the back based on different viewpoints and application
From carrying out various modifications or alterations under spirit of the invention.
Fig. 5 is please referred to Figure 12.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, only shown in schema then with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout kenel may also be increasingly complex.
3, Figure 13 is shown as the flow chart of post tensioned unbonded prestressed concrete forming method of the invention refering to fig. 1.The present invention provides a kind of rear grid
Pole forming method, wherein as shown in Figure 5 a, it is desirable to provide substrate, the substrate are equipped with source-drain electrode, set on the source-drain electrode
There is dielectric layer to have source electrode and drain electrode on provided substrate that is, before implementing post tensioned unbonded prestressed concrete forming method of the invention, and
And the source electrode and drain electrode is respectively covered with dielectric layer.Post tensioned unbonded prestressed concrete forming method of the invention include in the present embodiment with
Lower step:
Step 1: forming the interlayer dielectric layer of grid and the covering grid over the substrate；As shown in figure 5, Fig. 5
It is shown as that the structural schematic diagram of the interlayer dielectric layer of grid and covering grid is formed on the substrate in the present invention, it is described in Fig. 1
Grid is formed on substrate 10, interlayer dielectric layer is formed by the method for deposition on the grid.Further, the oxidation
Silicon separation layer is formed using the method for chemical vapor deposition.In the present embodiment preferably, as shown in figure 5, described in step 1
The grid formed on substrate is the multiple grids being spaced apart from each other, and is illustratively shown as foring 3 over the substrate in Fig. 5
A grid, and 3 grids are spaced each other.In practice, grid more than one formed on a substrate.
Further, in this embodiment the grid is dummy gate layer stack structure, as shown in figure 5, dummy grid stacking knot
Structure includes polysilicon gate 11 and covers the upper surface of the polysilicon gate and the separation layer of side wall, and the polysilicon gate is by more
Crystal silicon material is made, and the outer surface of the polysilicon gate 11 is covered by the separation layer, in the present embodiment preferably, directly
Contacting the polysilicon gate 11 and being covered on the separation layer of its 11 outer surface is nitride spacer 12, makes the silicon nitride
The step of separation layer 12 are as follows: the silicon nitride layer of one layer of covering 11 upper surface of polysilicon gate is first deposited on the substrate 10,
Successively the silicon nitride on the substrate is completely removed using lithography and etching processing step later, or is carved using autoregistration
Etching technique completely removes the silicon nitride on substrate, and is finally etched to the side for leaving behind polysilicon gate 11 as shown in Figure 5
The silicon nitride of wall and upper surface a thin layer forms the nitride spacer 12, that is to say, that polysilicon and silicon nitride layer, and
The laminated construction of polysilicon gate 11 and silicon nitride is formed using lithographic etch process, later in the redeposited one layer of silicon nitride in surface,
And generality etching is carried out, the grid curb wall of gate stack is formed, to form nitride spacer 12.Later, pass through deposition
Interlayer as shown in Figure 5 is formed on the surface of the nitride spacer 12 of 11 outer surface of the substrate 10 and the polysilicon gate
Dielectric layer 13, the interlayer dielectric layer be filled between the multiple dummy grid and with the substrate surface contact, in the pseudo- grid
The interlayer dielectric layer 13 is also covered above pole, forms multiple protrusions as described in Figure 5, it is convex described in the present embodiment
The height risen is h.In the present embodiment preferably, the interlayer dielectric layer is silica separation layer.That is, the oxidation
The interlayer dielectric layer of silicon insolated layer materials is covered on the polysilicon gate 11 and the nitride spacer of its outer surface,
It is to stop for providing hard grinding layer for subsequent dummy grid etching to provide grinding when subsequent metal gates grinding that it, which is acted on,
Only layer.
Step 2: being coated with anti-reflecting layer on the surface of the interlayer dielectric layer, and it is etched to and exposes the top portions of gates
Until interlayer dielectric layer.As shown in fig. 6, Fig. 6 is shown as the knot after the surface of the interlayer dielectric layer 13 is coated with anti-reflecting layer
Structure schematic diagram, the anti-reflecting layer 14 have certain thickness on the surface of the interlayer dielectric layer 13, and the anti-reflecting layer 14 covers
The top of the interlayer dielectric layer 13 is covered.Preferably, the mode for being coated with the anti-reflecting layer is coated with the present embodiment for litho machine
The mode of photoresist, the material of the anti-reflecting layer are organic antireflective coating.Its effect in the present invention is using organic
Anti-reflection coating forms even curface after being coated with, be then etched to top portions of gates interlayer dielectric layer using etching technics and appear
Out, after being coated with the anti-reflecting layer 14, dry etch process etches the anti-reflecting layer 14, and is etched to and exposes institute
Until the interlayer dielectric layer for stating top portions of gates.As shown in fig. 7, Fig. 7 is shown as etching the anti-reflecting layer in the present invention to exposing grid
The structural schematic diagram of interlayer dielectric layer at the top of pole.As shown in fig. 7, the anti-reflecting layer 14 is filled after etching anti-reflecting layer 14
Between the multiple protrusions formed on the dummy grid, after etching, the top of the protrusion is exposed.It is described anti-but after etching
Reflecting layer 14 is to expose a part at the top that the interlayer dielectric layer 13 forms protrusion, not completely by the protrusion
Exposure.
Step 3: performing etching to the interlayer dielectric layer 13, it is etched to the interlayer dielectric layer thickness of the top portions of gates
It is suitable with the thickness of dielectric layers on the source-drain electrode, the anti-reflecting layer is removed later；In the step, using dry etching side
Method performs etching the interlayer dielectric layer.As shown in figure 8, Fig. 8 is shown as being etched to grid to interlayer dielectric layer in the present invention
The interlayer dielectric layer thickness and the comparable structural schematic diagram of thickness of dielectric layers on source-drain electrode at top.In the step, to the layer
Between dielectric layer etching after, the interlayer dielectric layer of the top portions of gates is with a thickness of 400A-600A.After etching, the top portions of gates
Interlayer dielectric layer thickness and source-drain electrode be comparable be meant that perfect condition be it is identical, such whole surface be exactly it is flat,
Difference in height after grinding is also just smaller.On the interlayer dielectric layer thickness and the source-drain electrode of top portions of gates described in the present embodiment
Thickness of dielectric layers difference be no more than 300A.Preferably more than 150A.
The step to the interlayer dielectric layer be etched to thickness it is suitable with thickness of dielectric layers on the source-drain electrode when, then by institute
It states anti-reflecting layer to remove, Fig. 9 is shown as the structural schematic diagram after the structure removal anti-reflecting layer of Fig. 8.Wherein remove anti-reflecting layer
Method be removed using photoresist ashing mode.
Step 4: being ground to the interlayer dielectric layer, until being ground to the top portions of gates exposing.Due to this implementation
Example described in grid be dummy gate layer stack structure, as shown in figure 9, the dummy gate layer stack structure include polysilicon gate 11 and
Cover the upper surface of the polysilicon gate and the nitride spacer 12 of side wall.Preferably, in the step, expose the grid top
The grinding in portion includes the nitride spacer for removing the polysilicon gate upper surface, until exposing the polysilicon gate.
That is, the interlayer dielectric layer 13 be ground to until exposing the top portions of gates in step 4,
" exposure " at this refers to the top for exposing the polysilicon gate 11, that is, while grinding interlayer dielectric layer 13, institute
It states the nitride spacer 12 at the top of dummy gate layer stack structure to be also ground, that is to say, that in the layer for removing the top portions of gates
Between after dielectric layer 13, with the nitride spacer 12 at 11 top of polysilicon gate is removed, expose the polysilicon gate 11
Upper surface.In the step, the present embodiment preferably, grinds the method for the interlayer dielectric layer 13 using chemical mechanical grinding
Method remove the interlayer dielectric layer.
Step 5: performing etching to the grid, gate recess is formed；As shown in Figure 10, Figure 10 is shown as in the present invention
The structural schematic diagram of etching grid formation gate recess.The grid as described in the present embodiment is dummy gate layer stack structure, is passed through
After step 4 is to the etching of interlayer dielectric layer and nitride spacer at the top of the polysilicon gate, expose the polysilicon gate
Top.
The step, which performs etching the grid, to refer to continuing in the present embodiment carving the polysilicon gate 11
Erosion, by the polysilicon gate 11 is etched to whole removals, as shown in Figure 10, forms and is spaced apart from each other on the substrate 10
Groove has interlayer dielectric layer 13 between groove.Preferably, in the etching of the step, the polysilicon gate side wall will be retained
Nitride spacer, by substrate exposure in the groove after the polysilicon is removed after etching, therefore, the present embodiment is preferred
Ground performs etching including removing the polysilicon gate 11 completely and retaining the polysilicon gate grid in the step 5
The nitride spacer 12 of side wall.It is further preferred that the method for etching the polysilicon gate in the step is to be carved using dry method
Erosion mode.
Step 6: depositing one layer of gate dielectric layer to the gate recess, metal material is filled to groove again later, it is described
Metal material covers the interlayer dielectric layer and the groove upper surface.As shown in figure 11, Figure 11 is shown as in the present invention to grid
Pole groove deposits the structural schematic diagram after gate dielectric layer and metal material.Preferably, to the gate recess in the step 6
The gate dielectric layer of deposition is silica and work function material, it is preferable that the work function material includes titanium and titanium nitride.With
Rapid thermal oxidation mode carries out gate dielectric layer silica and is deposited, and deposits work function material with atomic layer deposition mode.
The work function material of deposition is the mixture for including titanium and titanium nitride.It is formed over the substrate by step 5 mutually
The gate recess at interval, the side wall of the gate recess remains nitride spacer 12, and the bottom of gate recess is lining
The upper surface at bottom 10 is the interlayer dielectric layer 13 on the substrate 10 between gate recess.First to the grid in step 6
Pole groove deposits one layer of gate dielectric layer 16, then fills metal material to the groove again, and the metal material is aluminium.Step
Physical chemistry vapor deposition mode is preferably used in rapid six to the method for the gate recess deposited metal material.
As seen from Figure 11, under normal circumstances, since the upper surface that will appear metal material after deposited metal material is higher than
The surface of the interlayer dielectric layer adjacent with metal material.That is, also deposited the metal material on the interlayer dielectric layer,
And the metal material of the interlayer dielectric layer excess surface is also needed to be removed later, obtain the gate recess upper surface
Metal material flushed with the upper surface of the interlayer dielectric layer.
Step 7: forming metal material and institute after removing the interlayer dielectric layer and the metal material of the groove upper surface
State the upper surface that interlayer dielectric layer flushes.As shown in figure 12, Figure 12 is shown as the metal gates that the present invention is formed.The step will
The method removal of the metal material of the groove upper surface and the grinding of the metal material of the interlayer dielectric layer upper surface
Afterwards, the upper surface that metal material as shown in figure 12 is flushed with the interlayer dielectric layer is formed.Obtain metal gate of the invention
Pole.
The interlayer dielectric layer upper surface is ground using the method for chemical mechanical grinding in the present embodiment, the purpose of grinding
It is so that gate surface planarization, finally obtains the metal gates of surfacing.
In conclusion post tensioned unbonded prestressed concrete forming method of the present invention is reduced by only performing etching to the dielectric layer on top portions of gates
The difference in height of dielectric layer and dielectric layer on source-drain electrode on top portions of gates improves flat in silicon wafer after chemical mechanical grinding
Smooth degree reduces aluminium remaining risk on dielectric layer, while also reducing milling time and reducing grinding consumptive material and using.
So the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, those of ordinary skill in the art institute without departing from the spirit and technical ideas disclosed in the present invention such as
All equivalent modifications or change completed, should be covered by the claims of the present invention.
Claims (15)
1. a kind of post tensioned unbonded prestressed concrete forming method, which is characterized in that provide a substrate, the substrate is equipped with source-drain electrode, the source and drain
It is extremely equipped with dielectric layer, this method at least includes the following steps:
Step 1: forming the interlayer dielectric layer of grid and the covering grid over the substrate；
Step 2: be coated with anti-reflecting layer on the surface of the interlayer dielectric layer, and the anti-reflecting layer is etched to exposing the grid
Until the interlayer dielectric layer at top；
Step 3: performed etching to the interlayer dielectric layer, be etched to the interlayer dielectric layer thickness of the top portions of gates with it is described
Thickness of dielectric layers on source-drain electrode is suitable, removes the anti-reflecting layer later；
Step 4: being ground to the interlayer dielectric layer, until being ground to the top portions of gates exposing；
Step 5: performing etching to the grid, gate recess is formed；
Step 6: depositing one layer of gate dielectric layer to the gate recess, metal material, the metal are filled to groove again later
Material covers the interlayer dielectric layer and the groove upper surface；
Step 7: forming metal material and the layer after removing the interlayer dielectric layer and the metal material of the groove upper surface
Between the upper surface that flushes of dielectric layer.
2. post tensioned unbonded prestressed concrete forming method according to claim 1, it is characterised in that: formed over the substrate in step 1
Grid is the multiple grids being spaced apart from each other.
3. post tensioned unbonded prestressed concrete forming method according to claim 2, it is characterised in that: grid described in step 1 is dummy gate layer
Stack structure including polysilicon gate and covers the upper surface of the polysilicon gate and the separation layer of side wall.
4. post tensioned unbonded prestressed concrete forming method according to claim 3, it is characterised in that: the separation layer is nitride spacer.
5. post tensioned unbonded prestressed concrete forming method according to claim 4, it is characterised in that: expose the top portions of gates in step 4
Grinding includes the nitride spacer for removing the polysilicon gate upper surface, until exposing the polysilicon gate.
6. post tensioned unbonded prestressed concrete forming method according to claim 5, it is characterised in that: performed etching in step 5 to the grid
Including removing the polysilicon gate completely and retaining the nitride spacer of the polysilicon gate side wall.
7. post tensioned unbonded prestressed concrete forming method according to claim 1 or 6, it is characterised in that: interlayer dielectric layer described in step 1
For silica separation layer.
8. post tensioned unbonded prestressed concrete forming method according to claim 7, it is characterised in that: the silica separation layer is using chemical gas
Mutually the method for deposition is formed.
9. post tensioned unbonded prestressed concrete forming method according to claim 1, it is characterised in that: filled in step 6 to the gate recess
Metal material be aluminium.
10. post tensioned unbonded prestressed concrete forming method according to claim 1, it is characterised in that: remove the metal material in step 7
Method be chemical and mechanical grinding method.
11. post tensioned unbonded prestressed concrete forming method according to claim 1, it is characterised in that: the anti-reflecting layer material in step 2
Material is organic antireflective coating.
12. post tensioned unbonded prestressed concrete forming method according to claim 1, it is characterised in that: the interlayer dielectric layer in step 3
With a thickness of 4000A-6000A.
13. post tensioned unbonded prestressed concrete forming method according to claim 1, it is characterised in that: the layer of top portions of gates described in step 3
Between thickness of dielectric layers differed with the thickness of dielectric layers on the source-drain electrode be no more than 150A.
14. post tensioned unbonded prestressed concrete forming method according to claim 1, it is characterised in that: the gate dielectric layer in step 6
Material be silica and work function material；The work function material includes titanium and titanium nitride.
15. post tensioned unbonded prestressed concrete forming method according to claim 14, it is characterised in that: carry out grid with rapid thermal oxidation mode
Dielectric layer silica is deposited, and deposits work function material with atomic layer deposition mode.
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Application publication date: 20190517 |