CN102543714A - Method for improving uniformity of chemical-mechanical planarization process at top of opened polycrystal gratings - Google Patents
Method for improving uniformity of chemical-mechanical planarization process at top of opened polycrystal gratings Download PDFInfo
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- CN102543714A CN102543714A CN2010106070419A CN201010607041A CN102543714A CN 102543714 A CN102543714 A CN 102543714A CN 2010106070419 A CN2010106070419 A CN 2010106070419A CN 201010607041 A CN201010607041 A CN 201010607041A CN 102543714 A CN102543714 A CN 102543714A
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Abstract
The invention relates to a method for improving the uniformity of a chemical-mechanical planarization process at the top of opened polycrystal gratings. Before aiming at the chemical-mechanical planarization process of silicon oxide layers, a one-step silicon oxide etching process is employed, so that the height difference of the silicon oxide layer between the adjacent polycrystal gratings and the silicon oxide layer over each polycrystal grating is greatly reduced. Therefore, the influence of a smaller height difference on the chemical-mechanical planarization process can be also greatly reduced, so that in a grinding process, the height difference cannot be transferred, the recesses in the silicon oxide layers are greatly reduced, a flat silicon oxide surface is obtained, and the probability of the existence of subsequent metal residues is eliminated, thereby improving the electrical performance and the yield of the finished products.
Description
Technical field
The present invention relates to a kind of process of making semiconductor device, relate to the method that polycrystalline grid top chemical-mechanical planarization process uniformity is opened in a kind of raising especially.
Background technology
The successful Application of high K/ metal gate engineering on 45 nm technology node makes it become the indispensable key modules chemical industry of the following technology node of 30 nanometers journey.At present, only adhere to that the Intel company of metal gate (gate last) route has obtained success on the volume production of 45 nanometers and 32 nm technology node behind the high K/.In recent years, the industry giants such as Samsung, Taiwan Semiconductor Manufacturing Co., Infineon that follow IBM industry alliance closely also will before research and develop emphasis and turn to gate last by high K/ elder generation's metal gate (gate first).
For gate last engineering, the exploitation of chemical-mechanical planarization wherein (CMP) technology is thought tool challenge by industry.In gate last engineering; One CMP technology of needs grinds off the silica and the silicon nitride separator at polycrystalline grid (poly gate) top; And after exposing polycrystalline grid top, stop to grind; This step is called as the CMP that opens polycrystalline grid top, and promptly polyopening polish nitride CMP abbreviates POP CMP as; Then, will dig up through the polycrystalline grid of traditional handicraft preparation, and fill metal, and form metal gate, and need a step or the multistep chemical-mechanical planarization to metal gate afterwards, promptly metal gate CMP finally obtains high K/ metal-gate structures.
POP CMP comprises the CMP of two steps, the one, and the CMP of silica, the one, the CMP of silicon nitride, and this two step CMP all has very high requirement to chip wafer inside grinding uniformity (within dieuniformity).Wherein, the most key to the grinding uniformity control of the silica CMP technology of at first carrying out.Referring to accompanying drawing 1; Because device density is bigger; And the height of polycrystalline grid 13 is generally 1000-1800
, and this causes behind cvd silicon oxide 11, and silica directly over the polycrystalline grid 13 and the silicon oxide thickness drop H between adjacent polycrystalline grid 13 can reach 1000-4000
even bigger.If adopt conventional silica CMP technology, can't effectively eliminate this bigger thickness drop, this drop can be delivered to silica CMP always and finish with the carrying out of CMP process, and this has just caused the silica 11 between the polycrystalline grid 13 to have depression.Although there is CMP afterwards to silicon nitride 12, should also be difficult to repair the depression of silica 11 by step CMP, and, also maybe the depression of silica 11 further be amplified because material is selected the difference of ratio, form last depression 14, referring to Fig. 2.Bigger silica depression 14 causes huge obstacle can for metal gate CMP technology, between polycrystalline grid 13, forms metal residual easily, thereby causes the device short circuit.
For satisfying POP CMP inhomogeneity high request is ground in chip wafer inside, need develop a kind of new process, eliminate the medium depression between grid, thereby improve device reliability.
Summary of the invention
The present invention adopts the silica etching to combine the method for using with silica CMP, improves and opens polycrystalline grid top chemical-mechanical planarization process uniformity.
The present invention provides a kind of raising to open polycrystalline grid top chemical-mechanical planarization process uniformity method, comprising:
Substrate is provided, and is positioned at the polycrystalline grid on the said substrate;
Deposited silicon nitride layer and is carried out patterning to said silicon nitride layer on said substrate, make said silicon oxide layer cover the top and the sidewall of said polycrystalline grid;
Silicon oxide layer deposited is on said substrate, and said silicon oxide layer is the gap between the said polycrystalline grid of complete filling at least;
Adopt the first chemical-mechanical planarization technology, said silicon oxide layer is carried out planarization, until exposing the said silicon nitride layer that covers said polycrystalline grid top;
Adopt the second chemical-mechanical planarization technology, the said silicon nitride layer that exposes is carried out planarization, until the top that exposes said polycrystalline grid;
Wherein, before the said first chemical-mechanical planarization technology, carry out following steps:
After the said silicon oxide layer of deposition; On said substrate, apply photoresist, make public, form a photoresist pattern through photomask; Said photoresist pattern exposes the said silicon oxide layer that is positioned at said polycrystalline grid over top, and covers the silicon oxide layer between adjacent said polycrystalline grid;
Adopt an etching technics, the said silicon oxide layer that is positioned at said polycrystalline grid over top that exposes is carried out etching, the etching depth of said etching technics is not more than the thickness of the said silicon oxide layer that is positioned at said polycrystalline grid over top;
After said etching technics, be reduced at the upper surface and the height fall between the upper surface of the said silicon oxide layer between the adjacent said polycrystalline grid of the said silicon oxide layer of said polycrystalline grid over top;
The employing technology of removing photoresist is removed the said photoresist pattern on the said substrate.
In the method for the invention, the main etching gas in the said etching technics is the fluorine-based etching gas of carbon; The fluorine-based etching gas of said carbon comprises CF
4, CHF
3, C
2F
6, C
4F
8, CH
2F
2, CH
3F, C
5F
8In one or more;
In the method for the invention, the auxiliary interpolation gas in the said etching technics comprises CO, O
2, Ar, He, SF
6, N
2In one or more;
In the method for the invention, the chemical-mechanical planarization of said first chemical-mechanical planarization for being the basis with silica CMP;
In the method for the invention, the polishing fluid in the said first chemical-mechanical planarization technology comprises alkaline SiO
2Base lapping liquid or alkaline CeO
2The base lapping liquid;
In the method for the invention, the polishing pad in the said first chemical-mechanical planarization technology comprises hard polishing pad or soft polishing pad.
In the method for the invention, the chemical-mechanical planarization of said second chemical-mechanical planarization for being the basis with silicon nitride CMP.
The invention has the advantages that: to before the chemical-mechanical planarization technology of silicon oxide layer, adopt the oxidation step silicon etching process, make that silicon oxide layer and the height fall of the silicon oxide layer directly over the polycrystalline grid between the adjacent polycrystalline grid significantly reduces; Therefore; Less height fall also can alleviate the influence of chemical-mechanical planarization technical process greatly, thereby in process of lapping, height fall can not hand on; Greatly reduce the depression in the silicon oxide layer; Obtain smooth silicon oxide surface, eliminated the possibility that has metal residual subsequently, thereby improved device electric property and rate of finished products.
Description of drawings
The preceding device architecture sketch map of silica CMP technology that Fig. 1 is conventional;
Device architecture sketch map after the silicon nitride CMP technology of Fig. 2 routine;
Fig. 3 has shown the device architecture after the silicon oxide layer deposited of the present invention;
Fig. 4 has shown that the present invention forms the photoresist pattern and carries out the process of etching;
Fig. 5 has shown the silicon oxide layer surface of the present invention through over etching;
Fig. 6 has shown that the device behind the silica CMP has flat surfaces;
Fig. 7 has shown that the device behind the silicon nitride CMP has flat surfaces.
Embodiment
Following with reference to accompanying drawing and combine schematic embodiment to specify the characteristic and the technique effect thereof of technical scheme of the present invention.
At first,, a substrate 1 is provided, has polycrystalline grid 2 on the substrate 1 referring to accompanying drawing 3.Substrate 1 can be various substrates common in the semiconductor device, for example silicon, GaAs etc.; Polycrystalline grid 2 form through conventional method; It has a height; Be generally 1000～1500
then; At the surface deposition silicon nitride layer 3 of substrate 1, silicon nitride layer 3 is carried out patterning, make it cover the top and the sidewall of polycrystalline grid 2.Then silicon oxide layer deposited 4, silicon oxide layer 4 has a thickness, makes its gap between at least can complete filling polycrystalline grid 2.Because polycrystalline grid 2 have height, therefore, silicon oxide layer 4 has a ledge 41, is positioned at the top at polycrystalline grid 2 tops.There is difference in height h between the upper surface of the silicon oxide layer 4 between the upper surface of ledge 41 and the polycrystalline grid 2
1, also be the projecting height of ledge 41, difference in height h
1Value can not be generally 1000～4000 usually less than the height of polycrystalline grid 2
Deposited silicon nitride layer 3 can adopt technologies such as CVD, PVD, ALD with silicon oxide layer 4.
After silicon oxide layer 4 depositions are accomplished, entire substrate 1 is applied photoresist; Through selecting the appropriate light mask, again through overexposure, development, form a photoresist pattern 5, the silicon oxide layer 4 that photoresist pattern 5 covers between adjacent polycrystalline grid 2, and the ledge 41 of silicon oxide layer 4 is come out, referring to accompanying drawing 4.
Adopt an etching technics, according to difference in height h
1Numerical value select suitable silica etching condition and etch period, the ledge 41 of the silicon oxide layer 4 that comes out is carried out etching processing, etching depth is not more than difference in height h
1, to subdue difference in height, referring to accompanying drawing 4, arrow is depicted as the direction that etching is subdued silicon oxide layer 4.Etching technics can adopt anisotropic dry etch process, and main etching gas is the fluorine-based etching gas of carbon, comprises CF
4, CHF
3, C
2F
6, C
4F
8, CH
2F
2, CH
3F, C
5F
8In one or more, the auxiliary gas that adds comprises CO, O
2, Ar, He, SF
6, N
2In one or more.After this etching technics, the difference in height h between the upper surface of the silicon oxide layer 4 between the upper surface of ledge 41 and the polycrystalline grid 2
1Be reduced to h
2, referring to accompanying drawing 5.Because the edge of ledge 41 is near photoresist; Receive the influence of photoresist, the edge etch rate of ledge 41 can be lower than the etching speed at ledge 41 middle parts, so; The speed that subdue at ledge 41 middle parts can be very fast; Therefore, when etching technics finished, can there be a concave surface in the top of ledge 41.Subsequently, through the technology of removing photoresist, remove photoresist pattern 5.Logical producing adopts wet etching or dry etching to get rid of photoresist pattern 5, and entire substrate 1 is carried out drying; For the flatness of the silicon oxide layer 4 that guarantees not to be etched, the condition of removing photoresist in the technology of removing photoresist should not have destruction to silicon oxide layer 4.
Next, carry out first chemical-mechanical planarization, this goes on foot first chemical-mechanical planarization and is the basis with silica CMP, and silicon oxide layer 4 is carried out planarization, exposes the silicon nitride layer 3 that covers polycrystalline grid 2 tops, referring to accompanying drawing 6.The polishing fluid that is adopted in the first chemical-mechanical planarization technology comprises alkaline SiO
2Base lapping liquid or alkaline CeO
2The base lapping liquid, the polishing pad that is adopted comprises hard polishing pad or soft polishing pad.Because difference in height h
2Numerical value less, therefore, this is also very little to the influence that this goes on foot first chemical-mechanical planarization, in process of lapping, the difference in height h in the silicon oxide layer 4
2Can't be passed on 4 surfaces of the silicon oxide layer between the polycrystalline grid 2, thereby avoid the generation of caving in, make remaining silicon oxide layer 4 have smooth surface.
Subsequently, carry out second chemical-mechanical planarization, this goes on foot second chemical-mechanical planarization and is the basis with silicon nitride CMP, and silicon nitride layer 3 is carried out planarization, exposes the top of polycrystalline grid 2, and makes device have smooth surface, referring to accompanying drawing 6.
Among the present invention, before first chemical-mechanical planarization, adopted etching technics that silicon oxide layer is carried out etching; Subdued the bigger difference in height that exists in the silicon oxide layer; Thereby, in the process of lapping of first chemical-mechanical planarization, can original bigger height fall be passed in the remaining silicon oxide layer; Obtain to have the device of flat surfaces, thereby improved device electric property and rate of finished products.
Although with reference to above-mentioned exemplary embodiment explanation the present invention, those skilled in the art can know and need not to break away from the scope of the invention and technical scheme of the present invention is made various suitable changes and equivalents.In addition, can make by disclosed instruction and manyly possibly be suitable for the modification of particular condition or material and do not break away from the scope of the invention.Therefore, the object of the invention does not lie in and is limited to as being used to realize preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture and manufacturing approach thereof will comprise all embodiment that fall in the scope of the invention.
Claims (8)
1. polycrystalline grid top chemical-mechanical planarization process uniformity method is opened in a raising, comprising:
Substrate is provided, and is positioned at the polycrystalline grid on the said substrate;
Deposited silicon nitride layer and is carried out patterning to said silicon nitride layer on said substrate, make said silicon oxide layer cover the top and the sidewall of said polycrystalline grid;
Silicon oxide layer deposited is on said substrate, and said silicon oxide layer is the gap between the said polycrystalline grid of complete filling at least;
Adopt the first chemical-mechanical planarization technology, said silicon oxide layer is carried out planarization, until exposing the said silicon nitride layer that covers said polycrystalline grid top;
Adopt the second chemical-mechanical planarization technology, the said silicon nitride layer that exposes is carried out planarization, until the top that exposes said polycrystalline grid;
It is characterized in that: before the said first chemical-mechanical planarization technology, carry out following steps:
After the said silicon oxide layer of deposition; On said substrate, apply photoresist, make public, form a photoresist pattern through photomask; Said photoresist pattern exposes the said silicon oxide layer that is positioned at said polycrystalline grid over top, and covers the silicon oxide layer between adjacent said polycrystalline grid;
Adopt an etching technics, the said silicon oxide layer that is positioned at said polycrystalline grid over top that exposes is carried out etching, the etching depth of said etching technics is not more than the thickness of the said silicon oxide layer that is positioned at said polycrystalline grid over top;
After said etching technics, be reduced at the upper surface and the height fall between the upper surface of the said silicon oxide layer between the adjacent said polycrystalline grid of the said silicon oxide layer of said polycrystalline grid over top;
The employing technology of removing photoresist is removed the said photoresist pattern on the said substrate.
2. polycrystalline grid top chemical-mechanical planarization process uniformity method is opened in raising as claimed in claim 1, it is characterized in that, the main etching gas in the said etching technics is the fluorine-based etching gas of carbon.
3. polycrystalline grid top chemical-mechanical planarization process uniformity method is opened in raising as claimed in claim 2, it is characterized in that, the fluorine-based etching gas of said carbon comprises CF
4, CHF
3, C
2F
6, C
4F
8, CH
2F
2, CH
3F, C
5F
8In one or more.
4. polycrystalline grid top chemical-mechanical planarization process uniformity method is opened in raising as claimed in claim 1, it is characterized in that, the auxiliary interpolation gas in the said etching technics comprises CO, O
2, Ar, He, SF
6, N
2In one or more.
5. polycrystalline grid top chemical-mechanical planarization process uniformity method is opened in raising as claimed in claim 1, it is characterized in that the chemical-mechanical planarization of said first chemical-mechanical planarization for being the basis with silica CMP.
6. polycrystalline grid top chemical-mechanical planarization process uniformity method is opened in raising as claimed in claim 1, it is characterized in that, in the method for the invention, the polishing fluid in the said first chemical-mechanical planarization technology comprises alkaline SiO
2Base lapping liquid or alkaline CeO
2The base lapping liquid.
7. polycrystalline grid top chemical-mechanical planarization process uniformity method is opened in raising as claimed in claim 1, it is characterized in that, the polishing pad in the said first chemical-mechanical planarization technology comprises hard polishing pad or soft polishing pad.
8. polycrystalline grid top chemical-mechanical planarization process uniformity method is opened in raising as claimed in claim 1, it is characterized in that the chemical-mechanical planarization of said second chemical-mechanical planarization for being the basis with silicon nitride CMP.
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| WO2014082356A1 (en) * | 2012-11-30 | 2014-06-05 | 中国科学院微电子研究所 | Planarization processing method |
| CN105261550A (en) * | 2014-07-18 | 2016-01-20 | 中国科学院微电子研究所 | Chemical mechanical polishing method for germanium |
| US9633855B2 (en) | 2012-11-30 | 2017-04-25 | Institute of Microelectronics, Chinese Academy of Sciences | Planarization process |
| CN107731929A (en) * | 2017-09-28 | 2018-02-23 | 信利（惠州）智能显示有限公司 | Thin film transistor (TFT) and preparation method thereof and array base palte and display device |
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| CN111430231A (en) * | 2020-05-21 | 2020-07-17 | 中国科学院微电子研究所 | Planarization method and semiconductor device |
| CN113808934A (en) * | 2021-09-09 | 2021-12-17 | 中山大学 | CMP optimization method |
| CN114683162A (en) * | 2020-12-29 | 2022-07-01 | 中芯集成电路（宁波）有限公司 | Planarization process method |
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| JPH11340174A (en) * | 1998-05-28 | 1999-12-10 | Nippon Steel Corp | Producing method for semiconductor device |
| JP2000058682A (en) * | 1998-08-05 | 2000-02-25 | Texas Instr Inc <Ti> | Improvement of anisotropical chemical etching method of silicon oxide in manufacturing mos transistor flash eprom device |
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| WO2014082356A1 (en) * | 2012-11-30 | 2014-06-05 | 中国科学院微电子研究所 | Planarization processing method |
| CN103854965A (en) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | Planarization processing method |
| US10068803B2 (en) | 2012-11-30 | 2018-09-04 | Institute of Microelectronics, Chinese Academy of Sciences | Planarization process |
| US9633855B2 (en) | 2012-11-30 | 2017-04-25 | Institute of Microelectronics, Chinese Academy of Sciences | Planarization process |
| CN105261550B (en) * | 2014-07-18 | 2018-04-03 | 中国科学院微电子研究所 | A kind of cmp method of germanium |
| CN105261550A (en) * | 2014-07-18 | 2016-01-20 | 中国科学院微电子研究所 | Chemical mechanical polishing method for germanium |
| CN107863294A (en) * | 2016-09-22 | 2018-03-30 | 英飞凌科技股份有限公司 | Semiconductor wafer and method |
| CN107731929A (en) * | 2017-09-28 | 2018-02-23 | 信利（惠州）智能显示有限公司 | Thin film transistor (TFT) and preparation method thereof and array base palte and display device |
| CN109767987A (en) * | 2019-01-28 | 2019-05-17 | 上海华虹宏力半导体制造有限公司 | A kind of post tensioned unbonded prestressed concrete forming method |
| CN111430231A (en) * | 2020-05-21 | 2020-07-17 | 中国科学院微电子研究所 | Planarization method and semiconductor device |
| CN114683162A (en) * | 2020-12-29 | 2022-07-01 | 中芯集成电路（宁波）有限公司 | Planarization process method |
| CN114683162B (en) * | 2020-12-29 | 2023-09-12 | 中芯集成电路（宁波）有限公司 | Planarization process method |
| CN113808934A (en) * | 2021-09-09 | 2021-12-17 | 中山大学 | CMP optimization method |
| CN113808934B (en) * | 2021-09-09 | 2022-09-16 | 中山大学 | CMP optimization method |
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