CN103021924A - Formation method of STI (shallow trench isolation) structure - Google Patents
Formation method of STI (shallow trench isolation) structure Download PDFInfo
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Abstract
A formation method of an STI (shallow trench isolation) structure includes: providing a semiconductor substrate, forming a pad oxide layer on the surface of the semiconductor substrate, forming a grinding barrier layer on the surface of the pad oxide layer, and forming a photoresist layer on the grinding barrier layer; etching the surface of the grinding barrier layer and the surface of the pad oxide layer to form a second opening by using the photoresist as a mask, allowing the second opening to penetrate the grinding barrier layer, the pad oxide layer and a depth-directional part of the semiconductor substrate, and allowing sidewalls of the second opening in the semiconductor substrate to incline at certain angle. Polymer is formed on the sidewalls of the second opening while the pad oxide layer is etched during etching process of the pad oxide layer, the sidewalls of the second opening in the semiconductor substrate are inclined at the certain angle, sidewalls of subsequently formed trenches are also inclined at certain angle, and accordingly sidewalls of the finally formed STI structure are smooth with no protrusion and the insulating property of the STI structure is unaffected.
Description
Technical field
The present invention relates to semiconductor technology, particularly a kind of formation method of fleet plough groove isolation structure.
Background technology
Along with semiconductor technology enters the deep-submicron epoch, between different devices, for example the nmos pass transistor in the CMOS transistor and the isolation between the PMOS transistor all adopt fleet plough groove isolation structure (STI) to isolate.
The formation method of traditional fleet plough groove isolation structure comprises: Semiconductor substrate is provided, forms pad oxide at described semiconductor substrate surface, form on described pad oxide surface and grind the barrier layer; Form patterned photoresist layer at described grinding barrier layer surface, described patterned photoresist layer exposes the subregion of grinding the barrier layer; Described grinding barrier layer, pad oxide and the Semiconductor substrate that exposes carried out etching, in described Semiconductor substrate, form groove; In described groove, fill full insulating material, form fleet plough groove isolation structure.
Development along with semiconductor technology, the size of device becomes more and more less, and it is more and more less that the opening size of formed groove also becomes, but because in order to guarantee insulation property, described fleet plough groove isolation structure need to keep certain degree of depth, and therefore the depth-to-width ratio of formed groove becomes increasing.For so that the dielectric material can successfully be filled the groove of completely described large depth-to-width ratio, avoid the final fleet plough groove isolation structure that forms because failing to fill fully forms the cavity, the groove that prior art forms is " V " shape groove or inverted trapezoidal groove.The formation technique of described " V " shape groove or inverted trapezoidal groove is: the opening sidewalls that forms in described etching in the time of the described Semiconductor substrate of etching forms polymer, so that the trenched side-wall of described final formation is what tilt.
More formation methods about fleet plough groove isolation structure please refer to the american documentation literature that the patent No. is US6713780B2.
Summary of the invention
The problem that the present invention solves provides a kind of formation method of fleet plough groove isolation structure, so that the sidewall of the fleet plough groove isolation structure that forms is smooth smooth, does not have projection.
For addressing the above problem, technical solution of the present invention provides a kind of formation method of fleet plough groove isolation structure, comprising:
Semiconductor substrate is provided, forms pad oxide at described semiconductor substrate surface, form on described pad oxide surface and grind the barrier layer, be formed for the photoresist layer of excimer lithography on described grinding barrier layer;
Utilize excimer lithography technique that described photoresist layer is carried out exposure imaging, form the first opening;
Take photoresist layer with first opening as mask, etching is carried out on described grinding barrier layer and pad oxide, form the second opening, described the second opening runs through the Semiconductor substrate of described grinding barrier layer, pad oxide and partial depth, wherein, form polymer at the second opening sidewalls in the time of the Semiconductor substrate of the described pad oxide of etching and partial depth, so that the second opening sidewalls in the Semiconductor substrate has certain gradient;
The Semiconductor substrate that described the second opening exposes is carried out etching, form the groove of sidewall slope;
In described groove, form insulating material with the grinding barrier layer, and described insulating material is carried out cmp, grind the barrier layer until end at, form fleet plough groove isolation structure.
Optionally, the technological parameter of the described pad oxide of etching comprises: etching gas comprises SF
6And CH
2F
2, wherein, described SF
6Range of flow be 10sccm～30sccm, described CH
2F
2Range of flow be 30sccm～50sccm, the scope of reaction chamber temperature is 60 degrees centigrade～70 degrees centigrade, the scope of reaction chamber pressure is 5 millitorrs～15 millitorrs, and the power bracket of radio frequency power source is 200 watts～600 watts, and the power bracket in bias power source is 70 watts～200 watts.
Optionally, by adjusting the C/F ratio of described etching gas, be controlled at the amount of the polymer of the second opening sidewalls formation, the sidewall slope degree of the second opening in the control Semiconductor substrate is so that the sidewall slope degree of the second opening in the Semiconductor substrate is consistent with the sidewall slope degree of groove.
Optionally, the material on described grinding barrier layer is silicon nitride or silicon oxynitride.
Optionally, also comprise: between described grinding barrier layer and photoresist layer, form hard mask layer, after forming the second opening, take described hard mask layer as mask, the Semiconductor substrate that described the second opening exposes is carried out etching, form the groove of sidewall slope, and after forming insulating material, utilize cmp to remove insulating material and the hard mask layer that grinds on the barrier layer.
Optionally, the material of described hard mask layer is silica or amorphous carbon.
Optionally, adopt the described hard mask layer of same etching technics etching, grinding barrier layer and pad oxide.
Optionally, the described pad oxide of the described hard mask layer of etching, the described grinding of etching barrier layer and etching adopts different etching technics.
Optionally, when forming the second opening, the degree of depth of the second opening in the described Semiconductor substrate is more than or equal to 100 dusts.
Optionally, also comprise: form bottom anti-reflection layer at described grinding barrier layer surface, be formed for the photoresist layer of excimer lithography on described bottom anti-reflection layer surface, described photoresist layer is carried out exposure imaging, after forming the first opening, etching is removed the bottom anti-reflection layer that is exposed by the first opening.
Compared with prior art, the present invention has the following advantages:
In the etching technics of pad oxide, form polymer at the second opening sidewalls in the time of the described pad oxide of etching, so that the second opening sidewalls in the Semiconductor substrate has certain gradient, and the sidewall of the groove of follow-up formation also has certain gradient, so that the sidewall of the final fleet plough groove isolation structure that forms is smooth, do not have projection, can not affect the insulation property of fleet plough groove isolation structure.
Description of drawings
Fig. 1 is the cross-sectional view of the groove of prior art formation;
Fig. 2 to Fig. 8 is the cross-sectional view of forming process of the fleet plough groove isolation structure of the embodiment of the invention.
Embodiment
From background technology, as can be known, usually has one deck pad oxide at semiconductor substrate surface.Because the etching gas of etching semiconductor substrate is not easy the described pad oxide of etching, therefore need to carve first and wear described pad oxide, adopt again different etching technics etching semiconductor substrates, the etching gas of the described pad oxide of etching generally includes heavy dose of CF
4Or He.The photoresist layer corresponding owing to traditional I Lithography technique is thicker, when the described pad oxide of etching, still have the photoresist layer of segment thickness to be retained in the grinding barrier layer surface, the photoresist of removing in the etching process can form polymer at the opening sidewalls that etching forms, so that the sidewall of described opening has certain angle of inclination.And the groove of follow-up formation also is " V " shape groove or inverted trapezoidal groove, the sidewall of described groove also has certain angle of inclination, by controlling so that the angle of inclination of described opening and groove is consistent, so that the sidewall of the final fleet plough groove isolation structure that forms is smooth smooth.
But along with the characteristic size of semiconductor technology becomes more and more less, the wavelength that is used for the exposure light source of photoetching also becomes more and more less, and the thickness of corresponding photoresist layer also thins down.At present, increasing manufacturer uses the alternative traditional I Lithography technique of excimer laser (ArF) photoetching process that photoresist layer is exposed.The photoresist layer corresponding with I Lithography technique compared, and photoresist layer corresponding to excimer lithography technique is thinner and softer, and etching selection is less, is removed in etching process easilier.Utilizing described excimer lithography technique to form in the technique of fleet plough groove isolation structure, utilize photoresist layer corresponding to described excimer lithography technique to be mask, carry out etching to grinding barrier layer, pad oxide and Semiconductor substrate, wear that described photoresist layer is etched when grinding the barrier layer not carving fully, so that can only be take described grinding barrier layer as mask when the remaining grinding of subsequent etching barrier layer, pad oxide and Semiconductor substrate.
Since when the etching pad oxide, there has not been photoresist layer residual, so that can not rely on photoresist layer to form polymer at the opening sidewalls that etching forms, and the CF of existing etching pad oxide process using
4, the gas such as He can not independently form polymer at described opening sidewalls, therefore described opening sidewalls near pad oxide approaches vertical.And wear all described pad oxides in order to guarantee to carve, the technique of etching pad oxide tends to the Semiconductor substrate of over etching segment thickness, so that the opening sidewalls of the close semiconductor substrate surface that forms in the etching pad oxide process approaches vertically.Because the sidewall of the groove that prior art forms need to have certain angle of inclination, so that the sidewall of the final groove that forms is rough smooth, has knuckle, please refer to Fig. 1, the cross-sectional view of the groove that forms for prior art, the sidewall out-of-flatness of the groove 11 of described Semiconductor substrate 10 interior formation can form knuckle 12.Described knuckle 12 can cause accumulation so that the sidewall of the final fleet plough groove isolation structure that forms has projection, affects the insulation property of fleet plough groove isolation structure.
Therefore, the embodiment of the invention provides a kind of formation method of fleet plough groove isolation structure, in the etching technics of pad oxide, form polymer at the second opening sidewalls in the time of the described pad oxide of etching, so that the second opening sidewalls in the Semiconductor substrate has certain gradient, and the sidewall of the groove of follow-up formation also has certain gradient, so that the sidewall of the final fleet plough groove isolation structure that forms is smooth, can not affect the insulation property of fleet plough groove isolation structure.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization in the situation of intension of the present invention.Therefore the present invention is not subjected to the restriction of following public implementation.
The embodiment of the invention provides a kind of formation method of fleet plough groove isolation structure, please refer to Fig. 2 to figure Fig. 8, is the cross-sectional view of the forming process of the fleet plough groove isolation structure of the embodiment of the invention.
Please refer to Fig. 2, Semiconductor substrate 100 is provided, form pad oxide 110 on described Semiconductor substrate 100 surfaces, form grinding barrier layer 120 on described pad oxide 110 surfaces, form hard mask layer 130 at described grinding barrier layer surface 120, form bottom anti-reflection layer 140 on described hard mask layer 130 surfaces, be formed for the photoresist layer 150 of excimer lithography on described bottom anti-reflection layer 140 surfaces.
Described Semiconductor substrate 100 comprises silicon substrate, germanium substrate, germanium silicon substrate, silicon carbide substrates, silicon-on-insulator substrate etc.In the present embodiment, described Semiconductor substrate 100 is silicon substrate.
The material of described pad oxide 110 is silica, and the material on described grinding barrier layer 120 is silicon nitride or silicon oxynitride, and the material of described hard mask layer 130 is silica or amorphous carbon.
Because the lattice constant of silicon nitride layer or silicon oxynitride layer and silicon substrate differs larger, directly form silicon nitride layer or silicon oxynitride layer meeting so that the interface that both contact can produce many defectives in described surface of silicon, affect the electric property of semiconductor structure, therefore, need to and grind formation pad oxide 110 between the barrier layer 120 at described silicon substrate 100.The technique that forms described pad oxide 110 is oxidation technology or chemical vapor deposition method.
Described grinding barrier layer 120 forms the grinding stop layer of fleet plough groove isolation structure as subsequent chemistry mechanical lapping, the thickness on described grinding barrier layer 120 defines the height that described fleet plough groove isolation structure is higher than semiconductor substrate surface, and described grinding barrier layer 120 is the single or multiple lift stacked structure.In the present embodiment, described grinding barrier layer 120 is silicon nitride layer.Owing to tended to grinding in the process of subsequent chemistry mechanical lapping insulating material, can remove the grinding barrier layer of segment thickness, therefore the thickness on described grinding barrier layer can not be too thin.If do not form described hard mask layer, photoresist layer and bottom anti-reflection layer are etched when wearing described grinding barrier layer owing to do not carve toward contact, follow-uply can only carry out etching to remaining grinding barrier layer, pad oxide, Semiconductor substrate as mask to grind the barrier layer, can cause the removal that is etched of the grinding barrier layer of segment thickness, therefore, in the present embodiment, also be formed with hard mask layer 130 on the surface of grinding barrier layer 120.Described hard mask layer 130 is different from the material that grinds barrier layer 120, take described hard mask layer 130 as mask remaining grinding barrier layer, pad oxide, Semiconductor substrate is carried out etching, and the thickness that grinds barrier layer 120 with protection is unaffected.In the present embodiment, described hard mask layer 130 is for utilizing the TEOS(tetraethoxysilane) silicon oxide layer that forms of depositing operation, described hard mask layer 130 can also conduct be avoided the barrier layer of the alkaline pollution of photoresist.
In other embodiments, described hard mask layer can also be as bottom anti-reflection layer or part bottom anti-reflection layer.
In other embodiments, also described hard mask layer be can not form, bottom anti-reflection layer or photoresist layer directly formed at described grinding barrier layer surface.
Described bottom anti-reflection layer 140 can be organic bottom antireflective layer or inorganic bottom anti-reflection layer.Described bottom anti-reflection layer 140 is single layer structure or multiple-level stack structure.In the present embodiment, the described bottom anti-reflection layer 140 multiple-level stack structure that is silicon nitride layer and silicon oxide layer.
In the present embodiment, described photoresist layer 150 for excimer lithography is photoresist corresponding to deep ultraviolet (DUV) photoetching, vacuum ultraviolet (VUV) (VUV) photoetching corresponding photoresist or photoresist corresponding to extreme ultraviolet (EUV) photoetching.Because molecular energy height and the easy damaged lens of excimer laser, so the energy of exposure should not be too large, and in order to improve the efficient of photoetching process, described photoresist layer 150 is chemical enhancement type photoetching gum (Chemically Amplified Resist, CAR).
Because excimer lithography (ArF) comprises deep ultraviolet (DUV), vacuum ultraviolet (VUV) (VUV) and extreme ultraviolet (EUV), wherein the wavelength of the exposure light source of deep ultraviolet is maximum, the wavelength of the exposure light source of extreme ultraviolet is minimum, corresponding, the thickness of the photoresist layer that described deep-UV lithography is corresponding is larger, and the thickness of the photoresist layer that extreme ultraviolet photolithographic is corresponding is minimum.Wherein, when described photoresist layer is photoresist layer corresponding to photoresist layer corresponding to vacuum ultraviolet (VUV) photoetching or extreme ultraviolet photolithographic, described photoresist layer is easier to be removed in etching process, so that utilize the sidewall that has the groove that forms technique formation now rough smooth, has knuckle.
Please refer to Fig. 3, utilize quasi-molecule laser source that described photoresist layer 150 is exposed, and to the exposure after photoresist layer develop, form patterned photoresist layer 151, have the first opening 155 in the described patterned photoresist layer 151, described the first opening 155 is corresponding to the position of the fleet plough groove isolation structure of follow-up formation.
Please refer to Fig. 4, please refer to Fig. 3 take described patterned photoresist layer 151() as mask, etching is carried out on 120 surfaces, grinding barrier layer to described bottom anti-reflection layer 140, hard mask layer 130 and segment thickness, form the 3rd opening 165, until described patterned photoresist layer 151 is etched.
In the present embodiment, when described patterned photoresist layer 151 is etched, only have the grinding barrier layer 120 of segment thickness to be etched.
In other embodiments, when described patterned photoresist layer is etched, only have the hard mask layer of segment thickness to be etched, described grinding barrier layer is not etched.
Former and later two etching technics that described patterned photoresist layer 151 is etched can adopt same etch step to form or adopt two different etch step to form.In the present embodiment, former and later two etching technics of being etched of described patterned photoresist layer 151 adopt same etch step to form.
Please refer to Fig. 5, please refer to Fig. 4 take described bottom anti-reflection layer 140(), hard mask layer 130 is mask, described the 3rd opening 165(be please refer to Fig. 4) bottom grinding barrier layer 120, pad oxide 110 carry out etching, form the second opening 160, so that the Semiconductor substrate 100 that described the second opening 160 runs through described hard mask layer 130, grinds barrier layer 120 and pad oxide 110 and partial depth, wherein, described the second opening 160 sidewalls have certain gradient.
Because the speed of dry etching and the density negative correlation of structure to be etched, compare with the zone that the second opening is sparse, the etch rate in the zone that the second opening is intensive is slower, so that when pad oxide corresponding to the second opening sparse region worn by quarter, the pad oxide that the second opening close quarters is corresponding is not carved fully to be worn, therefore, and in the present embodiment, form described the second opening and need to carry out over etching, until etching is removed the Semiconductor substrate 100 of partial depth.In the present embodiment, when forming the second opening 160, the degree of depth of the second opening 160 in the described Semiconductor substrate 100 is more than or equal to 100 dusts.
For so that insulating material can be filled completely described groove fully, the trenched side-wall that prior art forms all has certain gradient.And described the second opening 160 also has part to be positioned at Semiconductor substrate 100, and the described sidewall that is positioned at the second opening 160 of Semiconductor substrate 100 also needs to have specific gradient, so that described gradient equals the gradient of the final trenched side-wall that forms.And the CF that existing etching technics adopts
4, the gas such as He all can not independently form polymer at described opening sidewalls, so that the sidewall of the second opening 160 approaches is vertical.
In the present embodiment, the technique of the described bottom anti-reflection layer 140 of etching, hard mask layer 130, grinding barrier layer 120 and pad oxide 110 comprises: etching gas comprises SF
6And CH
2F
2, wherein, described SF
6Range of flow be 10sccm～30sccm, described CH
2F
2Range of flow be 30sccm～50sccm, the scope of reaction chamber temperature is 60 degrees centigrade～70 degrees centigrade, the scope of reaction chamber pressure is 5 millitorrs～15 millitorrs, and the power bracket of radio frequency power source is 200 watts～600 watts, and the power bracket in bias power source is 70 watts～200 watts.
Because the C/F of the etching gas of the embodiment of the invention is higher frequently, therefore in etching process, can form polymer at described the second opening sidewalls, make the sidewall of the second opening have gradient, make the sidewall slope degree of described the second opening that is positioned at Semiconductor substrate consistent with the sidewall slope degree of the final groove that forms, thereby the sidewall that guarantees the final fleet plough groove isolation structure that forms is smooth smooth.And utilize same etching technics that the Semiconductor substrate 100 of described bottom anti-reflection layer 140, hard mask layer 130, grinding barrier layer 120, pad oxide 110 and partial depth is carried out etching, saved the etching technics step.
In other embodiments, described etching gas can also comprise CHF
3, so that can form polymer at described the second opening sidewalls in the described etching process, make the sidewall of the second opening have gradient.And when etching formed described the second opening, the hard mask layer of described bottom anti-reflection layer and segment thickness was also removed simultaneously.
In other embodiments, the described pad oxide of the technique of the described bottom anti-reflection layer of etching, the technique of the described hard mask layer of etching, the described grinding of etching barrier layer and etching adopts different etching technics.In other embodiment, also can adopt first CF
4, the gas such as He carries out etching to bottom anti-reflection layer, hard mask layer, etch rate is very fast; Then adopt and comprise SF
6And CH
2F
2Etching gas carry out etching to grinding barrier layer and pad oxide, until pad oxide corresponding to all the second openings worn by quarter, and etching is removed the Semiconductor substrate of partial depth.
In other embodiments, can not form simultaneously polymer when the described bottom anti-reflection layer of etching, hard mask layer, grinding barrier layer, so that the described hard mask layer of described etching, the sidewall that grinds the second opening corresponding to barrier layer approach is vertical, be conducive to control the size of the second opening.
Please refer to Fig. 6, take described hard mask layer 130 as mask, described the second opening 160(be please refer to Fig. 5) Semiconductor substrate 100 that exposes carries out etching, forms the groove 170 of sidewall slope.
In the present embodiment, described etching technics is plasma etch process, and etching gas comprises at least: Cl
2, HBr, O
2, CF
4Deng, wherein, described Cl
2Range of flow be 10sccm～30sccm, the range of flow of described HBr is 100sccm～200sccm, described O
2Range of flow be 3sccm～9sccm, described CF
4Range of flow be 10sccm～30sccm.Owing to utilize above-mentioned etching technics to form polymer at trenched side-wall, therefore the sidewall of described groove 170 has certain gradient.
Please refer to Fig. 7, please refer to Fig. 6 at described groove 170() in and hard mask layer 130 surface form insulating material 180.
The material of described insulating material 180 is silica, silicon nitride or both combinations.In the present embodiment, utilize thermal oxidation technology to form one deck silicon oxide layer at described trenched side-wall first, utilize chemical vapor deposition method to form silicon oxide layer with hard mask layer 130 surfaces in described groove 170 again, the described silicon oxide layer that utilizes chemical vapor deposition method to form is filled completely described groove 170 fully.
Please refer to Fig. 8, described insulating material 180(be please refer to Fig. 7), hard mask layer 130(please refer to Fig. 7) carry out cmp, please refer to Fig. 7 until end at grinding barrier layer 120(), the insulating material that is positioned at described groove forms fleet plough groove isolation structure 185.After forming described fleet plough groove isolation structure 185, utilize wet-etching technology to remove described grinding barrier layer 120.
Although the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (10)
1. the formation method of a fleet plough groove isolation structure is characterized in that, comprising:
Semiconductor substrate is provided, forms pad oxide at described semiconductor substrate surface, form on described pad oxide surface and grind the barrier layer, be formed for the photoresist layer of excimer lithography on described grinding barrier layer;
Utilize excimer lithography technique that described photoresist layer is carried out exposure imaging, form the first opening;
Take photoresist layer with first opening as mask, etching is carried out on described grinding barrier layer and pad oxide, form the second opening, described the second opening runs through the Semiconductor substrate of described grinding barrier layer, pad oxide and partial depth, wherein, form polymer at the second opening sidewalls in the time of the Semiconductor substrate of the described pad oxide of etching and partial depth, so that the second opening sidewalls in the Semiconductor substrate has certain gradient;
The Semiconductor substrate that described the second opening exposes is carried out etching, form the groove of sidewall slope;
In described groove, form insulating material with the grinding barrier layer, and described insulating material is carried out cmp, grind the barrier layer until end at, form fleet plough groove isolation structure.
2. the formation method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that, the technological parameter of the described pad oxide of etching comprises: etching gas comprises SF
6And CH
2F
2, wherein, described SF
6Range of flow be 10sccm～30sccm, described CH
2F
2Range of flow be 30sccm～50sccm, the scope of reaction chamber temperature is 60 degrees centigrade～70 degrees centigrade, the scope of reaction chamber pressure is 5 millitorrs～15 millitorrs, and the power bracket of radio frequency power source is 200 watts～600 watts, and the power bracket in bias power source is 70 watts～200 watts.
3. the formation method of fleet plough groove isolation structure as claimed in claim 2, it is characterized in that, by adjusting the C/F ratio of described etching gas, be controlled at the amount of the polymer of the second opening sidewalls formation, the sidewall slope degree of the second opening in the control Semiconductor substrate is so that the sidewall slope degree of the second opening in the Semiconductor substrate is consistent with the sidewall slope degree of groove.
4. the formation method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that, the material on described grinding barrier layer is silicon nitride or silicon oxynitride.
5. the formation method of fleet plough groove isolation structure as claimed in claim 1, it is characterized in that, also comprise: between described grinding barrier layer and photoresist layer, form hard mask layer, after forming the second opening, take described hard mask layer as mask, the Semiconductor substrate that described the second opening exposes is carried out etching, form the groove of sidewall slope, and behind the formation insulating material, utilize cmp to remove insulating material and the hard mask layer that grinds on the barrier layer.
6. the formation method of fleet plough groove isolation structure as claimed in claim 5 is characterized in that, the material of described hard mask layer is silica or amorphous carbon.
7. such as the formation method of claim 1 or 5 described fleet plough groove isolation structures, it is characterized in that, adopt the described hard mask layer of same etching technics etching, grind barrier layer and pad oxide.
8. such as the formation method of claim 1 or 5 described fleet plough groove isolation structures, it is characterized in that the described pad oxide of the described hard mask layer of etching, the described grinding of etching barrier layer and etching adopts different etching technics.
9. the formation method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that, when forming the second opening, the degree of depth of the second opening in the described Semiconductor substrate is more than or equal to 100 dusts.
10. the formation method of fleet plough groove isolation structure as claimed in claim 1, it is characterized in that, also comprise: form bottom anti-reflection layer at described grinding barrier layer surface, be formed for the photoresist layer of excimer lithography on described bottom anti-reflection layer surface, described photoresist layer is carried out exposure imaging, after forming the first opening, etching is removed the bottom anti-reflection layer that is exposed by the first opening.
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