CN102074495B - Forming method for shallow trench isolation (STI) - Google Patents
Forming method for shallow trench isolation (STI) Download PDFInfo
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- CN102074495B CN102074495B CN 200910199227 CN200910199227A CN102074495B CN 102074495 B CN102074495 B CN 102074495B CN 200910199227 CN200910199227 CN 200910199227 CN 200910199227 A CN200910199227 A CN 200910199227A CN 102074495 B CN102074495 B CN 102074495B
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Abstract
The invention provides a forming method for shallow trench isolation (STI). The method comprises the following steps of: providing a semiconductor base where a barrier layer is etched, and providing a photo mask pattern on the etched barrier layer; performing a first etching on the etched barrier layer by using the photo mask pattern as a mask to consequently form a V-shaped first opening on the etched barrier layer; performing a second etching along with the first opening on the etched barrier layer by using the photo mask pattern as a mask till the semiconductor base is exposed to form a V-shaped second opening communicated with the first opening, wherein the inclination angle of the side wall of the second opening is smaller than that of the side wall of the first opening; etching on the semiconductor base by using the etched barrier layer as a mask to form a slot in the semiconductor base; and filling the slot with insulating medium. The method reduces the probability of cracked juncture between the etched barrier layer and the semiconductor base in the STI process.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly the formation method of a kind of STI.
Background technology
Along with semiconductor technology enters the deep-submicron epoch, the following element of 0.13 μ m is for example in the cmos device, and the isolation between nmos pass transistor and the PMOS transistor all adopts STI (shallow trench isolation from) technology to form.
The formation method of traditional STI generally includes the following step: at first, provide the semiconductor-based end, form etching barrier layer at the semiconductor-based end; Then, form light mask pattern at described etching barrier layer, make the subregion of described etching barrier layer be exposed; Etching is carried out at the semiconductor-based end to etching barrier layer and etching barrier layer lower floor, forms V-groove at described etching barrier layer with at described the semiconductor-based end; Then, in described groove, fill dielectric, form STI.
For example for being provided in the american documentation literature of " US6713780B2 ", a kind of polysilicon layer that utilizes does the method that etching barrier layer forms STI in document number, referring to figs. 1 to Fig. 2, comprise step: form etching barrier layer 20 on substrate 10 surfaces, it is the laminated construction of oxide skin(coating) 20a-polysilicon layer 20b-silicon nitride layer 20c from top to bottom, wherein nitride layer 20c is hard mask layer, and polysilicon layer 20b is resilient coating; Be etched in substrate 10 and the etching barrier layer 20 and form groove 30; The method that adopts thermal oxidation is growing silicon oxide layer 40 in the sidewall of groove 30 and substrate; To described groove 30 filled medias 50, and remove etching barrier layer 20, form STI.
Along with the development of semiconductor technology, size of devices is more and more littler, and therefore etching barrier layer 20 is also more and more thinner when forming STI.Fig. 3 utilizes the contrast schematic diagram that utilizes the conventional method etching before conventional method etching and the etching barrier layer attenuate behind the etching barrier layer attenuate, wherein be shown in dotted line the etching result before the etching barrier layer attenuate.With reference to figure 3, because the characteristic size (CD) of exposure on photoresist layer fixed, if therefore etching technics is constant, then the sidewall slope degree of the groove that forms in etching barrier layer and substrate is constant, because etching barrier layer attenuate, therefore the area of base of etching barrier layer exposure will increase like this, and the CD of the sti trench groove that forms in substrate will increase, and so just can not satisfy the demand of manufacturing process.Therefore in the conventional method, for the characteristic size of the sti trench groove that guarantees to form constant, just need to increase the inclined degree (angle of V-groove sidewall and bottom surface is reduced) of V-groove sidewall in the etching barrier layer, compensate because the etching barrier layer attenuate brings problem.
As can be seen from Figure 3, the inclined degree of trenched side-wall increases the problem bring and is in the etching barrier layer: because the trenched side-wall inclined degree of the inclined degree of the V-groove sidewall in the etching barrier layer in the substrate, therefore on the trenched side-wall of etching barrier layer and substrate intersection salient angle appears, dotted line circle 60 places as shown in Figure 3, bursting apart in the easy like this place that causes that in subsequent technique etching barrier layer and substrate are had a common boundary, thereby influences the reliability of the device of follow-up formation.
Summary of the invention
The technical problem that the present invention solves is to reduce to form the problem that etching barrier layer and intersection of the semiconductor-based end burst apart in the STI process.
In order to address the above problem, the invention provides the formation method of a kind of STI, comprise step:
The semiconductor-based end, be provided, have etching barrier layer at semiconductor-based the end, have light mask pattern at described etching barrier layer;
Utilize light mask pattern to do mask, described etching barrier layer is carried out first etching, thereby in etching barrier layer, form V-type first opening;
Utilize light mask pattern to do mask, along described first opening described etching barrier layer is carried out second etching, up to exposing at the semiconductor-based end, form and V-type second opening of first opening perforation, the inclination angle of described second opening sidewalls is less than the inclination angle of first opening sidewalls;
Utilize described etching barrier layer to do mask, to carrying out etching in the described semiconductor-based end, thereby in the semiconductor-based end, form groove;
Utilize dielectric to fill described groove.
Preferably, described etching barrier layer comprises nitride layer.
Preferably, the degree of depth of described first opening is 1/3 to 2/3 of described etching stopping layer thickness.
Preferably, the degree of depth of described second opening is 1/3 to 2/3 of described etching stopping layer thickness.
Preferably, in the etching gas that utilizes in described first etching mol ratio of hydrogen ion and fluorine ion greater than the mol ratio of hydrogen ion and fluorine ion in the etching gas that utilizes in described second etching.
Preferably, the etching gas of described first etching comprises CF
4And CH
2F
2, CF wherein
4And CH
2F
2Flow-rate ratio is 1: 1 to 1: 4.
Preferably, the etching gas of described second etching comprises CF
4And CHF
3, CF wherein
4And CHF
3Flow-rate ratio is 4: 1 to 1: 1.
Preferably, the mol ratio to hydrogen ion and fluorine ion in the etching gas that utilizes in the etching of semiconductor substrate and second etching is identical.
Preferably, the described semiconductor-based end, also comprise silicon oxide layer.
Preferably, the angle of inclination of described first opening sidewalls be 45 the degree to 85 the degree, the angle of inclination of described second opening sidewalls and described trenched side-wall be 10 the degree to 45 the degree.
Compared with prior art, the present invention mainly has the following advantages:
The present invention divides the step of etching etching barrier layer for two steps by utilizing, the second opening sidewalls inclination angle that the first opening sidewalls inclination angle that the first step forms formed greater than second step, therefore compare with conventional art, expose the etching barrier layer of same size at light mask pattern, under the identical situation of the CD in the zone at the semiconductor-based end that etching barrier layer exposes, the invention enables the etching barrier layer of trenched side-wall and the intersection salient angle at the semiconductor-based end less.Therefore like this in subsequent technique, the cmp of filling groove for example is not easy to cause that the place that etching barrier layer and substrate are had a common boundary bursts apart, thereby has improved the reliability of the device of follow-up formation.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing by actual size equal proportion convergent-divergent, focus on illustrating purport of the present invention.
Fig. 1 to Fig. 2 is the schematic diagram of existing a kind of STI formation method;
Fig. 3 utilizes the contrast schematic diagram that utilizes the conventional method etching before conventional method etching and the etching barrier layer attenuate behind the etching barrier layer attenuate;
Fig. 4 is the flow chart of STI formation method of the present invention;
Fig. 5 to Fig. 8 is the schematic diagram of STI formation method of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, when the embodiment of the invention is described in detail in detail; for ease of explanation; the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fig. 4 is the flow chart of STI formation method of the present invention; Fig. 5 to Fig. 8 is the schematic diagram of STI formation method of the present invention.Below in conjunction with Fig. 4 to Fig. 8 STI formation method of the present invention is described, comprise the following steps:
S10: the semiconductor-based end is provided, has etching barrier layer at semiconductor-based the end, have light mask pattern at described etching barrier layer.
With reference to figure 5, concrete, the silicon that the semiconductor-based end 110 can be monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe) they also can be silicon-on-insulators (SOI), the material that perhaps can also comprise other, for example indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide.Though in these several examples of having described the material that can form the semiconductor-based end 110, any material that can be used as the semiconductor-based end all falls into the spirit and scope of the present invention.
In a kind of preferred implementation; the described semiconductor-based end 110, comprise substrate 110a and the silicon oxide layer 110b that is positioned on the substrate 110a; described silicon oxide layer 110b utilizes the mode of thermal oxide growth to form; its compact structure, can be in forming the step of etching barrier layer the substrate 110a of its lower floor of protection.
Continuation forms etching barrier layer 120 at the semiconductor-based end 110, in a specific implementation with reference to figure 5, etching barrier layer 120 comprises nitride layer, for example being the laminated construction of nitride layer and other rete, perhaps is nitride layer, and wherein nitride can be silicon nitride.For example form silicon nitride layer method can for: 400 ℃ to 600 ℃ of depositing temperatures, for example 450 ℃, 500 ℃, 550 ℃, the reactant of utilization is: SiH
2CL
2And NH
3, SiH wherein
2CL
2And NH
3Flow-rate ratio be 1: 5 to 1: 10, for example 1: 6,1: 7,1: 8,1: 9, forming thickness was the silicon nitride layer of 800 dust to 1500 dusts.
At etching barrier layer 120 surperficial coating thicknesss be
The photomask layer, it can comprise bottom anti-reflection layer (BARC) and be positioned at photoresist layer on the bottom anti-reflection layer (BARC).Bottom anti-reflection layer and photoresist layer can utilize spin coating (spin on) technology to form.Then, utilize the above-mentioned photomask layers of art pattern CADization such as conventional photoetching process is for example exposed, development, cleaning, form light mask pattern 130.
S20: utilize light mask pattern 130 to do mask, described etching barrier layer 120 is carried out first etching, thereby in etching barrier layer, form V-type first opening.
With reference to figure 6, concrete, can utilize easy generation than the etching gas of heteropolymer, the hydrogen fluorine of etching gas is more more than the polymer that generates in the more big then etching process, for example in the etching gas mol ratio of hydrogen ion and fluorine ion greater than 1.Because when generating the more gas etching of polymer, can generate more polymer at the first opening 120a sidewall, thereby make that the V-type first opening 120a sidewall slope degree is bigger, just the angle of inclination of first opening sidewalls (opening sidewalls and perpendicular to the angle of bottom surface) θ 1 increases, and for example is that 45 degree are to 85 degree.Like this can be so that under the identical situation of the area size of the etching barrier layer 120 that light mask pattern 130 exposes, the bottom CD of the opening that forms in etching barrier layer reduces.
Described etching can utilize method well known to those skilled in the art to carry out etching, for example utilizes dry plasma etch.Specifically comprise: select inductively coupled plasma type etching apparatus for use, in etching process, for example etching gas comprises He and CF
4And CH
2F
2Deng fluoro-gas, CF
4And CH
2F
2Flow-rate ratio is 1: 1 to 1: 4, for example 1: 2,1: 3.Feed above-mentioned gas in reative cell simultaneously, wherein argon gas He plays the effect of dilution etching gas, and its flow is 100sccm～500sccm.Play in the gas of corrasion CF
4Flow be 10sccm～200sccm; CH
2F
2Flow be 10sccm～100sccm.The power output that in the reative cell with described gas ionization is the radio frequency power source of plasma is 100W～1000W, and the power output of bias voltage source is 100W～1000W.Pressure in the reative cell is set to 5mTorr～20mTorr.The process of above-mentioned plasma etching is a kind of anisotropic etching, it is the inclined-plane that the acting in conjunction of etching gas and diluent gas makes the sidewall of the first opening 120a after the etching, and angle of inclination (opening sidewalls and perpendicular to the angle of bottom surface) is bigger, and the degree of depth of the first opening 120a can be 1/3 to 2/3 of etching barrier layer.Described etching technics can also carry out in other etching apparatus, as capacitance coupling plasma type etching apparatus, inductive couple plasma etching apparatus.
S30: utilize light mask pattern 130 to do mask, along the described first opening 120a described etching barrier layer 120 is carried out second etching, up to exposing the semiconductor-based end, the second opening 120b that formation and the first opening 120a connect, the inclination angle of the described second opening 120b sidewall is less than the inclination angle of the first opening 120a sidewall.
Continuation is with reference to figure 6, and is concrete, can utilize the etching gas of the less polymer of easy generation, for example in the etching gas mol ratio of hydrogen ion and fluorine ion less than 1.Because when generating polymer less gas etching, can generate less polymer at the second opening 120b sidewall, thereby make that the V-type second opening sidewalls inclined degree is less, just the tiltangle 2 of the second opening 120b sidewall reduces, thereby makes the sidewall draft angles θ 2 of the second opening 120b less than the sidewall draft angles θ 1 of the first opening 120a.Preferred angle of inclination (opening sidewalls and perpendicular to the angle of bottom surface) is that 10 degree are to 45 degree.
Described etching can utilize method well known to those skilled in the art to carry out etching, for example utilizes dry plasma etch.Specifically comprise: select inductively coupled plasma type etching apparatus for use, in etching process, for example etching gas can comprise He, N
2And CF
4And CHF
3Deng fluoro-gas, CF
4And CHF
3Flow-rate ratio is 4: 1 to 1: 1, for example 3: 1,2: 1.In a specific implementation, in reative cell, feed He simultaneously, its flow is 100sccm～500sccm.Play in the gas of corrasion CF
4Flow be 10sccm～200sccm; CHF
3Flow be 100sccm～200sccm.The power output that in the reative cell with described gas ionization is the radio frequency power source of plasma is 100W～1000W; The power output of rf bias power source is 100W～1000W, and the pressure in the reative cell is set to 5mTorr～10mTorr.The process of above-mentioned plasma etching is a kind of anisotropic etching, and it is the inclined-plane that the acting in conjunction of etching gas and diluent gas makes the sidewall of second opening after the etching, and preferred angle of inclination is that 10 degree are to 45 degree.The degree of depth of second opening can be 1/3 to 2/3 of etching stop layer thickness.Described etching technics can also carry out in other etching apparatus, as capacitance coupling plasma type etching apparatus, inductive couple plasma etching apparatus.
S40: utilize described etching barrier layer to do mask, to carrying out etching in the described semiconductor-based end, thereby in the semiconductor-based end, form groove.
With reference to figure 7, remove light mask pattern, utilize etching barrier layer to do mask, etching is carried out in the semiconductor substrate, described etching can utilize method well known to those skilled in the art to carry out etching, for example utilizes dry plasma etch.In the present embodiment, the mol ratio to hydrogen ion and fluorine ion in the etching gas that utilizes in the etching of semiconductor substrate and second etching is identical.Specifically comprise: select inductively coupled plasma type etching apparatus for use, in etching process, for example etching gas comprises Ar and CF
4, C
2F
6And CHF
3Deng fluoro-gas.Feed above-mentioned gas in reative cell simultaneously, wherein Ar plays the effect of dilution etching gas.Play in the gas of corrasion CF
4Flow be 10sccm～100sccm; C
2F
6Flow be 10sccm～100sccm; CHF
3Flow be 10sccm～100sccm.The power output that in the reative cell with described gas ionization is the radio frequency power source of plasma is 50W～1000W; The power output of rf bias power source is 50W～1000W.Pressure in the reative cell is set to 5mTorr～20mTorr.The process of above-mentioned plasma etching is a kind of anisotropic etching, and it is the inclined-plane that the acting in conjunction of etching gas and diluent gas makes the sidewall of the groove 110c after the etching, and the degree of depth of groove 110c can be 2000 dusts～4000 dusts.Described etching technics can also carry out in other etching apparatus, as capacitance coupling plasma type etching apparatus, inductive couple plasma etching apparatus.
In another embodiment, also can not remove light mask pattern, utilize light mask pattern and etching barrier layer to do mask.
In the present invention because the step of etching etching barrier layer was divided for two steps, the second opening sidewalls inclination angle that the first opening sidewalls inclination angle that the first step forms formed greater than second step, therefore compare with conventional art, expose the etching barrier layer of same size at light mask pattern, under the identical situation of the CD in the zone at the semiconductor-based end that etching barrier layer exposes, the invention enables the etching barrier layer of trenched side-wall and the intersection salient angle at the semiconductor-based end less.Therefore like this in subsequent technique, the cmp of filling groove for example is not easy to cause that the place that etching barrier layer and substrate are had a common boundary bursts apart, thereby has improved the reliability of the device of follow-up formation.
S50: utilize the dielectric filling groove.
With reference to figure 8, can utilize HDP-CVD technology deposit dielectric 160, what the dielectric material can be in silicon dioxide, fluorine silex glass, unadulterated silicate glass (USG) and the positive tetraethyl orthosilicate is a kind of.Then, utilize cmp (CMP) technology, to dielectric 160 planarizations, making dielectric 160 upper surfaces is flat surfaces.Then, remove described etching barrier layer, form STI.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (9)
1. the formation method of a STI is characterized in that, comprises step:
The semiconductor-based end, be provided, have etching barrier layer at semiconductor-based the end, have light mask pattern at described etching barrier layer;
Utilize light mask pattern to do mask, described etching barrier layer is carried out first etching, thereby form V-type first opening in etching barrier layer, the angle of inclination of described first opening sidewalls is that 45 degree are to 85 degree;
Utilize light mask pattern to do mask, along described first opening described etching barrier layer is carried out second etching, up to exposing the semiconductor-based end, V-type second opening that formation and first opening connect, the inclination angle of described second opening sidewalls is less than the inclination angle of first opening sidewalls, and the angle of inclination of described second opening sidewalls is that 10 degree are to 45 degree;
Utilize described etching barrier layer to do mask, to carrying out etching in the described semiconductor-based end, thereby in the semiconductor-based end, form groove;
Utilize dielectric to fill described groove.
2. the formation method of STI according to claim 1 is characterized in that, described etching barrier layer comprises nitride layer.
3. the formation method of STI according to claim 1 is characterized in that, the degree of depth of described first opening is 1/3 to 2/3 of described etching stopping layer thickness.
4. the formation method of STI according to claim 1 is characterized in that, the degree of depth of described second opening is 1/3 to 2/3 of described etching stopping layer thickness.
5. the formation method of STI according to claim 1 is characterized in that, the mol ratio of hydrogen ion and fluorine ion is greater than the mol ratio of hydrogen ion and fluorine ion in the etching gas that utilizes in described second etching in the etching gas that utilizes in described first etching.
6. the formation method of STI according to claim 5 is characterized in that, the etching gas of described first etching comprises CF
4And CH
2F
2, CF wherein
4And CH
2F
2Flow-rate ratio is 1:1 to 1:4.
7. the formation method of STI according to claim 5 is characterized in that, the etching gas of described second etching comprises CF
4And CHF
3, CF wherein
4And CHF
3Flow-rate ratio is 4:1 to 1:1.
8. the formation method of STI according to claim 1 is characterized in that, and is identical to the mol ratio of hydrogen ion and fluorine ion in the etching gas that utilizes in the etching of semiconductor substrate and second etching.
9. the formation method of STI according to claim 1 is characterized in that, the described semiconductor-based end comprises substrate and the silicon oxide layer that is positioned on the substrate.
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| CN103021924A (en) * | 2012-12-21 | 2013-04-03 | 上海宏力半导体制造有限公司 | Formation method of STI (shallow trench isolation) structure |
| CN105448704B (en) * | 2014-09-30 | 2018-08-10 | 中芯国际集成电路制造(上海)有限公司 | Lithographic method |
| US9613848B2 (en) * | 2015-02-12 | 2017-04-04 | Infineon Technologies Ag | Dielectric structures with negative taper and methods of formation thereof |
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| US7091105B2 (en) * | 2002-10-28 | 2006-08-15 | Hynix Semiconductor Inc. | Method of forming isolation films in semiconductor devices |
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