CN113808934B - CMP optimization method - Google Patents
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- CN113808934B CN113808934B CN202111058335.5A CN202111058335A CN113808934B CN 113808934 B CN113808934 B CN 113808934B CN 202111058335 A CN202111058335 A CN 202111058335A CN 113808934 B CN113808934 B CN 113808934B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
Abstract
The invention relates to the technical field of micro-nano device preparation, in particular to a CMP (chemical mechanical polishing) optimization method. Before CMP processing of a sample, carrying out alignment once, and etching grooves on two sides of a target recess, wherein the specific process is that after a filling material is deposited on the sample, carrying out alignment once, including exposure, development and etching, and finally realizing that the grooves with specific sizes are arranged on two sides of the target recess; through the grooves etched on the two sides of the target waveguide, the target is prevented from sinking and transferring to the sample layer through the design of the grooves, so that after the sample is subjected to CMP treatment, the upper surface of the sample is relatively flattened, the problem of sinking and transferring after the traditional CMP treatment is avoided, the performance of a device is optimized, the relatively flat upper surface is obtained, and a foundation is provided for subsequent design and processing of the upper surface.
Description
Technical Field
The invention relates to the technical field of micro-nano device preparation, in particular to a CMP (chemical mechanical polishing) optimization method.
Background
CMP, collectively known as Chemical Mechanical Polishing, is a high-end upgrade to common Polishing technology. The integrated circuit manufacturing process is better than building a house, and when one floor is built, the floor needs to be level and neat enough, another floor can be built above the building, otherwise, the floor is uneven, the overall reliability is affected, and the technology for making the floor flat integrally is a chemical mechanical polishing technology in the integrated circuit manufacturing.
CMP is a process technique for smoothing and highly planarizing the surface of an integrated circuit device by organically combining the physical polishing action of nano-particles with the chemical etching action of a polishing solution. In the current integrated circuit, the surface of a wafer is polished with precision mainly by a CMP process, and the ultrahigh flatness with the global flatness drop of 100A-1000A degrees (equivalent to the atomic scale of 10-100 nm) can be achieved.
CMP processes are often accompanied by both physical reactions, physical polishing, and chemical reactions, which typically include oxidation, mild water and reaction, and electrochemical reactions. In the micro-nano processing process, a sample filled by CVD is often uneven, and due to the simultaneous action of physical and chemical reactions in the polishing process, depressions on the surface of the sample are often transferred downwards in the CMP process, which is not consistent with the expected design and also greatly affects the performance of a device.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a CMP optimization method, so that the depression of a sample is not transferred downwards after the sample is subjected to CMP treatment, and the planarization of the upper surface of the sample is ensured.
In order to solve the technical problems, the invention adopts the technical scheme that: a CMP optimization method, comprising the steps of:
s1, spin coating: spin-coating electronic glue on the surface of a sample to be subjected to CMP treatment;
s2, electron beam exposure: after processing the layout needing electron beam exposure, carrying out electron beam exposure on the sample, and developing to obtain a required electron glue layer; grooves extending to the sample layer are formed in the electronic glue layer, and the grooves are arranged beside the target recess at intervals;
s3, hardening the film: placing the developed sample on a hot plate, and after the temperature is set, carrying out rapid thermal reflux on the electronic glue layer by using the hot plate;
s4, reactive ion etching: coating vacuum grease on the back of the reflowed sample, placing the reflowed sample on a carrying disc, putting the reflowed sample and the carrying disc into a reactive ion etching machine together, and setting a specific etching menu and etching time; in the etching process, because the surface of the sample is partially covered with the electronic glue layer, the electronic glue layer has strong etching resistance, the sample cannot be etched, and the area without the electronic glue layer on the surface of the sample, namely the area provided with the groove, is etched, so that the groove is transferred from the electronic glue layer to the sample layer after the etching is finished;
s5, removing the photoresist: placing the etched sample into a reactive ion etcher, setting a photoresist removing menu,
starting to remove the photoresist, and removing the residual electronic photoresist layer of the sample;
s6, CMP: and (3) fixing the sample with the electronic glue pattern layer removed in a groove of a sample carrying disc of a chemical physical polishing machine, polishing according to set polishing conditions, and cleaning the sample after polishing.
In the invention, before the sample is subjected to CMP treatment, the sample is firstly subjected to alignment once, grooves are etched on two sides of a target depression, and the specific process is that after the sample deposits a filling material, the sample is subjected to alignment once, including exposure, development and etching, so that the grooves with specific sizes are formed on two sides of the target depression; through the concave both sides sculpture recess of target, through the design of recess, avoided the sunken sample layer transmission to of target for after carrying out CMP to the sample, the upper surface of sample is the planarization relatively, has avoided the sunken problem of transmitting after traditional CMP processing, has optimized the device performance, has obtained the upper surface of relatively flat simultaneously, provides the basis for follow-up ability at last surface design processing.
In one embodiment, the step S2 includes:
s21, fixing a sample coated with electronic glue in a spinning mode on a sample table exposed by an electron beam, adjusting the height of the sample table through the assistance of a distance measuring instrument to enable the sample to be in a horizontal state on the sample table, and recording the position coordinates of the sample on the sample table through a coordinate meter; then putting the sample stage into an electron beam exposure sample feeding cavity;
s22, processing a layout to be exposed through Beamer and electron beam exposure control software, wherein the final target effect of the layout is to etch grooves on two sides of a target recess of a sample layer; then, obtaining a job file controlled by an electron beam exposure instrument; while inputting the coordinates of the position of the sample recorded in step S21 in the file; then the sample stage is sent into the direct-writing cavity from the sample sending cavity; starting electron beam exposure after the feeding is finished;
and S23, after exposure is finished, taking down the sample from the sample table, and processing the sample by using a corresponding developing solution to obtain the required electronic glue layer.
In one embodiment, the sample to be subjected to CMP processing is a waveguide structure processed by a damascene process.
In one embodiment, the grooves on the electronic glue layer are located on two sides of the target recess, or an annular groove is formed around the target recess.
In one embodiment, the sample sequentially comprises a silicon substrate layer, a silicon dioxide layer and a silicon nitride layer from bottom to top; the silicon nitride layer is a polishing layer to be CMP.
In one embodiment, the electronic glue is positive glue with the model number of AR-P6200.13.
In one embodiment, the thickness of the electronic glue layer is 350 nm-450 nm.
In one embodiment, the temperature for performing the rapid thermal reflow on the electronic glue layer is 80-300 ℃.
In one embodiment, the polishing conditions include sample carrier plate rotation speed, abrasive plate rotation speed, pressure, polishing solution flow rate, and polishing time.
In one embodiment, in step S6, the sample is sequentially placed into acetone, isopropanol, and deionized water, and then sequentially subjected to ultrasound for a certain time to clean the sample.
Compared with the prior art, the beneficial effects are: according to the CMP optimization method provided by the invention, after the sample is subjected to CMP treatment, the upper surface of the sample is flattened, the problem of depression transfer after the traditional CMP treatment is avoided, the performance of a device is optimized, and meanwhile, the flat upper surface is obtained, so that a foundation is provided for subsequent design and processing of the upper surface.
Drawings
FIG. 1 is a schematic process flow diagram of the present invention.
FIG. 2 is a schematic diagram of the structure of a sample to be processed according to the present invention.
FIG. 3 is a schematic structural diagram of a sample to be processed after grooves are etched on two sides of a target recess.
FIG. 4 is a schematic diagram of the experimental results of the sample to be processed after grooves are etched on two sides of the target recess.
FIG. 5 is a graphical representation of the results of a CPM treatment of a sample by the method of the present invention.
Detailed Description
The drawings are for illustration purposes only and are not to be construed as limiting the invention; for the purpose of better illustrating the present embodiments, certain elements of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted. The positional relationships depicted in the drawings are for illustrative purposes only and are not to be construed as limiting the invention.
As shown in fig. 1, a CMP optimization method includes the following steps:
s1, spin coating: spin-coating electronic glue on the surface of a sample to be subjected to CMP treatment;
s2, electron beam exposure: after processing the layout needing electron beam exposure, carrying out electron beam exposure on the sample, and developing to obtain a required electron photoresist layer; grooves extending to the sample layer are formed in the electronic glue layer, and the grooves are arranged beside the target recess at intervals;
s3, hardening the film: placing the developed sample on a hot plate, and after the temperature is set, carrying out rapid thermal reflux on the electronic glue layer by using the hot plate;
s4, reactive ion etching: coating vacuum grease on the back of the reflowed sample, placing the reflowed sample on a carrying disc, putting the reflowed sample and the carrying disc into a reactive ion etching machine together, and setting a specific etching menu and etching time; in the etching process, because the surface of the sample is partially covered with the electronic glue layer, the electronic glue layer has strong etching resistance, the sample cannot be etched, and the area without the electronic glue layer on the surface of the sample, namely the area provided with the groove, is etched, so that the groove is transferred from the electronic glue layer to the sample layer after the etching is finished;
s5, removing the photoresist: placing the etched sample into a reactive ion etcher, starting to remove the photoresist after a photoresist removing menu is set, and removing the residual electronic photoresist layer of the sample;
s6, CMP: and (3) fixing the sample with the electronic glue pattern layer removed in a groove of a sample carrying disc of a chemical physical polishing machine, polishing according to set polishing conditions, and cleaning the sample after polishing.
In the invention, before the sample is subjected to CMP treatment, the sample is firstly subjected to alignment once, grooves are etched on two sides of a target recess, and the specific process is that after the sample deposits a filling material, the alignment once, including exposure, development and etching, is carried out, and finally the grooves with specific sizes are formed on two sides of the target recess; through the concave both sides sculpture recess of target, through the design of recess, avoided the sunken sample layer transmission to of target for after carrying out CMP to the sample, the upper surface of sample is the planarization relatively, has avoided the sunken problem of transmitting after traditional CMP processing, has optimized the device performance, has obtained the upper surface of relatively flat simultaneously, provides the basis for follow-up ability at last surface design processing.
In one embodiment, the step S2 includes:
s21, fixing a sample coated with the electronic glue in a spinning mode on a sample table exposed by an electron beam, adjusting the height of the sample table through the assistance of a distance measuring instrument to enable the sample to be in a horizontal state on the sample table, and recording position coordinates of the sample on the sample table through a coordinate meter; then putting the sample stage into an electron beam exposure sample feeding cavity;
s22, processing a layout to be exposed through Beamer and electron beam exposure control software, wherein the final target effect of the layout is to etch grooves on two sides of a target recess of a sample layer; then, obtaining a job file controlled by an electron beam exposure instrument; while inputting the coordinates of the position of the sample recorded in step S21 in the file; then the sample stage is sent into the direct-writing cavity from the sample sending cavity; starting electron beam exposure after the feeding is finished;
and S23, after exposure is finished, taking down the sample from the sample table, and processing the sample by using a corresponding developing solution to obtain the required electronic glue layer.
In one embodiment, the sample to be subjected to CMP processing is a waveguide structure processed by a damascene process. It should be noted that, it is easy for those skilled in the art to think that the samples processed by other processes are processed by the CMP optimization processing method of the present invention to obtain a smooth polished surface, and this embodiment only shows a preferred sample processing manner, and samples obtained by other methods are processed by the method of the present invention, and it is within the scope of the present invention.
In one embodiment, the grooves on the electronic glue layer are located on two sides of the target recess, or an annular groove is formed around the target recess. In the invention, different layout designs can be adopted for different sample structures of the layout of the electronic glue coating and the structural oil pipe of the sample to be treated by CMP, as long as the final result is that grooves are etched on the periphery or two sides of the target depression, and the target depression is prevented from being transferred to the sample layer during the CMP treatment through the grooves.
In one embodiment, the sample sequentially comprises a silicon substrate layer, a silicon dioxide layer and a silicon nitride layer from bottom to top; the silicon nitride layer is a polishing layer to be CMP.
In one embodiment, the electronic glue is positive glue with the model number of AR-P6200.13. The selection of the positive glue is only a preferable scheme of the embodiment, and for different samples and different layouts, the proper electronic glue can be selected according to the specific layout, and is not limited to the positive glue.
In one embodiment, the thickness of the electronic glue layer is 350 nm-450 nm. The thickness is related to the etching depth of the reactive ions in step S4, and the different etching depths should be different from each other.
In one embodiment, the temperature for performing the rapid thermal reflow on the electronic glue layer is 80-300 ℃. The temperature is related to the selection of the electronic glue, and the proper temperature is selected according to the specifically selected electronic glue.
In one embodiment, the polishing conditions include sample carrier plate rotation speed, abrasive plate rotation speed, pressure, polishing solution flow rate, and polishing time.
In one embodiment, in step S6, the sample is sequentially placed into acetone, isopropanol, and deionized water, and then sequentially subjected to ultrasound for a certain time to clean the sample.
In some embodiments, the width of the etched groove and the distance from the target recess may be selected according to the material of the sample; as shown in FIG. 3, W 1 Denotes the width of the etched groove, W 2 Indicating the distance between the etched groove and the target recess; as shown in table 1, by setting a plurality of different sets of W 1 And W 2 To verify the effect of the present invention, the result of etching the groove is shown in fig. 4, and the final experimental result after CMP is shown in fig. 5; as can be seen from the figure, grooves are etched on two sides of the target depression, so that after the sample is subjected to CMP treatment, the upper surface of the sample is relatively flattened, the problem of depression transfer after the traditional CMP treatment is avoided, the performance of a device is optimized, and meanwhile, the relatively flat upper surface is obtained, and a foundation is provided for subsequent design and processing of the upper surface.
TABLE 1W in each set of experiments 1 And W 2 Corresponding value
| Numbering | W 1 (um) | W 2 (um) |
| 1 | 5 | 5 |
| 2 | 5 | 2 |
| 3 | 2 | 2 |
| 4 | 2 | 1 |
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
It should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.
Claims (10)
1. A CMP optimization method, comprising the steps of:
s1, spin coating: spin-coating electronic glue on the surface of a sample to be subjected to CMP treatment;
s2, electron beam exposure: after processing the layout needing electron beam exposure, carrying out electron beam exposure on the sample, and developing to obtain a required electron photoresist layer; grooves extending to the sample layer are formed in the electronic glue layer, and the grooves are arranged beside the target recess at intervals;
s3, hardening the film: placing the developed sample on a hot plate, and after the temperature is set, carrying out rapid thermal reflux on the electronic glue layer by using the hot plate;
s4, reactive ion etching: coating vacuum grease on the back of the reflowed sample, placing the reflowed sample on a carrying disc, putting the reflowed sample and the carrying disc into a reactive ion etching machine, setting an etching menu, starting etching, and transferring the groove from the electronic glue layer to the sample layer after etching is finished;
s5, removing the photoresist: placing the etched sample into a reactive ion etcher, starting photoresist stripping after a photoresist stripping menu is set, and removing the residual electronic photoresist layer of the sample;
s6, CMP: and (3) fixing the sample with the electronic glue pattern layer removed in a groove of a sample carrying disc of a chemical physical polishing machine, polishing according to set polishing conditions, and cleaning the sample after polishing.
2. The CMP optimization method of claim 1, wherein the step S2 includes:
s21, fixing a sample coated with the electronic glue in a spinning mode on a sample table exposed by an electron beam, adjusting the height of the sample table through the assistance of a distance measuring instrument to enable the sample to be in a horizontal state on the sample table, and recording position coordinates of the sample on the sample table through a coordinate meter; then putting the sample stage into an electron beam exposure sample feeding cavity;
s22, processing a layout to be exposed through Beamer and electron beam exposure control software, wherein the final target effect of the layout is to etch grooves on two sides of a target recess of a sample layer; then, obtaining a job file controlled by an electron beam exposure instrument; while inputting the coordinates of the position of the sample recorded in step S21 in the file; then the sample stage is sent into the direct-writing cavity from the sample sending cavity; starting electron beam exposure after the feeding is finished;
and S23, after exposure is finished, taking down the sample from the sample table, and processing the sample by using a corresponding developing solution to obtain the required electronic glue layer.
3. The CMP optimization method of claim 1, wherein the sample to be CMP processed is a waveguide structure processed by a Damascus process.
4. The CMP optimization method of claim 1, wherein the grooves on the electronic glue layer are located on two sides of the target recess, or form a ring-shaped groove around the target recess.
5. The CMP optimization method according to claim 1, wherein the sample comprises a silicon substrate layer, a silicon dioxide layer, and a silicon nitride layer in sequence from bottom to top; the silicon nitride layer is a polishing layer to be CMP.
6. The CMP optimization method of claim 1, wherein the electronic glue is a positive glue with a model number AR-P6200.13.
7. The CMP optimization method of claim 1, wherein the thickness of the electronic glue layer is 350nm to 450 nm.
8. The CMP optimization method of claim 1, wherein the temperature for the rapid thermal reflow of the electronic glue layer is 80 ℃ to 300 ℃.
9. The CMP optimization method of claim 1, wherein the polishing conditions include sample carrier rotation speed, abrasive disc rotation speed, pressure, slurry flow rate, and polishing time.
10. The CMP optimization method of claim 1, wherein in step S6, the sample is sequentially placed in acetone, isopropanol, and deionized water, and sequentially subjected to ultrasound for a certain period of time, so as to clean the sample.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102543714A (en) * | 2010-12-27 | 2012-07-04 | 中国科学院微电子研究所 | Method for improving uniformity of chemical-mechanical planarization process at top of opened polycrystal gratings |
| CN102856249A (en) * | 2011-10-12 | 2013-01-02 | 上海华力微电子有限公司 | Method for reducing surface butterfly-shaped sunken portion formed by copper chemical mechanical polishing |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20140097539A1 (en) * | 2012-10-08 | 2014-04-10 | Stmicroelectronics, Inc. | Technique for uniform cmp |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102543714A (en) * | 2010-12-27 | 2012-07-04 | 中国科学院微电子研究所 | Method for improving uniformity of chemical-mechanical planarization process at top of opened polycrystal gratings |
| CN102856249A (en) * | 2011-10-12 | 2013-01-02 | 上海华力微电子有限公司 | Method for reducing surface butterfly-shaped sunken portion formed by copper chemical mechanical polishing |
Non-Patent Citations (1)
| Title |
|---|
| 嵌入式闪存中浮栅多晶硅CMP制程的研究与改善;李冠华 等;《电子与封装》;20111130;第11卷(第11期);第4-8页 * |
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