CN117790319B - Method for forming semiconductor device - Google Patents
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- CN117790319B CN117790319B CN202410211060.1A CN202410211060A CN117790319B CN 117790319 B CN117790319 B CN 117790319B CN 202410211060 A CN202410211060 A CN 202410211060A CN 117790319 B CN117790319 B CN 117790319B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
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- 239000011229 interlayer Substances 0.000 claims abstract description 89
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 82
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 81
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 61
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 239000002184 metal Substances 0.000 claims abstract description 39
- 239000000463 material Substances 0.000 claims abstract description 35
- 238000005530 etching Methods 0.000 claims abstract description 32
- 238000012546 transfer Methods 0.000 claims description 16
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- 238000011049 filling Methods 0.000 claims description 4
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- 238000001039 wet etching Methods 0.000 claims description 4
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- 238000012360 testing method Methods 0.000 abstract description 4
- 238000005429 filling process Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 11
- 238000001312 dry etching Methods 0.000 description 7
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
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- 230000003090 exacerbative effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
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Abstract
The invention provides a method for forming a semiconductor device, which comprises the following steps: providing a semiconductor substrate, wherein a plurality of dummy gates are formed on the semiconductor substrate at intervals, a silicon nitride layer and an oxide layer are sequentially formed on the dummy gates, and an interlayer dielectric layer is filled between adjacent dummy gates; flattening the interlayer dielectric layer until the silicon nitride layer is exposed; sequentially forming a BARC layer and a patterned photoresist layer on the interlayer dielectric layer; sequentially etching the BARC layer and the silicon nitride layer by taking the patterned photoresist layer as a mask; the dummy gate is etched and removed to provide a special mask etching process for removing the silicon nitride layer, so that when the silicon nitride layer is removed by a dry method, the BARC layer covers the dielectric layer between layers, thereby solving the problem of electrical test failure caused by too low metal gate in the subsequent metal gate material filling process and the problem of silicon nitride layer residue caused by uneven thickness of the silicon nitride layer in the interlayer dielectric layer flattening process.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor device.
Background
As shown in fig. 1, the metal gate is prepared by providing a substrate 1, forming a plurality of dummy gate structures 2 on the substrate 1 at intervals, sequentially forming a silicon nitride layer 3 and a silicon oxide layer 4 on each dummy gate structure 2, forming an interlayer dielectric layer 5 on the substrate 1 between adjacent dummy gate structures 2, and covering the silicon oxide layer 4 with the interlayer dielectric layer 5.
As shown in fig. 2, the interlayer dielectric layer 5 is then planarized by a first cmp process until a portion of the silicon nitride layer 3 is exposed. In this step, a photomask is not required, so that the cost is reduced due to the process step of saving, but because the chemical mechanical polishing process needs to polish a plurality of film layers made of different materials, the interlayer dielectric layers 5 between the adjacent dummy gate structures 2 have a butterfly shape (i.e., the interlayer dielectric layers 5 are concave, at this time, the concave height of the interlayer dielectric layers 5 is h 1), and meanwhile, the problem of non-uniformity of the silicon nitride layer 3 also exists, which results in non-uniformity of the thickness of the remaining silicon nitride layer 3. When a shallow trench isolation structure is present in the substrate 1 below a portion of the dummy gate structure 2, the silicon nitride layer 3 remaining above the shallow trench isolation structure is particularly thick, further exacerbating the non-uniformity of the thickness of the remaining silicon nitride layer 3.
As shown in fig. 3, the silicon nitride layer 3 is then removed by a dry etching process to expose the dummy gate structure 2. In this step, since the etching gas used in the dry etching process also has an etching effect on the interlayer dielectric layer 5, this step will aggravate the butterfly shape of the interlayer dielectric layer 5, so that the concave height of the interlayer dielectric layer 5 is increased from h1 to h2, that is, the height of the interlayer dielectric layer 5 is further reduced. Meanwhile, due to the fact that the silicon nitride layer 3 is uneven, the problem that part of the silicon nitride layer 3 remains is caused, so that the removing process cannot be normally performed due to shielding of the silicon nitride layer 3 when the dummy gate structure 2 is removed later, if the etching time is required to be prolonged in order to solve the problem, the contact time between etching gas and an interlayer dielectric layer is increased, the butterfly-shaped shape of the interlayer dielectric layer 5 is further increased, the concave height of the interlayer dielectric layer 5 is further increased, and the height of the interlayer dielectric layer 5 is further reduced.
As shown in fig. 4, the dummy gate structure 2 is removed by wet etching to expose the recess filled by the dummy gate structure; as shown in fig. 5, a metal gate material 6 is filled in the groove, and the metal gate material 6 also covers the interlayer dielectric layer 5; as shown in fig. 6 and 7, the metal gate material 6 is planarized by the second cmp process, and in fig. 6, when the recess opening is not polished, since the interlayer dielectric layer 5 has a low height, there is a metal residue on the interlayer dielectric layer 5, and the residue has a height h2, further polishing is required to polish the metal gate material 6 of the interlayer dielectric layer 5 until there is no metal residue on the interlayer dielectric layer 5, at this time, the metal gate material 6 of the recess opening is also polished, i.e., the recess is reduced by a height h2, so that the metal gate material is excessively polished, and eventually cannot function as a communication circuit or has an excessively high resistance, thereby causing the situations of failure, rejection, etc. of the electrical test.
Disclosure of Invention
The invention aims to provide a method for forming a semiconductor device, which solves the problem of electrical test failure caused by too low metal grid.
In order to solve the above problems, the present invention provides a method for forming a semiconductor device, comprising the steps of:
providing a semiconductor substrate, wherein a plurality of dummy gates arranged at intervals are formed on the semiconductor substrate, a silicon nitride layer and an oxide layer are sequentially formed on the dummy gates, an interlayer dielectric layer is filled between adjacent dummy gates, and the interlayer dielectric layer also covers the oxide layer;
flattening the interlayer dielectric layer until the silicon nitride layer is exposed;
sequentially forming a BARC layer and a patterned photoresist layer on the interlayer dielectric layer, wherein the patterned photoresist layer is provided with an opening above the silicon nitride layer;
Sequentially etching the BARC layer and the silicon nitride layer by taking the patterned photoresist layer as a mask at the opening, and removing the photoresist layer and the BARC layer;
and etching to remove the dummy gate.
Optionally, the step of the dummy gate specifically includes:
A high-k gate dielectric layer, a pseudo gate layer, a silicon nitride layer, an oxide layer and a pattern transfer structure layer are sequentially formed on the semiconductor substrate;
patterning the pattern transfer structure layer by adopting a first mask plate to obtain a patterned pattern transfer structure layer;
Sequentially etching the oxide layer, the silicon nitride layer, the pseudo gate electrode layer and the high-k gate dielectric layer by taking the patterned pattern transfer structure layer as a mask so as to expose the semiconductor substrate and form a pseudo gate electrode and a first groove positioned between the pseudo gate electrodes;
And removing the pattern transfer structure layer.
Further, before the interlayer dielectric layer is filled between the adjacent dummy gates, the method further comprises:
And forming a CESL layer on the upper surface of the semiconductor substrate between the adjacent dummy gates, wherein the CESL layer covers the sidewalls of the high-k gate dielectric layer, the dummy gates, the silicon nitride layer and the oxide layer and also covers the upper surface of the oxide layer, and the interlayer dielectric layer covers the CESL layer on the oxide layer.
Further, the step of flattening the interlayer dielectric layer specifically includes:
And flattening the interlayer dielectric layer by adopting a chemical mechanical polishing process, and removing the CESL layer, the oxide layer and part of the thickness of the silicon nitride layer above the dummy gate.
Furthermore, a butterfly-shaped interlayer dielectric layer is formed between adjacent dummy gates, and the concave height of the interlayer dielectric layer is h1.
Further, the step of forming the patterned photoresist layer specifically comprises:
sequentially forming a BARC layer and a photoresist layer on the interlayer dielectric layer, wherein the BARC layer also covers the silicon nitride layer;
and patterning the photoresist layer by using a first mask plate through a negative photoetching process to form a patterned photoresist layer.
Further, the step of removing the BARC layer specifically includes:
Etching the BARC layer at the opening by taking the patterned photoresist layer as a mask so as to expose the silicon nitride layer;
Etching to remove the silicon nitride layer by taking the patterned photoresist layer and the patterned BARC layer as masks so as to expose the pseudo grid electrode;
and removing the photoresist layer and the BARC layer.
Further, the step of etching to remove the dummy gate specifically includes:
and removing the pseudo gate by a wet etching process, exposing the high-k gate dielectric layer, and forming a second groove.
Further, the method further comprises the following steps:
filling a metal gate material in the second groove, wherein the metal gate material also covers the interlayer dielectric layer and the CESL layer;
and flattening the metal gate material until the interlayer dielectric layer is exposed.
Further, when the metal gate material is planarized, the metal gate material with the h2 height at the opening of the second groove is removed.
Compared with the prior art, the invention has the unexpected technical effects that:
The invention provides a method for forming a semiconductor device, which comprises the following steps: providing a semiconductor substrate, wherein a plurality of dummy gates arranged at intervals are formed on the semiconductor substrate, a silicon nitride layer and an oxide layer are sequentially formed on the dummy gates, an interlayer dielectric layer is filled between adjacent dummy gates, and the interlayer dielectric layer also covers the oxide layer; flattening the interlayer dielectric layer until the silicon nitride layer is exposed; sequentially forming a BARC layer and a patterned photoresist layer on the interlayer dielectric layer, wherein the patterned photoresist layer is provided with an opening above the silicon nitride layer; sequentially etching the BARC layer and the silicon nitride layer by taking the patterned photoresist layer as a mask at the opening, and removing the photoresist layer and the BARC layer; and etching to remove the dummy gate. The invention sequentially etches the BARC layer and the silicon nitride layer by taking the patterned photoresist layer as a mask, and achieves the unexpected technical effects that: the special mask etching process can be provided to remove the silicon nitride layer, so that when the silicon nitride layer is removed by a dry method, the BARC layer covers the interlayer dielectric layer, and therefore etching gas of the dry etching process does not influence the interlayer dielectric layer.
In addition, the mask plate used for forming the patterned photoresist layer is the same as the mask plate used for forming the dummy gate and is the first mask plate, so that a new mask plate is not introduced in the subsequent step of removing the silicon nitride layer, and the cost of the mask plate is not increased.
Drawings
FIG. 1 is a schematic view of a structure of a substrate provided in the prior art;
FIG. 2 is a schematic diagram of a structure of a first chemical mechanical polishing process according to the prior art;
FIG. 3 is a schematic diagram of a prior art structure after removing a silicon nitride layer;
FIG. 4 is a schematic diagram of a prior art structure after removal of a dummy gate structure;
Fig. 5 is a schematic structural diagram of a prior art method in which a metal gate material is filled in a groove;
FIGS. 6-7 are schematic views of a structure of a conventional chemical mechanical polishing process after a second chemical mechanical polishing process
Fig. 8 is a flowchart illustrating a method for forming a semiconductor device according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of a semiconductor substrate according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of a structure of an embodiment of the present invention after planarization of the interlayer dielectric layer;
FIG. 11 is a schematic diagram of a patterned photoresist layer according to an embodiment of the present invention;
FIG. 12 is a schematic diagram of a structure after etching a BARC layer according to an embodiment of the present invention;
FIG. 13 is a schematic diagram of an embodiment of the present invention after etching a silicon nitride layer;
FIG. 14 is a schematic diagram of a structure of an embodiment of the present invention after filling metal gate material;
Fig. 15 is a schematic diagram of a structure after planarizing a metal gate material according to an embodiment of the invention.
Wherein,
In fig. 1-7: 1-a substrate; 2-dummy gate structure; a 3-silicon nitride layer; a 4-silicon oxide layer; 5-an interlayer dielectric layer; 6-metal gate material;
Fig. 9 to 15:
100-a semiconductor substrate; 210-a high-k gate dielectric layer; 220-dummy gate; 221-a second groove; 310-a silicon nitride layer; 320-oxide layer; 330-CESL layer; 340-an interlayer dielectric layer; 410-BARC layer; 420-a photoresist layer; 421-opening; 500-metal gate material.
Detailed Description
A method of forming a semiconductor device of the present invention will be described in further detail below. The present invention will be described in more detail below with reference to the attached drawings, in which preferred embodiments of the present invention are shown, it being understood that one skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It should be appreciated that in the development of any such actual embodiment, numerous implementation details must be made to achieve the developer's specific goals, such as compliance with system-related or business-related constraints, which will vary from one implementation to another. In addition, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
In order to make the objects and features of the present invention more comprehensible, embodiments accompanied with figures are described in detail below. It is noted that the drawings are in a very simplified form and utilize non-precise ratios, and are intended to facilitate a convenient, clear, description of the embodiments of the invention.
As shown in fig. 8, the present embodiment provides a method for forming a semiconductor device, including the steps of:
step S1: providing a semiconductor substrate, wherein a plurality of dummy gates arranged at intervals are formed on the semiconductor substrate, a silicon nitride layer and an oxide layer are sequentially formed on the dummy gates, an interlayer dielectric layer is filled between adjacent dummy gates, and the interlayer dielectric layer also covers the oxide layer;
step S2: flattening the interlayer dielectric layer until the silicon nitride layer is exposed;
Step S3: sequentially forming a BARC layer and a patterned photoresist layer on the interlayer dielectric layer, wherein the patterned photoresist layer is provided with an opening above the silicon nitride layer;
Step S4: sequentially etching the BARC layer and the silicon nitride layer by taking the patterned photoresist layer as a mask at the opening, and removing the photoresist layer and the BARC layer;
step S5: and etching to remove the dummy gate.
A method of forming a semiconductor device according to this embodiment will be described in detail with reference to fig. 9 to 15.
As shown in fig. 9, step S1 is first performed to provide a semiconductor substrate 100, a plurality of dummy gates 220 disposed at intervals are formed on the semiconductor substrate 100, a silicon nitride layer 310 and an oxide layer 320 are sequentially formed on the dummy gates 220, an interlayer dielectric layer 340 is filled between adjacent dummy gates 220, and the interlayer dielectric layer 340 also covers the oxide layer 320.
The method specifically comprises the following steps:
First, a semiconductor substrate 100 is provided, and the semiconductor substrate 100 is a silicon substrate, a germanium substrate, a silicon nitride substrate, a silicon-on-insulator substrate, or the like. Those skilled in the art may select the type of the semiconductor substrate 100 according to the semiconductor device formed on the semiconductor substrate 100, and thus the type of the semiconductor substrate 100 should not limit the scope of the present invention.
Optionally, an STI structure (shallow trench isolation structure) is further formed in the semiconductor substrate 100, and the STI structure is an electrical isolation structure.
Next, a high-k gate dielectric layer 210, a dummy gate layer, a silicon nitride layer 310, an oxide layer 320, and a pattern transfer structure layer are sequentially formed on the semiconductor substrate 100. The pattern transfer structure layer sequentially comprises an SOC (spin on carbon) layer, an SOG (spin on glass coating, spin on glass) layer and an initial photoresist layer from bottom to top, wherein the initial photoresist layer is a positive photoresist layer.
And then, adopting a first mask plate to graphically process the graph transfer structure layer so as to obtain the graphical graph transfer structure layer. In this step, a positive tone lithography process is used to form the patterned initial photoresist layer.
Next, the oxide layer 320, the silicon nitride layer 310, the dummy gate layer, and the high-k gate dielectric layer 210 are etched in sequence with the patterned pattern transfer structure layer as a mask, so as to expose the semiconductor substrate 100, thereby forming a plurality of dummy gates arranged at intervals, and a first groove between adjacent dummy gates. And removing the pattern transfer structure layer, wherein the STI structure is positioned below the dummy gate.
Next, a CESL layer 330 (Contact Etch Stop Layer ) is formed on the upper surface of the semiconductor substrate 100 between adjacent dummy gates, the CESL layer 330 covering sidewalls of the high-k gate dielectric layer 210, dummy gate 220, silicon nitride layer 310, and oxide layer 320, and also covering the upper surface of the oxide layer 320.
Next, an interlayer dielectric layer 340 is filled in the first recess between the dummy gates 220, and the interlayer dielectric layer 340 covers the CESL layer 330 on the oxide layer 320.
As shown in fig. 10, step S2 is performed to planarize the interlayer dielectric layer 340 until the silicon nitride layer 310 is exposed.
Specifically, in this step, the interlayer dielectric layer 340 is planarized by a chemical mechanical polishing process, and the CESL layer 330, the oxide layer 320 and a portion of the thickness of the silicon nitride layer 310 above the dummy gate 220 are removed. Since the cmp process needs to polish a plurality of film layers with different materials (i.e., different hardness), the thickness of the remaining silicon nitride layer 310 is not uniform, and a butterfly-shaped interlayer dielectric layer 340 is formed between adjacent dummy gates 220, and at this time, the concave height of the interlayer dielectric layer 340 is h1. At the same time, the silicon nitride layer 310 on the dummy gate 220 above the STI structure is particularly thick, i.e., thickness non-uniformity of the remaining silicon nitride layer 310 is further exacerbated.
As shown in fig. 11, step S3 is performed, and a BARC layer 410 (Bottom Anti-REFLECTIVE COATING) and a patterned photoresist layer 420 are sequentially formed on the interlayer dielectric layer 340, wherein the patterned photoresist layer 420 has an opening 421 above the silicon nitride layer 310.
The method specifically comprises the following steps:
First, a BARC layer 410 and a photoresist layer 420 are sequentially formed on the interlayer dielectric layer 340, the BARC layer 410 also covering the silicon nitride layer 310. Wherein the photoresist layer 420 is a negative photoresist layer.
Next, the photoresist layer 420 is patterned by a negative tone lithography process using a first mask to form a patterned photoresist layer 420. Wherein the patterned photoresist layer 420 has an opening 421 over the silicon nitride layer 310. The mask used in this step is the same as the mask used in forming the dummy gate 220, and is the first mask, so that no new mask is introduced in the subsequent step of removing the silicon nitride layer 310, and therefore, the cost of the mask is not increased.
As shown in fig. 12, step S4 is performed, where the patterned photoresist layer 420 is used as a mask to sequentially etch the BARC layer 410 and the silicon nitride layer 310, and the photoresist layer 420 and the BARC layer 410 are removed.
The method specifically comprises the following steps:
first, the BARC layer 410 is etched at the opening 421 using the patterned photoresist layer 420 as a mask to expose the silicon nitride layer 310.
Next, the patterned photoresist layer 420 and BARC layer 410 are used as a mask to etch away the silicon nitride layer 310, thereby exposing the dummy gate 220. In detail, the patterned photoresist layer 420 is used as a mask, and the silicon nitride layer 310 is removed by a dry etching process to expose the dummy gate 220. In the dry etching process of this step, since the interlayer dielectric layer 340 and the CESL layer 330 on the dummy gate sidewall are covered by the BARC layer 410, the etching gas of the dry etching process does not affect the CESL layer 330 and the interlayer dielectric layer 340. In this step, the remaining silicon nitride layer 310 is removed by a special mask etching process, so that the butterfly shape caused by the interlayer dielectric layer 340 after the planarization process is not aggravated, that is, the concave height of the interlayer dielectric layer 340 between adjacent dummy gates 220 is still h1.
Finally, the photoresist layer 420 and BARC layer 410 are removed and the dummy gate 220, interlayer dielectric layer 340, and CESL layer 330 between the dummy gate 220 and interlayer dielectric layer 340 are exposed.
As shown in fig. 13, step S5 is performed to etch and remove the dummy gate 220. In detail, a wet etching process removes the dummy gate 220 and exposes the high-k gate dielectric layer 210 and the second recess 221.
Next, as shown in fig. 14, a metal gate material 500 is filled in the second recess 221, and the metal gate material 500 further covers the interlayer dielectric layer 340 and the CESL layer 330.
As shown in fig. 15, the metal gate material 500 is then planarized until the interlayer dielectric layer 340 is exposed.
In the planarization process, the metal gate material 500 and the CESL layer 330 in the second recess 221 are exposed first, and the metal gate material 500 with the h1 height is still remained on the interlayer dielectric layer 340 due to the butterfly-shaped interlayer dielectric layer 340, so that the metal gate material 500 on the interlayer dielectric layer 340 needs to be further planarized, i.e. the metal gate material 500 with the h1 height is removed, so that the metal gate material 500 with the h1 height at the opening of the second recess 221 needs to be removed, and compared with the metal gate material 500 with the h2 height at the opening of the second recess 221 in the prior art, excessive grinding of the metal gate material 500 at the opening of the second recess 221 is avoided, so that the metal gate material 500 with a sufficient height can be remained, and the problem of electrical test failure caused by too low metal gate is solved.
In summary, the present invention provides a method for forming a semiconductor device, including the following steps: providing a semiconductor substrate, wherein a plurality of dummy gates arranged at intervals are formed on the semiconductor substrate, a silicon nitride layer and an oxide layer are sequentially formed on the dummy gates, an interlayer dielectric layer is filled between adjacent dummy gates, and the interlayer dielectric layer also covers the oxide layer; flattening the interlayer dielectric layer until the silicon nitride layer is exposed; sequentially forming a BARC layer and a patterned photoresist layer on the interlayer dielectric layer, wherein the patterned photoresist layer is provided with an opening above the silicon nitride layer; sequentially etching the BARC layer and the silicon nitride layer by taking the patterned photoresist layer as a mask at the opening, and removing the photoresist layer and the BARC layer; and etching to remove the dummy gate. The invention sequentially etches the BARC layer and the silicon nitride layer by taking the patterned photoresist layer as a mask, and achieves the unexpected technical effects that: the special mask etching process can be provided to remove the silicon nitride layer, so that when the silicon nitride layer is removed by a dry method, the BARC layer covers the interlayer dielectric layer, and therefore etching gas of the dry etching process does not influence the interlayer dielectric layer.
In addition, the mask plate used for forming the patterned photoresist layer is the same as the mask plate used for forming the dummy gate and is the first mask plate, so that a new mask plate is not introduced in the subsequent step of removing the silicon nitride layer, and the cost of the mask plate is not increased.
Furthermore, unless specifically stated or indicated otherwise, the description of the terms "first," "second," and the like in the specification merely serve to distinguish between various components, elements, steps, etc. in the specification, and do not necessarily represent a logical or sequential relationship between various components, elements, steps, etc.
It will be appreciated that although the invention has been described above in terms of preferred embodiments, the above embodiments are not intended to limit the invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
Claims (10)
1. A method of forming a semiconductor device, comprising the steps of:
providing a semiconductor substrate, wherein a plurality of dummy gates arranged at intervals are formed on the semiconductor substrate, a silicon nitride layer and an oxide layer are sequentially formed on the dummy gates, an interlayer dielectric layer is filled between adjacent dummy gates, and the interlayer dielectric layer also covers the oxide layer;
flattening the interlayer dielectric layer until the silicon nitride layer is exposed;
Sequentially forming a BARC layer and a patterned photoresist layer on the interlayer dielectric layer, wherein the patterned photoresist layer is provided with an opening above the silicon nitride layer, and a mask plate used for the patterned photoresist layer is the same as a mask plate used for forming the pseudo gate;
Sequentially etching the BARC layer and the silicon nitride layer by taking the patterned photoresist layer as a mask at the opening, and removing the photoresist layer and the BARC layer;
and etching to remove the dummy gate.
2. The method of forming a semiconductor device of claim 1, wherein the step of dummy gate is specifically:
A high-k gate dielectric layer, a pseudo gate layer, a silicon nitride layer, an oxide layer and a pattern transfer structure layer are sequentially formed on the semiconductor substrate;
patterning the pattern transfer structure layer by adopting a first mask plate to obtain a patterned pattern transfer structure layer;
Sequentially etching the oxide layer, the silicon nitride layer, the pseudo gate electrode layer and the high-k gate dielectric layer by taking the patterned pattern transfer structure layer as a mask so as to expose the semiconductor substrate and form a pseudo gate electrode and a first groove positioned between the pseudo gate electrodes;
And removing the pattern transfer structure layer.
3. The method of forming a semiconductor device of claim 2, further comprising, prior to filling an interlayer dielectric layer between adjacent dummy gates:
And forming a CESL layer on the upper surface of the semiconductor substrate between the adjacent dummy gates, wherein the CESL layer covers the sidewalls of the high-k gate dielectric layer, the dummy gates, the silicon nitride layer and the oxide layer and also covers the upper surface of the oxide layer, and the interlayer dielectric layer covers the CESL layer on the oxide layer.
4. The method for forming a semiconductor device according to claim 3, wherein the step of planarizing the interlayer dielectric layer comprises:
And flattening the interlayer dielectric layer by adopting a chemical mechanical polishing process, and removing the CESL layer, the oxide layer and part of the thickness of the silicon nitride layer above the dummy gate.
5. The method of forming a semiconductor device of claim 4, wherein a butterfly-shaped interlayer dielectric layer is further formed between adjacent dummy gates, and a recess height of the interlayer dielectric layer is h1.
6. The method of forming a semiconductor device of claim 3, wherein the step of forming a patterned photoresist layer comprises:
sequentially forming a BARC layer and a photoresist layer on the interlayer dielectric layer, wherein the BARC layer also covers the silicon nitride layer;
and patterning the photoresist layer by using a first mask plate through a negative photoetching process to form a patterned photoresist layer.
7. The method of forming a semiconductor device of claim 3, wherein the step of removing the BARC layer comprises:
Etching the BARC layer at the opening by taking the patterned photoresist layer as a mask so as to expose the silicon nitride layer;
Etching to remove the silicon nitride layer by taking the patterned photoresist layer and the patterned BARC layer as masks so as to expose the pseudo grid electrode;
and removing the photoresist layer and the BARC layer.
8. The method for forming a semiconductor device according to claim 3, wherein the step of etching to remove the dummy gate comprises:
and removing the pseudo gate by a wet etching process, exposing the high-k gate dielectric layer, and forming a second groove.
9. The method of forming a semiconductor device according to claim 8, further comprising:
filling a metal gate material in the second groove, wherein the metal gate material also covers the interlayer dielectric layer and the CESL layer;
and flattening the metal gate material until the interlayer dielectric layer is exposed.
10. The method of forming a semiconductor device of claim 9, wherein the metal gate material is planarized to remove a height h2 of the metal gate material at the second recess opening.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6281082B1 (en) * | 2000-03-13 | 2001-08-28 | Chartered Semiconductor Manufacturing Ltd. | Method to form MOS transistors with a common shallow trench isolation and interlevel dielectric gap fill |
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| US8574990B2 (en) * | 2011-02-24 | 2013-11-05 | United Microelectronics Corp. | Method of manufacturing semiconductor device having metal gate |
| KR101850409B1 (en) * | 2012-03-15 | 2018-06-01 | 삼성전자주식회사 | Method for manufacturing semiconductor device having dual gate dielectric layer |
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