TWI512797B - Planarization method applied in process of manufacturing semiconductor component - Google Patents

Description

Flattening method applied to semiconductor device manufacturing

The present invention provides a planarization method, and more particularly to a planarization method that can be applied to a semiconductor device process.

With the rapid development of semiconductor devices in recent years, the size of the device has entered the nanometer level. Therefore, the thickness of the gate dielectric layer in the MOS semiconductor device is relatively thinner as the channel size is reduced. However, the thickness of the excessively thin insulating layer is bound to induce a serious gate leakage current, and this leakage current will affect the characteristics of the component, resulting in an increase in the energy consumption of the product. Therefore, it is necessary to introduce a high dielectric constant (hereinafter referred to as High-k) material to complete the gate insulating layer to reduce the gate leakage current. In addition, the High-k process is often combined with a metal gate process to reduce the resistance of the gate electrode. In order to improve the thermal stability and prevent the metal gate from reacting with the high dielectric constant gate insulating layer, a barrier layer is usually added between the metal gate and the high dielectric constant gate insulating layer. The layer can usually be done with titanium nitride (TiN). However, in the manufacturing process of the above-mentioned gate structure, problems often arise due to poor planarization of the surface of the device, and how to improve these defects is the main purpose of developing the present case.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a planarization method that can be applied to an integrated circuit process to improve the lack of planarization of conventional devices.

The present invention provides a planarization method for use in a semiconductor device process, the method comprising the steps of: providing a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer has a trench; Forming a barrier layer and a metal layer; using a first reactant to perform a first planarization process on the metal layer to remove a portion of the metal layer to expose the barrier layer, wherein the first reactant is opposite to the metal layer The etching rate is greater than the etching rate of the barrier layer; and the second planarizing process is performed on the barrier layer and the metal layer by using the second reactant to remove part of the barrier layer and the metal layer to expose the dielectric layer. The etching rate of the second reactant to the barrier layer is greater than the etching rate of the metal layer.

In a preferred embodiment of the invention, the planarization method further includes forming a gate dielectric layer under the dielectric layer.

In a preferred embodiment of the present invention, the planarization method further includes forming a gate dielectric layer in the trench before forming the barrier layer.

In a preferred embodiment of the invention, the gate dielectric layer is a high-k dielectric layer, the barrier layer is a gate barrier layer, and the metal layer is a gate metal layer.

In a preferred embodiment of the present invention, the high-k dielectric layer may be a single layer of a material such as hafnium oxide (HfO ₂ ), hafnium oxynitride (HfSiON) or hafnium oxide (HfSiO) or Multi-layer structure.

In a preferred embodiment of the present invention, the barrier layer may be titanium nitride (TiN), tantalum carbide (TaC), tungsten carbide (WC), titanium carbide (TiC), tantalum nitride (TaN), nitrogen. A single or multi-layer structure made of a material such as titanium aluminum (TiAlN).

In a preferred embodiment of the present invention, the metal layer may be titanium nitride (TiN), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), tantalum nitride (TaN). A single layer or a multilayer structure made of a material such as cobalt (Co), copper (Cu) or nickel (Ni).

In a preferred embodiment of the present invention, the first planarization process and the second planarization process may be a first chemical mechanical polishing process and a second chemical mechanical polishing process, respectively, and the first reactant is The second reactant may be a first chemical mechanical abrasive and a second chemical mechanical abrasive, respectively. The first planarization process and the second planarization process can be performed on a single machine or separately on a plurality of machines providing different chemical mechanical abrasives, and the first chemical mechanical abrasive and the second chemical mechanical polishing The agent may further comprise an adhesive material of cerium oxide, cerium oxide or aluminum oxide powder.

In a preferred embodiment of the present invention, the first chemical mechanical abrasive and the second chemical mechanical abrasive may both contain an oxidizer, and the first chemical mechanical abrasive may have an oxidant concentration lower than the second The concentration of oxidant in a chemical mechanical abrasive.

In a preferred embodiment of the invention, the oxidant described above may be hydrogen peroxide.

In a preferred embodiment of the present invention, the concentration of hydrogen peroxide in the first chemical mechanical abrasive may range from 0% to 1%, and the concentration of hydrogen peroxide in the second chemical mechanical abrasive may be greater than one. %.

The present invention further proposes another planarization method for use in a semiconductor device process, the method comprising the steps of: providing a substrate having a gate structure including a polysilicon dummy gate and a dielectric layer thereon; removing the polysilicon dummy gate Forming at least a trench in the dielectric layer; forming a gate barrier layer on the sidewall and the bottom of the trench and a surface of the dielectric layer; forming a gate metal layer on the surface of the gate barrier layer and filling the surface a first planarization process for removing the gate metal layer to expose the gate barrier layer by using a first reactant to expose the gate barrier layer, wherein the first reactant An etch rate of the gate metal layer is greater than an etch rate of the gate barrier layer; and a second planarization process is performed on the gate barrier layer and the gate metal layer by using a second reactant to remove the portion The gate barrier layer and the gate metal layer are exposed to expose the dielectric layer, wherein an etching rate of the second reactant to the gate barrier layer is greater than an etching rate of the gate metal layer.

In a preferred embodiment of the invention, the planarization method further includes forming a gate dielectric layer under the dielectric layer.

In a preferred embodiment of the present invention, the planarization method further includes forming a gate dielectric layer in the trench before forming the barrier layer.

In a preferred embodiment of the present invention, the step of removing the portion of the gate metal layer to expose the gate barrier layer may further include the following steps: using the third reactant to perform the gate metal layer The third planarization process is for reducing the thickness of the gate metal layer to a predetermined thickness, and the etching rate of the third reactant to the gate metal layer is greater than the etching rate of the first reactant to the gate metal layer.

In a preferred embodiment of the invention, the predetermined thickness may be greater than 100 angstroms.

In a preferred embodiment of the present invention, the gate dielectric layer is a high-k dielectric layer, and the high-k dielectric layer is made of hafnium oxide (HfO ₂ ) or hafnium oxynitride (HfSiON). Or a material such as hafnium oxide (HfSiO) to complete a single layer or a multilayer structure.

In a preferred embodiment of the present invention, the barrier layer may be titanium nitride (TiN), tantalum carbide (TaC), tungsten carbide (WC), titanium carbide (TiC), tantalum nitride (TaN), nitrogen. A single or multi-layer structure made of a material such as titanium aluminum (TiAlN).

In a preferred embodiment of the present invention, the metal layer may be titanium nitride (TiN), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), tantalum nitride (TaN). A single layer or a multilayer structure made of a material such as cobalt (Co), copper (Cu) or nickel (Ni).

In a preferred embodiment of the present invention, the first planarization process and the second planarization process may be a first chemical mechanical polishing process and a second chemical mechanical polishing process, respectively, and the first reactant is The second reactants can be a first chemical mechanical abrasive and a second chemical mechanical abrasive, respectively. The first planarization process and the second planarization process can be performed on a single machine or separately on a plurality of machines providing different chemical mechanical abrasives, and the first chemical mechanical abrasive and the second chemical mechanical polishing The agent may further comprise an adhesive material of cerium oxide, cerium oxide or aluminum oxide powder.

In a preferred embodiment of the present invention, the first chemical mechanical abrasive has an etching selectivity ratio of the gate metal layer to the gate barrier layer greater than 20, and the second chemical mechanical abrasive is for the gate metal The etch selectivity ratio of the layer to the gate barrier layer is greater than 20.

In a preferred embodiment of the present invention, the first chemical mechanical abrasive and the second chemical mechanical abrasive may include an oxidizer, and the first chemical mechanical abrasive has an oxidant concentration lower than the oxidant. The concentration of the oxidant in the second chemical mechanical abrasive.

In a preferred embodiment of the invention, the oxidant described above may be hydrogen peroxide.

In a preferred embodiment of the present invention, the concentration of hydrogen peroxide in the first chemical mechanical abrasive may range from 0% to 1%, and the concentration of hydrogen peroxide in the second chemical mechanical abrasive may be greater than one. %.

The present invention further proposes another gate structure comprising a substrate, a dielectric layer, a gate barrier layer, and a gate metal layer. The dielectric layer is over the substrate and has at least one trench. The gate barrier layer is located in the trench. The gate metal layer is on the surface of the gate barrier layer and fills the trench. The top surface of the gate metal layer is lower than the sidewall of the trench, and the height difference between the two is less than 50 angstroms.

Please refer to the first figure (a), (b), (c), which is a schematic diagram of the process steps for the planarization method developed in order to improve the lack of conventional means, and can be widely applied in the process of semiconductor components. First, a substrate 10, such as a common germanium substrate, is first provided, and then a high dielectric constant/metal gate (HKMG) process is performed on the substrate 10 to complete the gold oxide semi-transistor element, as shown in the first figure (a). A dielectric layer 101 is formed over the substrate 10, and a trench 104 is formed in the dielectric layer 101, and a gate dielectric layer 1010 and a barrier layer are formed in the trench 104. The barrier layer 102 and the metal layer 103 complete a gate structure. The trench 104 can be formed by removing a polysilicon dummy (not shown). As for the gate dielectric layer 1010 in the gate structure, it may be formed after the trench 104 is formed, thereby completing the structure as shown in the first diagram (a), but the gate may be formed before the trench 104 is formed. The dielectric layer 1010 is as shown in the second diagram (a). The gate dielectric layer 1010 can be completed by a high-k dielectric material. The barrier layer may be a gate barrier layer in the gate structure, and the metal layer may be a gate metal layer in the gate structure.

Then, the first planarizing process is performed on the metal layer 103 by using the first reactant to remove a portion of the metal layer 103 to expose the barrier layer 102, wherein the composition of the first reactant is controlled to The etch rate adjustment of the metal layer 103 is greater than the etch rate of the barrier layer 102. In this way, the etching operation can be stopped on the barrier layer 102, but also because the metal layer 103 is etched faster, the structure as shown in the first figure (b) is generated, and the barrier layer 102 is exposed and the metal is exposed. Layer 103 produces a slight dishing 1030.

In order to eliminate the above-mentioned dish-shaped recess 1030, the second reactive agent is used in the present invention to perform a second planarization process for the exposed barrier layer 102 and the metal layer 103 to remove part of the barrier layer 102 and portions. The metal layer 103 exposes the dielectric layer 101 outside the opening of the trench 104, wherein the etching rate of the second reactant to the barrier layer 102 is greater than the etching rate of the metal layer 103. In this way, the etching operation can be stopped on the dielectric layer 101. However, since the etching of the barrier layer 102 is faster and the etching of the metal layer 103 is slower, the structure as shown in the first figure (c) is generated. The dished recess 1030 originally provided by layer 103 will be eliminated, thereby achieving a flat surface. The top surface of the metal layer 103 is lower than the sidewall of the trench 104, that is, the height difference from the top surface of the dielectric layer 101 on both sides is less than 50 angstroms. After cleaning, it can be sent to the next process, such as the fabrication of the inner dielectric layer.

According to the description of the above steps, the present invention can effectively improve the flatness of the product after the completion of the process by selecting different planarization processes through two etchings, thereby improving the lack of conventional means and achieving the main purpose of developing the case. The first planarization process and the second planarization process may be a first chemical mechanical polishing process and a second chemical mechanical polishing process, respectively, and the first reactant and the second reactant may be the first chemical mechanical polishing agent and The second chemical mechanical abrasive. The planarization process can be performed on a single pad (CMP) or separately on a plurality of machines providing different chemical mechanical abrasives (multi-pad CMP), and the chemical mechanical abrasives Further, an abrasive material such as cerium oxide (SiO2), cerium oxide (CeO2) or aluminum oxide (Al ₂ O ₃ ) powder or the like may be contained. In addition, the first chemical mechanical polishing agent and the second chemical mechanical polishing agent all comprise an oxidizer, and the oxidant concentration of the first chemical mechanical polishing agent is lower than the first oxidizer. The concentration of the oxidant in the second chemical mechanical polishing agent, and the oxidizing agent may be hydrogen peroxide or the like. For example, the concentration of hydrogen peroxide in the first chemical mechanical polishing agent may range from 0% to 1%, the second chemical The concentration of hydrogen peroxide in the mechanical abrasive may be greater than 1%, such as 3% or 5%, such that the first chemical mechanical abrasive has an etching selectivity ratio for the gate metal layer and the gate barrier layer. Controllable at greater than 20, the etching selectivity of the second chemical mechanical abrasive to the gate metal layer and the gate barrier layer can be controlled to be greater than 20.

The gate dielectirc layer 1010 can be mainly formed by a high-k dielectric layer, such as hafnium oxide (HfO 2 ), hafnium oxynitride (HfSiON) or hafnium oxide (HfSiO). The single-layer or multi-layer structure of the material is mainly formed under the barrier layer 102. If the gate dielectric layer 1010 is formed before the trench 104 is completed, the so-called HK first, the gate dielectric layer 1010 will only Formed at the bottom of the trench 104 to form a schematic diagram of the gate structure completed by the technique of the present invention as shown in the second diagram (a), but if the polysilicon gate is removed, the gate dielectric layer 1010 is formed, that is, the so-called HK Last, the gate dielectric layer 1010 is formed in a U-shaped cross section at the bottom and sidewalls of the trench 104 to form a gate structure as shown in the second diagram (b). The barrier layer 102 may be made of titanium nitride (TiN), tantalum carbide (TaC), tungsten carbide (WC), titanium carbide (TiC), tantalum nitride (TaN), titanium aluminum nitride (TiAlN). The single or multi-layer structure, the barrier layer 102 can be used to function as a work function metal layer, a strained layer, a work function tuning metal layer, or a work function tuning metal layer in a gate structure. A role such as a liner layer or a sealant layer. As for the metal layer 103, it may be composed of titanium nitride (TiN), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), copper (Cu). ) A single layer or a multilayer structure made of a material such as nickel (Ni).

In addition, in order to increase the capacity, before the step of removing a portion of the gate metal layer by using the first reactant to expose the gate barrier layer, the third layer may be first used to the metal layer 103. A third planarization process is performed to reduce the thickness of the gate metal layer to a predetermined thickness and then stop and switch to the first planarization process. The predetermined thickness can be set to be close to 100 angstroms but greater than 100 angstroms, and since the third reactant can be adjusted to have a faster etch rate for the metal layer 103, that is, the etch rate of the third reactant to the metal layer 103. It is larger than the etching rate of the first reactant to the metal layer 103, so the thickness of the metal layer 103 can be quickly reduced to reduce the processing time.

In summary, after the technology of the present invention is improved, the problem of poor flattening in the conventional means can be effectively eliminated. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

10. . . Substrate

101. . . Dielectric layer

1010. . . Gate dielectric layer

102. . . Barrier layer

103. . . Metal layer

104. . . Trench

1030. . . Dish

The first figure (a), (b), (c), which is a schematic diagram of the process steps for the planarization method developed in order to improve the lack of conventional means.

The second figures (a) and (b) are schematic diagrams of the two gate structures completed by the technique of the present invention.

10. . . Substrate

101. . . Dielectric layer

1010. . . Gate dielectric layer

102. . . Barrier layer

103. . . Metal layer

Claims (26)

A planarization method for use in a semiconductor device process, the method comprising the steps of: providing a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer has a trench; Forming a barrier layer and a metal layer; performing a first chemical mechanical polishing process on the metal layer by using a first chemical mechanical abrasive to remove a portion of the metal layer to expose the barrier layer, wherein The first chemical mechanical abrasive etch rate of the metal layer is greater than the etching rate of the barrier layer; and a second chemical mechanical polishing is performed on the barrier layer and the metal layer by a second chemical mechanical polishing a process for removing a portion of the barrier layer and the metal layer to expose the dielectric layer, wherein the second chemical mechanical abrasive etches the barrier layer at a rate greater than an etch rate of the metal layer, wherein The first chemical mechanical abrasive and the second chemical mechanical abrasive both comprise an oxidizer, and the first chemical mechanical abrasive has an oxidant concentration lower than the oxidant in the second chemical mechanical abrasive Concentration, and the first and second chemical mechanical polishing processes can be performed on a single machine or separately on a plurality of machines providing different chemical mechanical abrasives, and the chemical mechanical abrasives can be further included An adhesive material having cerium oxide, cerium oxide or aluminum oxide powder. The planarization method of claim 1, further comprising the step of forming a gate dielectric layer under the dielectric layer. The planarization method of claim 1, wherein the forming of the barrier layer further comprises the step of forming a gate dielectric layer in the trench. The planarization method of claim 3, wherein the gate dielectric layer is a high-k dielectric layer, and the barrier layer is a gate barrier layer, and the metal layer is A gate metal layer. The planarization method according to claim 4, wherein the high-k dielectric layer is made of materials such as hafnium oxide (HfO ₂ ), hafnium oxynitride (HfSiON) or hafnium oxide (HfSiO). Single or multi-layer structure. The planarization method according to claim 1, wherein the barrier layer is made of titanium nitride (TiN), tantalum carbide (TaC), tungsten carbide (WC), titanium carbide (TiC), tantalum nitride ( TaN), titanium aluminide (TiAlN) and other materials to complete the single layer or multilayer structure. The planarization method according to claim 1, wherein the metal layer is made of titanium nitride (TiN), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), and nitride. A single layer or a multilayer structure made of a material such as tantalum (TaN), cobalt (Co), copper (Cu) or nickel (Ni). The method of planarizing according to claim 1, wherein the oxidizing agent is hydrogen peroxide. The planarization method of claim 8, wherein the concentration of hydrogen peroxide in the first chemical mechanical abrasive ranges from 0% to 1%, and the concentration range of hydrogen peroxide in the second chemical mechanical abrasive Is greater than 1%. A planarization method for use in a semiconductor device process, the method comprising the steps of: providing a substrate having a polysilicon gate and a dielectric thereon a gate structure of the layer; removing the polysilicon dummy gate to form at least one trench in the dielectric layer; forming a gate barrier layer on the sidewall and the bottom of the trench and the surface of the dielectric layer; forming a gate metal layer on the surface of the gate barrier layer and filling the trench; using a first chemical mechanical abrasive to perform a first chemical mechanical polishing process on the gate metal layer for removing the portion Dividing the gate metal layer to expose the gate barrier layer, wherein the first chemical mechanical abrasive etch rate to the gate metal layer is greater than an etch rate of the gate barrier layer; and utilizing a second a chemical mechanical polishing agent to perform a second chemical mechanical polishing process on the gate barrier layer and the gate metal layer to remove a portion of the gate barrier layer and the gate metal layer to expose the dielectric a layer, wherein the second CMP agent etches the gate barrier layer at an etch rate greater than the etch rate of the gate metal layer, wherein the first CMP agent and the second CMP agent are both included There is an oxidizer, the first chemical machine The oxidant concentration of the mechanical abrasive is lower than the oxidant concentration of the second chemical mechanical abrasive, and the first and second chemical polishing processes can be performed on a single machine or separately provided to provide different chemical mechanical abrasives The machine is completed on the machine, and the chemical mechanical abrasive may further comprise an adhesive material of cerium oxide, cerium oxide or aluminum oxide powder. The planarization method of claim 10, further comprising the step of forming a gate dielectric layer under the dielectric layer. The planarization method of claim 10, further comprising the step of forming a gate dielectric layer in the trench before forming the barrier layer. The planarization method of claim 10, wherein the step of removing the portion of the gate metal layer to expose the gate barrier layer further comprises the step of: utilizing a third reactant to The gate metal layer performs a third planarization process for reducing the thickness of the gate metal layer to a predetermined thickness, and the etching rate of the third reactant to the gate metal layer is greater than the first reactant Etching rate of the gate metal layer. The planarization method of claim 13, wherein the predetermined thickness is greater than 100 angstroms. The planarization method of claim 10, wherein the gate dielectric layer is a high-k dielectric layer, the high-k dielectric layer is made of hafnium oxide (HfO ₂ ), nitrogen. A single layer or a multilayer structure completed by a material such as hafnium oxide (HfSiON) or hafnium oxide (HfSiO). The planarization method according to claim 10, wherein the barrier layer is made of titanium nitride (TiN), tantalum carbide (TaC), tungsten carbide (WC), titanium carbide (TiC), tantalum nitride ( TaN), titanium aluminide (TiAlN) and other materials to complete the single layer or multilayer structure. The planarization method according to claim 10, wherein the metal layer is made of titanium nitride (TiN), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), and nitride. A single layer or a multilayer structure made of a material such as tantalum (TaN), cobalt (Co), copper (Cu) or nickel (Ni). The planarization method of claim 10, wherein the first chemical mechanical abrasive has an etching selectivity ratio of the gate metal layer to the gate barrier layer greater than 20, and the second chemical mechanical abrasive is The gate metal layer and the gate barrier layer The etching selectivity ratio is greater than 20. The method of planarizing according to claim 10, wherein the oxidizing agent is hydrogen peroxide. The method of planarizing according to claim 19, wherein the concentration of hydrogen peroxide in the first chemical mechanical abrasive ranges from 0% to 1%, and the concentration range of hydrogen peroxide in the second chemical mechanical abrasive Is greater than 1%. A gate structure comprising: a substrate; a dielectric layer over the substrate and having at least one trench; a gate barrier layer located in the trench; and a gate metal layer located at the gate The trench is filled on the surface of the gate barrier layer, the top surface of the gate metal layer is lower than the sidewall of the trench, and the height difference between the two is less than 50 angstroms, wherein the height difference is via a first chemical mechanism The abrasive is formed by performing a first chemical mechanical polishing process and a second chemical mechanical polishing agent to perform a second chemical mechanical polishing process, and the etching rate of the first chemical mechanical abrasive to the gate metal layer is greater than the gate The etching rate of the pole barrier layer, the etching rate of the second chemical mechanical abrasive to the gate barrier layer is greater than the etching rate of the gate metal layer. The gate structure of claim 21, further comprising a gate dielectric layer under the dielectric layer or under the barrier layer in the trench. The gate structure of claim 22, wherein the gate dielectric layer is a high-k dielectric layer. The gate structure according to claim 23, wherein the high-k dielectric layer is made of materials such as hafnium oxide (HfO ₂ ), hafnium oxynitride (HfSiON) or hafnium oxide (HfSiO). Single or multi-layer structure. The gate structure according to claim 21, wherein the gate barrier layer is made of titanium nitride (TiN), tantalum carbide (TaC), tungsten carbide (WC), titanium carbide (TiC), nitrogen. A single layer or a multilayer structure made of a material such as TaN or TiAlN, the gate barrier layer can be used as a work function metal layer or a strained layer. , a work function tuning metal layer, a liner layer or a seamant layer. The gate structure according to claim 21, wherein the gate metal layer is made of titanium nitride (TiN), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), A single layer or a multilayer structure made of tantalum nitride (TaN), cobalt (Co), copper (Cu) or nickel (Ni).