CN102646580B - It is applied to the flattening method in semiconductor element technique and gate configuration - Google Patents

It is applied to the flattening method in semiconductor element technique and gate configuration Download PDF

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CN102646580B
CN102646580B CN201110040219.0A CN201110040219A CN102646580B CN 102646580 B CN102646580 B CN 102646580B CN 201110040219 A CN201110040219 A CN 201110040219A CN 102646580 B CN102646580 B CN 102646580B
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gate
layer
reactant
barrier layer
dielectric
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CN201110040219.0A
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CN102646580A (en
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谢雅雪
蔡腾群
林文钦
许信国
黄任鹏
陈志仙
杨智钦
吕宏源
林仁杰
曹玮哲
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联华电子股份有限公司
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Abstract

The present invention discloses a kind of flattening method being applied in semiconductor element technique and gate configuration.The method includes: have the substrate of the gate configuration including polycrystalline silicon dummy gate pole and dielectric layer above offer;Remove polycrystalline silicon dummy gate pole and form groove;Form gate barrier layer in groove;Form gate metal layer and and fill up groove on the surface of gate barrier layer;Utilizing the first reactant to carry out the first flatening process to gate metal layer, in order to remove the gate metal layer of part, the etch-rate to gate metal layer for first reactant is more than the etch-rate to gate barrier layer;Utilizing the second reactant to carry out the second flatening process to gate barrier layer and gate metal layer, in order to remove gate barrier layer and the gate metal layer of part, the etch-rate to gate barrier layer for second reactant is more than the etch-rate to gate metal layer.

Description

It is applied to the flattening method in semiconductor element technique and gate configuration

Technical field

The present invention relates to a kind of flattening method, espespecially can be applicable to the planarization in semiconductor element technique Method.

Background technology

With semiconductor element developing rapidly in recent years, component size has been enter into nano-scale so far, because of Gate insulator (Gate Dielectric Layer) thickness in this metal-oxide semiconductor transistor component Certainly will be relatively thinning with reducing of channel dimensions, but excessively thin thickness of insulating layer certainly will induce seriously Grid leakage current, and this leakage current will influence whether the characteristic of element, cause the power consumption of product to increase. Therefore, import high-k (hereinafter referred to as High-k) material and complete gate insulator, in order to reduce The generation of grid leakage current is necessary means.Additionally, High-k technique usually can be with metal gates (metal Gate) technique collocation, in order to reduce the resistance of gate electrode.And be to improve heat endurance, prevent metal Grid and high dielectric constant gate insulating layer react, generally at metal gates and high dielectric constant grid All setting up barrier layer between insulating barrier, this barrier layer generally can use titanium nitride (TiN) to complete.But above-mentioned In the manufacture process of gate configuration, often come into question because the planarization of element surface is not good, how to improve These are not enough, for development the main object of the present invention.

Content of the invention

The purpose of the present invention is exactly to provide a kind of flattening method, can be applicable in integrated circuit technology, The deficiency not good in order to improve any means known planarization.

The present invention proposes a kind of flattening method, is applied in semiconductor element technique, under the method includes Row step: substrate is provided;Form dielectric layer on this substrate, its dielectric layer has groove;In this Groove sequentially forms barrier layer and metal level;The first reactant is utilized to carry out first to metal level smooth Metallization processes, exposes barrier layer in order to remove the metal level of part, and wherein the first reactant is to metal level Etch-rate is more than the etch-rate to barrier layer;And utilize the second reactant to come to barrier layer and metal Layer carries out the second flatening process, exposes dielectric layer in order to remove the barrier layer of part and metal level, its In the second reactant to the etch-rate of barrier layer more than the etch-rate to metal level.

In a preferred embodiment of the invention, above-mentioned flattening method also include formed gate dielectric in Below this dielectric layer.

In the preferred embodiments of the present invention, above-mentioned flattening method also included shape before forming barrier layer Become gate dielectric in groove.

In a preferred embodiment of the invention, above-mentioned gate dielectric is dielectric layer with high dielectric constant, resistance Barrier layer is gate barrier layer, and metal level is gate metal layer.

In a preferred embodiment of the invention, above-mentioned dielectric layer with high dielectric constant can be by hafnium oxide (HfO2)、 The single or multiple lift structure that the materials such as hafnium silicon oxynitride (HfSiON) or hafnium silicon oxide (HfSiO) complete.

In a preferred embodiment of the invention, above-mentioned barrier layer can be by titanium nitride (TiN), ramet (TaC), the materials such as tungsten carbide (WC), titanium carbide (TiC), tantalum nitride (TaN), TiAlN (TiAlN) The single or multiple lift structure completing.

In a preferred embodiment of the invention, above-mentioned metal level can be by titanium nitride (TiN), tungsten (W), aluminium (A1), the materials such as titanium (Ti), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), copper (Cu) or nickel (Ni) complete Single or multiple lift structure.

In a preferred embodiment of the invention, the first above-mentioned flatening process and this second flatening process Can be respectively the first CMP process and the second CMP process, and this first reactant The first chemical mechnical polishing agent and the second chemical mechnical polishing agent can be respectively with this second reactant.First Flatening process and the second flatening process can complete on single board, or being divided among providing does not assimilates Learn and complete on multiple boards of mechnical polishing agent, and the first chemical mechnical polishing agent and the second chemical machinery are thrown Photo etching may also include the sticky material of silica, ceria or alumina powder.

In a preferred embodiment of the invention, the first above-mentioned chemical mechnical polishing agent and this second chemistry machine Tool polishing agent all can include oxidant (oxidizer), the oxidant concentration of the first chemical mechnical polishing agent Can be less than the oxidant concentration in the second chemical mechnical polishing agent.

In a preferred embodiment of the invention, above-mentioned oxidant can be hydrogen peroxide.

In a preferred embodiment of the invention, the above-mentioned hydrogen peroxide in the first chemical mechnical polishing agent is dense Degree scope can be 0%~1%, and the concentration of hydrogen peroxide scope in this second chemical mechnical polishing agent can be more than 1%.

The present invention also proposes another kind of flattening method, is applied in semiconductor element technique, the method bag Include the following step: providing substrate, surface has the grid structure including polycrystalline silicon dummy gate pole and dielectric layer Make;Remove polycrystalline silicon dummy gate pole and in dielectric layer, form at least groove;Form gate barrier layer in this ditch On the surface of groove sidewall and bottom and this dielectric layer;Form gate metal layer in the table of this gate barrier layer On face and fill up this groove;The first reactant is utilized to carry out the first smooth chemical industry to this gate metal layer Skill, exposes this gate barrier layer in order to remove this gate metal layer of part, wherein this first reactant Etch-rate to this gate barrier layer is more than to the etch-rate of this gate metal layer;And utilize second Reactant carries out the second flatening process to this gate barrier layer and this gate metal layer, in order to removing unit Point this gate barrier layer and this gate metal layer and expose this dielectric layer, wherein this second reactant is to this The etch-rate of gate barrier layer is more than the etch-rate to this gate metal layer.

In a preferred embodiment of the invention, above-mentioned flattening method also include formed gate dielectric in Below this dielectric layer.

In the preferred embodiments of the present invention, above-mentioned flattening method also included shape before forming barrier layer Become gate dielectric in groove.

In a preferred embodiment of the invention, it is above set forth in this gate metal layer that removing unit divides and expose grid The following step is may also include: utilize the 3rd reactant to carry out to gate metal layer before the step of barrier layer Three flatening process, in order to reduce the thickness of gate metal layer to preset thickness, the 3rd reactant is to this grid The etch-rate of pole metal level is more than this first reactant etch-rate to gate metal layer.

In a preferred embodiment of the invention, above-mentioned preset thickness can be more than 100 angstroms.

In a preferred embodiment of the invention, above-mentioned gate dielectric is dielectric layer with high dielectric constant, this Dielectric layer with high dielectric constant is by hafnium oxide (HfO2), hafnium silicon oxynitride (HfSiON) or hafnium silicon oxide Etc. (HfSiO) the single or multiple lift structure that material completes.

In a preferred embodiment of the invention, above-mentioned barrier layer can be by titanium nitride (TiN), ramet (TaC), the materials such as tungsten carbide (WC), titanium carbide (TiC), tantalum nitride (TaN), TiAlN (TiAlN) The single or multiple lift structure completing.

In a preferred embodiment of the invention, above-mentioned metal level can be by titanium nitride (TiN), tungsten (W), aluminium (A1), the materials such as titanium (Ti), tantalum (Ta), tantalum nitride (TaN), cobalt (Co), copper (Cu) or nickel (Ni) complete Single or multiple lift structure.

In a preferred embodiment of the invention, the first above-mentioned flatening process and this second flatening process Can be the first CMP process and the second CMP process respectively, and this first reactant Can be the first chemical mechnical polishing agent and the second chemical mechnical polishing agent respectively with this second reactant.First Flatening process and the second flatening process can complete on single board, or being divided among providing does not assimilates Learn and complete on multiple boards of mechnical polishing agent, and the first chemical mechnical polishing agent and the second chemical machinery are thrown Photo etching may also include the sticky material of silica, ceria or alumina powder.

In a preferred embodiment of the invention, the first above-mentioned chemical mechnical polishing agent is for this gate metal Layer is more than 20 with the etching selectivity of this gate barrier layer, and this second chemical mechnical polishing agent is for this grid Metal level is more than 20 with the etching selectivity of this gate barrier layer.

In a preferred embodiment of the invention, above-mentioned this first chemical mechnical polishing agent and this second chemistry Mechnical polishing agent all can include oxidant (oxidizer), the oxidant of this first chemical mechnical polishing agent Concentration is less than the oxidant concentration in this second chemical mechnical polishing agent.

In a preferred embodiment of the invention, above-mentioned oxidant can be hydrogen peroxide.

In a preferred embodiment of the invention, the above-mentioned hydrogen peroxide in the first chemical mechnical polishing agent is dense Degree scope can be 0%~1%, and the concentration of hydrogen peroxide scope in this second chemical mechnical polishing agent can be more than 1%.

The present invention also proposes another kind of gate configuration, and this construction includes substrate, dielectric layer, gate barrier layer And gate metal layer.Dielectric layer is positioned at surface and has at least one groove.Gate barrier layer is positioned at In groove.Gate metal layer is positioned on the surface of gate barrier layer and fills up groove.Gate metal layer end face Less than trenched side-wall, and both differences in height are less than 50 angstroms.

Brief description

Fig. 1 (a), 1 (b), 1 (c), which is the present invention by improve any means known deficiency be developed with regard to put down The processing step schematic diagram of smoothization method.

Fig. 2 (a), 2 (b), which is two kinds of gate configuration schematic diagrames that the technology of the present invention is completed.

Description of reference numerals

Substrate 10 dielectric layer 101

Gate dielectric 1010

Barrier layer 102 metal level 103

Groove 104 saucerization 1030

Detailed description of the invention

Refer to Fig. 1 (a), 1 (b), 1 (c), which is the present invention and be developed by improving any means known deficiency With regard to the processing step schematic diagram of flattening method, can be widely applied in semiconductor element technique.First, First provide substrate 10, for example common silicon substrate, then carry out on this substrate 10 high-k/ Metal gates (HKMG) technique completes metal-oxide semiconductor transistor component, as shown in Fig. 1 (a), Form dielectric layer 101 above this substrate 10, this dielectric layer 101 is formed groove 104, and this ditch Groove 104 is formed gate dielectric (gate dielectirc layer) the 1010th, barrier layer (barrier Layer) 102 grid structure (gate structure) is completed with metal level 103.This groove 104 can be for will be many Crystal silicon false grid (dummy poly, figure not shown in) is formed after removing.As for the grid in grid structure Pole dielectric layer 1010 can re-form after groove 104 is formed, and then completes the structure as shown in Fig. 1 (a) Make, but before groove 104 is formed, also just can form gate dielectric 1010, shown such as Fig. 2 (a). And this gate dielectric 1010 can be completed by high-k dielectric materials.Permissible as this barrier layer Being the gate barrier layer in gate configuration, this metal level can be then the gate metal in gate configuration Layer.

Followed by the first reactant, the first flatening process is carried out to this metal level 103, in order to remove This metal level 103 of part and expose this barrier layer 102, the wherein composition through control the first reactant, The etch-rate of this metal level 103 will be adjusted more than the etch-rate to this barrier layer 102.Such one Come, just etching action can be parked on barrier layer 102, but also because the etching of metal level 103 is very fast, Just producing the structure as shown in Fig. 1 (b), barrier layer 102 exposes and metal level 103 produces a little dish Depression (dishing) 1030.

For eliminating above-mentioned saucerization 1030, the present invention just recycles the second reactant to the resistance exposing Barrier layer 102 and metal level 103 carry out the second flatening process, in order to remove the barrier layer 102 of part with This metal level 103 of part and expose the dielectric layer 101 outside groove 104 opening, wherein this second reaction The etch-rate to this barrier layer 102 for the agent is more than the etch-rate to metal level 103.Consequently, it is possible to erosion Action at quarter can be parked on dielectric layer 101, but the metal level 103 because the etching of barrier layer 102 is very fast Etching is relatively slow, just produces the structure as shown in Fig. 1 (c), the saucerization 1030 that metal level 103 has originally To be eliminated, and then reach smooth surface.The end face of metal level 103 is less than groove 104 sidewall, also It i.e. is less than 50 angstroms less than the difference in height of the end face of both sides dielectric layer 101.After eventually passing cleaning, just may be used Send into lower one technique, the making of such as inner layer dielectric layer.

And according to the explanation of above-mentioned steps, the present invention passes through the different planarization of etching selectivity twice Technique, by can the planarization of product after effectively lifting process completes, and then improve the deficiency of any means known, Reach development the main object of the present invention.And above-mentioned first flatening process and the second flatening process can divide It is not the first CMP process and the second CMP process, and the first reactant and second Reactant can be respectively the first chemical mechnical polishing agent and the second chemical mechnical polishing agent.And these planarizations Technique can complete on single board (Single pad CMP), or is divided among providing different chemical machinery to throw Complete (multi-pad CMP) on multiple boards of photo etching, and these chemical mechnical polishing agents may also include Have sticky material (abrasive material), such as silica (SiO2), ceria (CeO2) or oxygen Change aluminium (Al2O3) powder (powder) etc..In addition, this first chemical mechnical polishing agent and this second chemistry machine All including oxidant (oxidizer) in tool polishing agent, for adjusting suitable etching selectivity, this is first years old The oxidant that the oxidant concentration of chemical mechnical polishing agent will be less than in this second chemical mechnical polishing agent is dense Degree, and this oxidant can be hydrogen peroxide etc., for example, the peroxide in the first chemical mechnical polishing agent Changing range of hydrogen concentrations can be 0%~1%, the concentration of hydrogen peroxide scope in this second chemical mechnical polishing agent Then can be more than 1%, such as 3% or 5%, consequently, it is possible to the first chemical mechnical polishing agent is for this grid Metal level can be controlled in more than 20 with the etching selectivity of this gate barrier layer, the second chemical mechnical polishing agent Etching selectivity for this gate metal layer and this gate barrier layer then can be controlled in more than 20.

As for this gate dielectric (gate dielectirc layer) 1010, mainly can be by high K dielectric Layer completes, for example, can be hafnium oxide (HfO2), hafnium silicon oxynitride (HfSiON) or hafnium silicon oxide (HfSiO) The single or multiple lift structure completing Deng material, is mainly formed at the lower section of barrier layer 102, and grid is situated between If electric layer 1010 is formed at (i.e. so-called " HK First ") before groove 104 completes, gate dielectric 1010 Just only can be formed at bottom groove 104, and form what the technology of the present invention as shown in Fig. 2 (a) was completed Gate configuration schematic diagram, if but removing polycrystalline silicon dummy gate and re-form gate dielectric 1010 (i.e. institute extremely afterwards Meaning " HK Last "), gate dielectric 1010 then can be formed at bottom groove 104 with sidewall and U-shaped Section, forms the gate configuration as shown in Fig. 2 (b).As for this barrier layer 102 can by titanium nitride (TiN), Ramet (TaC), tungsten carbide (WC), titanium carbide (TiC), tantalum nitride (TaN), TiAlN (TiAlN) The single or multiple lift structure completing Deng material, this barrier layer 102 may be used to play the part of work content in gate configuration Number metal level (Work Function metal layer), stressor layers (strained layer), work function fine setting gold Belong to layer (Work Function tuning metal layer), inner liner (liner layer) or sealing layer (sealant The role such as layer).As for metal level 103 can be by titanium nitride (TiN), tungsten (W), aluminium (Al), titanium (Ti), The metals such as tantalum (Ta), tantalum nitride (TaN), cobalt (Co), copper (Cu) or nickel (Ni) or metallic alloy complete Single or multiple lift structure.

In addition, for production capacity can be increased, utilize the first reactant remove part this gate metal layer and Before exposing the step of this gate barrier layer, also first with the 3rd reactant, this metal level 103 can be carried out 3rd flatening process, the thickness in order to reduce this gate metal layer stops reconvert extremely to preset thickness This first flatening process.Preset thickness can be set to close to 100 angstroms but be more than 100 angstroms, and due to the 3rd Reactant is adjustable into the faster etching speed with this metal level 103, implies that the 3rd reactant pair The etch-rate of this metal level 103 is more than this first reactant etch-rate to this metal level 103, because of The thickness of this metal level 103 can quickly be contracted by and reduce the process time.

In sum, after technology is improved by the present invention, can effectively eliminate in any means known smooth Change not good problem.Although the present invention discloses as above with preferred embodiment, so it is not limited to this Invention, any persons skilled in the art, without departing from the spirit and scope of the present invention, when can make A little change and retouching, therefore protection scope of the present invention ought be defined depending on claim and is as the criterion.

Claims (23)

1. a flattening method, is applied in semiconductor element technique, and the method comprises the following steps:
Substrate is provided;
Form dielectric layer on this substrate, wherein this dielectric layer has groove;
Gate dielectric, barrier layer and metal level, wherein this gate dielectric is sequentially formed in this groove It is only formed in this groove;
The first reactant is utilized to carry out the first flatening process to this metal level, in order to remove being somebody's turn to do of part Metal level and expose this barrier layer, wherein this first reactant to the etch-rate of this metal level more than to this The etch-rate of barrier layer;And
The second reactant is utilized to carry out the second flatening process to this barrier layer and this metal level, in order to remove Going this barrier layer of part and this metal level to expose this dielectric layer, wherein this second reactant is to this barrier The etch-rate of layer is more than the etch-rate to this metal level, wherein this first reactant and this second reaction All including oxidant in agent, the oxidant concentration of this first reactant is less than the oxygen in this second reactant Agent concentration.
2. flattening method as claimed in claim 1, wherein this gate dielectric is that high-k is situated between Electric layer, this barrier layer is gate barrier layer, and this metal level is gate metal layer.
3. flattening method as claimed in claim 2, wherein this dielectric layer with high dielectric constant is by aoxidizing The single or multiple lift structure that hafnium, hafnium silicon oxynitride or hafnium silicon oxide complete.
4. flattening method as claimed in claim 1, wherein this barrier layer be by titanium nitride, ramet, The single or multiple lift structure that tungsten carbide, titanium carbide, tantalum nitride, TiAlN complete.
5. flattening method as claimed in claim 1, wherein this metal level be by titanium nitride, tungsten, aluminium, The single or multiple lift structure that titanium, tantalum, tantalum nitride, cobalt, copper or nickel complete.
6. flattening method as claimed in claim 1, wherein this first flatening process is second flat with this Smooth metallization processes is respectively the first CMP process and the second CMP process, and this first Reactant and this second reactant are respectively the first chemical mechnical polishing agent and the second chemical mechnical polishing agent, These flatening process complete on single board, or are divided among providing different chemical mechnical polishing agent Complete on multiple boards, and these chemical mechnical polishing agents also include silica, ceria or It is the sticky material of alumina powder.
7. flattening method as claimed in claim 1, wherein this oxidant is hydrogen peroxide.
8. flattening method as claimed in claim 6, the wherein mistake in this first chemical mechnical polishing agent Hydrogen peroxide concentration scope is 0~1, the concentration of hydrogen peroxide scope in this second chemical mechnical polishing agent For more than 1.
9. a flattening method, is applied in semiconductor element technique, and the method comprises the following steps:
There is provided substrate, this surface has the gate configuration including polycrystalline silicon dummy gate pole and dielectric layer;
Remove this polycrystalline silicon dummy gate pole and in this dielectric layer, form at least one groove;
Form gate dielectric only in the groove;
Form gate barrier layer on the surface of this trenched side-wall and bottom and this dielectric layer;
Form gate metal layer and and fill up this groove on the surface of this gate barrier layer;
The first reactant is utilized to carry out the first flatening process to this gate metal layer, in order to remove part This gate metal layer and expose this gate barrier layer, wherein this first reactant is to this gate metal layer Etch-rate is more than the etch-rate to this gate barrier layer;And
The second reactant is utilized to carry out the second smooth chemical industry to this gate barrier layer and this gate metal layer Skill, exposes this dielectric layer in order to remove this gate barrier layer of part and this gate metal layer, wherein should The etch-rate to this gate barrier layer for second reactant is more than the etch-rate to this gate metal layer, should First reactant and this second reactant all include oxidant, the oxidant concentration of this first reactant Less than the oxidant concentration in this second reactant.
10. flattening method as claimed in claim 9, wherein in this gate metal layer removing part Also comprise the following steps: before the step exposing this gate barrier layer
The 3rd reactant is utilized to carry out the 3rd flatening process to this gate metal layer, in order to reduce this grid The thickness of pole metal level is more than to preset thickness, the etch-rate to this gate metal layer for the 3rd reactant This first reactant etch-rate to this gate metal layer.
11. flattening methods as claimed in claim 10, wherein this preset thickness is more than 100 angstroms.
12. flattening methods as claimed in claim 9, wherein this gate dielectric is that high-k is situated between Electric layer, this dielectric layer with high dielectric constant is the list being completed by hafnium oxide, hafnium silicon oxynitride or hafnium silicon oxide Layer or sandwich construction.
13. flattening methods as claimed in claim 9, wherein this barrier layer be by titanium nitride, ramet, The single or multiple lift structure that tungsten carbide, titanium carbide, tantalum nitride, TiAlN complete.
14. flattening methods as claimed in claim 9, wherein this metal level be by titanium nitride, tungsten, aluminium, The single or multiple lift structure that titanium, tantalum, tantalum nitride, cobalt, copper or nickel complete.
15. flattening methods as claimed in claim 9, wherein this first flatening process is second flat with this Smooth metallization processes is respectively the first CMP process and the second CMP process, and this first Reactant and this second reactant are respectively the first chemical mechnical polishing agent and the second chemical mechnical polishing agent, These flatening process complete on single board, or are divided among providing different chemical mechnical polishing agent Complete on multiple boards, and these chemical mechnical polishing agents also include silica, ceria or It is the sticky material of alumina powder.
16. flattening methods as claimed in claim 15, wherein this first chemical mechnical polishing agent for This gate metal layer is more than 20 with the etching selectivity of this gate barrier layer, this second chemical mechnical polishing agent Etching selectivity for this gate metal layer and this gate barrier layer is more than 20.
17. flattening methods as claimed in claim 15, wherein this oxidant is hydrogen peroxide.
18. flattening methods as claimed in claim 17, wherein in this first chemical mechnical polishing agent Concentration of hydrogen peroxide scope is 0~1, the concentration of hydrogen peroxide model in this second chemical mechnical polishing agent Enclose for more than 1.
19. 1 kinds of gate configuration, comprising:
Substrate;
Dielectric layer, is positioned at this surface and has at least one groove;
Gate dielectric, is positioned at below this dielectric layer or is only located in this groove;
Gate barrier layer, is positioned in this groove, on the surface of this gate dielectric;And
Gate metal layer, is positioned on the surface of this gate barrier layer and fills up this groove, this gate metal layer End face is less than this trenched side-wall, and both differences in height are less than 50 angstroms.
20. gate configuration as claimed in claim 19, wherein this gate dielectric is that high-k is situated between Electric layer.
21. gate configuration as claimed in claim 20, wherein this dielectric layer with high dielectric constant is by aoxidizing The single or multiple lift structure that hafnium, hafnium silicon oxynitride or hafnium silicon oxide complete.
22. gate configuration as claimed in claim 19, wherein this gate barrier layer is for by titanium nitride, carbon The single or multiple lift structure that change tantalum, tungsten carbide, titanium carbide, tantalum nitride, TiAlN complete, this grid Barrier layer is as workfunction layers, stressor layers, work function fine setting metal level, inner liner or sealing layer.
23. gate configuration as claimed in claim 19, wherein this gate metal layer be by titanium nitride, tungsten, The single or multiple lift structure that aluminium, titanium, tantalum, tantalum nitride, cobalt, copper or nickel complete.
CN201110040219.0A 2011-02-18 2011-02-18 It is applied to the flattening method in semiconductor element technique and gate configuration CN102646580B (en)

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