JP2013093438A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology capable of improving reliability of a semiconductor device; and especially a technology capable of obtaining stable performance characteristics in a semiconductor device having a field effect transistor with a gate electrode composed of a metal material.SOLUTION: A semiconductor device manufacturing method comprises: forming a gate electrode 13n or a gate electrode 13p by dry etching using a resist pattern 12 as a mask; subsequently, performing an ashing treatment in a plasma atmosphere containing oxygen and hydrogen to remove the resist pattern 12; oxidizing a reaction product 14 adhered to a lateral face of the gate electrode 13n or the gate electrode 13p; and subsequently, performing a cleaning treatment to remove the reaction product 14.

Description

  The present invention relates to a method for manufacturing a semiconductor device. In particular, the present invention relates to a technique that is effective when applied to the manufacture of a semiconductor device having a field effect transistor having a gate electrode made of a metal material.

  For example, Japanese Patent Application Laid-Open No. 2010-161350 (Patent Document 1) describes a substrate processing method used in an ashing apparatus, and after heating a substrate coated with a resist mixed with a dopant, at least an oxygen component and A technique is disclosed in which a reaction gas containing a hydrogen component and having a hydrogen component concentration of 60% or more and 70% or less is supplied to a processing chamber, and the substrate is processed in a plasma state.

JP 2010-161350 A

Along with the miniaturization of field effect transistors, a technique of using a high-k material instead of conventional silicon oxide (SiO ₂ ) or silicon oxynitride (SiON) for the gate insulating film is being studied. This is because the gate leakage current that increases due to the tunnel effect is suppressed, and the effective equivalent film thickness (EOT: Equivalent Oxide Thickness) is reduced to improve the gate capacitance, thereby increasing the driving capability of the field effect transistor. .

  Manufacturing of HK (High-k) / MG (Metal Gate) transistors (hereinafter referred to as HK / MG transistors) in which the gate insulating film is made of a high-k material having a high relative dielectric constant and the gate electrode is made of a metal material. There are two methods: a gate first process and a gate last process.

  The gate first process is a method of forming a source / drain diffusion layer by forming a gate insulating film and a gate electrode, and then performing impurity ion implantation and subsequent high-temperature activation annealing, and is consistent with the conventional manufacturing process. This is a highly reliable method. On the other hand, the gate last process is a method of forming a gate insulating film and a gate electrode after forming a source / drain diffusion layer by performing impurity ion implantation and subsequent high-temperature activation annealing.

  In the gate last process, when the gate electrode is formed, the high-k material and the metal material are not exposed to various reaction gases, and are not subjected to high-temperature activation annealing. Can be avoided. However, since the gate last process is a more complicated process than the gate first process, there is a concern that the manufacturing yield may be lowered.

  Therefore, the present inventors examined application of a gate-first process as a method for manufacturing an HK / MG transistor. However, it is clear that when the gate electrode is formed, the metal material is exposed to various reaction gases, so that the property and shape of the gate electrode change and the operating characteristics of the HK / MG transistor fluctuate. became. Therefore, how to suppress changes in the properties and shape of the metal material when forming the gate electrode is an important issue to be solved.

  An object of the present invention is to improve the reliability of a semiconductor device.

  In particular, it is an object of the present invention to provide a technique capable of obtaining stable operating characteristics in a semiconductor device having a field effect transistor whose gate electrode is made of a metal material.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, an embodiment of a representative one will be briefly described as follows.

  In this embodiment, a metal insulating film and a gate insulating film are formed by a step of forming a gate insulating film on a main surface of a semiconductor substrate, a step of forming a metal film on the gate insulating film, and dry etching using a resist pattern as a mask. A step of forming a gate electrode made of a metal film by sequentially processing the film, a step of removing a resist pattern by performing an ashing process in a plasma atmosphere containing oxygen and hydrogen, and a gate insulating film and a gate electrode are formed. And a step of cleaning the semiconductor substrate to remove reaction products formed on the side surfaces of the gate insulating film and the gate electrode.

  Among the inventions disclosed in the present application, effects obtained by one embodiment of a representative one will be briefly described as follows.

  That is, the reliability of the semiconductor device can be improved.

It is principal part sectional drawing of the n channel type HK / MG transistor and p channel type HK / MG transistor which show the manufacturing process of the semiconductor device by one embodiment of this invention. FIG. 2 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 1; FIG. 3 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 2; FIG. 4 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 3; FIG. 5 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 4; FIG. 6 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 5; FIG. 7 is an essential part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 6; FIG. 8 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 7; FIG. 9 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 8; FIG. 10 is an essential part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 9; FIG. 11 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 10; FIG. 12 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 11; FIG. 13 is a principal part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 12; FIG. 14 is an essential part cross-sectional view of the same place as in FIG. 1 in the process of manufacturing the semiconductor device, following FIG. 13; FIG. 4 is a cross-sectional view of a main part of an n-channel HK / MG transistor and a p-channel HK / MG transistor showing a manufacturing process of a semiconductor device studied by the present inventors prior to the present invention. FIG. 16 is a principal part cross-sectional view of the same place as in FIG. 15 in the process of manufacturing the semiconductor device, following FIG. 15;

  In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Further, in the drawings used in the following embodiments, hatching may be added to make the drawings easy to see even if they are plan views. In the following embodiments, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) representing a field effect transistor is abbreviated as MIS, a p-channel type MISFET is abbreviated as pMIS, and an n-channel type MISFET is abbreviated as nMIS. In the following embodiments, the term “wafer” is mainly a silicon (Si) single crystal wafer. However, not only that, but also an SOI (Silicon On Insulator) wafer and an integrated circuit are formed thereon. Insulating film substrate or the like. The shape includes not only a circle or a substantially circle but also a square, a rectangle and the like.

  In the following embodiments, a gate or a gate structure refers to a stacked film of a gate insulating film and a gate electrode, and is distinguished from a gate electrode.

  In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  The gate structure of the n-channel HK / MG transistor described here includes an interface layer (eg, a silicon oxide film) and a high dielectric film containing lanthanum (La) (eg, a hafnium oxynitride (HfLaON) film containing lanthanum)). And a gate electrode made of a laminated film of a metal film (for example, titanium nitride (TiN) film) formed on the gate insulating film and a polycrystalline silicon film.

  The gate structure of the p-channel HK / MG transistor is a stack of an interface layer (eg, a silicon oxide film) and a high dielectric film containing aluminum (Al) (eg, a hafnium oxynitride (HfAlON) film containing aluminum)). A gate insulating film made of a film, and a gate electrode made of a laminated film of a metal film (for example, titanium nitride (TiN) film) and a polycrystalline silicon film formed thereon.

  Therefore, the gate structure (gate insulating film and gate electrode) of the n-channel type HK / MG transistor is the gate stack structure for Nch, and the gate structure (gate insulating film and gate electrode) of the p-channel type HK / MG transistor is the gate stack for Pch. The structure is marked to distinguish between the two structures. In addition, the Nch gate stack structure or the Pch gate stack structure refers to both a structure with and without an interface layer constituting the lower layer of the gate insulating film.

  First, since it seems that the manufacturing method of the HK / MG transistor according to the present embodiment will become clearer, the cause of the variation in the operating characteristics of the HK / MG transistor found by the present inventors will be described with reference to FIGS. Will be described below.

  As shown in FIG. 15, the gate of the HK / MG transistor is formed on the main surface of the semiconductor substrate 51 made of single crystal Si. The gate includes an interface layer 52, a high dielectric film having a predetermined dielectric constant (a dielectric film having a higher dielectric constant than silicon oxide or silicon oxynitride) 53, a metal film 54 having a predetermined work function, And a stack structure in which the polycrystalline silicon films 55 are stacked.

  Here, as the interface layer 52, for example, an insulating film such as silicon oxide or silicon oxynitride is applied.

In the case of an n-channel HK / MG transistor, the high dielectric film 53 includes a hafnium-based dielectric film containing lanthanum (for example, hafnium silicon oxynitride (HfSiON), hafnium silicon oxynitride (HfSiO), hafnium oxynitride ( HfON) or hafnium oxide (HfO ₂ ) or the like is applied. By including lanthanum, the threshold voltage of the n-channel HK / MG transistor (threshold voltage of the hafnium-based dielectric film) is adjusted. In the case of a p-channel HK / MG transistor, as the high dielectric film 53, a hafnium-based dielectric film containing aluminum (for example, hafnium silicon oxynitride (HfSiON), hafnium silicon oxynitride (HfSiO), hafnium oxynitride ( HfON) or hafnium oxide (HfO ₂ ) or the like is applied. By including aluminum, the threshold voltage of the p-channel HK / MG transistor (the threshold voltage of the hafnium-based dielectric film) is adjusted.

  As the metal film 54, for example, transition metal such as titanium (Ti), tantalum (Ta), nickel (Ni), zirconium (Zr), ruthenium (Ru), cobalt (Co), or tungsten (W), or A metal nitride such as titanium nitride (TiN) is applied.

  Immediately after forming the gate of the stack structure, a resist pattern 56 used as a mask for patterning the gate remains on the upper surface of the gate of the stack structure, and a reaction product (polymer) is formed on the side surface of the gate of the stack structure. ) 57 is attached.

  Next, an ashing process is performed in an oxygen plasma atmosphere to remove the resist pattern 56 and oxidize the reaction product 57. Subsequently, the oxidized reaction product 57 is removed by a cleaning process using an aqueous solution of hydrogen fluoride (HF) or the like. Since the reaction product 57 is difficult to be completely removed only by the ashing process or the washing process alone, the reaction product 57 is once oxidized by the ashing process and then removed by the washing process.

  However, when the ashing process is performed in an oxygen plasma atmosphere, the reaction product 57 is oxidized, but the inner metal film 54 is also oxidized. When the metal film 54 is oxidized, the work function of the metal film 54 varies. For example, in the case of an n-channel HK / MG transistor, the threshold voltage increases when the metal film 54 is oxidized.

  Further, as shown in FIG. 16, a metal oxide 58 is formed on the side surface of the metal film 54. Since the metal oxide 58 is removed by a subsequent cleaning process, the width of the metal film 54 in the gate length direction is shortened. As a result, the gate length of the HK / MG transistor becomes shorter than the design dimension, causing a problem that a desired threshold voltage cannot be obtained. Further, when the region where the source / drain region overlaps with the metal film 54 becomes smaller in a top view, the parasitic resistance increases and the on-current decreases. As the gate length of the HK / MG transistor becomes shorter, the above problem becomes more serious.

(Embodiment)
About a manufacturing method of a CMIS (Complementary Metal Insulator Semiconductor) device composed of an n-channel HK / MG transistor (hereinafter referred to as nMIS) and a p-channel HK / MG transistor (hereinafter referred to as pMIS) according to the present embodiment It demonstrates in order of a process using FIGS. 1 to 14 are main-portion cross-sectional views along the channel length direction of nMIS and pMIS.

  First, as shown in FIG. 1, for example, a semiconductor substrate (in this stage, a semiconductor plate having a substantially circular shape called a semiconductor wafer) in which, for example, p-type impurities (for example, boron (B)) are introduced into single crystal silicon, 1 Prepare. Subsequently, the element isolation portion 2 is formed in a predetermined region of the semiconductor substrate 1, and the active region where the nMIS is formed and the active region where the pMIS is formed are separated from each other by the element isolation portion 2.

Next, a p-type well 3 is formed by selectively introducing a p-type impurity (for example, boron) into the semiconductor substrate 1 in the nMIS region using an ion implantation method. For example, conditions for ion implantation of boron include an implantation energy of 150 keV and a dose amount of 2 × 10 ¹³ cm ⁻² . Further, a p-type impurity (such as boron) is selectively introduced into the channel region by an ion implantation method. For example, conditions for ion implantation of boron include an implantation energy of 5 keV and a dose amount of 2 × 10 ¹² cm ⁻² .

Similarly, an n-type well 4 is formed by selectively introducing an n-type impurity (for example, arsenic (As) or phosphorus (P)) into the semiconductor substrate 1 in the pMIS region using an ion implantation method. For example, as conditions for ion implantation of phosphorus, an implantation energy of 250 keV and a dose of 2 × 10 ¹³ cm ⁻² can be exemplified. Further, an n-type impurity (such as arsenic or phosphorus) is selectively introduced into the channel region by an ion implantation method. For example, as conditions for ion implantation of arsenic, an implantation energy of 50 keV and a dose amount of 5 × 10 ¹² cm ⁻² can be exemplified.

Next, as shown in FIG. 2, an interface layer 5 is formed on the main surface of the semiconductor substrate 1. For example, an insulating film such as silicon oxide or silicon oxynitride is applied to the interface layer 5, and the thickness thereof is, for example, about 1 nm. Subsequently, a high-k film (a dielectric film having a higher dielectric constant than silicon oxide or silicon oxynitride) 6 having a predetermined dielectric constant is formed on the main surface of the semiconductor substrate 1. As the high-k film 6, for example, a hafnium-based dielectric film such as hafnium silicon oxynitride (HfSiON), hafnium silicon oxide (HfSiO), hafnium oxynitride (HfON), or hafnium oxide (HfO ₂ ) is applied. . The High-k film 6 is formed by using, for example, a CVD (Chemical Vapor Deposition) method or ALD (Atomic Layer Deposition), and the effective equivalent film thickness is, for example, about 1.5 nm.

Subsequently, after performing nitriding treatment, a capping layer 7 p for adjusting the threshold voltage of pMIS is deposited on the High-k film 6. The capping layer 7p is formed of a metal film or a metal oxide film. As such a metal film or metal oxide film, for example, aluminum oxide (Al ₂ O ₃ ) or aluminum is applied. The capping layer 7p is formed using, for example, a sputtering method, and the thickness thereof is, for example, about 0.5 to 1 nm. Subsequently, a metal film 8 is deposited on the capping layer 7p. As the metal film 8, for example, a transition metal such as titanium, tantalum, nickel, zirconium, ruthenium, cobalt, or tungsten, or a metal nitride such as titanium nitride is applied. The metal film 8 is formed using, for example, a sputtering method, and the thickness thereof is, for example, about 10 nm.

  Next, as shown in FIG. 3, a resist pattern (not shown) that covers the pMIS formation region is formed by photolithography. Subsequently, using the resist pattern as a mask, the metal film 8 and the capping layer 7p exposed from the resist pattern are removed, and then the resist pattern is removed.

  Next, as shown in FIG. 4, a capping layer 7 n for adjusting the threshold voltage of nMIS is deposited on the main surface of the semiconductor substrate 1. The capping layer 7n is formed of a metal film or a metal oxide film made of a material different from that of the capping layer 7p. As such a metal film or metal oxide film, for example, lanthanum oxide (LaO) or lanthanum is applied. The capping layer 7n is formed using, for example, a sputtering method, and the thickness thereof is, for example, about 0.5 to 1 nm.

  Subsequently, heat treatment is performed. This heat treatment is performed at 1000 ° C. for 10 seconds, for example. By this heat treatment, aluminum is thermally diffused from the capping layer 7p to the high-k film 6, and the high-k film 6 in the pMIS formation region is a high dielectric film (for example, a hafnium oxynitride (HfAlON) film containing aluminum) 6p. It becomes. Further, by this heat treatment, lanthanum is thermally diffused from the capping layer 7n to the high-k film 6, and the high-k film 6 in the nMIS formation region is a high dielectric film (for example, a hafnium oxynitride (HfLaON) film containing lanthanum). ) 6n.

  Next, as shown in FIG. 5, the metal film 8 and the capping layers 7n and 7p are removed. Note that all of the capping layers 7n and 7p may be removed or may be partially left without being removed. FIG. 5 shows a mode in which the capping layers 7n and 7p are partially left.

  As a result, the gate insulating film 9n composed of the interface layer 5 and the high dielectric film 6n is formed in the nMIS formation region, and the gate insulating film 9p composed of the interface layer 5 and the high dielectric film 6p is formed in the pMIS formation region. It is formed.

  Next, as shown in FIG. 6, a metal film 10 is deposited on the main surface of the semiconductor substrate 1. As the metal film 10, for example, a transition metal such as titanium, tantalum, nickel, zirconium, ruthenium, cobalt, or tungsten, or a metal nitride such as titanium nitride is applied. The metal film 10 is formed by using, for example, a sputtering method, and the thickness thereof is, for example, about 10 nm. Subsequently, a polycrystalline silicon film 11 is deposited on the metal film 10. The polycrystalline silicon film 11 is formed by using, for example, a CVD method, and the thickness thereof is, for example, about 100 nm. Subsequently, heat treatment is performed. This heat treatment is performed at 1000 ° C. for 10 seconds, for example.

Next, as shown in FIG. 7, a resist pattern 12 for forming gates in the nMIS formation region and the pMIS formation region is formed by photolithography. Subsequently, using the resist pattern 12 as a mask, the polycrystalline silicon film 11, the metal film 10, the capping layers 7n and 7p, the high dielectric films 6n and 6p, and the interface layer 5 exposed from the resist pattern 12 are processed. . Etching gases used for processing the polycrystalline silicon film 11 until the metal film 10 is exposed are, for example, sulfur hexafluoride (SF ₆ ), tetrafluoromethane (CF ₄ ), trifluoromethane (CHF ₃ ), and nitrogen (N ₂ ) and an etching gas used for processing the polycrystalline silicon film 11 after the metal film 10 is exposed is, for example, a mixed gas of hydrogen bromide (HBr), oxygen (O ₂ ), and helium (He). is there. The etching gas used for processing the metal film 10 is, for example, a mixed gas of hydrogen bromide (HBr), chlorine (Cl ₂ ), nitrogen (N ₂ ), and argon (Ar). An etching gas used for processing the high dielectric films 6n and 6p is, for example, a mixed gas of boron trichloride (BCl ₃ ) and chlorine (Cl ₂ ).

  As a result, in the nMIS formation region, the gate insulating film 9n made of a laminated film of the interface layer 5 and the high dielectric film 6n, the capping layer 7n, and the gate electrode made of the laminated film of the metal film 10 and the polycrystalline silicon film 11 are formed. The gate of the Nch stack gate structure composed of 13n is formed.

  Further, in the pMIS formation region, a gate insulating film 9p made of a laminated film of the interface layer 5 and the high dielectric film 6p, a capping layer 7p, and a gate electrode 13p made of a laminated film of the metal film 10 and the polycrystalline silicon film 11 are formed. The gate of the Pch stack gate structure constituted by is formed.

  The side surface of the gate of the nMIS Nch stack gate structure (hereinafter referred to as nMIS gate) and the side of the gate of the pMIS Pch stack gate structure (hereinafter referred to as pMIS gate) have a reaction product (polymer). 14 is attached. The reaction product 14 is a compound made of, for example, silicon, titanium, hafnium, lanthanum, aluminum, bromine, or chlorine. Hafnium and aluminum are contained in the high dielectric films 6n and 6p and the capping layers 7n and 7p, and bromine and chlorine are contained in the etching gas.

  Next, as shown in FIG. 8, by performing an ashing process in a plasma atmosphere containing oxygen and hydrogen, the resist pattern 12 used as a mask when patterning the nMIS gate and the pMIS gate is removed.

  By the way, the reaction product 14 is attached to the side surface of the nMIS gate and the side surface of the pMIS gate. The reaction product 14 can be removed by a cleaning process using an aqueous solution of hydrogen fluoride or the like, but the reaction product 14 needs to be oxidized by an ashing process.

  However, when the ashing process is performed in an oxygen plasma atmosphere (oxygen alone or diluted oxygen diluted with nitrogen or the like), the reaction product 14 is oxidized, but the inner metal film 10 is also oxidized. This causes a problem that the work functions of the metal film 10 constituting the nMIS gate and a part of the pMIS gate fluctuate, and the desired threshold voltages of the nMIS and pMIS cannot be obtained.

  Furthermore, when a metal oxide is formed on the side surface of the metal film 10, the metal oxide is removed in a later step, and the width of the metal film 10 in the gate length direction is shortened. Thereby, the gate length of the nMIS and the gate length of the pMIS are shorter than the design dimension, and the desired threshold voltage of the nMIS and the pMIS cannot be obtained, and the region where the source / drain region and the metal film 10 overlap when viewed from above. As the resistance becomes smaller, the parasitic resistance increases and the on-current decreases.

  On the other hand, when an ashing process is performed in a hydrogen plasma atmosphere (hydrogen alone or diluted hydrogen diluted with nitrogen or the like), the resist pattern 12 is removed, but the reaction product 14 is not oxidized. Therefore, the reaction product 14 cannot be removed by a cleaning process using an aqueous solution of hydrogen fluoride or the like.

  Therefore, in this embodiment mode, the ashing process is performed in a plasma atmosphere containing oxygen and hydrogen. Since hydrogen is reducible, by controlling the ratio between the oxygen concentration and the hydrogen concentration in the plasma atmosphere, the reaction product 14 is oxidized, but the inner metal film 10 is not oxidized. it can. As the relationship between the oxygen concentration and the hydrogen concentration in the plasma atmosphere, for example, it is considered that the oxygen concentration is in the range of 0.7 to 4.0 times the hydrogen concentration. The range is considered to be most suitable (not to be limited to this range depending on other conditions). When the oxygen concentration is lower than 0.7 times the hydrogen concentration, the reaction product 14 is not oxidized, and when the oxygen concentration is higher than 4.0 times the hydrogen concentration, the metal film 10 inside the reaction product 14 is oxidized. The

Further, an inert gas such as nitrogen or argon may be added to the plasma atmosphere containing oxygen and hydrogen. For example, by adding nitrogen, oxygen separation is promoted and plasma is easily generated. Specifically, the mixing ratio of nitrogen, hydrogen, and oxygen is N ₂ : H ₂ : O ₂ = 24: 1: 1. In this case, the oxygen concentration is 1.0 times the hydrogen concentration. As other conditions for the ashing treatment, a power of 1000 to 3000 W, a pressure of 500 to 3000 mT, and a temperature of 100 to 250 ° C. can be exemplified.

  Next, the reaction product 14 is removed by a cleaning process using an aqueous solution of hydrogen fluoride or the like. Since the reaction product 14 is oxidized, it can be easily removed by this washing treatment.

  Thus, in the ashing process for removing the resist pattern 12, the reaction product 14 attached to the side surface of the nMIS gate and the side surface of the pMIS gate can be oxidized by using a plasma atmosphere containing oxygen and hydrogen. Therefore, in the subsequent steps, the reaction product 14 can be removed by a cleaning process using an aqueous solution of hydrogen fluoride or the like.

  On the other hand, the oxidation of the metal film 10 constituting part of the nMIS gate and the pMIS gate can be suppressed. As a result, changes in the work function of the metal film 10 constituting the nMIS gate and a part of the pMIS gate can be suppressed, so that desired threshold voltages of nMIS and pMIS can be obtained. Furthermore, since a metal oxide is not formed on the side surface of the metal film 10, a phenomenon that the width of the metal film 10 in the gate length direction is shortened can be prevented. Thereby, desired threshold voltages of nMIS and pMIS can be obtained. In addition, since a region where the source / drain regions of nMIS and pMIS overlap with the metal film 10 can be secured in a top view, an increase in parasitic resistance can be prevented and desired ON currents of nMIS and pMIS can be obtained. .

Next, as shown in FIG. 9, since the metal film 10 constituting the nMIS gate and a part of the pMIS gate is exposed to oxidation and other modifications, the nMIS An offset sidewall 15 made of an insulating film is formed on the side surface of the gate and the side surface of the gate of pMIS. The offset sidewall 15 is formed by forming an insulating film having a thickness of, for example, about 5 nm on the main surface of the semiconductor substrate 1 by using, for example, a CVD method, and then anisotropically etching the insulating film by using a dry etching method. It is formed by doing. For example, a silicon nitride (Si ₃ N ₄ ) film is used as the insulating film. Since the silicon nitride film is less likely to pass oxygen than the silicon oxide film, the silicon nitride film is preferable to the silicon oxide film from the viewpoint of preventing oxidation.

  Subsequently, the pMIS formation region is covered with a resist pattern, and n-type diffusion is performed in a self-aligned manner with respect to the gate and the offset sidewall 15 in the semiconductor substrate 1 (p-type well 3) in the nMIS formation region using an ion implantation method. Region 16 is formed. The n-type diffusion region 16 is a semiconductor region and is formed by introducing an n-type impurity such as phosphorus or arsenic into the semiconductor substrate 1. Thereafter, the resist pattern is removed by ashing in an oxygen plasma atmosphere. The ashing process may be performed in a plasma atmosphere containing oxygen and hydrogen, but the hydrogen concentration contained in the plasma atmosphere is used as a mask when patterning the resist pattern 12 (the nMIS gate and the pMIS gate). The concentration of hydrogen contained in the plasma atmosphere of the ashing treatment for removing the resist pattern) is preferably lower. The reason is that in this step, the metal film 10 is covered with the offset sidewall 15 and is less likely to be oxidized. Therefore, the polymer generated in this step can be more reliably oxidized by performing the ashing treatment at a low hydrogen concentration. Therefore, the polymer can be more reliably removed in the subsequent washing step.

  Similarly, the nMIS formation region is covered with a resist pattern, and p-type diffusion is performed in a self-aligned manner with respect to the gate and the offset sidewall 15 in the semiconductor substrate 1 (n-type well 4) in the pMIS formation region using an ion implantation method. Region 17 is formed. The p-type diffusion region 17 is a semiconductor region and is formed by introducing a p-type impurity such as boron into the semiconductor substrate 1. Thereafter, the resist pattern is removed by ashing in an oxygen plasma atmosphere. The ashing process may be performed in a plasma atmosphere containing oxygen and hydrogen, but the hydrogen concentration contained in the plasma atmosphere is higher than the hydrogen concentration contained in the plasma atmosphere of the ashing process for removing the resist pattern 12 described above. Preferably it is low. The reason is the same as that in the process of forming the n-type diffusion region 16 described above.

  Next, as shown in FIG. 10, after a silicon nitride film and a silicon oxide film are sequentially deposited on the main surface of the semiconductor substrate 1, the silicon nitride film and the silicon oxide film are anisotropically formed using a dry etching method. Etching. Thus, the sidewalls 18 are formed on the side surfaces of the nMIS gate and the pMIS gate via the offset sidewalls 15.

  Subsequently, the pMIS formation region is covered with a resist pattern, and an n-type diffusion region is formed on the semiconductor substrate 1 (p-type well 3) in the nMIS formation region in a self-aligned manner with respect to the gate and the sidewall 18 by using an ion implantation method. 19 is formed. The n-type diffusion region 19 is a semiconductor region and is formed by introducing an n-type impurity such as phosphorus or arsenic into the semiconductor substrate 1. Thereafter, the resist pattern is removed by ashing in an oxygen plasma atmosphere. The ashing process may be performed in a plasma atmosphere containing oxygen and hydrogen, but the hydrogen concentration contained in the plasma atmosphere is higher than the hydrogen concentration contained in the plasma atmosphere of the ashing process for removing the resist pattern 12 described above. Preferably it is low. The reason is that in this step, the metal film 10 is covered with the offset sidewalls 15 and the sidewalls 18 and is less likely to be oxidized. Therefore, the polymer generated in this step can be more reliably oxidized by performing the ashing treatment at a low hydrogen concentration. Therefore, the polymer can be more reliably removed in the subsequent washing step.

  Similarly, the nMIS formation region is covered with a resist pattern, and a p-type diffusion region is formed in a self-aligned manner with respect to the gate and the sidewall 18 on the semiconductor substrate 1 (n-type well 4) in the pMIS formation region by using an ion implantation method. 20 is formed. The p-type diffusion region 20 is a semiconductor region and is formed by introducing a p-type impurity such as boron into the semiconductor substrate 1. Thereafter, the resist pattern is removed by ashing in an oxygen plasma atmosphere. The ashing process may be performed in a plasma atmosphere containing oxygen and hydrogen, but the hydrogen concentration contained in the plasma atmosphere is higher than the hydrogen concentration contained in the plasma atmosphere of the ashing process for removing the resist pattern 12 described above. Preferably it is low. The reason is the same as that in the process of forming the n-type diffusion region 19 described above.

  Subsequently, heat treatment is performed. This heat treatment is performed, for example, at 1000 ° C. for 10 seconds and at 1230 ° C. for several milliseconds. By this heat treatment, the n-type impurity introduced into the n-type diffusion region 16 and the n-type diffusion region 19 in the nMIS formation region is activated, and the p-type introduced into the p-type diffusion region 17 and the p-type diffusion region 20 in the pMIS formation region. The type impurities are activated to form respective source / drain regions.

Next, as shown in FIG. 11, a nickel film is formed on the main surface of the semiconductor substrate 1, and then heat treatment is performed. This heat treatment is performed at 450 ° C., for example. By this heat treatment, silicon and nickel constituting the semiconductor substrate 1 and silicon and nickel constituting the polycrystalline silicon film 11 are solid-phase reacted to form nickel silicide (NiSi). Subsequently, unreacted nickel is removed using a mixed solution of sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide solution (H ₂ O ₂ ), whereby the surface of the source / drain region of nMIS and the gate electrode 13n. A nickel silicide film 21 is formed on the upper surface of the substrate. Similarly, a nickel silicide film 21 is formed on the surface of the source / drain region of pMIS and the upper surface of the gate electrode 13p. Instead of the nickel silicide film 21, for example, a platinum silicide (PtSi) film, a cobalt silicide (CoSi ₂ ) film, or the like can be used.

  Next, as shown in FIG. 12, a stopper insulating film 22 is deposited on the main surface of the semiconductor substrate 1. The stopper insulating film 22 is a silicon nitride film formed by using, for example, a CVD method, and the thickness thereof is, for example, about 30 nm.

Subsequently, an interlayer insulating film 23 is formed on the main surface of the semiconductor substrate 1. The interlayer insulating film 23 is formed using, for example, a plasma CVD method, for example, a plasma CVD method using TEOS (Tetra Ethyl Ortho Silicate; Si (OC ₂ H ₅ ) ₄ ) and ozone (O ₃ ) as source gases. A TEOS film formed using Subsequently, the surface of the interlayer insulating film 23 is planarized using, for example, a CMP (Chemical Mechanical Polishing) method, and then connected to the stopper insulating film 22 and the interlayer insulating film 23 using a photolithography method and a dry etching method. 24 is formed.

  Next, as shown in FIG. 13, a barrier metal film 25 a is formed on the interlayer insulating film 23 including the bottom and side surfaces of the connection hole 24 by using, for example, a sputtering method. The barrier metal film 25a is, for example, a titanium nitride (TiN) film, a tantalum (Ta) film, or a tantalum nitride (TaN) film, and prevents the material embedded in the connection hole 24 from diffusing in a later process. It has a so-called barrier function. Subsequently, a tungsten film 25 b is formed on the main surface of the semiconductor substrate 1 so as to fill the inside of the connection hole 24. The tungsten film 25b is formed using, for example, a CVD method or a sputtering method. Subsequently, the tungsten film 25b and the barrier metal film 25a are polished by using, for example, a CMP method, thereby forming a plug 25 made of the barrier metal film 25a and the tungsten film 25b inside the connection hole 24.

  Next, as shown in FIG. 14, a wiring insulating film 26 is formed on the main surface of the semiconductor substrate 1. The wiring insulating film 26 is, for example, a TEOS film. Subsequently, a wiring groove 27 is formed in the wiring insulating film 26 by using a photolithography method and a dry etching method.

  Subsequently, a barrier metal film 28a is formed on the wiring insulating film 26 including the bottom and side surfaces of the wiring groove 27 by using, for example, a sputtering method. The barrier metal film 28a is, for example, a titanium nitride film, a tantalum film, or a tantalum nitride film. Subsequently, after a copper (Cu) seed layer is formed on the barrier metal film 28a by using, for example, a sputtering method, a copper film 28b is formed so as to fill the inside of the wiring groove 27 by a plating method. Subsequently, after performing heat treatment, the copper film 28b, the copper seed layer, and the barrier metal film 28a are polished by using, for example, a CMP method, so that the wiring having the copper film 28b as a main conductor inside the wiring groove 27 is provided. 28 is formed. Thereafter, an upper layer wiring is formed, but the description thereof is omitted here.

  Note that the n-type diffusion region 16, the p-type diffusion region 17, the n-type diffusion region 19, and the p-type diffusion region described above also in the step of removing the resist pattern used when forming the connection hole 24 and the wiring groove 27. It is preferable to perform an ashing process with a low hydrogen concentration in the same manner as the step of removing the resist pattern used when forming 20. The same applies to the reason.

  The CMIS device (nMIS and pMIS) according to the present embodiment is substantially completed through the above manufacturing process.

  As described above, according to the present embodiment, in the step of forming the nMIS gate and the pMIS gate, the work function change and the gate length direction of the metal film 10 constituting a part of the nMIS gate and the pMIS gate are formed. Can be reduced. Thereby, desired threshold voltages of nMIS and pMIS can be obtained. Further, it is possible to prevent the parasitic resistance from increasing and obtain the desired on-currents of nMIS and pMIS.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied to the manufacture of a semiconductor device having a field effect transistor whose gate electrode is made of a metal material.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation | separation part 3 P-type well 4 N-type well 5 Interface layer 6 High-k film 6n, 6p High dielectric material film 7n, 7p Capping layer 8 Metal film 9n, 9p Gate insulating film 10 Metal film 11 Polycrystal Silicon film 12 Resist pattern 13n, 13p Gate electrode 14 Reaction product (polymer)
15 Offset sidewall 16 n-type diffusion region 17 p-type diffusion region 18 sidewall 19 n-type diffusion region 20 p-type diffusion region 21 nickel silicide film 22 stopper insulating film 23 interlayer insulating film 24 connection hole 25 plug 25a barrier metal film 25b tungsten Film 26 Insulating film for wiring 27 Wiring groove 28 Wiring 28a Barrier metal film 28b Copper film 51 Semiconductor substrate 52 Interface layer 53 High dielectric film 54 Metal film 55 Polycrystalline silicon film 56 Resist pattern 57 Reaction product 58 Metal oxide

Claims (16)

A semiconductor device manufacturing method including the following steps:
(A) forming a first insulating film on the main surface of the semiconductor substrate;
(B) forming a metal film on the first insulating film;
(C) processing the metal film by dry etching using the first resist pattern as a mask to form a gate electrode made of the metal film;
(D) a step of removing the first resist pattern by performing an ashing process in a first plasma atmosphere containing oxygen and hydrogen after the step (c);
(E) A step of performing a cleaning process on the semiconductor substrate on which the gate electrode is formed after the step (d).   2. The method of manufacturing a semiconductor device according to claim 1, wherein the oxygen concentration is 0.7 to 4.0 times the hydrogen concentration in the first plasma atmosphere in the step (d). Production method.   2. The method of manufacturing a semiconductor device according to claim 1, wherein an oxygen concentration is 1.0 to 2.5 times a hydrogen concentration in the first plasma atmosphere in the step (d). Production method.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the metal film contains titanium nitride. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step between the step (b) and the step (c).
(F) forming a polycrystalline silicon film on the metal film;
Including
In the step (c), the polycrystalline silicon film and the metal film are processed by dry etching using the first resist pattern as a mask.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first plasma atmosphere in the step (d) further includes nitrogen or argon. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising, after the step (e),
(G) forming a semiconductor region in the semiconductor substrate on both sides of the gate electrode by ion implantation of impurities using the second resist pattern as a mask;
(H) After the step (g), performing an ashing process in a second plasma atmosphere to remove the second resist pattern;
Including
The method of manufacturing a semiconductor device, wherein a hydrogen concentration contained in the second plasma atmosphere in the step (h) is lower than a hydrogen concentration contained in the first plasma atmosphere in the step (d). 8. The method of manufacturing a semiconductor device according to claim 7, wherein after the step (e) and before the step (g),
(I) forming a second insulating film on a side surface of the gate electrode;
A method for manufacturing a semiconductor device, comprising:   9. The method of manufacturing a semiconductor device according to claim 8, wherein the second insulating film is a silicon nitride film. 8. The method of manufacturing a semiconductor device according to claim 7, further comprising, after the step (h),
(J) forming an interlayer insulating film on the semiconductor substrate so as to cover the gate electrode and the semiconductor region;
(K) forming a connection hole reaching the semiconductor region in the interlayer insulating film using the third resist pattern as a mask;
(L) After the step (k), performing an ashing process in a third plasma atmosphere to remove the third resist pattern;
Including
A method for manufacturing a semiconductor device, wherein a hydrogen concentration contained in the third plasma atmosphere in the step (l) is lower than a hydrogen concentration contained in the first plasma atmosphere in the step (d).   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film is a hafnium-based dielectric film containing lanthanum or aluminum.   12. The method of manufacturing a semiconductor device according to claim 11, wherein the hafnium-based dielectric film is hafnium silicon oxynitride, hafnium silicon oxide, hafnium oxynitride, or hafnium oxide.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film is a laminated film of an interface layer and a hafnium-based dielectric film containing lanthanum or aluminum. .   14. The method of manufacturing a semiconductor device according to claim 13, wherein the hafnium-based dielectric film is hafnium silicon oxynitride, silicon oxide hafnium, hafnium oxynitride, or hafnium oxide. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising: (m) forming a capping layer containing lanthanum or aluminum between the step (a) and the step (b);
(N) performing a heat treatment on the semiconductor substrate to diffuse the lanthanum or the aluminum into the first insulating film;
A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
After the step (c), a polymer is attached to the side surface of the gate electrode,
The method of manufacturing a semiconductor device, wherein the polymer is exposed to the ashing process in the step (d) and removed by the cleaning process in the step (e).

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