TW201232625A - Planarization method applied in process of manufacturing semiconductor component - Google Patents

Abstract

A planarization method applied in a process of manufacturing a semiconductor component includes the following steps. A dielectric layer, a barrier layer and a metal layer are formed above the substrate in sequence. A first planarization process is applied to the metal layer by using a first reactant so that a portion of the metal layer is removed to expose the barrier layer. An etching rate of the first reactant to the metal layer is greater than that of the first reactant to the barrier layer. A second planarization process is applied to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and a portion of the metal layer are removed to expose the dielectric layer. An etching rate of the second reactant to the barrier layer is greater than that of the second reactant to the metal layer.

Description

201232625 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention provides a planarization method, and more particularly to a planarization method that can be applied to a rotating element. [Prior Art] P legacy semiconductor tree material (4) speed Wei, the component size has entered the rice level so far, so the gold oxide semi-transistor element shoots ___((}ate Didee=

The thickness of the layer is thinner and thinner, but the thickness of the thin layer is bound to severely limit the leakage current. The mechanical leakage current will affect the characteristics of the component, resulting in an increase in the energy consumption of the product. Therefore, the high dielectric constant (the following High_k) material is used to complete the insulation layer, and the rib reduces the gate leakage current: the means. In addition, the High_k process is often combined with a metal gate (here (four) is used to reduce the resistance of the gate electrode. To improve the thermal conductivity, the gate is protected against the gate and the high dielectric is often used. , through f in the Jinxian ^ dielectric constant between the insulating layer is added - the barrier layer, the barrier layer pass = case titanium 〇 _ to complete. But in the above construction of the production of kerchiefs, often due to =: The problem is that it is not good, and how to improve these defects is the development of the present invention. The object of the present invention is to provide a flattening method for improving the lack of planarization of the manufacturing method. ~, integrated body method, applied to the material component process, the electrical layer has a - trench; in the trench sequentially formed a = layer and electro-layer metal layer t 201232625 using the first reaction The first planarization process is performed on the metal layer to remove a portion of the metal layer to expose the barrier layer, wherein the etching rate of the first reactant to the metal layer is greater than the rate of the first layer of the barrier layer; a second reactant to perform a second planarization of the barrier layer and the metal layer The method for removing a portion of the barrier layer and the metal layer, wherein the etching rate of the second reactant to the barrier layer is greater than the etching of the metal layer. In the preferred embodiment of the present invention, the planarization method described above The method further includes forming a gate dielectric layer under the dielectric layer. In a preferred embodiment of the invention, the planarization method further comprises forming a gate dielectric layer in the trench before forming the barrier layer. In a preferred embodiment of the invention, the gate dielectric layer is a high dielectric constant η electrical layer, the turn layer is a gate turn layer, and the metal layer is a gate metal layer. In the preferred side towel of the present invention, the high-k dielectric layer may be a single layer or a multilayer structure of hafnium oxide (HfO 2 ), niobium oxynitride (N-N) or oxidized stone (knot). In a preferred embodiment of the present invention, the barrier layer may be made of titanium nitride, tantalum carbide (TaC), tantalum carbide (wc), carbonized (called, nitrided light (τ • nitrogen) a single layer or a multilayer structure completed by a material such as Ti-Ti (Ti Shi). In a preferred embodiment of the present invention, the above metal It can be made of single or multiple layers of materials such as gas ΓΠΝ, crane (w), titanium, Ti, New Zealand, Ta, gasification, copper, or nickel. The structure of the flat Chen Jiashi, the above-mentioned flat-touching and the second- 1 weight can be a first chemical mechanical polishing process and a: grinding process, and the first reactant and the second reaction The agent can be - mechanical abrasive and - second chemical mechanical abrasive. The first - flattening process: l can be done on a single-individual basis, or separately in the same material as the chemical mechanical research 201232625 Finished on the machine 'and the first - chemical mechanical research material = grinding agent can further contain two _, cerium oxide oxidized in the preferred embodiment of the invention 'the first = two f mechanical abrasive All may contain oxidant 2: the concentration of the abrasive may be lower than the second chemical mechanical abrasive 2 = 2 = = = = ^ 峨 feather peroxidation gas. The hydrogen peroxide concentration in the (10) to 1% agent may be greater than 1%. In the case of peroxidation in mechanical abrasives, another planarization method is proposed, which is applied to a semiconductor device with a dummy gate and a dielectric material comprising polycrystalline germanium = trough: r-pole barrier layer in the 'wall trench: The first is greater than the _^, ^= 则 卿 卿 ( 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述 上述The front portion further includes forming a gate dielectric layer in the trench. In a preferred embodiment of the present invention, the step of removing the portion of the gate metal layer to expose the gate barrier layer may further include the following steps: using the third reactant to perform the gate metal layer The third planarization process is used to reduce the thickness of the gate metal layer to the pre-5 thickness. The third rate of the gate metal layer is greater than the rate of etching of the reactant to the gate metal layer. In the preferred embodiment of the invention, the predetermined thickness may be greater than 100 angstroms. In a preferred embodiment of the present invention, the gate dielectric layer is a high-k dielectric layer, and the high-k dielectric layer is formed by oxidized yttrium oxide ... oxynitride (leg ON) Or a single layer or a multilayer structure of materials such as oxidized stone cerium (cerebral palsy). In a preferred embodiment, the barrier layer may be made of a material such as a tantalum nitride tab (TaC), a carbonized crane (wc), a titanium carbide (Tic), or a nitrided titanium nitride (TU1N). Layer or multilayer structure. In the ^_ preferably real closed towel, the upper gold system can be made of nitrogen: tungsten (W), aluminum (A1), titanium (five), button (10), nitride button (dog copper (Cu) or chain (four) and other materials. The completed single-layer or multi-layer structure. In the present invention, the first-flattening process disk flattening process can be respectively - the first - chemical mechanical polishing system - the second - polishing process, and the first The shore agent 盥兮__ a first mechanical mechanical abrasive and a second chemical mechanical polishing: the grinding agent may further comprise oxidized oxo 2::3⁄4 in a preferred embodiment of the invention , the above-mentioned coffee-knitted axial barrier layer _ selection ratio is large === 201232625 ^Mechanical grinding #|The ratio of Xia·Gold and her barrier is greater than in the preferred embodiment of the present invention, the above-mentioned piano Flute one = chemical mechanical abrasives can contain aerobic two = ^ research _ oxidized thief New Zealand material two chemical thieves _; ' ^ invention inspection Jia Shi Guan, the above oxidation ship can be better for the oxygen rhyme In the embodiment, the above-mentioned first-chemical mechanical abrasive can be 〇%~1%, and the hydrogen concentration in the first episode can be more than 1%. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ In the trough. _ metal layer is located in the turn layer

Fill it up on the surface. The top surface of the metal layer is lower than the groove contact, and the difference between the two is less than 50 angstroms. X [Embodiment] Please refer to the figure - (8), (b), (6), which is developed in order to improve the use of f. The remaining steps of the flattening method can be widely used for the production of semiconductor components. Wei, first provides a substrate 1G, such as a common German board, and then completes the gold-oxygen semi-transistor element on the substrate 1G, as shown in the first figure (a). A dielectric layer 101 is formed over the substrate 1'. The dielectric layer 101 is formed with a trench 1〇4, and a gate dielectric layer 1010 is formed in the trench 1〇4. A barrier layer 101 and a metal layer 103 complete a gate structure. The trench 1〇4 may be formed by removing a polycrystalline whisker (not shown;). As for the 201232625 formation of the inter-electrode dielectric layer 1010', as shown in Figure t, the composition of the first-reactant can be controlled before the formation of the trench 104, which will be based on the gold-axis = over-block layer 1 〇 2 Stop the Lang action in the structure shown in the block, and it will produce the _ing qing. The layer is exposed and the metal layer 103 produces a slight dish-shaped depression to eliminate the above-mentioned dish-shaped depression. In this case, the exposed layer (10) and the gold-colored 1G3 are subjected to a second level. 103 is exposed to the trench 1 〇 = to the metal ^ The rate of the resist to the barrier layer 1 () 2 is greater than the rate of the metal layer (9). In this way, the _ action can be stopped on the dielectric layer (10) ^, but because the rhyme of the barrier layer 102 is faster and the metal layer 1 〇 3 is slower, the structure shown in the first -_ The dish-shaped depression originally possessed by the metal layer 1〇3 will be settled by the mine-flat surface. The top surface of the gold ω3 is lower than the groove 104, that is, the height difference of the top surface of the dielectric layer 1〇1 is less than % = after the cleaning, the person can be sent to the next channel, for example, (10) According to the above steps, the case is that the two sides select different than the different flattening processes, which will effectively improve the flatness of the products after the completion of the process, and thus the lack of 201232625, and achieve the main purpose of the development of the case. The first flattening and smashing machine ^ 帛 - flattening county can be divided into county 帛 - chemical frequency grinding process and the second 'and the first reverse _ and the second reactant can be the first - single r machine second chemical machine Abrasive. The planarization process can be carried out on an abrasive: multi: rdCMP, or separately from providing different chemical machinery, oxidized tree Ce02) or oxidized (Al2〇3) powder owfe). Further oxidizing L-rhenium chemical mechanical polishing, the second chemical mechanical polishing unit, including the argon H cap, and the oxidizing agent concentration in the first chemical mechanical polishing agent may have a hydrogen peroxide concentration range of more than 1%. ^如ς^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ However, if the structure of the gate completed by the technology shown in 夂夂^!7 is the god's m丨, and the gate of the eve of the day is formed, the gate dielectric layer is formed by 1〇1〇, and it will form _ ^ The female model is shown in Figure (b). As for the barrier 201232625, the layer 102 can be composed of titanium nitride (TiN), carbonization group (TaC), tungsten carbide (wc), titanium carbide (Tie), a single layer or a multilayer structure of a material such as a nitrided layer (TaN) or a titanium aluminum nitride (TiAIN), the barrier layer 102 being used to function as a work function metal layer in a gate structure (w〇rkFuncti〇n metal layer) , strained layer, work function fine metal layer (w〇rk function tuning metal layer), inner lining layer (iiner iayer) or sealant layer (sealant layer) special role. The metal layer IQ] may be composed of titanium nitride (BN), crane (w), Ilu^Al), titanium (Τι), button (Ta), nitride button (TaN), cobalt (c〇), A single or multi-layer structure made of copper (Cu) or nickel.

In addition, in order to increase the capacity, before the step of removing the portion of the gate metal layer* to expose the gate turn layer by using the first reactant, the doping layer 103 may be first performed by the third reaction = The third planarization process is configured to reduce the thickness of the gate gold π layer to a predetermined thickness and then stop and then switch to the first planarization process. The pre-f degree can be set to be close to 1 angstrom but larger than the touch, and since the third reactant can be adjusted, the metal layer 103 has a faster etch rate, meaning that the third reactant is :: layer I. The rate of 3 is greater than the rate at which the reactant removes the metal layer. Therefore, the thickness of the metal layer 1〇3 can be quickly reduced to reduce the process. After that, it has effectively eliminated the problem of poor generalization in the past. The invention has been disclosed in the preferred embodiments as the invention is not limited to the invention. Anyone who is familiar with the bribe can make some changes and refinements without departing from the present, so the invention is guaranteed. Attached to the application specific _ defined as the standard. [Simple description of the schema] The development of the missing means is in (b), (e)' This is the schematic diagram of the process steps of the improvement and the method. 201232625 The second figure (a), (b), which is a schematic diagram of the two gate structures completed by the technology of the present invention. [Description of main component symbols] Substrate 10 Dielectric layer 101 Gate dielectric layer 1010 Barrier layer 102 Metal layer 103 Trench 104 Dish recess 1030

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Claims (1)

201232625 Seven patent application scope: = flattening method - the semiconductor component is made of the following steps: providing a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer has a trench; Forming a barrier layer and a metal layer in the trench; The first planarization process is performed by using a ruthenium-reactant to the metal layer, and the barrier layer is exposed by a portion of the metal layer, wherein the first reactant etch rate of θ is greater than the barrier layer Etching rate; and using a second reactant to perform the second barrier layer on the barrier layer and the metal layer - (10) removing a portion of the barrier layer and the metal layer to reveal the dielectric layer, ^ φ and The rate of decay of the first-reactant to the layer is greater than the rate of etching of the layer. The planarization method of claim 1, further comprising the step of forming a gate dielectric layer under the dielectric layer. The planarization method of claim 1, wherein the forming of the barrier layer further comprises the step of forming a gate dielectric layer in the trench. 4. The planarization method according to the third aspect of the patent, wherein the gate dielectric layer is a south dielectric constant dielectric layer, and the barrier layer is a gate barrier layer. The metal layer is a gate metal layer. The planarization method according to claim 4, wherein the high dielectric constant, the electrical layer is oxidized to (Hf〇2), nitrous oxide (HfSiON) or oxidized stone (ΗβίΟ) A single or multi-layer structure that is completed by materials. 13 201232625 6. For the flattening method described in the patent application section IM(TiN) ^ „^(TaC) . „, U|(WC) . „,b„(Tic;:^; (pass), rat Single or multi-layer structure completed by materials such as TiA1N. See 7. For the application of the shed shed, the flat-field method = titanium (10)), the outline, the 嗔, _, the nitrogen (Cu) or the record (4) Single or multi-layer structure completed by materials. 8. The method for planarizing according to item i of the patent application, wherein the second planarization process is a first-chemical mechanical process disk, the first chemical conversion process, and the first reaction agent and the first reaction agent The first chemical-mechanical abrasive is the first one, and the other is the first one. The first one is done on the flat-twisting machine, and the servants are hungry. The oxygen of the Qilu Shanmen Chemical Machinery abrasives is yours. The chemical spray can also contain the dioxide, the emulsified enamel or the Oxygen County. $Wei Shixi, as stated in the patent scope 帛 8 items of the flattening method, the abrasive and the second chemical mechanical polishing all include the first - chemical machinery: Second, the school grinding 敎 _ 丨 her _ Second, the gasification agent twist. 9th tearing machine in the chemical mechanical abrasive, (4) oxygen__ u. The flattening method described in the patent application (4), wherein the first chemical machine 201232625 mechanical abrasive has a hydrogen peroxide concentration range of 0 %~1%, the concentration of hydrogen peroxide in the second chemical mechanical agent is in the range of more than 1%. 12·- kinds of planarization method 'finer than—semiconductor component process towel, column step: 匕3 卜 provides-substrate' has a gate structure including a polycrystalline sand dummy gate layer above the substrate; and removing the polysilicon a dummy gate forming at least one trench in the dielectric layer; forming a gate-transfer layer on the trench (four) and the bottom surface and the surface of the dielectric layer, forming a gate metal layer at the closed-pole resistor The trench is filled on the surface of the barrier layer. The first metal layer of the gate metal layer is removed by using a first-reactant to remove a portion of the gate metal layer to expose the closed-pole resistor. The barrier layer has a gate metal layer with a rate greater than that of the gate barrier layer - the first reaction age is performed on the impurity barrier layer and the gated metal layer to remove a portion of the gate The rate of the side of the pole barrier layer and the layer of the electrode layer is greater than the rate of etching of the gate metal layer. The _ 12 is a flattened green, and the shots include the following steps. Open > into a gate dielectric layer below the dielectric layer. The planarization method of claim 12, wherein the forming of the barrier layer comprises the step of forming a gate dielectric layer in the trench. The method of claim 12, wherein the step of removing the portion of the gate metal layer to expose the layer of the layer further comprises the following steps: using a third reactant Performing a third planarization process on the gate metal layer to reduce the thickness of the gate metal layer to a predetermined thickness, and the third (A) rate A against the gate metal layer is in the first-counter The gate gold method of claim 15, wherein the predetermined thickness of the towel is 100 angstroms. The method of planarizing according to claim 14, wherein the gate dielectric layer is a high dielectric dielectric layer, and the high dielectric constant is controlled by oxidation (Hf)单 2), a single layer or a multilayer structure of a material such as hafnium oxynitride (HfSiON) or hafnium oxide (HfSi〇). 18. The planarization method according to claim 12, wherein the barrier layer is made of titanium nitride, tantalum carbide (TaC), carbonized crane (wc), carbonized (Tic), nitrided. Single or multi-layer structure made of materials such as New Zealand (TaN) and titanium aluminum nitride (TiAIN). 19. The planarization method according to claim 12, wherein the metal layer is made of titanium nitride (TiN), H(W), #(Α1), titanium (9), group (9), nitrided group ( Single or multi-layer structure made of materials such as TaN), Ming (Co), copper (Cu) or nickel (Ni). 20. The planarization method of claim 12, wherein the first planarization process and the first planarization process are: a first chemical mechanical polishing process and a second chemical mechanical polishing process And the first reactant and the second reactant are respectively a chemical mechanical abrasive and a first chemical mechanical abrasive, and the planarization process is 201232625: the machine is completed or separated to provide different chemistry The majority of the mechanical abrasive is a oxidizing agent. The powder contains a dioxin, a sputum, and a chemical machine. The second chemistry; the ratio of the layer to the side of the pole is greater than the rice. The planarization method described in item 20 of the patent scope of the _ pole metal layer and the outline barrier layer is more than 2G1 1 , and the middle chemistry and the second chemical mechanical polishing agent The concentration of the oxidant in the first chemical machine/chemical mechanical abrasive, the oxidant concentration of the chemical mechanical polishing agent is lower than that of the method of the invention, the planarization method as described in claim n, the hydrogen peroxide wherein the oxidant Is #24 as Please patentable scope of the hydrogen peroxide concentration in the abrasive Μ item through the first planarizing method of the mechanical and the second _ is ⑽ ,,;: = peroxide gas concentration in the range of the chemical agent machine is greater than 1%. Thousand mechanical grinding 25. a gate structure, the structure comprising: a substrate; > π electrical layer, located above the substrate and having at least a trench; a gate blocking early layer, located in the trench; a gate metal layer on the surface of the gate barrier layer and filled with gas, sample 201232625 and the height difference between the two is less than 5 〇. The top surface of the gate metal layer is lower than the sidewall of the trench, = application The electrical shutdown layer of claim 25, located below the dielectric layer or in the trench, the barrier layer is further closed, and the gate structure is the gate structure. For example, if the application is specific, the high dielectric is U, and the gate structure described in the 25th item is included in the gate structure, which is the gate barrier layer; ΤιΝ), carbon (TaQ, carbon tilt (wc), titanium carbide (Tic), nitrogen 匕 (, N), t / (匕 办 办 (10) called the material to complete the single layer or multi-layer structure, the resistance The barrier layer can be used as a work function metal layer (rice touch _ annihilation (four), a trained layer, a work function tuning metal layer, an inner lining ( Linerlayer) 4 is a layered layer (10) 1 & pool (4). 30. The gate structure of claim 25, wherein the gate metal layer is made of titanium nitride (TiN), tantalum (W), Single or multi-layer structure made of materials such as Ming (A1), Titanium (Ti), Group (Ta), Nitrided Group (TaN), Cobalt (Co), Copper (Cu) or Nickel (Ni). Schema: 18