TW200935518A - Method of forming a semiconductor device - Google Patents

Method of forming a semiconductor device

Info

Publication number
TW200935518A
TW200935518A TW097141560A TW97141560A TW200935518A TW 200935518 A TW200935518 A TW 200935518A TW 097141560 A TW097141560 A TW 097141560A TW 97141560 A TW97141560 A TW 97141560A TW 200935518 A TW200935518 A TW 200935518A
Authority
TW
Taiwan
Prior art keywords
dielectric constant
layer
high dielectric
forming
heat treatment
Prior art date
Application number
TW097141560A
Other languages
Chinese (zh)
Other versions
TWI482218B (en
Inventor
Hui Ouyang
Jean-Luc Everaert
Laura Nyns
Rita Vos
Original Assignee
Taiwan Semiconductor Mfg
Imec Inter Uni Micro Electr
Univ Leuven Kath
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg, Imec Inter Uni Micro Electr, Univ Leuven Kath filed Critical Taiwan Semiconductor Mfg
Publication of TW200935518A publication Critical patent/TW200935518A/en
Application granted granted Critical
Publication of TWI482218B publication Critical patent/TWI482218B/en

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    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
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Abstract

The present invention is related to a method for forming a high-k gate dielectric, comprising the steps of: providing a semiconductor substrate; cleaning the substrate; performing a thermal treatment; performing a high-k dielectric material deposition, characterised in that said thermal treatment step id performed in a non-oxidizing ambient, leading to the forming of a thin interfacial layer.

Description

200935518 I 九、發明說明： 【發明所屬之技術領域】 _ 本發明係有關於積體電路的製備方法，且特別是有 . 關於一種沉積高介電常數材料於基材上的方法，藉此提 供一適合高介電常數材料沉積之界面層，更特別是關於 製備閘極介電結構時沉積高介電常數材料之方法。 【先前技術】 ❿ 目前需要縮小（降低）半導體元件之尺寸，以增加半導 體晶片之上的元件密度，使得半導體元件操作得更快且 消耗較少的功率。 二氧化矽最常作為半導體元件之閘極介電材料。然 而，將二氧化石夕應用作為閘極介電材料時，隨著二氧化 矽厚度的下降，伴隨對氧化過程的嚴格限制。使用這些 介電材料時，是需要控制整個晶圓之次埃（sub-angstrom) 均勻度與厚度。 © 再者，當介電層厚度降低的同時，量子穿隧效應 (quantum tunneling effects)傾向增加，造成不想要的電流 流經閘極與通道之間。 近來關於降低元件之尺寸，許多研究已經致力開發 另一種介電常數材料，其形成的厚度大於二氧化矽，且 仍然具有相同之場效表現。這些材料通常稱為高介電常 數(high-k)材料，因為其介電常數值高於二氧化矽之介電 常數值（3.9)。 0503-A33877TWF/linlm 5 200935518 此種高介電常數（high-k)材料的相對性能通常表示為 等效氧化層厚度（Equivalent oxide thickness, EOT)，因為 ^ 此種替代材料層可以更厚，但其仍然提供與相對較薄之 . 二氧化石夕層同樣的電性效果。 然而，使用較高介電常數材料之缺點在於，其容易 提供較差品質之界面。較差品質之界面容易損害最終閘 極電極微結構之電性表現，於上述例子中，高介電常數 材料係直接沉積於矽基材之上。 ® 因此，先前技術WO 2005/013349中提及介電材料（例 如二氧化珍或類似之材料）可提供一緩衝層（或界面或橋 樑）介於半導體晶圓和高介電常數材料之間，當使用高介 電常數材料時，用以改善其電性表現。 不幸地，很難發展超薄之界面層（例如厚度低於10 埃），且又具有均勻性。 缺乏均勻性可能會損害最終元件之電性特性。 為了整合高介電常數材料到目前CMOS製程系統 _ 中，良好品質（平坦、平滑、均勻且展現連續界面氧化物 成長）之界面層將有利於半導體基材和面介電常數材料之 界面。 此處的挑戰在於，將半導體晶圓基材（特別是二氧化 珍晶圓基材）和而介電常數材料之間的界面層品質隶佳 化，因該處的品質將決定最終電晶體之性能表現與可靠 度（reliablity)。 0503-A33877TWF/linlin 6 200935518 【發明内容】 f卷明的目的之一就是提供 法，其能解決先前技術之缺點。 °且替代之方 本發明的另—目的就是提供一種方法， 生一種均勻超薄之χ /、特別能產 電常數之材料一a+^ σ/几積具有高介 + (例如南介電常數（high-k)材料）。 圓）和介電層的在於改善介於半導體基材（或晶 ❿於基材之上間的界面，特別是沉積-高介電常數材料 ::月穴供—種尚介電常數閛極 二=下列步驟:提供-半導體基材；=方 -、以土、材4仃—熱處理；沉積一高介電 土，， 該熱處理於—益& 吊被材科，其中 热虱化％境中進行，導致 較佳者，上述清洗基材包括一最级之氫公層。 季佳者，於本發明的方法中，埶 期。C，較佳約高於1()()(^，處理之^皿度約高於 ❹ 較佳去，认4 約而於1050°c。 ^ Μ /· ;發明的方法中，其中該叙氧化p h 括一純氣’更佳包括氦氣及/或氬氣。，、，'氧化3^兄包 較佳者’於本發明的方法中，更 到無氧化環境中。 力入4分氫氣 較佳者，於本發明的方法 積約少於10%，較佳約介於1%〜10%、。中0刀風氣之體 2者’該無氧化環境中不包括氮氣。 較佳者，於本發明 在中其中熱處理之時間約 0503-A33877TWP/]iniin 7 200935518 少於2分鐘，較佳約少於ί分鐘，更佳約少於40秒。 較it者，依知、本發明的方法，其中於熱處理之後， 形成一薄化學氧化層。 車乂么者，上述之薄化學氧化層之形成藉由施加一 p 式臭氧（03)/最終去離子水(卿)處理或一 uv增強式氧^ ^^^^(UV-enhanced oxide growth method) 〇 Ο 粗者’依照本發明的方法中，其中高介電常數村 '、、、工何種’丨電吊數值(k)高於二氧化矽之介電材料。 >較佳者，上述之高介電常數材料係藉由原子層沉 在⑴mic Layer Deposition)沉積而得。 數材::本發明的方法中，其中沉積該高介電常 數糾^後，接著進行—沉積後退火處理。 =者，上述之薄界面層之厚度較佳約少於〇,6 _。 閑極介電材料。之方法’可用於形成的高介電常數 閘極介電材料上= 其包括-高介電常數 少於、o.6nm之薄界中面=電常數閘極介電材料包括一約 為讓本發明之上述和 明顯易懂，下文特兴…+ ’特徵和優點能更 作詳細說明如下··，牛出較佳貫施例，並配合所附圖式， 實施方式] 本發明係基於音& & 包括 心外發現一實行本發明之方法， 〇503-A33S77TWF/liniin 8 200935518 於含有鈍氣之無氧化環境中進行熱處理，以形成一薄界 面層。 本發明所謂之“無氧化環境”係指沒有氧氣的環境。 此環境較佳包括一鈍氣環境或鈍氣混合物，以及視需要 地包括其他添加劑。 特別是，添加氫氣於包含純氣環境或鈍氣混合物之 無氧環境中，可增加上述薄界面層之表面平滑度。 於本發明中，熱處理之步驟係進行於清洗基材之 ⑮後，以及未沉積高介電常數材料之前。 本發明所謂之“高介電常數”係指任何介電材料，其 具有一介電常數值k(相對於真空下）高於3.9(此為二氧化 矽之介電常數），且較佳高於8.0。 於包含鈍氣之無氧化環境中施加熱處理，會形成一 薄界面層。 上述之界面層可能包括氧化;5夕和次氧化物（SiOx， 0<xS 2) 〇 ® 本發明新穎之處在於形成一均勻（平滑或平整）薄的 (厚度小於10埃）界面層，其具有合理之缝隙（leakage)且 能增強電荷載子（charge carrier)的遷移率，然而使用先前 技術卻會得到低品質之界面層（粗糙（既不平整，不平滑， 也不均勻）且沒有連續之界面氧化層成長），造成較高的 缝隙（leakage)與較高的界面陷味密度（interface trap density, Dit)，且最終結果造成半導體元件較差的性能表 現。 0503-A33877TWF/linlin 9 200935518 已知當裸矽基材上曝露於含有氧氣的環境中時，自 身氧化層（native oxide)會成長於裸石夕基材上。 此種自身氧化層本質上是SiO和Si02的異質混合 物。 此種自身氧化層的品質與厚度在整個基材表面上是 不一致的，因此，於矽基材表面上的這些自身氧化薄膜 會阻礙對超薄閘極氧化薄膜厚度的準確控制。 因此，除了清潔其他物質以外，主要用於清潔基材 ❹上的自身氧化物，以避免污染以及為了產生優異的電性 表現。 清潔基材經常包括最終之氫氟酸（HF)疏水處理，用 以抑制氧自由基（redical)和石夕結合。 上述之最終氫氟酸疏水處理，亦稱為IMEC-foob， 是先使用臭氧和去離子水（〇3/DIW)之氧化步驟，接著使 用一氧化物移除步驟（使用HF/HC1)。最後，用去離子水 (去離子水掺鹽酸）潤洗，再進行含有異丙醇和氮氣之馬南 哥尼乾燥法（Marangoni drying)。 此最終氫氟酸處理（IMEC-foob)造成表面無氧化物。 但是，經由最終氫氟酸(IMEC-foob)之清潔所產生之 無氧化物的表面，其無法提供適合後續沉積高介電常數 (high-k)材料所需要之末端OH鍵。 因此，本發明建議基材經過清潔步驟後，接著於無 氧化環境中進行一熱處理。 上述之熱處理會形成一均勻薄氧化物及/或次氧化物 0503-A33877TWF/linlin 10 200935518 的界:U位於閘極介電層與半導體基材之間。 上述潯界面氧化物/次氧化物 面層:藉由於無氧化環境中施加—熱；^中溥界 弟1圖為一流程圖，用 半導體製備過程中的各階段步驟/友照本發明之方法於 如淺半導體主體中形成隔離結構，例 φ200935518 I IX. Description of the invention: [Technical field to which the invention pertains] _ The present invention relates to a method for preparing an integrated circuit, and in particular to a method for depositing a high dielectric constant material on a substrate, thereby providing An interfacial layer suitable for deposition of high dielectric constant materials, and more particularly a method of depositing a high dielectric constant material when preparing a gate dielectric structure. [Prior Art] It is currently required to reduce (reduce) the size of semiconductor elements to increase the density of components above the semiconductor wafer, so that the semiconductor elements operate faster and consume less power. Cerium oxide is most commonly used as a gate dielectric material for semiconductor components. However, when the application of the dioxide as a gate dielectric material, as the thickness of the cerium oxide decreases, it is accompanied by severe restrictions on the oxidation process. When using these dielectric materials, it is necessary to control the sub-angstrom uniformity and thickness of the entire wafer. Furthermore, as the thickness of the dielectric layer decreases, quantum tunneling effects tend to increase, causing unwanted current to flow between the gate and the channel. Recently, with regard to reducing the size of components, many studies have been devoted to the development of another dielectric constant material which is formed to a thickness greater than that of cerium oxide and still has the same field effect. These materials are commonly referred to as high-k materials because their dielectric constant values are higher than the dielectric constant values of cerium oxide (3.9). 0503-A33877TWF/linlm 5 200935518 The relative performance of such high-k material is usually expressed as Equivalent oxide thickness (EOT), because the alternative material layer can be thicker, but It still provides the same electrical effect as the relatively thinner. However, the disadvantage of using a higher dielectric constant material is that it is easy to provide a poor quality interface. The poor quality interface tends to impair the electrical performance of the final gate electrode microstructure. In the above example, the high dielectric constant material is deposited directly on the tantalum substrate. ® Thus, the prior art WO 2005/013349 mentions that a dielectric material, such as a dioxide or similar material, can provide a buffer layer (or interface or bridge) between the semiconductor wafer and the high dielectric constant material, When a high dielectric constant material is used, it is used to improve its electrical performance. Unfortunately, it is difficult to develop ultra-thin interface layers (eg, thicknesses below 10 angstroms) with uniformity. Lack of uniformity can compromise the electrical properties of the final component. In order to integrate high dielectric constant materials into current CMOS process systems, an interface layer of good quality (flat, smooth, uniform, and exhibiting continuous interfacial oxide growth) will facilitate the interface between the semiconductor substrate and the surface dielectric constant material. The challenge here is to optimize the quality of the interface layer between the semiconductor wafer substrate (especially the TiO2 substrate) and the dielectric constant material, because the quality of the wafer will determine the final transistor. Performance and reliability (reliablity). 0503-A33877TWF/linlin 6 200935518 SUMMARY OF THE INVENTION One of the purposes of f-volume is to provide a solution that addresses the shortcomings of the prior art. °Alternatively, another object of the present invention is to provide a method for producing a uniform ultra-thin χ /, particularly a material capable of producing a constant constant - a + ^ σ / product has a high dielectric + (for example, a south dielectric constant ( High-k) material). The round and dielectric layers are designed to improve the interface between the semiconductor substrate (or wafers on the substrate, especially the deposition - high dielectric constant material:: moon hole supply - species dielectric constant bucks two = the following steps: providing - semiconductor substrate; = square -, soil, material 4 - heat treatment; deposition of a high dielectric soil, the heat treatment in - Yi & hang hanging materials, which in the heat of the environment Preferably, the cleaning substrate comprises a level of hydrogen common layer. Preferably, in the method of the present invention, the period C, preferably about 1 () (), is processed. The degree of the dish is higher than ❹, preferably 4, about 1050 ° C. ^ Μ /· In the method of the invention, wherein the oxidizing ph includes a pure gas 'more preferably including helium and/or argon In the method of the present invention, the gas is more preferably in an oxidizing environment. The force of 4 minutes is preferred, and the method of the present invention is less than 10%. Preferably, it is between about 1% and 10%, and the body of the gas is not included in the oxidation-free environment. Preferably, in the present invention, the heat treatment time is about 0503-A3. 3877TWP/]iniin 7 200935518 is less than 2 minutes, preferably less than ί minutes, more preferably less than 40 seconds. More preferably, the method of the present invention, wherein after heat treatment, forms a thin chemical oxide layer In the case of the rut, the above-mentioned thin chemical oxide layer is formed by applying a p-type ozone (03) / final deionized water (clear) treatment or a uv-enhanced oxygen ^ ^ ^ ^ ^ (UV-enhanced oxide growth Method) 〇Ο 粗 粗 'in accordance with the method of the present invention, wherein the high dielectric constant village ',,, what kind of 'electrical hoisting value (k) is higher than the dielectric material of cerium oxide. The high dielectric constant material is deposited by atomic layer deposition (1) mic layer Deposition. The material: in the method of the invention, wherein the high dielectric constant is deposited, followed by post-deposition annealing The thickness of the thin interfacial layer is preferably less than about 〇, 6 _. The dielectric material of the dielectric material can be used to form a high dielectric constant gate dielectric material = it includes - high The dielectric constant is less than the thin boundary of o.6nm = the electrical constant gate dielectric material includes an approximately The above and clearly understandable, the following special features: + 'characteristics and advantages can be more detailed as follows · · · · · · · · · · · · · · · · · · · · · · · · · · · & Including the method of practicing the present invention, 〇503-A33S77TWF/liniin 8 200935518 is heat-treated in an oxidizing environment containing an blunt gas to form a thin interfacial layer. The so-called "oxidation-free environment" system of the present invention Refers to an environment without oxygen. Preferably, the environment comprises an inert gas or a mixture of blister gases, and optionally other additives. In particular, the addition of hydrogen to an oxygen-free environment containing a pure gas atmosphere or a blunt gas mixture can increase the surface smoothness of the above thin interface layer. In the present invention, the heat treatment step is performed after the substrate 15 is cleaned, and before the high dielectric constant material is deposited. The term "high dielectric constant" as used in the present invention means any dielectric material having a dielectric constant value k (relative to vacuum) higher than 3.9 (this is the dielectric constant of cerium oxide), and preferably higher. At 8.0. Applying a heat treatment in an oxidizing environment containing a blunt gas creates a thin interfacial layer. The above interface layer may include oxidation; 5th and epoxide (SiOx, 0 < xS 2) 〇® The novelty of the invention is to form a uniform (smooth or flat) thin (thickness less than 10 angstrom) interface layer, It has a reasonable leakage and can enhance the mobility of the charge carrier. However, using the prior art, a low-quality interface layer is obtained (rough (neither uneven, uneven, uneven) and continuous. The interface oxide layer grows, resulting in a higher gap and a higher interface trap density (Dit), and the resulting result is poor performance of the semiconductor device. 0503-A33877TWF/linlin 9 200935518 It is known that when a bare tantalum substrate is exposed to an oxygen-containing environment, the native oxide grows on the bare stone substrate. This self-oxidation layer is essentially a heterogeneous mixture of SiO and SiO 2 . The quality and thickness of such self-oxidized layers are inconsistent across the surface of the substrate, and therefore, these self-oxidizing films on the surface of the tantalum substrate can impede the accurate control of the thickness of the ultrathin gate oxide film. Therefore, in addition to cleaning other substances, it is mainly used to clean the self-oxide on the substrate to avoid contamination and to produce excellent electrical performance. The cleaning substrate often includes a final hydrofluoric acid (HF) hydrophobic treatment to inhibit oxygenation and the combination of oxygen and red. The final hydrofluoric acid hydrophobic treatment described above, also known as IMEC-foob, is an oxidation step using ozone and deionized water (〇3/DIW) followed by an oxide removal step (using HF/HC1). Finally, it was rinsed with deionized water (deionized water mixed with hydrochloric acid), followed by Marangoni drying containing isopropanol and nitrogen. This final hydrofluoric acid treatment (IMEC-foob) caused the surface to be free of oxides. However, the oxide-free surface produced by the cleaning of the final hydrofluoric acid (IMEC-foob) does not provide the terminal OH bonds required for subsequent deposition of high-k materials. Accordingly, the present invention suggests that the substrate undergo a cleaning step followed by a heat treatment in an oxidizing environment. The heat treatment described above forms a uniform thin oxide and/or suboxide 0503-A33877TWF/linlin 10 200935518 boundary: U is between the gate dielectric layer and the semiconductor substrate. The above-mentioned tantalum interface oxide/sub-oxide surface layer: by the application of heat in an oxidizing-free environment; ^ Zhongjiejiedi 1 is a flow chart, using various stages in the semiconductor preparation process / the method of the present invention Forming an isolation structure in a shallow semiconductor body, for example φ

G (Shallow Trench Isolation, STI) 〇 開始製備閘極之步驟，首先進行 處理以清潔半導體主體之上表面，此、生、、“歧疏水 氧化環境中進行熱處理步驟之前。❼V驟進打於無 於一包括鈍氣之無氧化環境中 驟以產生高品質薄界面層於半導體主體之丁上广熱處理步 接著，視需要地形成一化學氧化物 最終去離子水(DIW)清㈢“式〇3/ 捭強4处1 “冉為1MEC-cleanM uv 曰強，化物成長法’造成表面具有—薄化學氧化芦。 沉=之後’高介電常數⑽叫閑極介電層 :二=此高介電常數㈤处懒極介電層可 匕括或夕層南介電常數(high_k)介電材料。 後退對高介電常數(high_k)介電材料進行一沉積 一導電金屬間極接觸（或祕電極）形成於高介 閘極介電層之上，因而形成閘極結構或閉極堆 此閘極電極可包括一或多層導電材料 】】 0503-A33877TWF/Jinlin 200935518 再者，夕日日石夕覆蓋層（capping layer)沉積 之上。 趣鹎 閘極接觸、高介電常數(high_k)閘極介電爲 接著一起被圖案化形成—閘極結構。 ㈢輿界面層 藉由離子佈值、擴散摻雜適當的η或p雜杯 成半導體主體之源極/汲極區域並進行内連線掣貝，以形 當形成淺溝隔離結構時，藉由乾式蝕刻。 成溝槽，再填充介電材料以提供電性之絕緣。土材中形 此閘極介電材料可以是一高介電常數(high_ 例如氧化铪，氧化鋁或氧化锆。 、枓， 閘極電極（或閘極接觸）可由半導體材料構成，例如夕 晶矽、矽化鍺、鍺、金屬矽化物或擇自於下述群組之^ 屬材料：金屬、金屬氮化物、金屬碳氮化物以及上述^ 組合（例如鈦（Ti)、鈕（Ta)、鎢（W)、釕（Ru)、氮（碳）化鈦 (Ti(C)N)、氮(碳)化鈕(Ta(C)N)、氮(唉）化鶴（W(C)N)。G (Shallow Trench Isolation, STI) 〇 begins the step of preparing the gate, first processing to clean the upper surface of the semiconductor body, this, raw, "different hydrophobic oxidation environment before the heat treatment step. ❼V rush into the An oxidizing environment including an blunt gas is used to produce a high-quality thin interfacial layer on the semiconductor body. Then, a chemical oxide is finally formed to form a deionized water (DIW). (3) "Formula 〇 3/ Reluctantly 4 places 1 "冉 is 1MEC-cleanM uv reluctant, the compound growth method" causes the surface to have - thin chemical oxidation of the reed. After the sink = after 'high dielectric constant (10) called the idle dielectric layer: two = this high dielectric The lazy dielectric layer at the constant (five) may include a dielectric material with a high dielectric constant (high_k) dielectric material. The recession is a deposition of a high dielectric constant (high_k) dielectric material, a conductive metal interpole contact (or a secret electrode). Formed on the high dielectric gate dielectric layer, thus forming a gate structure or a closed-pole stack. The gate electrode may comprise one or more layers of conductive material.] 0503-A33877TWF/Jinlin 200935518 Furthermore, the day and night stone cover layer (capping layer) Above the deposition. Interesting gate contact, high dielectric constant (high_k) gate dielectric is then patterned together - gate structure. (3) 舆 interface layer by ion cloth value, diffusion doping appropriate η or The p-cup is formed into the source/drain region of the semiconductor body and interconnected with mussels to form a shallow trench isolation structure by dry etching. The trench is filled and the dielectric material is filled to provide electrical properties. Insulation. The gate dielectric material in the soil material may be a high dielectric constant (high_such as yttria, alumina or zirconia. 枓, gate electrode (or gate contact) may be composed of a semiconductor material, such as eve Crystalline, antimony telluride, antimony, metal telluride or materials selected from the group consisting of metals, metal nitrides, metal carbonitrides, and combinations of the above (eg, titanium (Ti), button (Ta), Tungsten (W), Ruthenium (Ru), Nitrogen (Ti(C)N), Nitrogen (Ta(C)N), Nitrogen (W), W(C)N ).

閘極結構分隔兩側之源極與汲極，其中源極與汲極 接觸通道區域（channel region)之相對兩側。 側壁間隔物（sidewall spacer)形成閘極結構側壁，侧 壁間隔物通常與源極和汲極的邊界對齊。 物可由例如氧化矽、氮化矽及/或碳化矽所組成。 依照本發明之一較佳實施例，形成高介電常數 (high-k)閘極介電土士粗古太七 电材枓之方法包括以下步驟：提供一半 ^ 土材，清洗讀基材，於無氧化環境中進行—熱處理， 以及接著沉積-高介電常數(high_k)材料。 〇503-A33877TWF/linlii 12 200935518 依照本發明之方法，於無氧化環境中進行一熱處 理，尚包括鈍氣混合物，造成一薄界面層之形成。 再者，此均勻薄界面層，由施加熱處理而得，其具 有適合的表面末端，因此能使表面適合高介電常數 (high-k)材料之沉積，且減少EOT。 上述之均勻薄界面層，提供改良之界面特性，此界 面層介於石夕結構與高介電常數（high-k)材料之間，藉由下 述沉積步驟而得。 ® 於包含鈍氣混合物之無氧化環境中進行之熱處理， 較佳進行於一快速熱處理（rapid thermal process，RTP)腔 體中。 ‘ 上述熱處理進行於約高於700°C之溫度，較佳約高於 1000°C，更佳約高於l〇50°C。 上述熱處理之期間較佳約少於2分鐘，更佳約少於1 分鐘，又更佳約少於40秒。 依照本發明之方法，熱處理可以進行於爐管中（例如 ® LPCVD低壓化學氣相沉積反應爐），或使用瞬間退火 (spike anneal)。當於LPCVD反應爐中進行熱處理時，需 要較長期間（至少10分鐘至幾小時），而瞬間退火一般約 於1050°C中進行1秒鐘。 進行熱處理期間，一包括氧化矽與次氧化物（SiOx,0 < 2)均勻薄的層被揭開（unraveled)於基材表面上。 進行熱處理期間，上述之無氧化環境之鈍氣較佳為 氦氣(He)及/或氬氣(Ar)。 0503-A33877TWF/linlin 13 200935518 氮氣不適合加入無氧化環境中，當其併入於界面且 增加界面狀態密度時，會導致通道遷移率之降低，影響 此元件之電性特性。 較佳者’力π入部分氫氣到包括鈍氣之無氧化環境中。 較佳者部分氫氣之體積約少於10%，較佳介於1〜10% 之間。 無氧化環境之壓力較佳介於10到20托耳（torr)。 依照本發明之方法，會獲得薄界面層之厚度約少於 ® 0.6 nm。 再者’依照本發明之方法獲得的高品質界面層，其 平整（或平滑或均勻）且呈現連續的界面氧化物成長。 於本發明之方法中，形成上述之薄界面層，接著後 續沉積一高介電常數(high-k)材料。 上述之高介電常數(high-k)材料之沉積可使用本技藝 人士所知之沉積技術，較佳為原子層沉積法（Atomic Layer Deposition, ALD)、 金屬有機氣相沉積法 (Metal_Organic Chemical Vapor Deposition, MOCVD)、分 子束蠢晶法（Molecular Beam Epitaxy, MBE)、化學氣相沉 積法（Chemical Vapor Deposition, CVD)或物理氣相沉積 法（Physical Vapor Deposition，PVD)。 高介電常數（high-k)材料之例子包括，但不限於二元 之金屬氧化物，包括 Zr02、Hf02、La203、Y203、Ti02， 以及其矽化鹽類和鋁酸鹽類；金屬氧氮化物包括Α10Ν、 ZrON、HfON、LaON、YON等，以及其矽酸鹽和鋁酸鹽 0503-A33877TWF/Iinlin 14 200935518 類例如 ZrSiON、HfSiON、LaSiON、YSiON ;鈣鈦礦型 之氧化物’包括鈦酸鹽系統之材料，例如鈦酸鋇、鈦酸 锶、碳酸鋇鋇（(BaSr)Ti03, BST) 較佳者，高介電常數（high-k)材料之沉積視需要地伴 隨一沉積後退火處理以進一步降低界面陷阱密度 (interface trap density, Dit)。 於一實施例令，於無氧化環境中之熱處理之後，立 即進行高介電常數(high-k)材料之沉積步驟。 於另一實施例中’於無氧化環境中之熱處理之後， 視需要地進行化學氧化成長步驟。 化學成長氧化物係將裸露之半導體表面和較佳為薄 界面層與液體及/或氣體化學物接觸以氧化其表面。 依照本發明’化學氧化物之形成較佳藉由進行濕式 例如臭氧（〇3)/最終之去離子水（DiW)(IMEC-clean)之清潔 處理或UV增強式氧化物成長法，兩種方法可擇一選擇。 上述之濕式臭氧（〇3)/最終去離子水(DIW)清潔，亦稱 為IMEC-cleam，是先使用臭氧和去離子水（〇3/DIW)，接 著使用一氧化物移除步驟（使用HF/HC1)。最後，用臭氧 化之去離子（臭氧/去離子水摻鹽酸）潤洗，再進行含有異 丙醇和氮氣之馬南哥尼乾燥法（Marangoni drymg)。 上述之濕式臭氧（〇3)/最終去離子水（DIW)清潔 (IMEC-clean)，會使表面留下一非常乾淨且薄化學氧化物 〇 上述之UV增強式氧化物成長法是於空氣中進行uv 0503-A33877TWF/linlin 200935518 照射以成長一薄氧化層。氬氣連續地注入基材之上，以 降低空氣中之氧化物成長的速度。 利用上述之uv增強式氧化物成長法而得之化學氧 化層，其厚度薄於用濕式臭氧（〇3)/最終去離子水（DIW) 清潔（IMEC-clean)而得之氧化層。 藉由進行濕式臭氧（〇3)/最終去離子水（DIW)清潔 (IMEC-clean)或UV增強式氧化物成長法而得之化學氧化 物層，可提供除了施加熱處理所造成之效果之外，另外 ©能使表面具有後續沉積高介電常數（high-k)材料所需要的 合適的末端（例如OH鍵）。 因此，總氧化層來自於兩種貢獻，其一來自於無氧 化環境中進行熱處理而得之界面層，另一來自於進行濕 式臭氧（〇3)/最終去離子水（DIW)清潔（IMEC-clean)或UV 增強式氧化物成長法而得之化學氧化層。 只進行化學氧化物沉積，而未進行一熱處理，會得 到有缝隙（leakage)、較差品質之化學氧化物（對照下列討 ®論之第3圖與第6圖），其不適合後續沉積高介電常數 (high-k)材料’因此得到低品質之半導體元件。 接著，視需要地進行化學氧化物形成步驟之後，進 行ALD南介電常數(high-k)材料之沉積步驟。 上述之半導體基材較佳為矽基材或包含矽晶圓或矽 層之絕緣層上覆石夕基材（silicon-on-insulator，SOI)，例如 多晶碎、蟲晶梦或非晶碎5具有或不具有導電之換雜物。 上述之半導體基材可以為任何半導體基材5只要此 0503-A33877TWF/linlin 16 200935518 基材能抵抗本發明所需要的高溫。 此基材可能包括各種絕緣區域，例如淺溝隔離區域 (Shallow Trench Isolation，STI)、局部氧化區（Local Oxidation of Silicon, LOCOS)或其他類似之隔離區域，其 形成於基材或上述之表面上。 第2圖顯示依照本發明之不同表面處理步驟，由 AR-XPS測量到界面層與沉積高介電常數(high-k)介電材 料Hf022厚度。 於第2圖中之界面層（interfaciallayer, IL)，係藉由於 無氧化環境中之熱處理而得，或藉由化學氧化物成長法 搭配或不搭配前者之熱處理而得。 第2圖中標出熱處理法不同的條件，包括無氧化環 境的成份與溫度。 上述化學氧化層係藉由進行濕式臭氧（〇3)/最終去離 子水（DIW)清潔（IMEC-clean)或UV增強式氧化物成長法 (第2圖中標示為UV/Air/Ar)而得。 第2圖顯示界面層與高介電常數（high-k)之1^02材 料層兩者只進行熱處理步驟，兩者之厚度具有非常好之 結果。 例如H2/He/1050°C熱處理與He/1050°C熱處理形成 超薄之界面層，其厚度分別為0.4 nm和0.5 nm。 再者，如第2圖所示，H2/He/1050°C熱處理幫助限制 後續之化學氧化物成長。 因此，依照本發明之方法可用於達到EOT縮小化。 0503-A33877TWF/linlin 17 200935518 藉由進行熱處理搭配uv增強式氧化物成長法所形 成之界面層，其總氧化物之厚度亦少於只利用UV增強 式氧化物成長法所得之厚度。 但是，如第3圖所示，相較於熱處理搭配UV增強 式氧化物成長法，進行UV增強式氧化物成長法得到較 低之Hf〇2覆蓋率（coverage)。可能之解釋在於，UV增強 式氧化物方法無法於表面上顯示足夠的、合適的活化官 能基末端（例如OH鍵），因此對於後續高介電常數（high-k) ®材料沉積步驟時，表面為粗糙且低品質成核層 (nucleation)，因此，造成後續元件的電性特性出問題。 的確，第3圖顯示依照本發明之方法，其Hf02覆蓋 率對應氧化物之厚度關係圖。 藉由進行熱處理，與視需要地進行化學氧化物形成 法（UV增強式氧化物成長法或濕式臭氧（〇3)/最終去離子 水（DIW)清潔（IMEC-clean))。The gate structure separates the source and the drain on both sides, wherein the source and the drain contact the opposite sides of the channel region. The sidewall spacers form sidewalls of the gate structure, and the sidewall spacers are generally aligned with the boundaries of the source and drain. The material may be composed of, for example, cerium oxide, cerium nitride, and/or cerium carbide. In accordance with a preferred embodiment of the present invention, a method of forming a high-k gate dielectric tape is used to provide a halves of the earth material and to clean the substrate. The heat treatment is carried out in an oxidizing environment, and then the deposition - high dielectric constant (high_k) material. 〇503-A33877TWF/linlii 12 200935518 In accordance with the method of the present invention, a heat treatment is carried out in an oxidizing-free environment, which also includes a blunt gas mixture, resulting in the formation of a thin interfacial layer. Furthermore, the uniform thin interfacial layer is obtained by applying a heat treatment having a suitable surface end, thereby enabling the surface to be suitable for deposition of a high-k material and reducing EOT. The uniform thin interfacial layer described above provides improved interfacial properties between the shi shi structure and the high-k material, obtained by the deposition step described below. ® is heat treated in an oxidizing environment containing a blunt gas mixture, preferably in a rapid thermal process (RTP) chamber. The above heat treatment is carried out at a temperature higher than about 700 ° C, preferably higher than 1000 ° C, more preferably higher than 10 ° C ° C. The period of the above heat treatment is preferably less than about 2 minutes, more preferably less than about 1 minute, and still more preferably less than about 40 seconds. In accordance with the method of the present invention, the heat treatment can be carried out in a furnace tube (e.g., ® LPCVD low pressure chemical vapor deposition reactor) or using a spike anneal. When the heat treatment is carried out in an LPCVD reactor, it takes a long period of time (at least 10 minutes to several hours), and the instantaneous annealing is generally carried out at about 1050 ° C for 1 second. During the heat treatment, a layer including a uniform thin layer of cerium oxide and a suboxide (SiOx, 0 < 2) is unraveled on the surface of the substrate. During the heat treatment, the above-mentioned oxidizing atmosphere-free gas is preferably helium (He) and/or argon (Ar). 0503-A33877TWF/linlin 13 200935518 Nitrogen is not suitable for addition to an oxidizing environment. When it is incorporated into the interface and increases the density of the interface state, it will result in a decrease in channel mobility and affect the electrical properties of this component. Preferably, the force is π into a portion of the hydrogen to an oxidizing environment that includes a blunt gas. Preferably, part of the hydrogen gas has a volume of less than about 10%, preferably between 1 and 10%. The pressure in the non-oxidizing environment is preferably between 10 and 20 torr. In accordance with the method of the present invention, a thin interfacial layer is obtained having a thickness of less than about 0.6 nm. Further, the high quality interfacial layer obtained in accordance with the method of the present invention is flat (or smooth or uniform) and exhibits continuous interfacial oxide growth. In the method of the present invention, the thin interfacial layer described above is formed, followed by deposition of a high-k material. The deposition of the above high-k material can be carried out using deposition techniques known to those skilled in the art, preferably Atomic Layer Deposition (ALD), Metal Organic Vapor (Metal_Organic Chemical Vapor). Deposition, MOCVD), Molecular Beam Epitaxy (MBE), Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD). Examples of high dielectric constant (high-k) materials include, but are not limited to, binary metal oxides including ZrO2, HfO2, La203, Y203, Ti02, and their deuterated salts and aluminates; metal oxynitrides Including Α10Ν, ZrON, HfON, LaON, YON, etc., and its citrate and aluminate 0503-A33877TWF/Iinlin 14 200935518 such as ZrSiON, HfSiON, LaSiON, YSiON; perovskite type oxides including titanate Materials of the system, such as barium titanate, barium titanate, barium carbonate ((BaSr) Ti03, BST). Preferably, the deposition of a high-k material is optionally accompanied by a post-deposition annealing process. Further reduce the interface trap density (Dit). In one embodiment, the deposition step of a high-k material is performed immediately after the heat treatment in an oxidizing-free environment. In another embodiment, after the heat treatment in an oxidizing-free environment, a chemical oxidation growth step is optionally performed. The chemically grown oxide contacts the exposed semiconductor surface and preferably the thin interfacial layer with a liquid and/or gas chemistry to oxidize its surface. In accordance with the present invention, the formation of a chemical oxide is preferably carried out by a wet treatment such as ozone (〇3)/final deionized water (DiW) (IMEC-clean) or a UV-enhanced oxide growth method. The method can be chosen one by one. The above-mentioned wet ozone (〇3)/final deionized water (DIW) cleaning, also known as IMEC-cleam, is to use ozone and deionized water (〇3/DIW) first, followed by an oxide removal step ( Use HF/HC1). Finally, it was rinsed with ozonized deionized (ozone/deionized water plus hydrochloric acid), followed by Manangoni drymg containing isopropyl alcohol and nitrogen. The above-mentioned wet ozone (〇3) / final deionized water (DIW) cleaning (IMEC-clean) will leave a very clean and thin chemical oxide on the surface. The above-mentioned UV-enhanced oxide growth method is in the air. The uv 0503-A33877TWF/linlin 200935518 is irradiated to grow a thin oxide layer. Argon gas is continuously injected over the substrate to reduce the rate at which oxides in the air grow. The chemical oxidized layer obtained by the above uv-enhanced oxide growth method is thinner than the oxide layer obtained by wet ozone (〇3)/final deionized water (DIW) cleaning (IMEC-clean). A chemical oxide layer obtained by performing wet ozone (〇3) / final deionized water (DIW) cleaning (IMEC-clean) or UV-enhanced oxide growth method can provide effects other than the application of heat treatment. In addition, the additional surface enables the surface to have suitable ends (e.g., OH bonds) required for subsequent deposition of high-k materials. Therefore, the total oxide layer comes from two contributions, one from the interface layer obtained by heat treatment in an oxidizing-free environment, and the other from the wet ozone (〇3)/final deionized water (DIW) cleaning (IMEC). -clean) or a chemically oxidized layer derived from a UV-enhanced oxide growth process. Only chemical oxide deposition, without a heat treatment, will result in a leaky, poor quality chemical oxide (cf. Figures 3 and 6 below), which is not suitable for subsequent deposition of high dielectric The constant (high-k) material 'has thus obtained low quality semiconductor components. Next, after the chemical oxide forming step is carried out as needed, a deposition step of an ALD south high-k material is performed. Preferably, the semiconductor substrate is a germanium substrate or an insulating layer comprising a germanium wafer or a germanium layer, or a silicon-on-insulator (SOI), such as polycrystalline, insect crystal or amorphous. 5 with or without conductive changes. The semiconductor substrate described above can be any semiconductor substrate 5 as long as the 0503-A33877TWF/linlin 16 200935518 substrate is resistant to the high temperatures required by the present invention. The substrate may include various insulating regions, such as Shallow Trench Isolation (STI), Local Oxidation of Silicon (LOCOS), or other similar isolation regions formed on the substrate or the surface described above. . Figure 2 shows the thickness of the interfacial layer and deposited high-k dielectric material Hf022 as measured by AR-XPS in accordance with various surface treatment steps of the present invention. The interfacial layer (IL) in Fig. 2 is obtained by heat treatment in an oxidizing-free environment, or by chemical oxide growth method with or without heat treatment of the former. Figure 2 shows the different conditions for the heat treatment, including the composition and temperature of the non-oxidizing environment. The above chemical oxide layer is subjected to wet ozone (〇3)/final deionized water (DIW) cleaning (IMEC-clean) or UV enhanced oxide growth method (labeled as UV/Air/Ar in Fig. 2). And got it. Figure 2 shows that both the interface layer and the high-k material layer of the high-k constant are only subjected to a heat treatment step, and the thickness of both has very good results. For example, H2/He/1050 °C heat treatment and He/1050 °C heat treatment form an ultra-thin interface layer with thicknesses of 0.4 nm and 0.5 nm, respectively. Furthermore, as shown in Figure 2, H2/He/1050 °C heat treatment helps limit subsequent chemical oxide growth. Therefore, the method according to the invention can be used to achieve EOT downsizing. 0503-A33877TWF/linlin 17 200935518 The thickness of the total oxide is also less than that obtained by the UV-enhanced oxide growth method by the heat treatment combined with the uv-reinforced oxide growth method. However, as shown in Fig. 3, the UV-enhanced oxide growth method is used to obtain a lower Hf〇2 coverage than the heat treatment in combination with the UV-enhanced oxide growth method. A possible explanation is that the UV-enhanced oxide method does not display sufficient, suitable activated functional end groups (such as OH bonds) on the surface, so for subsequent high-k (high-k) ® material deposition steps, the surface It is a rough and low-quality nucleation, thus causing problems in the electrical properties of subsequent components. Indeed, Figure 3 shows a plot of Hf02 coverage versus oxide thickness for a method in accordance with the present invention. The chemical oxide formation method (UV-enhanced oxide growth method or wet ozone (〇3) / final deionized water (DIW) cleaning (IMEC-clean)) is carried out by heat treatment.

形成上述界面層後，進行例如5次ALDHf02單層沉 A 積之循環。 一般的ALD技術與Hf02之ALD對界面層表面條件 特別敏感，因此，進行Hf02之ALD時，依據界面層之 粗糙度、界面層表面之活性官能基末端（例如OH鍵）與界 面層之連續性/均勻性（例如無島狀類似物）對界面層之品 質進行評估。 據此，具有較多OH官能基末端且較平滑（較低粗糙 度）的界面層表面，較有利於Hf02之ALD沉積。 0503-A33877TWF/linlin 18 200935518 如第3圖所示，藉由熱處理形成界面層（不論搭配或 不搭配進行UV增強式氧化物成長法）提供較佳之Hf02 覆蓋率，因此為較佳品質、平滑之界面層。 上述之Hf02覆蓋率亦高於利用臭氧（03)/最終去離子 水（DIW)化學氧化物成長法（不論搭配或不搭配熱處理形 成界面層）而得之Hf02覆蓋率，且特別能改善只進行UV 增強式氧化物成長法獲得之較差的覆蓋率。 第4圖顯示依照本發明之不同表面處理步驟而依序 ® 成長（step-by-step)之氧化層厚度（藉由光學測厚儀 (Eilipsometry)測量）。 每一次進行清潔步驟（IMFOOB)後，於無氧化環境中 進行熱處理或一化學氧化物成長（濕式臭氧（03)/最終去 離子水（DIW)清潔（IMEC-clean)或UV/Air/Ar)，或上述之 組合。 由熱處理所形成之界面層，第4圖中指出不同的實 驗條件，包括無氧化環境之組成和溫度。 化學氧化物係由UV增強式氧化物成長法或由濕式 臭氧（〇3)/最終去離子水(DIW)清潔（IMEC-clean)而得。 第4圖測出的總氧化層厚度，包括於無氧化環境中 進行熱處理而得之界面層，與由UV增強式氧化物成長 法或由濕式臭氧（〇3)/最終去離子水（DIW)清潔 (IMEC-clean)而得之化學氧化物層。 在此須注意的是，由光學測厚儀所測之氧化層厚 度，其準確度不如由AR-XPS所測。 0503-A33877TWF/linlin 19 200935518 事實上，由光學測厚儀所測之厚度會厚於由AR_XPS 所測之厚度。 但是，第4圖所顯示之趨勢符合第2圖之結果。 第 5圖顯示藉由原子力顯微鏡（Atomic Force Microscope，AFM)測得之表面粗糙度。 第5圖所測量為進行熱處理而得之界面層及/或進行 氧化物成長法而得之化學氧化物。 由熱處理形成之界面層，第5圖中指出不同的實驗 ϋ w條件，包括無氧化環境之組成和溫度。 化學氧化物係由UV增強式氧化物成長法或由濕式 臭氧（〇3)/最終去離子水(DIW)清潔（IMEC-clean)而得。 如第5圖所示，只由UV增強式氧化物成長法或只 由濕式臭氧（03)/最終去離子水（DIW)清潔（IMEC-clean)而 得之化學氧化層，不進行熱（預）處理形成界面層，會得到 相對較粗糙之氧化層表面。例如，由濕式臭氧（〇3)/最終 ©去離子水（DIW)清潔（IMEC-clean)而得之化學氧化層，其 Rms=0.18nm，而由UV增強式氧化物成長法而得之化學 氧化層，其Rms=0.14 nm，其中每一次Rms測量之範圍 為 Ιχίμηι。 相反地，進行H2/He/1050°C熱處理形成界面層有助 於平滑界面層之表面，且當化學氧化層沉積於其上時， 對於1\10111之範圍，111115值達到〇.〇8〜〇.〇911111，。 再者，低溫處理（例如700°C)將會降低表面平滑度之 表現（對於1x1 μιη之範圍，Rms= 0.146nm)。 〇503-A33877TWF/linlin 20 200935518 如第6圖所示，只進行熱處理，或只有化學氧化物 成長，或結合熱處理與化學氧化物成長（UV增強式氧化 物標示為UV/Air/Ar/ls)所得之元件的電容對應電壓曲線 圖。 電容（MOS)為一種P型基材，其具有TaN/TiN金屬 閘極電極。 進行H2/He/1050°C之熱處理及/或進行UV增強式氧 化物成長法，接著藉由40次ALD單層Hf02沉積循環。 由第6圖得知，只進行UV增強式氧化物成長法會 得到非常多缝隙（leakage)，且薄氧化層。 此種多縫隙（leakage)可由形成第一界面層所抑制，不 論拾配或不搭配UV增強式氧化物成長法。 第7圖顯示形成薄界面層可能之機制。包括HF-iast 疏水性處理之清潔步驟’會留下氫原子末端的表面（si_H 鍵’如第7a圖）’此會抑制氧原子自由基與矽上層結合。 有水的存在時（潤洗過程中），溶氧及/或〇H-自由基可能 攻擊内層之Si-Si鍵，而不破壞Si-H鍵，留下SiOx次氧 化物於（無氧化物）表面之下。當進行熱處理期間，包含氧 化石夕與久氧化物（SiOx, 0<χ $ 2)之薄層被揭開（unraveied) 於矽表面上（第7b圖）。此薄層是連續的（沒有島狀物形 成）’均勻且疏水性，是一種適合介於基材和藉由ALD沉 積高介電常數(high-k)材料（例如Hf氧化物）之間的界面 層。 因此，依照本發明之方法’產生一均勻超薄界面層 0503-A33877TWF/nnlin 21 200935518 其位於高介電常數材料（high-k)底下。 依照本發明之方法，能產生均勻且薄的、具有適當 的末端（例如OH鍵）之界面層，使其能夠相容於後續高介 電常數(high-k)材料之沉積。 再者，實行本發明之方法，能改善界面層之粗糙度 與品質。 同時，於本發明之架構下，能增進於半導體元件中 的電荷載子遷移率。 © 雖然本發明已以數個較佳實施例揭露如上，然其並 非用以限定本發明，任何所屬技術領域中具有通常知識 者，在不脫離本發明之精神和範圍内，當可作任意之更 動與潤飾，因此本發明之保護範圍當視後附之申請專利 範圍所界定者為準。 ❿ 0503-A33877TWF/linlin 22 200935518 【圖式簡單說明】 第1圖為一系列流程圖，用以說明依照本發明之方 法製備表面的流程。 第2圖為利用角度解析X-光光電子光譜儀（AR-XPS) 測量之厚度圖，用以顯示本發明之界面層與用不同方法 沉積之高介電常數(high-k)材料Hf02層之厚度。 第3圖顯示Hf02覆蓋率相對於氧化物厚度。 第4圖藉由光學測厚儀測量依序形成之氧化層厚度。 〇 第5圖藉由原子力顯微鏡確認表面粗糙度。 第6圖顯示利用不同表面處理而得之電容對應電壓 圖。 第7圖顯示形成薄界面層可能之機制。 【主要元件符號說明】 無。After the formation of the above interface layer, for example, a cycle of ALDHf02 single layer deposition is performed five times. The general ALD technology and ALD of Hf02 are particularly sensitive to the surface condition of the interface layer. Therefore, when performing ALD of Hf02, the continuity of the functional layer end (such as OH bond) and the interface layer depending on the roughness of the interface layer and the surface of the interface layer. / Uniformity (eg, no island-like analogs) evaluates the quality of the interface layer. Accordingly, the surface of the interfacial layer having a more OH functional end and a smoother (lower roughness) is more advantageous for ALD deposition of HfO 2 . 0503-A33877TWF/linlin 18 200935518 As shown in Figure 3, the interface layer formed by heat treatment (with or without UV-enhanced oxide growth) provides better Hf02 coverage, so it is better quality and smoother. Interface layer. The above Hf02 coverage is also higher than the Hf02 coverage obtained by the ozone (03)/final deionized water (DIW) chemical oxide growth method (with or without heat treatment to form the interface layer), and can be improved particularly. Poor coverage obtained by UV enhanced oxide growth. Figure 4 shows the step-by-step oxide thickness (measured by an optical thickness gauge) in accordance with the different surface treatment steps of the present invention. After each cleaning step (IMFOOB), heat treatment or chemical oxide growth in a non-oxidizing environment (wet ozone (03) / final deionized water (DIW) cleaning (IMEC-clean) or UV/Air/Ar ), or a combination of the above. The interfacial layer formed by the heat treatment, in Fig. 4, indicates different experimental conditions, including the composition and temperature of the non-oxidizing environment. The chemical oxide is obtained by a UV-enhanced oxide growth method or by wet ozone (〇3)/final deionized water (DIW) cleaning (IMEC-clean). The total oxide thickness measured in Figure 4, including the interfacial layer obtained by heat treatment in an oxidizing-free environment, with UV-enhanced oxide growth or wet ozone (〇3)/final deionized water (DIW) ) A chemical oxide layer obtained by cleaning (IMEC-clean). It should be noted here that the thickness of the oxide layer measured by the optical thickness gauge is not as accurate as that measured by AR-XPS. 0503-A33877TWF/linlin 19 200935518 In fact, the thickness measured by the optical thickness gauge is thicker than the thickness measured by AR_XPS. However, the trend shown in Figure 4 is consistent with the results of Figure 2. Figure 5 shows the surface roughness measured by an Atomic Force Microscope (AFM). Fig. 5 shows the interface layer obtained by heat treatment and/or the chemical oxide obtained by the oxide growth method. The interface layer formed by heat treatment, and the different experimental conditions in Fig. 5, including the composition and temperature of the non-oxidizing environment. The chemical oxide is obtained by a UV-enhanced oxide growth method or by wet ozone (〇3)/final deionized water (DIW) cleaning (IMEC-clean). As shown in Figure 5, the chemical oxide layer obtained only by the UV-enhanced oxide growth method or only by the wet ozone (03) / final deionized water (DIW) cleaning (IMEC-clean) does not carry out heat ( Pre-treatment to form the interfacial layer results in a relatively rough oxide surface. For example, a chemical oxide layer obtained by wet ozone (〇3)/final deionized water (DIW) cleaning (IMEC-clean), which has an Rms of 0.18 nm and is obtained by a UV-enhanced oxide growth method. The chemical oxide layer has an Rms of 0.14 nm, wherein each Rms measurement ranges from Ιχίμηι. Conversely, the H2/He/1050 °C heat treatment to form the interfacial layer helps to smooth the surface of the interface layer, and when the chemical oxide layer is deposited thereon, for the range of 1\10111, the value of 111115 reaches 〇.〇8~ 〇.〇911111,. Furthermore, low temperature processing (e.g., 700 ° C) will reduce the surface smoothness (Rms = 0.146 nm for a range of 1 x 1 μηη). 〇503-A33877TWF/linlin 20 200935518 As shown in Figure 6, only heat treatment, or only chemical oxide growth, or combined heat treatment and chemical oxide growth (UV-enhanced oxide labeled UV/Air/Ar/ls) The capacitance of the resulting component corresponds to a voltage graph. The capacitor (MOS) is a P-type substrate having a TaN/TiN metal gate electrode. Heat treatment at H2/He/1050 °C and/or UV enhanced oxide growth followed by 40 ALD monolayer Hf02 deposition cycles. From Fig. 6, it is known that only the UV-enhanced oxide growth method results in a very large number of leaks and a thin oxide layer. Such a plurality of leaks can be suppressed by the formation of the first interfacial layer, regardless of whether or not the UV-enhanced oxide growth method is used. Figure 7 shows the possible mechanism for forming a thin interfacial layer. The cleaning step including the HF-iast hydrophobic treatment 'will leave the surface of the hydrogen atom end (si_H bond 'as shown in Fig. 7a)' which inhibits the oxygen atom radical from binding to the upper layer of the ruthenium. In the presence of water (during the rinsing process), dissolved oxygen and/or hydrazine H-radicals may attack the Si-Si bond of the inner layer without destroying the Si-H bond, leaving the SiOx suboxide (no oxide) Under the surface. During the heat treatment, a thin layer comprising an oxide oxide and a long-lasting oxide (SiOx, 0 < χ $ 2) is unraveied on the surface of the crucible (Fig. 7b). This thin layer is continuous (no island formation) 'uniform and hydrophobic, is a suitable between the substrate and ALD deposition of high-k materials (such as Hf oxide) Interface layer. Thus, the method according to the present invention produces a uniform ultra-thin interface layer 0503-A33877TWF/nnlin 21 200935518 which is located under a high dielectric constant material (high-k). In accordance with the method of the present invention, a uniform and thin interfacial layer having suitable ends (e.g., OH bonds) can be produced to be compatible with subsequent deposition of high-k materials. Further, by carrying out the method of the present invention, the roughness and quality of the interface layer can be improved. At the same time, under the framework of the present invention, the charge carrier mobility in the semiconductor element can be improved. The present invention has been disclosed in terms of several preferred embodiments as described above, but is not intended to limit the invention, and any one of ordinary skill in the art can be arbitrarily carried out without departing from the spirit and scope of the invention. The scope of protection of the present invention is defined by the scope of the appended claims. ❿ 0503-A33877TWF/linlin 22 200935518 [Simple description of the drawings] Fig. 1 is a series of flow charts for explaining the flow of preparing a surface in accordance with the method of the present invention. Figure 2 is a thickness diagram measured by an angle-analytical X-ray photoelectron spectroscopy (AR-XPS) to show the thickness of the interface layer of the present invention and the high-k material Hf02 layer deposited by different methods. . Figure 3 shows the Hf02 coverage relative to the oxide thickness. Figure 4 measures the thickness of the oxide layer formed in sequence by an optical thickness gauge. 〇 Figure 5 confirms the surface roughness by atomic force microscopy. Figure 6 shows the corresponding voltage diagram of the capacitor obtained by different surface treatments. Figure 7 shows the possible mechanism for forming a thin interfacial layer. [Main component symbol description] None.

0503-A33877TWF/linlin 230503-A33877TWF/linlin 23

Claims (1)

200935518 十、申請專利範圍： 下物―種高介”數閘極介電材料的形成方法，包括 提供一半導體基材； 〉月洗該基材； 對忒基材進行一熱處理；以及 〉儿積一高介電常數材料，其 ❹ ❹ 環境中進行1致形成-薄界面層…、處理於—無氧化 •如申睛專利範圍第1項所述之高介 電材料的形成方法，”、青電常數間極介 酸處理。 4 #中❿先該基材包括-最終之氫敦 數門3搞請專利範圍第1項或第2項所述之高介電常 於^^電材料的形成方法，其中該熱處理之溫度約高 數閘專利範圍第1項或第2項所述之高介電常 於ιοοοί料的形成方法’其中該熱處理之溫度約高 數請專利範圍第1項或第2項所述之高介電常 於;050^電材料的形成方法，其中該熱處理之溫度約高 如申請專利範圍第丨項所述之高介電常數間極介 晃材料的形成核，其巾減氧化環境包括一純氣。 带7、.如申請專利範圍第1項所述之高介電常數閘極介 才料的形成方法，其中該無氧化環境包括氦氣及/或氬 05Q3-A33877TWF/iinlin 24 200935518 氣。 8.如申請專利範圍第丨項所述之 電材料的形成方法，其中更包括加入部 化環境中。 1刀11軋到该無氧 電材料第8項所述之高介電常數閘極介 1〇如m 部分氫氣之體積約少於1〇%。 ❹ ❹ 介電材料的形成方法，其中該部分氯氣編極 〜10%。 刀孔札之肢積約介於1 〇/〇 項所述之高介電常數閘極 氣。化成方法，其中於該無氧化環境中不包括氮 12. 如申請專利範圍第i 古八 ；；電材料的形成方法，其中該熱處理； 13. 如申請專利範圍第1 :電材料㈣成方法，其中該“= 15.如申請專利範圍第i 、一入功40秒。 介電材料的形成方法，其中於，之“電常數閉極 化學氧化層。 熱處理之後，形成-薄 16·如申請專利範圍第15項所述之高介電常數閘極 0503^3877TWF/lini 25 200935518 施加形成方法’其中該薄化學氧化層之形成藉由 #式臭氧（a)/最終去離子水(DIw)處理或一 υν择 式虱化物成長法（uv-enhanced oxide growth meth〇d)。0 介電L如申請專利範㈣1項所述之高介電常數閑極 種介電常法，其中該高介電常數材料為任何-包吊數i(k)尚於二氧化矽之介電材料。 0 其中該高介電常數材料係藉由原 積法（Atoimc Layer Deposition)% 積而得 介電申請專利範圍第1項所述之高介電常數間择 後一著隹 法’其中沉積該高介電常數村料之 次者進行一沉積後退火處理。 20.如申請專利範圍第丨項所述之 :電材料的爾㈣中㈣界心厚^數^ 21 ❹ 一種半導體元件，其包括依照申請 項所述之方法所形成的高 軏圍第1 材料’其中該高介電常數閘極介電材料^閘極介電 nm之薄界面層。 一約少於0.6 0503^A33877TWF/linlin 26200935518 X. Patent application scope: The method for forming a gate-polar dielectric material includes providing a semiconductor substrate; 〉 monthly washing the substrate; performing a heat treatment on the ruthenium substrate; a high dielectric constant material, which is formed in a ❹ ❹ environment - a thin interfacial layer ..., treated in - no oxidation - such as the method of forming a high dielectric material according to claim 1 of the patent scope, ", Electrochemical treatment between the electrical constants. 4 #中❿先 The substrate includes - the final hydrogen number gate 3, please refer to the method of forming a high dielectric constant electrical material according to the first or second aspect of the patent range, wherein the temperature of the heat treatment is about The high dielectric of the high number gate patent range 1 or 2 is often used in the formation method of ιοοο ί ' 其中 其中 其中 ' ' ' ' 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中 其中a method for forming an electrical material, wherein the temperature of the heat treatment is about as high as the formation of a high dielectric constant intercalating material as described in the scope of the patent application, and the oxidation reducing environment includes a pure gas. . The method of forming a high dielectric constant gate dielectric according to claim 1, wherein the non-oxidizing environment comprises helium gas and/or argon 05Q3-A33877TWF/iinlin 24 200935518 gas. 8. The method of forming an electrical material as described in the scope of the patent application, further comprising adding to a partial environment. 1 knife 11 is rolled to the high dielectric constant gate according to item 8 of the anaerobic material. For example, the volume of hydrogen in part m is less than about 1%. ❹ 形成 A method of forming a dielectric material in which the portion of the chlorine gas is entangled to 10%. The jaw hole has a limb volume of about 1 〇/〇 as described in the high dielectric constant gate gas. a chemical conversion method in which nitrogen is not included in the non-oxidizing environment. 12. For example, the method for forming an electrical material, wherein the heat treatment is performed; 13. The method for applying the patent range 1: the method for forming an electrical material (four), Wherein "= 15. For example, the scope of application of the patent i, one for 40 seconds. The method of forming a dielectric material, wherein, the "electrical constant closed chemical oxidation layer. After the heat treatment, a thin film 16 is formed as described in claim 15 of the high dielectric constant gate 0503^3877TWF/lini 25 200935518. The formation method is described in which the thin chemical oxide layer is formed by # ozone (a ) / Final deionized water (DIw) treatment or a uv-enhanced oxide growth meth〇d. 0 dielectric L, as claimed in the patent specification (4), the high dielectric constant idle dielectric constant method, wherein the high dielectric constant material is any - package number i (k) is still in the dielectric of cerium oxide material. 0 wherein the high dielectric constant material is obtained by the method of the original product method (Atoimc Layer Deposition), and the dielectric constant of the high dielectric constant according to the first application of the first application is described in the first method. The second of the dielectric constants is subjected to a post-deposition annealing treatment. 20. As described in the scope of the patent application: (4) of the electrical material (4), the thickness of the boundary is ^ 21 ❹ a semiconductor component comprising the high-strength first material formed according to the method described in the application. 'The high dielectric constant gate dielectric material ^ gate dielectric layer nm thin interface layer. One is less than 0.6 0503^A33877TWF/linlin 26
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI408822B (en) * 2009-12-31 2013-09-11 Lu Sheng Hong Thin silicon solar cell and its manufacturing method
TWI484564B (en) * 2009-09-18 2015-05-11 Taiwan Semiconductor Mfg Co Ltd Semiconductor device and fabrication method thereof

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060072680A (en) * 2004-12-23 2006-06-28 주식회사 하이닉스반도체 Capacitor for semiconductor device and manufacturing method thereof
US8564066B2 (en) 2010-06-18 2013-10-22 International Business Machines Corporation Interface-free metal gate stack
CN102468152B (en) * 2010-11-01 2013-12-04 中芯国际集成电路制造(上海)有限公司 Manufacturing method of gate medium layer and transistor
US8735244B2 (en) 2011-05-02 2014-05-27 International Business Machines Corporation Semiconductor device devoid of an interfacial layer and methods of manufacture
US8492290B2 (en) * 2011-06-21 2013-07-23 International Business Machines Corporation Fabrication of silicon oxide and oxynitride having sub-nanometer thickness
CN103295891B (en) * 2012-03-02 2016-03-16 中芯国际集成电路制造(上海)有限公司 The manufacture method of gate dielectric layer, the manufacture method of transistor
JP2014187238A (en) * 2013-03-25 2014-10-02 Toyoda Gosei Co Ltd Mis semiconductor device manufacturing method
US9281249B2 (en) * 2014-01-15 2016-03-08 Globalfoundries Inc. Decoupling measurement of layer thicknesses of a plurality of layers of a circuit structure
CN104821276B (en) * 2014-01-30 2018-08-10 中芯国际集成电路制造(上海)有限公司 The production method of MOS transistor
KR102353662B1 (en) * 2014-09-26 2022-01-21 인텔 코포레이션 Metal oxide metal field effect transistors(momfets)
JP6456764B2 (en) * 2015-04-28 2019-01-23 株式会社Ｋｏｋｕｓａｉ Ｅｌｅｃｔｒｉｃ Semiconductor device manufacturing method, substrate processing apparatus, and program
US10727055B2 (en) * 2017-02-10 2020-07-28 International Business Machines Corporation Method to increase the lithographic process window of extreme ultra violet negative tone development resists
US20210193468A1 (en) * 2019-05-03 2021-06-24 Applied Materials, Inc. Treatments To Improve Device Performance
WO2022187299A1 (en) * 2021-03-04 2022-09-09 Applied Materials, Inc. Treatments to improve device performance
CN115579279A (en) 2021-07-06 2023-01-06 联华电子股份有限公司 Cleaning process method in semiconductor device manufacturing process

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10231196A (en) * 1996-12-17 1998-09-02 Sony Corp Production of oxide laminated structure, and apparatus for chemical vapor-phase growth of organic metal compound
US20060177987A1 (en) * 1997-05-09 2006-08-10 Bergman Eric J Methods for forming thin oxide layers on semiconductor wafers
US6020024A (en) * 1997-08-04 2000-02-01 Motorola, Inc. Method for forming high dielectric constant metal oxides
JP3746153B2 (en) * 1998-06-09 2006-02-15 信越半導体株式会社 Heat treatment method for silicon wafer
US6328809B1 (en) * 1998-10-09 2001-12-11 Scp Global Technologies, Inc. Vapor drying system and method
US6417041B1 (en) * 1999-03-26 2002-07-09 Advanced Micro Devices, Inc. Method for fabricating high permitivity dielectric stacks having low buffer oxide
US6492186B1 (en) * 1999-08-05 2002-12-10 Eaton Corporation Method for detecting an endpoint for an oxygen free plasma process
JP3399413B2 (en) * 1999-09-13 2003-04-21 日本電気株式会社 Oxynitride film and method for forming the same
US6939816B2 (en) * 2000-11-10 2005-09-06 Texas Instruments Incorporated Method to improve the uniformity and reduce the surface roughness of the silicon dielectric interface
US6448192B1 (en) * 2001-04-16 2002-09-10 Motorola, Inc. Method for forming a high dielectric constant material
US6806145B2 (en) * 2001-08-31 2004-10-19 Asm International, N.V. Low temperature method of forming a gate stack with a high k layer deposited over an interfacial oxide layer
US6737302B2 (en) * 2001-10-31 2004-05-18 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method for field-effect transistor
US6821873B2 (en) * 2002-01-10 2004-11-23 Texas Instruments Incorporated Anneal sequence for high-κ film property optimization
JP3778432B2 (en) * 2002-01-23 2006-05-24 東京エレクトロン株式会社 Substrate processing method and apparatus, and semiconductor device manufacturing apparatus
JP4001498B2 (en) * 2002-03-29 2007-10-31 東京エレクトロン株式会社 Insulating film forming method and insulating film forming system
DE10240408A1 (en) * 2002-09-02 2004-03-25 Advanced Micro Devices, Inc., Sunnyvale Transistor element with an anisotropic gate dielectric MI large ε
KR100520433B1 (en) * 2003-06-30 2005-10-11 광주과학기술원 Method for forming high-k gate dielectric by annealing in high-pressure hydrogen ambient
US6809370B1 (en) * 2003-07-31 2004-10-26 Texas Instruments Incorporated High-k gate dielectric with uniform nitrogen profile and methods for making the same
EP1652224A2 (en) 2003-07-31 2006-05-03 FSI International, Inc. Controlled growth of highly uniform, oxide layers, especially ultrathin layers
US7075161B2 (en) * 2003-10-23 2006-07-11 Agilent Technologies, Inc. Apparatus and method for making a low capacitance artificial nanopore
US7135361B2 (en) * 2003-12-11 2006-11-14 Texas Instruments Incorporated Method for fabricating transistor gate structures and gate dielectrics thereof
CN100485885C (en) * 2003-12-18 2009-05-06 东京毅力科创株式会社 Method for forming film
FR2864457B1 (en) * 2003-12-31 2006-12-08 Commissariat Energie Atomique METHOD OF WET CLEANING A SURFACE, IN PARTICULAR A MATERIAL OF SILICON GERMANIUM TYPE.
CN1950473B (en) * 2004-05-11 2010-10-27 Jsr株式会社 Insulating film forming composition, preparing method thereof, silica dioxide insulating film and preparing method thereof
US20060121742A1 (en) * 2004-12-07 2006-06-08 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US7494852B2 (en) * 2005-01-06 2009-02-24 International Business Machines Corporation Method for creating a Ge-rich semiconductor material for high-performance CMOS circuits
US7393736B2 (en) * 2005-08-29 2008-07-01 Micron Technology, Inc. Atomic layer deposition of Zrx Hfy Sn1-x-y O2 films as high k gate dielectrics
JP2007294874A (en) * 2006-03-31 2007-11-08 Sanyo Electric Co Ltd Semiconductor device and manufacturing method therefor
US7939396B2 (en) * 2006-06-09 2011-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Base oxide engineering for high-K gate stacks
US20080032510A1 (en) * 2006-08-04 2008-02-07 Christopher Olsen Cmos sion gate dielectric performance with double plasma nitridation containing noble gas
US20080237694A1 (en) * 2007-03-27 2008-10-02 Michael Specht Integrated circuit, cell, cell arrangement, method for manufacturing an integrated circuit, method for manufacturing a cell, memory module
US7855153B2 (en) * 2008-02-08 2010-12-21 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
EP2786427A4 (en) * 2011-12-01 2016-08-17 Quarkstar Llc Solid-state lighting device and method of manufacturing same
US9018639B2 (en) * 2012-10-26 2015-04-28 Dow Corning Corporation Flat SiC semiconductor substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI484564B (en) * 2009-09-18 2015-05-11 Taiwan Semiconductor Mfg Co Ltd Semiconductor device and fabrication method thereof
TWI408822B (en) * 2009-12-31 2013-09-11 Lu Sheng Hong Thin silicon solar cell and its manufacturing method

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