JP3647785B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a MIS field effect transistor.
[0002]
[Prior art]
A gate insulating film of a sub 0.1 um generation CMOS (Complementary Metal-Oxide-Semiconductor) device is required to have a performance of 1.5 nm or less in terms of SiO ₂ . SiO _{2 having a} thickness of 1.5 nm has poor insulation, and cannot be practically used even in a Logic device in which high speed is more important than an increase in power consumption due to leakage current. In addition, the greatest demand for LSI devices for personal portable electronic devices for which more demand is anticipated is low power consumption, and the leakage current density is a large part of the power consumption of the entire device. For the occupied gate insulating film, it is essential to introduce a new material having a lower leakage current at each stage than conventional SiO ₂ .
[0003]
In order to realize an insulating film capacity of 1.5 nm or less in terms of SiO ₂ and to obtain low leakage characteristics, a material having a higher dielectric constant than that of SiO ₂ (High-K material) is used and the physical film thickness is increased. Is effective. For example, if a material having a relative dielectric constant 10 times that of SiO ₂ is used, the physical film thickness for obtaining a performance equivalent to 1.5 nm in terms of SiO ₂ can be set to 15 nm, and the insulation breakdown of the film due to direct tunnel current is avoided. I can do it.
[0004]
There are many High-K materials exhibiting a relative dielectric constant higher than that of SiO ₂ , but the High-K materials applicable to actual LSI processes are limited due to the restriction that they must withstand process temperatures close to 1000 ° C. Among them, metal oxides of titanium, zirconium, and hafnium have superior heat resistance compared to other materials, and are expected to be applied to LSI.
However, the use of these metal oxides for LSI gate insulating films involves some fundamental difficulties. Of these, the biggest problem is recognized as the poor electrical properties of the interface between these metal oxides and the silicon substrate. In order to avoid this problem, a method of improving the interface characteristics by inserting a material such as SiO ₂ or SiON having excellent electrical characteristics at the interface with the silicon substrate into the interface has been proposed.
[0005]
However, this method has a big problem. This is because the dielectric constant of the insulating film such as SiO ₂ inserted to improve the interface characteristics (hereinafter referred to as the interface buffer layer) is low, so the SiO ₂ equivalent film thickness of the entire stack with the metal oxide is reduced. It is impossible to do so. At present, the thinnest SiO ₂ film that can be formed on the silicon substrate with the most controlled technique with good reproducibility is about 8 Å. Based on this fact, in principle, an insulating film having a thickness of 8 angstroms or less in terms of SiO ₂ cannot be realized by stacking a metal oxide and SiO ₂ . Furthermore, there is a fact that the interface buffer layer grows almost without exception in the manufacturing process such as film formation of metal oxide and post-heat treatment, and it is substantially less than 15 angstroms in terms of SiO _{2 in} the laminated structure of metal oxide and SiO ₂ . It is estimated that it is difficult to realize an insulating film.
[0006]
Further, the metal oxide and the interface buffer layer are different materials, and it is considered that many lattice defects are introduced in principle at the interface between them. This is a fatal evil factor that degrades the electrical properties of the gate insulating film.
[0007]
[Problems to be solved by the invention]
As described above, in the manufacturing method in which a high-K material (particularly metal oxide) is laminated with an interface buffer layer such as SiO ₂ or SiON to form a gate insulating film, it is considered from the principle side and the manufacturing method side. It was difficult to form an insulating film of 15 angstroms or less in terms of SiO ₂ , and it was difficult to maintain good electrical characteristics.
[0008]
The present invention has been made in consideration of the above-mentioned problems, and its purpose is to maintain the physical thickness of the interface buffer layer for maintaining good interface characteristics with the silicon substrate while maintaining the physical film thickness. An object of the present invention is to provide a method for manufacturing a silicon LSI device having an insulating film with a controllable reduction and an SiO ₂ equivalent of 15 angstroms or less.
[0009]
[Means for Solving the Problems]
The method for manufacturing a semiconductor device of the present invention includes a step of forming an insulating film containing at least silicon and oxygen on a silicon substrate, and a composition in which oxygen is less than the stoichiometric composition on the insulating film, titanium, A step of forming a metal oxide containing any one element of zirconium and hafnium, or any element of titanium, zirconium, and hafnium and silicon, and a gate electrode material of 10 nm or more and 200 nm on the insulating film and the metal oxide And a step of redistributing oxygen in the insulating film and the metal oxide by heat-treating the layered structure.
[0011]
FIG. 1 is a schematic diagram for explaining the features of the present invention. As shown in FIG. 1, the greatest feature of the present invention is that an insulating film such as SiO ₂ is formed as an interface buffer layer on a silicon substrate, and an oxygen buffer is formed above the interface buffer layer rather than the stoichiometric composition. The manufacturing method includes a step of forming a metal oxide having a composition lacking, and a step of applying a heat treatment step after the upper portion is covered with a conductive film such as a gate electrode. By such a manufacturing method, the upper part of the interface buffer layer formed thick in advance is dissociated, and the oxygen generated therein is absorbed by the oxygen-deficient metal oxide to bring the metal oxide back to the stoichiometric composition, The physical film thickness of the interface buffer layer is reduced. The reduction width of the interface buffer layer according to the present invention can be freely controlled by the physical film thickness of the metal oxide and the degree of oxygen deficiency, that is, the oxygen absorption capacity of the metal oxide portion. One of the features of the present invention is that an interface buffer layer having a physical film thickness as thin as possible is formed by a conventional method, and a metal oxide is stacked as statically as possible on the interface buffer layer. Then, the idea is changed in that the interface buffer layer is formed thick in advance and a physical film thickness is reduced by actively incorporating a part of the interface buffer layer into the metal oxide.
[0012]
Schematic diagrams for explaining the characteristics of the conventional method are shown in FIGS. In the conventional method, even when the thinnest 8 angstroms of SiO ₂ at the current level is formed, as shown schematically in FIG. 2, in most cases, the interface buffer layer grows during the deposition of the metal oxide. In view of this fact, even if a SiO ₂ film thinner than 8 angstroms could be made in the future with good reproducibility, the conventional method would increase the thickness of the interface buffer layer to a level where it could not be used at the time of metal oxide deposition. Turn into.
[0013]
The second feature of the present invention is that the interface buffer layer / metal oxide stack is covered with a gate electrode and then heat-treated. The reason is as follows. In the conventional method, after forming the interface buffer layer as thin as possible and then laminating the metal oxide by a static method as much as possible, annealing for recovering the defects in the film is essential. This annealing is generally performed in a nitrogen atmosphere, but as shown schematically in FIG. 3, very few oxygen atoms contained as impurities in the nitrogen atmosphere reach the silicon substrate and grow the interface buffer layer. The fact of letting it be confirmed.
As a result, the SiO2 equivalent film thickness of this laminated structure is significantly deteriorated. On the other hand, the present invention is characterized in that annealing is performed after a metal oxide is coated on the metal oxide, for example, from the viewpoint of simplification of the process, preferably from a gate electrode material. The conductive film effectively blocks impurity oxygen in the nitrogen atmosphere and completely suppresses the growth of the interface buffer layer. From a certain point of view, it can be said that the buffer layer / oxygen-deficient metal oxide stack is heat-treated by “covering” with the gate electrode, thereby utilizing the oxygen redistribution inside the stack structure. In-film defect recovery performed by a conventional method is performed by redistribution of oxygen that constitutes the interface buffer layer in the present invention.
[0014]
Furthermore, in the present invention, in addition to the matters described above, it can be predicted in principle that an accompanying advantage will occur.
[0015]
The first advantage predicted in principle is that the interface characteristics between the interface buffer layer and the silicon substrate are more likely to be better than the conventional method. The thinning of SiO ₂ performed by the conventional method is performed by a technique such as the formation of a very thin SiO ₂ film by rapid thermal oxidation or the formation of a surface oxide film by chemical solution treatment. There is no doubt that SiO ₂ with a physical thickness of less than 10 angstroms can be realized by these methods, but the feature of such a thin SiO ₂ film is not really well understood. Dogma that interfacial characteristics between SiO ₂ and Si is good, is for the existing SiO ₂ film formed by slowly thermally oxidized in a thermal equilibrium state, SiO ₂ film formed by the above specific techniques Does not necessarily hold. On the other hand, in the present invention, normal thermal oxide SiO ₂ or SiON film having a known feature is formed in a range that can be controlled by conventional techniques, and then a part of the vicinity of the interface with the metal oxide is consumed to reduce the thickness. Therefore, the conventional quality is definitely maintained for the interface characteristics with the silicon substrate. FIG. 4 schematically shows the contents described above.
[0016]
A second attendant advantage of the present invention is that the interface between the metal oxide and the interface buffer layer is structurally stabilized. In the description so far, it has been described that a part of the interface buffer layer is dissociated at the interface with the metal oxide. It should not be forgotten that the oxygen generated at this time is sucked into the metal oxide and that silicon atoms are also generated in addition to oxygen. It is predicted that the generated silicon atoms will diffuse toward the remetal oxide side with the concentration gradient as a driving force. Oxygen atoms spread throughout the metal oxide because of its large diffusion constant, but silicon atoms cannot be freely diffused because of its relatively large atomic radius, and the local distribution is located below the metal oxide (on the interface buffer layer side). To do. Under the conditions of the production method defined in the present invention, silicon atoms in the metal oxide are expected to be bonded to oxygen and exhibit an oxidation state. Although the added silicon atoms slightly reduce the relative permittivity of the metal oxide, the distribution is localized and the amount of diffusion itself is very small compared to the volume of the entire metal oxide. The influence on the SiO ₂ equivalent film thickness of the entire insulating film need not be considered. Rather, the presence of a region in which the metal oxide and the silicon oxide are mixed at the interface between the metal oxide and the interface buffer layer has the effect of relaxing the steepness of the interface atomic structure and reducing the defect density. . The matters described above are schematically shown in FIG.
Subsequently, the feasibility of the present invention will be described. 6 and 7 are cross-sectional TEM photographs demonstrating that the physical film thickness of the interface buffer layer can be reduced by the method of the present invention.
[0017]
FIG. 6 shows the change in interface structure when a sample deposited with polysilicon is annealed at 1000 ° C. after oxygen oxide heat treatment is performed at 600 ° C. for 60 minutes after the zirconium oxide is deposited to reach a sufficient stoichiometric composition. It is a cross-sectional TEM photograph shown. In this case, the physical film thickness of the interface buffer layer is not reduced even by annealing at 1000 ° C. In contrast, FIG. 7 shows that the interface buffer layer (in this case, SiON) is deposited on the silicon substrate, the oxygen-deficient zirconium oxide is deposited thereon, and polysilicon is deposited as the gate electrode by the procedure of the present invention. This is a change in the interface structure when heat-treated at 1000 ° C. later. By applying the concept of the present invention, the physical thickness of the interfacial SiON film was successfully reduced from 15 Å to 10 Å by 1000 ° C. annealing. The difference between FIG. 6 and FIG. 7 is whether or not there is room for oxygen absorption as the initial state of zirconium oxide, and whether or not oxygen redistribution occurs or does not occur due to the difference in the initial condition setting. .
[0018]
FIG. 8 is a capacitance-voltage characteristic of a polysilicon gate / zirconium oxide / SiON / Si structure fabricated according to the present invention. FIG. 9 is a capacitance-voltage characteristic of a gold gate / zirconium oxide / SiON / Si structure according to a conventional method shown for reference. First, the results of the conventional method shown in FIG. 9 will be described. In this structure, a large hysteresis characteristic is generated due to lattice defects at the interface between the zirconium oxide and the SiON. It can be seen that there is a lot of density. On the other hand, according to the method of the present invention, the hysteresis characteristic disappears completely as shown in FIG. 8, and the interface state density has reached a practical level from the shape of the CV curve. Understand. This suggests that the laminated insulating film structure obtained by the manufacturing method of the present invention has an ideal structure containing almost no lattice defects.
[0019]
In the present invention, it is desirable that the metal element constituting the metal oxide contains titanium, zirconium, hafnium, and silicon in addition to these metal elements. This is because these elements are thermally stable and are most suitable for the production method proposed in the present invention.
[0020]
As described above, according to the method for manufacturing a metal oxide / interface buffer layer stacked gate insulating film of the present invention, it is possible to manufacture a stacked insulating film having a thinner SiO ₂ equivalent film thickness than the conventional one with good controllability. Become. In addition, there are incidental advantages such as stabilization of the structure of the metal oxide / interface buffer layer interface and improvement of electrical characteristics of the interface buffer layer / silicon substrate interface. This can be obtained only by the method of manufacturing the laminated insulating film structure proposed in the present invention.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a MISFET (Metal-Insulator-Semiconductor Field Effect Transistor) using the present invention and a manufacturing method thereof will be described with reference to the drawings.
[0022]
FIG. 10 shows a cross-sectional structure of the MISFET of this example.
[0023]
As shown in the figure, a MIS structure composed of a stack of a gate electrode 8 / metal oxide film 7 / interface buffer layer 6 is formed on the silicon substrate 1, and the gate electrode 8 is surrounded by a gate side wall 9. In the silicon substrate 1, a deep diffusion region 3 and a shallow diffusion region 4 in which impurities are diffused at a high concentration and a salicide 5 are formed in a self-aligned manner in the MIS structure.
[0024]
Next, a manufacturing method of the MISFET according to the present embodiment will be described with reference to FIGS.
[0025]
A silicon substrate 1 subjected to element isolation 2 by a normal process is prepared. Next, the natural oxide film on the surface of the silicon substrate is peeled off by dilute HF solution treatment, and the silicon surface is terminated with hydrogen. Subsequently, an insulating film having good interface characteristics with the silicon substrate is formed as an interface buffer layer (initial state) 10 on the silicon surface. Here, as an example, a SiON film was formed to a thickness of about 1.5 nm by heat treatment at 850 ° C. in a NO atmosphere. In the present invention, the material of the interface buffer layer is a compound containing silicon and oxygen as essential components, and includes SiO ₂ or SiON. In particular, SiO ₂ or SiON containing oxygen as an essential component is desirable. It is desirable to add nitrogen to the interface buffer layer in addition to silicon and oxygen. In that case, the desirable range of the nitrogen concentration is desirably 15 atomic% or less. Within this range, effects such as an increase in relative dielectric constant and suppression of impurity diffusion occur, and lattice defects are not generated at the interface with the Si substrate, and electrical characteristics are not deteriorated.
[0026]
As a method for forming the interface buffer layer, a known method may be used, and thermal oxidation, thermal oxynitridation, plasma oxidation, plasma oxynitridation, thermal oxidation plus plasma nitridation, or the like can be used. Further, metal elements such as titanium, zirconium, hafnium, etc. may be mixed in SiO ₂ or SiON. The concentration of the metal element is desirably 10 atomic% or less, because when the concentration is higher than this, the interface characteristics are significantly deteriorated. FIG. 11 shows a cross-sectional structure of the element in this state. The thickness of the interface buffer layer (initial state) is preferably in the range of 3 angstroms to 15 angstroms. The reason for limiting the physical film thickness range of the interface buffer layer (initial state) as described above is that, as will be described later, the minimum physical film thickness of the interface buffer layer (final state) is 3 angstroms and the maximum physical film thickness is 15 angstroms. It is to do.
[0027]
Thereafter, a metal oxide film 11 having an oxygen-deficient composition is deposited on the interface buffer layer 10. There are various methods, and this does not limit the applicable range of the present invention. Here, as an example, a zirconium oxide target is used and an RF sputtering method using an argon atmosphere plasma is used to form a ZrOx (X <2) was deposited (FIG. 12). In this example, the lack of oxygen in the plasma atmosphere during sputtering causes oxygen desorption from the film, thereby forming an oxygen-deficient metal oxide. In addition, for example, a method of performing dry oxidation at a low temperature of 500 ° C. or lower after depositing zirconium metal is conceivable. Under such experimental conditions, it has been found that zirconium does not have a completely stoichiometric composition but has an oxygen-deficient composition.
[0028]
As a metal oxide film having a composition in which oxygen is insufficient compared to the stoichiometric composition, an oxide of any element of titanium, zirconium, or hafnium, or an oxide containing any element of titanium, zirconium, or hafnium and silicon, That is, a silicate of any element of titanium, zirconium, and hafnium can be given. In any compound, it is desirable that oxygen is deficient in the range of 0 <x <= 40 atomic% or less, where x is the percentage of deficient oxygen, from the stoichiometric composition. The reason why 0 <x is that even if the metal oxide is slightly oxygen deficient, the effects such as reduction of the interface film thickness and reduction of interface defects described in the present invention can be obtained, while oxygen deficiency This is because when the degree is 40 atomic% or less, a stable structure is maintained and oxygen is better absorbed from the lower interface film.
[0029]
Subsequently, a gate electrode 8 was deposited as a conductive film to obtain the structure of FIG. In the present invention, examples of the conductive film include gate electrode materials. For example, refractory metal materials such as polysilicon, titanium, tantalum, tungsten, and molybdenum, and nitrides thereof can be used. The existing method may be used. The thickness of the conductive film is preferably 10 nm or more and less than 200 nm. The reason why the thickness is defined as 10 nm or more is that oxygen diffusion from the heat treatment atmosphere can be sufficiently suppressed regardless of the type of the conductive material if the thickness is more than this. On the other hand, the reason why the thickness is less than 200 nm is that the thickness of the standard gate electrode material in the existing LSI does not exceed this, and comes from the structural characteristics of the LSI.
[0030]
Further, the structure of FIG. 13 is heat-treated to obtain the structure of FIG. Here, as an example, polysilicon is used for the gate electrode, and the heat treatment is performed at a temperature increase rate of 100 ° C./sec, 1000 ° C., and in a nitrogen atmosphere for 20 seconds. By this heat treatment, the upper portion of the interface buffer layer (initial state) 10 is reduced, and the generated oxygen is compensated for in the oxygen-deficient composition metal oxide film 11, and a laminated structure of the metal oxide film 7 and the interface buffer layer (final state) 6. Is formed. The interface buffer layer (final state) 6 receives a partial reduction action, and its physical film thickness is reduced as compared with the initial state. In the present invention, it is desirable that the heat treatment conditions are 800 ° C. or more and 1050 ° C. or less, and the heating time is 5 seconds or more and 30 seconds or less.
[0031]
Subsequent processing of the gate electrode, formation of the shallow diffusion region 4, formation of the gate sidewall 9, formation of the deep diffusion region 4, and formation of the salicide 5 are performed by known methods, thereby obtaining the structure of FIG.
The gate insulating film after the heat treatment has an interface buffer layer of 0.3 nm to 1.5 nm.
Hereinafter, when the metal oxide layer has a laminated structure in the range of 1.5 nm or more and 3 nm or less, the SiO ₂ equivalent film thickness can be kept low.
[0032]
【The invention's effect】
As described above in detail, according to the present invention, while maintaining the substantial presence of the interface buffer layer for maintaining good interface characteristics with the silicon substrate, the physical film thickness is reduced with good controllability, and SiO ₂ It is possible to obtain a silicon LSI device having an insulating film with a conversion of 15 angstroms or less.
[Brief description of the drawings]
FIG. 1 is a schematic diagram illustrating the characteristics of a method for manufacturing a gate insulating film according to the present invention.
FIG. 2 is a schematic diagram showing problems in the conventional method.
FIG. 3 is a schematic diagram showing problems in the conventional method.
FIG. 4 is a schematic diagram showing an improvement over the conventional method of the present invention.
FIG. 5 is a schematic diagram showing an improvement over the conventional method of the present invention.
FIG. 6 is a cross-sectional TEM photograph showing the change of the interface buffer layer during heat treatment in the conventional method.
FIG. 7 is a cross-sectional TEM photograph showing the change of the interface buffer layer during heat treatment in the present invention.
FIG. 8 is a characteristic diagram showing capacitance-voltage characteristics showing improvement of electrical characteristics in the present invention.
FIG. 9 is a characteristic diagram showing capacitance-voltage characteristics indicating deterioration of electrical characteristics in a conventional method.
FIG. 10 is a cross-sectional view showing an example of a MISFET in the present invention.
FIG. 11 is a cross-sectional view showing an example of a manufacturing process of a MISFET in the present invention.
FIG. 12 is a cross-sectional view showing an example of a manufacturing process of a MISFET in the present invention.
FIG. 13 is a cross-sectional view showing an example of a manufacturing process of a MISFET in the present invention.
FIG. 14 is a cross-sectional view showing an example of a manufacturing process of a MISFET in the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Element isolation region 3 ... Deep diffusion layer 4 ... Shallow diffusion layer 5 ... Salicide 6 ... Interface buffer layer (final state)
7 ... Metal oxide film 8 ... Gate electrode 9 ... Gate sidewall 10 ... Interface buffer layer (initial state)
11 ... Oxygen-deficient metal nitride

Claims (2)

Forming an insulating film containing at least silicon and oxygen on a silicon substrate;
On the insulating film, oxygen is Chi lifting a composition that is insufficient than the stoichiometric composition of titanium, zirconium, any element hafnium or metal oxide containing titanium, zirconium, one of the elements and silicon hafnium Forming a product,
A step of depositing a gate electrode material of 10 nm or more and less than 200 nm on the insulating film and the metal oxide to form a stacked structure ;
By annealing the laminated structure, a step of re-distribution of oxygen in the insulating film and the metal oxide,
A method for manufacturing a semiconductor device, comprising:   The heat treatment 800 ℃ or more 1050 In the temperature range below ℃ Five More than seconds 30 2. The method of manufacturing a semiconductor device according to claim 1, wherein the time is less than a second.

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