JP4047075B2

JP4047075B2 - Semiconductor device

Info

Publication number: JP4047075B2
Application number: JP2002163983A
Authority: JP
Inventors: 佳尚原田
Original assignee: Panasonic Corp; Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Corp; Panasonic Holdings Corp
Priority date: 2001-06-21
Filing date: 2002-06-05
Publication date: 2008-02-13
Anticipated expiration: 2022-06-05
Also published as: JP4712560B2; JP2008078675A; JP2011018926A; JP2003059926A; JP4713518B2; JP2003008005A; JP4165076B2; JP3773448B2; JP2003008011A; JP2007194652A; JP2006165589A

Description

【０００１】
【発明の属する技術分野】
本発明は、高誘電体からなるゲート絶縁膜を有する半導体装置に関する。
【０００２】
【従来の技術】
近年の半導体装置における高集積化及び高速化に対する技術進展に伴い、ＭＯＳＦＥＴの微細化が進められている。微細化に伴いゲート絶縁膜の薄膜化を進めると、トンネル電流によるゲートリーク電流の増大等の問題が顕在化してくる。この問題を抑制するために、ＨｆＯ₂、ＺｒＯ₂、Ｌａ₂Ｏ₃、ＴｉＯ₂又はＴａ₂Ｏ₅等の高誘電率材料を用いたゲート絶縁膜（以下、high-kゲート絶縁膜と称する）により、小さいＳｉＯ₂換算膜厚（以下、ＥＯＴ（Equivalent Oxide Thickness）と称する）を実現しながら物理的膜厚を厚くするという手法が研究されている。
【０００３】
また、昨今のシステムＬＳＩにおいては、演算処理を行なう内部回路、入出力を受け持つ周辺回路、及びＤＲＡＭ等の複数の機能を持つ回路を１つのチップに集積することが一般的になっている。このようなシステムＬＳＩを構成するＭＯＳＦＥＴに対しては、高駆動力と低リーク電流とが求められる。
【０００４】
従来のhigh-kゲート絶縁膜の形成方法として、特開2000-058832号公報（United States Patent 6,013,553 ）に記載された方法が知られている。
【０００５】
図５は、前記公報に開示された従来の半導体装置、具体的には、オキシ窒化ジルコニウム又はオキシ窒化ハフニウムよりなるhigh-kゲート絶縁膜を有するＭＯＳＦＥＴの断面構成を示している。
【０００６】
図５に示すように、Ｓｉ基板１の上にエピタキシャルＳｉ層２が形成されている。エピタキシャルＳｉ層２の上部には不純物がドーピングされており、該上部は電圧印加時にチャネル領域３となる。チャネル領域３の上にはhigh-kゲート絶縁膜４を介して導電性のゲート電極５が形成されている。
【０００７】
high-kゲート絶縁膜４の形成方法は次の通りである。すなわち、Ｓｉ基板１の上に、チャネル領域３となる部分を含むエピタキシャルＳｉ層２を形成した後、圧力１．３３×１０^-1Ｐａ程度の酸素雰囲気内で、Ｓｉ基板１に対して６００〜７００℃程度の加熱処理を３０秒間程度行なうことによって、厚さ１ｎｍ未満の酸化物層を形成する。その後、この酸化物層に対して、そのまま残存させるか、希釈ＨＦにより取り除いてＳｉ表面を水素終端させるか、又は、クラスターツールを用いた超高真空状態（１．３３×１０^-6Ｐａ程度）での７８０℃程度の加熱処理により昇華して原子的に平滑なＳｉ表面を形成するかのいずれかの処理が行なわれる。酸化物層つまりシリコン酸化膜を残存させる代わりに、オキシ窒化シリコン膜の超薄膜よりなる保護障壁層を形成してもよい。
【０００８】
以上のようにクリーンなＳｉ表面、酸化物層又は保護障壁層のいずれかを持つＳｉ基板１を準備した後、Ｓｉ基板１の上に、スパッタ法、蒸着法、化学的気相成長（ＣＶＤ）法又はプラズマＣＶＤ法等により、ジルコニウム又はハフニウムよりなる金属層を堆積する。その後、該金属層に対して、ＮＯ若しくはＮ₂Ｏ等の酸素及び窒素を含むガスを用いた酸窒化処理、Ｎ₂及びＯ₂を用いた低温下での遠隔プラズマ処理（基板処理チャンバーとプラズマ生成チャンバーとが異なっている）、又は、ＮＨ₃を用いた遠隔プラズマ窒化処理及びそれに引き続く酸化処理を行なうこと等により、オキシ窒化ジルコニウム又はオキシ窒化ハフニウムよりなるhigh-kゲート絶縁膜４を形成する。
【０００９】
その後、Ａｒ等の不活性ガス雰囲気中又は還元性ガス雰囲気中で、high-kゲート絶縁膜４に対して７５０℃程度のアニールを２０秒間行なうことにより、high-kゲート絶縁膜４を緻密化する。このように形成されたhigh-kゲート絶縁膜４は非晶質又は多結晶であり、ＳｉＯ₂の比誘電率と比べて著しく高い比誘電率を有する。
【００１０】
【発明が解決しようとする課題】
しかしながら、前述の従来のＭＯＳＦＥＴにおいては、high-kゲート絶縁膜の信頼性寿命が短くなるという問題がある。
【００１１】
前記に鑑み、本発明は、長い信頼性寿命を持つhigh-kゲート絶縁膜を実現することを目的とする。
【００１２】
【課題を解決するための手段】
前記の目的を達成するため、本願発明者は、従来のhigh-kゲート絶縁膜の信頼性寿命が短くなる原因を検討した結果、次のような知見を得た。すなわち、前述の従来の方法を用いてシリコン基板上にhigh-kゲート絶縁膜を形成した場合、シリコン基板界面に、ＳｉＯ₂の組成に近いシリケート（high-k材料（ジルコニウム酸化物等の金属酸化物）とシリコンとの３元系化合物）が形成される。一般的に、シリケートは、シリコンを含まない元のhigh-k材料よりも比誘電率が低い。また、high-kゲート絶縁膜堆積後のアニール（ゲート絶縁膜を緻密化するためのＰＤＡ（Post Deposition Anneal））によって、ゲート絶縁膜を構成するhigh-k材料の結晶化が進む結果、該high-k材料から結晶粒界を介して酸素がシリコン基板まで拡散し、それによりシリコン基板界面にＳｉＯ₂が形成されてしまう。すなわち、high-kゲート絶縁膜は、比誘電率の低いＳｉＯ₂又はＳｉＯ₂の組成に近いシリケートよりなる界面層と、比誘電率の高いhigh-k材料又はhigh-k材料の組成に近いシリケートよりなるhigh-k層との積層構造を持つ。ところが、このような積層構造においては、ゲート電極を介して電圧が印加されると低誘電率の界面層に電界集中が起こり、その結果、絶縁破壊が生じやすくなって、high-kゲート絶縁膜の重要な特性である信頼性が劣化してしまうと考えられる。
【００１３】
そこで、本願発明者は、high-kゲート絶縁膜の信頼性寿命の長さと、界面層厚さのhigh-kゲート絶縁膜全体の厚さに対する比Ｔ１／（Ｔ１＋Ｔ２）（但しＴ１は界面層の物理的厚さ、Ｔ２はhigh-k層の物理的厚さ）との相関をシミュレーションを用いて調べてみた。その結果を図１に示す。シミュレーションは、trap generation model（J.H.Stathis, Technical Digest of International Electron Device and Material (1998), p167.）をhigh-kゲート絶縁膜に応用することによって行なった。具体的には、high-kゲート絶縁膜について、リーク電流Ｊ_g、ストレス印加直後のリーク電流Ｊ₀、注入電荷当たりの欠陥生成率Ｐ_g（＝絶縁破壊時の電流増加比ΔＪ_g／Ｊ₀）、及び絶縁破壊に至るときの臨界欠陥密度Ｎ_bdのそれぞれの値を求め、これらの値に基づいて、high-kゲート絶縁膜における絶縁破壊寿命Ｔ_bd（＝Ｎ_bd／Ｐ_g）を求めた。また、シュミュレーションにおいては、high-kゲート絶縁膜のＥＯＴが常に１．５ｎｍを保つように各物理的厚さＴ１及びＴ２を調整しながら比Ｔ１／（Ｔ１＋Ｔ２）を変化させていった場合における、印加電圧１Ｖのストレス下（温度は室温）でのhigh-kゲート絶縁膜の信頼性寿命を算出した。但し、シュミュレーションにおいては、界面層の比誘電率ε１を３．９の一定値に固定したのに対して、high-k層の比誘電率ε２を８．０、１２．０、１８．０及び２４．０の複数の値に変化させた。ここで、ＥＯＴ＝Ｔ１＋（ε１／ε２）×Ｔ２の関係が成り立つ。
【００１４】
図１に示すように、比Ｔ１／（Ｔ１＋Ｔ２）、つまりhigh-kゲート絶縁膜全体の厚さに対する界面層厚さの比が０．２以下である場合、high-kゲート絶縁膜の信頼性を高く維持できる。また、比Ｔ１／（Ｔ１＋Ｔ２）が増加するに従い、high-kゲート絶縁膜の信頼性が劣化する傾向がある。さらに、図１の縦軸に対数目盛りを用いていることを考慮すると、比Ｔ１／（Ｔ１＋Ｔ２）を０．２以下に設定することは、high-kゲート絶縁膜の信頼性を飛躍的に向上させる効果を持っていることが分かる。具体的には、比Ｔ１／（Ｔ１＋Ｔ２）を０．２以下に設定することによって、例えば比Ｔ１／（Ｔ１＋Ｔ２）が０．５程度である場合と比べて、信頼性寿命を３桁以上も長くすることができる。
【００１５】
また、図１に示すように、比Ｔ１／（Ｔ１＋Ｔ２）が０．０〜０．２である構造を持つゲート絶縁膜においては、high-k層の比誘電率ε２が８．０から１２．０へ増加するに従って信頼性寿命の長さも増加し、ε２が１２．０から１８．０までの範囲で信頼性寿命の長さがほぼ飽和して最大値を示す。一方、ε２が１８．０から２４．０へ増加すると、信頼性寿命の長さは逆に減少してしまう。ところで、一般的に、high-k層における比誘電率ε２の値は厚さ方向に変化している。従って、high-k層における比誘電率ε２の平均値をε２_avとしたときには、ε２_avは１２．０以上で且つ１８．０以下であることが好ましい。また、high-k層として、一の金属とシリコンと酸素とを含むシリケート膜を用いた場合、high-k層の組成をＭ_XＳｉ_YＯ（但しＭは一の金属を表し、Ｘ＞０、Ｙ＞０である）とすると、前述の１２．０≦ε２_av≦１８．０の条件は、０．２０≦Ｙ／（Ｘ＋Ｙ）≦０．３０の条件と等価である。すなわち、high-kゲート絶縁膜の信頼性の観点からは、high-k層の材料としてシリコンを含まない完全な金属酸化物を用いるよりも、０．２０≦Ｙ／（Ｘ＋Ｙ）≦０．３０の関係を満たす、シリコン含有のシリケートＭ_XＳｉ_YＯを用いた方が好ましい。その理由は、high-k層と界面層との間の比誘電率の差を小さくすることによって、界面層への電界集中が緩和されるためと考えられる。尚、界面層もＭ_XＳｉ_YＯで表せるシリケートを含むことがあるが、このシリケートにおけるＹ／（Ｘ＋Ｙ）は０．９０以上であって、組成的にはＳｉＯ₂とほぼ同等である。
【００１６】
さらに、本願発明者は、high-kゲート絶縁膜の信頼性寿命の長さと、界面層厚さＴ１のhigh-kゲート絶縁膜全体の厚さ（Ｔ１＋Ｔ２）（但しＴ２はhigh-k層の物理的厚さ）に対する比との相関を実験により調べてみた。その結果を図２に示す。尚、実験に用いた界面層は、組成がＳｉＯ₂に近いＳｉＯＮ膜（比誘電率ε１＝３．９）であり、実験に用いたhigh-k層はＣＶＤ（chemical vapor deposition ）法により形成されたＳｉ₃Ｎ₄膜（比誘電率ε２＝７．５）である。また、実験においては、high-kゲート絶縁膜のＥＯＴが常に３．０ｎｍを保つように各物理的厚さＴ１及びＴ２を調整しながら比Ｔ１／（Ｔ１＋Ｔ２）を変化させていった場合における、印加電圧３．５Ｖのストレス下（温度は１００℃）で絶縁破壊が生じるまでに絶縁膜に注入された総電荷量（絶縁破壊総電荷量Ｑ_bd）を測定した。ここで、絶縁破壊総電荷量Ｑ_bdの大きさがhigh-kゲート絶縁膜の信頼性寿命の長さと対応する。
【００１７】
図２に示すように、比Ｔ１／（Ｔ１＋Ｔ２）が０．２以下である場合、high-kゲート絶縁膜の信頼性を高く維持できる一方、該比が０．３を越えると信頼性が急激に劣化することが実験的に実証された。また、図２の縦軸に対数目盛りを用いていることを考慮すると、比Ｔ１／（Ｔ１＋Ｔ２）を０．２以下に設定することは、high-kゲート絶縁膜の信頼性を飛躍的に向上させる効果を持っていることが分かる。
【００１８】
以上のように、図１及び図２に示す結果から、high-kゲート絶縁膜の信頼性の観点からは、界面層厚さＴ１の全体厚さ（Ｔ１＋Ｔ２）に対する比を０．３以下にすることが必須であり、また、比Ｔ１／（Ｔ１＋Ｔ２）を０．２以下にすることがより好ましい。
【００１９】
本発明は、以上の知見に基づきなされたものであって、具体的には、本発明に係る半導体装置は、半導体基板上に形成された高誘電率絶縁膜を有する半導体装置を前提とし、高誘電率絶縁膜は、半導体基板との界面に形成された界面層と、界面層の上に形成され、界面層よりも比誘電率が高い高誘電率層とを有し、界面層の厚さＴ１及び高誘電率層の厚さＴ２は、Ｔ１／（Ｔ１＋Ｔ２）≦０．３の関係を満たす。
【００２０】
本発明の半導体装置によると、高誘電率絶縁膜における界面層厚さＴ１の全体厚さ（Ｔ１＋Ｔ２）に対する比を０．３以下にするため、高誘電率絶縁膜に電圧が印加された場合にも界面層への電界集中を抑制できる。従って、このような高誘電率絶縁膜を用いることによって、長い信頼性寿命を持つhigh-kゲート絶縁膜を実現することができる。また、このとき、比誘電率の低い界面層が薄く且つ比誘電率の高い高誘電率層が厚いので、high-kゲート絶縁膜のＥＯＴを小さくすることができる。
【００２１】
本発明の半導体装置において、Ｔ１及びＴ２は、Ｔ１／（Ｔ１＋Ｔ２）≦０．２の関係を満たすことが好ましい。
【００２２】
このようにすると、高誘電率絶縁膜の信頼性をより向上させることができる。
【００２３】
本発明の半導体装置において、界面層の比誘電率ε１は３．９以上で且つ７．０以下であると共に高誘電率層の比誘電率ε２は７．０よりも大きく、高誘電率層における比誘電率ε２の平均値ε２_avは１２．０以上で且つ１８．０以下であることが好ましい。
【００２４】
このようにすると、高誘電率層と界面層との間の比誘電率の差が所定の範囲内に制限されるため、電圧印加時の界面層への電界集中がより緩和され、高誘電率絶縁膜の信頼性をより向上させることができる。
【００２５】
本発明の半導体装置において、界面層の比誘電率ε１は３．９以上で且つ７．０以下であると共に高誘電率層の比誘電率ε２は７．０よりも大きく、高誘電率層は、一の金属とシリコンと酸素とを含むシリケートよりなり、高誘電率層の組成をＭ_XＳｉ_YＯ（但し、Ｍは一の金属を表し、Ｘ＞０、Ｙ＞０である）としたときに、Ｘ及びＹは、０．２０≦Ｙ／（Ｘ＋Ｙ）≦０．３０の関係を満たすことが好ましい。
【００２６】
このようにすると、高誘電率層の材料としてシリコンを含まない完全な金属酸化物を用いた場合と比べて、高誘電率層と界面層との間の比誘電率の差が小さくなるため、電圧印加時の界面層への電界集中がより緩和され、その結果、高誘電率絶縁膜の信頼性をより向上させることができる。
【００２７】
本発明の半導体装置において、高誘電率層は、ハフニウム又はジルコニウムとシリコンと酸素とを含むシリケートよりなることが好ましい。
【００２８】
このようにすると、長い信頼性寿命を持つhigh-kゲート絶縁膜を確実に実現することができる。
【００２９】
【発明の実施の形態】
以下、本発明の一実施形態に係る半導体装置及びその製造方法について図面を参照しながら説明する。
【００３０】
図３（ａ）〜（ｅ）は本実施形態に係る半導体装置の製造方法の各工程を示す断面図である。
【００３１】
図３（ａ）に示すように、例えばＳｉ（１００）基板１１上に素子分離用絶縁膜１２を形成し、それによってデバイス領域Ｒ_Dを規定する。
【００３２】
次に、Ｓｉ基板１１に対して、標準ＲＣＡ洗浄及び希釈ＨＦ洗浄を順次行なった後、例えばＮＨ₃ガス中でＳｉ基板１１に対して６００〜７００℃程度の熱処理を行なう。これにより、図３（ｂ）に示すように、デバイス領域Ｒ_DのＳｉ基板１１上にシリコン窒化膜（Ｓｉ₃Ｎ₄膜）１３が形成される。
【００３３】
次に、図３（ｃ）に示すように、例えばＣＶＤ法を用いて、Ｓｉ₃Ｎ₄膜１３の上にＨｆＯ₂膜１４を形成する。具体的には、液体ＨｆソースであるＨｆ t-butoxide （Ｃ₁₆Ｈ₃₆ＨｆＯ₄）中にＮ₂等のキャリアガスを吹き込んでバブリングを行なう。これにより、液体Ｈｆソースを気体状態にして該ソースガスをキャリアガスと共に反応炉内に導入し、５００℃程度の温度下でＲＴ−ＣＶＤ（Rapid Thermal CVD ）処理を使用してＨｆＯ₂膜１４を形成する。このとき、ＨｆＯ₂膜１４の成長速度又は膜質の向上のために乾燥Ｏ₂ガスを反応炉内に導入する。このように形成されたＨｆＯ₂膜１４に対して組成分析を行なったところ、Ｈｆソース中にＨｆ、Ｏ、Ｃ及びＨが含まれているため、ＨｆＯ₂膜１４の内部に１〜２原子％程度以下の微量なＣ及びＨが含有されていた。尚、反応炉内にはＮ₂ガスも導入されるが、５００℃程度の温度下ではＮ₂ガスは非常に不活性であるため、Ｎ₂ガスの寄与は非常に小さい。
【００３４】
次に、例えばＮ₂ガス中で、ＨｆＯ₂膜１４に対して６００〜８００℃程度のＰＤＡ処理を３０秒間程度行なう。これにより、Ｓｉ基板１１の酸化、ＨｆＯ₂膜１４からの水素の脱離、ＨｆＯ₂膜１４の緻密化及び微結晶化、並びに、Ｓｉ基板１１又はＳｉ₃Ｎ₄膜１３とＨｆＯ₂膜１４との間におけるＳｉ及びＨｆの相互拡散等の反応が生じる。その結果、ＨｆＯ₂膜１４の堆積当初（図３（ｃ）参照）における、Ｓｉ基板１１上にＳｉ₃Ｎ₄膜１３が形成され且つＳｉ₃Ｎ₄膜１３上にＨｆＯ₂膜１４が形成された構造は、最終的に、図３（ｄ）に示すように、Ｓｉ基板１１上に比誘電率の低い界面層１５が形成され且つ界面層１５上に比誘電率の高いhigh-k層１６が形成された構造に変化する。ここで、界面層１５はＳｉＯ₂又はＳｉＯ₂の組成に近いシリケートよりなり、high-k層１６はＨｆＯ₂又はＨｆＯ₂の組成に近いシリケートよりなる。また、界面層１５及びhigh-k層１６にはそれぞれ微量のＮが含まれる。
【００３５】
次に、図３（ｅ）に示すように、界面層１５とhigh-k層１６との積層構造を有するhigh-kゲート絶縁膜の上に、例えばポリシリコンよりなるゲート電極１７を形成する。具体的には、ＳｉＨ₄を用いて５４０℃程度の蒸着温度でポリシリコン膜を形成した後、該ポリシリコン膜に対して例えば５×１０¹⁵ｃｍー2のドーズ量でＰイオンを注入し、その後、イオン注入されたポリシリコン膜をパターン化することによりゲート電極１７を形成する。これにより、ｎＭＯＳＦＥＴ構造が完成する。尚、ゲート電極１７に注入された不純物に対する活性化アニールは、乾燥Ｎ₂ガス中における９００℃、３０秒間のＲＴＰ（Rapid Thermal Process ）により行なった。
【００３６】
本実施形態の特徴は、例えばＨｆＯ₂膜１４の形成前にＳｉ基板１１上にＳｉ₃Ｎ₄膜１３を形成することにより、又は例えばＨｆＯ₂膜１４に対するＰＤＡの処理温度を低めに設定したり若しくは該ＰＤＡの処理時間を短めに設定すること等により、high-kゲート絶縁膜全体の厚さに対する界面層１５の厚さの比を所定の範囲内に設定することである。具体的には、high-kゲート絶縁膜全体の厚さ、つまり界面層１５の厚さＴ１とhigh-k層１６の厚さＴ２との合計厚さ（Ｔ１＋Ｔ２）に対する界面層１５の厚さＴ１の比を０．３以下、より好ましくは０．２以下に設定することである。これにより、本実施形態においては、ゲート電圧印加時にも界面層１５への電界集中を抑制できるので、長い信頼性寿命を持つhigh-kゲート絶縁膜を実現することができる。また、界面層１５とhigh-k層１６とが積層されてなるゲート絶縁膜を有するＭＯＳキャパシタに対して、ＬＣＲ（inductance - capacitance - resistance ）メータを用いてＣＶ（capacitance - voltage ）測定を行ない、その測定結果に基づいて、ゲート電極の空乏化又は基板の量子化効果等を考慮して、シミュレーションプログラムによりゲート絶縁膜のＥＯＴを算出したところ、十分に小さなＥＯＴが得られた。すなわち、本実施形態においては、比誘電率の低い界面層１５が薄く且つ比誘電率の高いhigh-k層１６が厚いので、high-kゲート絶縁膜のＥＯＴを小さくすることができる。
【００３７】
図４（ａ）は、本実施形態の半導体装置、つまりＨｆプレカーサーを用いて形成されたＨｆＯ₂誘電体をhigh-k材料とするゲート絶縁膜を備えたＭＯＳＦＥＴの高分解能断面ＴＥＭ（transmission electron microscope）像を示している。図４（ａ）に示すように、本実施形態の半導体装置におけるhigh-kゲート絶縁膜の全体厚さ（界面層１５の厚さＴ１とhigh-k層１６の厚さＴ２との合計（Ｔ１＋Ｔ２））は３．０〜３．３ｎｍ程度である。また、界面層１５の厚さＴ１は０．４〜０．５ｎｍ程度である。すなわち、high-kゲート絶縁膜全体の厚さに対する界面層１５の厚さの比Ｔ１／（Ｔ１＋Ｔ２）は０．１２〜０．１７程度であり、本発明で推奨する関係：Ｔ１／（Ｔ１＋Ｔ２）≦０．３（より好ましくはＴ１／（Ｔ１＋Ｔ２）≦０．２）を十分に満たしている。
【００３８】
図４（ｂ）は、比較例としての半導体装置、つまり本実施形態と同様の方法により形成されたＨｆＯ₂誘電体をhigh-k材料とするゲート絶縁膜を備えた他のＭＯＳＦＥＴの高分解能断面ＴＥＭ像を示している。図４（ｂ）に示すように、比較例の半導体装置においては、図４（ａ）に示す本実施形態のＭＯＳキャパシタ構造と対応するように、Ｓｉ基板２１上に、界面層２５とhigh-k層２６との積層構造からなるゲート絶縁膜を介して、Ｐｏｌｙ−Ｓｉよりなるゲート電極２７が形成されている。また、比較例の半導体装置においては、high-kゲート絶縁膜の全体厚さ（界面層２５の厚さＴ１’とhigh-k層２６の厚さＴ２’との合計（Ｔ１’＋Ｔ２’））は３．０〜３．３ｎｍ程度である。また、界面層２５の厚さＴ１’は１．０ｎｍ程度である。すなわち、high-kゲート絶縁膜全体の厚さに対する界面層２５の厚さの比Ｔ１’／（Ｔ１’＋Ｔ２’）は０．３０〜０．３３程度であり、前述の本発明で推奨する関係を満たしていない。
【００３９】
図４（ａ）に示す本実施形態のＭＯＳキャパシタ構造、及び、図４（ｂ）に示す比較例のＭＯＳキャパシタ構造のそれぞれについて、ゲート面積を５０００μｍ²として、印加電圧３．０Ｖ（ゲート電極側が低電位）のストレス下（温度は室温）でのゲート絶縁膜の信頼性寿命を算出した。その結果、界面層の相対厚さが小さい本実施形態のゲート絶縁膜の信頼性寿命は１×１０⁴秒程度であり、界面層の相対厚さが大きい比較例のゲート絶縁膜の信頼性寿命は１×１０²秒程度であった。すなわち、high-kゲート絶縁膜全体の厚さに対する界面層の厚さの比Ｔ１／（Ｔ１＋Ｔ２）が０．２以下であると、high-kゲート絶縁膜の信頼性寿命が劇的に向上する。これは、Ｓｉ基板表面に形成される低誘電率の界面層を薄くできると、該界面層に集中する強い電界強度に起因して信頼性劣化が生じる事態を回避できるためと考えられる。
【００４０】
ところで、図４（ａ）及び（ｂ）に示すように、high-kゲート絶縁膜の高分解能断面ＴＥＭ像においては、界面層の像はhigh-k層の像と比べて明らかに白くなる。ここで、high-kゲート絶縁膜の組成をＨｆ_XＳｉ_YＯ（但しＸ＞０、Ｙ＞０）とすると、Ｙ／（Ｘ＋Ｙ）＝０．９０が界面層とhigh-k層との境界に対応する。尚、high-kゲート絶縁膜の組成は、Ｓｉ基板側から次第にＳｉ組成が減少するように、言い換えると、Ｙ／（Ｘ＋Ｙ）の値が１．０から次第に減少するように変化する。すなわち、０．９０≦Ｙ／（Ｘ＋Ｙ）≦１．０の関係を満たす範囲が界面層であり、Ｙ／（Ｘ＋Ｙ）＜０．９０の関係を満たす範囲がhigh-k層である。このとき、界面層の比誘電率ε１は３．９以上で且つ７．０以下であると共にhigh-k層の比誘電率ε２は７．０よりも大きい。
【００４１】
尚、本実施形態において、Ｓｉ基板１１上にＳｉ₃Ｎ₄膜１３を介してＨｆＯ₂膜１４を形成した後、ＨｆＯ₂膜１４に対してＰＤＡ処理を行ない、それにより、界面層１５とhigh-k層１６との積層構造を有するhigh-kゲート絶縁膜を形成したが、このとき、窒素原子がゲート絶縁膜のいずれかの部分（基板近傍、電極近傍、膜中央部等）に含まれていてもよい。また、ＰＤＡ処理条件は特に限定されるものではないが、ＰＤＡ処理温度は８００℃程度以下であり、ＰＤＡ処理温度は３０秒程度以下であることが好ましい。
【００４２】
また、本実施形態において、液体ＨｆソースであるHf t-butoxide を用いてＨｆＯ₂膜１４を形成したが、ＨｆＯ₂膜１４の形成方法は特に限定されるものではない。具体的には、例えば固体原料であるＨｆ nitrato（Ｈｆ（ＮＯ₃）₄）を加熱して液体状態にすると共に該液状の原料中にＡｒ等のキャリアガスを吹き込んでバブリングを行なった後、気化した原料をキャリアガスと共に、基板ヒーターとコールドウォールとを有するＣＶＤ装置の反応炉内に導入し、その後、２００℃程度の温度下でＲＴ−ＣＶＤ処理を使用してＨｆＯ₂膜１４を形成してもよい。このとき、ＨｆＯ₂膜１４の成長速度又は膜質の向上のために乾燥Ｏ₂ガスを反応炉内に導入する。このように形成されたＨｆＯ₂膜１４に対して組成分析を行なった場合、Ｈｆソース中にＨｆ、Ｏ、及びＮが含まれているため、ＨｆＯ₂膜１４の内部に１〜２原子％程度以下の微量なＮが含有される。尚、反応炉内にはＡｒガスも導入されるが、２００℃程度の温度下ではＡｒガスは非常に不活性であるため、Ａｒガスの寄与は非常に小さい。
【００４３】
また、本実施形態において、high-kゲート絶縁膜（つまりその中のhigh-k層１６）の材料としてＨｆＯ₂を用いた。しかし、これに代えて、他の金属酸化物、具体的には、Ｈｆと同様の性質を持つＺｒの酸化物（ＺｒＯ₂）、ＴｉＯ₂、Ｔａ₂Ｏ₅、Ｌａ₂Ｏ₃又はＡｌ₂Ｏ₃等を用いた場合にも、界面層１５の厚さＴ１及びhigh-k層１６の厚さＴ２がＴ１／（Ｔ１＋Ｔ２）≦０．３の関係（より好ましくはＴ１／（Ｔ１＋Ｔ２）≦０．２の関係）を満たす限り、high-kゲート絶縁膜の信頼性寿命について本実施形態と同様の劇的な向上効果が生じる。特に、界面層の比誘電率ε１が３．９以上で且つ７．０以下であると共にhigh-k層１６の比誘電率ε２が７．０よりも大きく、さらに、high-k層１６における比誘電率ε２の平均値ε２_avが１２．０以上で且つ１８．０以下である場合には、次のような特別な効果が得られる。すなわち、high-k層１６と界面層１５との間の比誘電率の差が所定の範囲内に制限されるため、電圧印加時の界面層１５への電界集中がより緩和され、high-kゲート絶縁膜の信頼性をより向上させることができる。
【００４４】
また、本実施形態において、high-kゲート絶縁膜（つまりその中のhigh-k層１６）の材料として、組成がＭ_XＳｉ_YＯ（但しＭは一の金属を表し、Ｘ＞０、Ｙ＞０である）で表される金属シリケート（金属、シリコン及び酸素以外の元素を含んでいてもよい）、例えばＨｆシリケート（Ｈｆ_XＳｉ_YＯ₂）又はＺｒシリケート（Ｚｒ_XＳｉ_YＯ₂）等を用いた場合にも、比Ｔ１／（Ｔ１＋Ｔ２）≦０．３の関係（好ましくはＴ１／（Ｔ１＋Ｔ２）≦０．２の関係）を満たす限り、high-kゲート絶縁膜の信頼性寿命について本実施形態と同様の劇的な向上効果が生じる。特に、界面層の比誘電率ε１が３．９以上で且つ７．０以下であると共にhigh-k層１６の比誘電率ε２が７．０よりも大きく、さらに、high-k層１６が０．２０≦Ｙ／（Ｘ＋Ｙ）≦０．３０の関係を満たす金属シリケートＭ_XＳｉ_YＯである場合には、次のような特別な効果が得られる。すなわち、シリコンを含まない完全な金属酸化物を用いた場合と比べて、high-k層１６と界面層１５との間の比誘電率の差が小さくなるため、電圧印加時の界面層１５への電界集中がより緩和され、その結果、high-kゲート絶縁膜の信頼性をより向上させることができる。
【００４５】
ところで、本実施形態のＨｆＯ₂膜１４に代えて例えばＨｆシリケート膜を形成する場合、次のような方法を用いることができる。すなわち、液体ＨｆソースであるＨｆ t-butoxide （Ｃ₁₆Ｈ₃₆ＨｆＯ₄）及びＳｉソースであるＴＤＥＡＳ（Tetrakis Diethyl Amino Silicon：Si[N(C₂H₅)₂]₄）を気化して、キャリアガスであるＮ₂ガスと共に反応炉内に導入した後、３００〜５００℃程度の温度下でＣＶＤ処理を行なうことにより、Ｈｆシリケート膜を形成できる。このとき、ＨｆソースとＳｉソースとの混合比、又はＣＶＤ処理の温度を調節することによって、Ｈｆシリケート膜の組成を変化させることができる。また、Ｈｆシリケート膜の成長速度又は膜質の向上のために、乾燥Ｏ₂ガスを反応炉内に導入してもよい。
【００４６】
また、本実施形態において、基板としてＳｉ基板１１を用いたが、これに代えて、他の半導体基板、例えばＳｉＧｅ基板又はＳｉＣ基板等を用いてもよい。
【００４７】
また、本実施形態において、ゲート電極１７としてＰｏｌｙ−Ｓｉゲート電極を用いたが、これに代えて、メタルゲート電極を用いてもよい。具体的には、例えばＡｒスパッタによるＰＶＤ（physical vapor deposition ）法を用いて、ＴｉＮ膜とＡｌ膜との積層構造、又はＴａＮ膜の単層構造を有するメタルゲート電極を形成してもよい。
【００４８】
【発明の効果】
本発明によると、high-kゲート絶縁膜における界面層厚さＴ１の全体厚さ（Ｔ１＋Ｔ２）に対する比を０．３以下、より好ましくは０．２以下にするため、ゲート電圧印加時における界面層への電界集中を抑制できるので、high-kゲート絶縁膜の信頼性寿命を向上させることができる。
【図面の簡単な説明】
【図１】 high-kゲート絶縁膜の信頼性寿命の長さと、界面層厚さＴ１のhigh-kゲート絶縁膜全体の厚さ（Ｔ１＋Ｔ２）（但しＴ２はhigh-k層の物理的厚さ）に対する比との相関をシミュレーションを用いて調べた結果を示す図である。
【図２】 high-kゲート絶縁膜の信頼性寿命の長さと、界面層厚さＴ１のhigh-kゲート絶縁膜全体の厚さ（Ｔ１＋Ｔ２）（但しＴ２はhigh-k層の物理的厚さ）に対する比との相関を実験により調べた結果を示す図である。
【図３】（ａ）〜（ｅ）は本発明の一実施形態に係る半導体装置の製造方法の各工程を示す断面図である。
【図４】（ａ）は本発明の一実施形態に係る半導体装置の高分解能断面ＴＥＭ像を示す図であり、（ｂ）は比較例に係る半導体装置の高分解能断面ＴＥＭ像を示す図である。
【図５】従来の半導体装置の断面図である。
【符号の説明】
１１Ｓｉ基板
１２素子分離用絶縁膜
１３Ｓｉ₃Ｎ₄膜
１４ＨｆＯ₂膜
１５界面層
１６ high-k層
１７ゲート電極
２１Ｓｉ基板
２５界面層
２６ high-k層
２７ゲート電極
Ｒ_D デバイス領域[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a gate insulating film made of a high dielectric material.
[0002]
[Prior art]
With the recent progress in technology for higher integration and higher speed in semiconductor devices, MOSFETs have been miniaturized. As the gate insulating film is made thinner with miniaturization, problems such as an increase in gate leakage current due to tunneling current become obvious. In order to suppress this problem, HfO ₂ , ZrO ₂ , La ₂ O _Three TiO ₂ Or Ta ₂ O _Five By using a gate insulating film (hereinafter referred to as a high-k gate insulating film) using a high dielectric constant material such as ₂ A method of increasing the physical film thickness while realizing the equivalent film thickness (hereinafter referred to as EOT (Equivalent Oxide Thickness)) has been studied.
[0003]
In recent system LSIs, it is common to integrate an internal circuit that performs arithmetic processing, a peripheral circuit that handles input and output, and a circuit having a plurality of functions such as a DRAM on a single chip. For a MOSFET constituting such a system LSI, high driving force and low leakage current are required.
[0004]
As a conventional method for forming a high-k gate insulating film, a method described in JP 2000-058832 A (United States Patent 6,013,553) is known.
[0005]
FIG. 5 shows a cross-sectional structure of a conventional semiconductor device disclosed in the above publication, specifically, a MOSFET having a high-k gate insulating film made of zirconium oxynitride or hafnium oxynitride.
[0006]
As shown in FIG. 5, an epitaxial Si layer 2 is formed on the Si substrate 1. The upper portion of the epitaxial Si layer 2 is doped with impurities, and the upper portion becomes the channel region 3 when a voltage is applied. A conductive gate electrode 5 is formed on the channel region 3 via a high-k gate insulating film 4.
[0007]
The formation method of the high-k gate insulating film 4 is as follows. That is, after forming the epitaxial Si layer 2 including the portion to become the channel region 3 on the Si substrate 1, the pressure is 1.33 × 10 × 10. ^-1 An oxide layer having a thickness of less than 1 nm is formed by performing a heat treatment at about 600 to 700 ° C. for about 30 seconds on the Si substrate 1 in an oxygen atmosphere of about Pa. Thereafter, the oxide layer is left as it is, or is removed by dilute HF, and the Si surface is terminated with hydrogen, or an ultrahigh vacuum state (1.33 × 10 6 using a cluster tool) is used. ^-6 Either a sublimation by a heat treatment at about 780 ° C. at about Pa) to form an atomically smooth Si surface is performed. Instead of leaving the oxide layer, that is, the silicon oxide film, a protective barrier layer made of an ultrathin silicon oxynitride film may be formed.
[0008]
After preparing the Si substrate 1 having either a clean Si surface, an oxide layer, or a protective barrier layer as described above, a sputtering method, vapor deposition method, chemical vapor deposition (CVD) is performed on the Si substrate 1. A metal layer made of zirconium or hafnium is deposited by a method or a plasma CVD method. Then, NO or N against the metal layer ₂ Oxynitriding treatment using a gas containing oxygen and nitrogen such as O, N ₂ And O ₂ Remote plasma processing at low temperature using a substrate (the substrate processing chamber and the plasma generation chamber are different), or NH _Three A high-k gate insulating film 4 made of zirconium oxynitride or hafnium oxynitride is formed by performing a remote plasma nitridation process using silicon and a subsequent oxidation process.
[0009]
Thereafter, the high-k gate insulating film 4 is densified by annealing the high-k gate insulating film 4 at about 750 ° C. for 20 seconds in an inert gas atmosphere such as Ar or a reducing gas atmosphere. To do. The high-k gate insulating film 4 thus formed is amorphous or polycrystalline, and SiO ₂ The dielectric constant is significantly higher than the relative dielectric constant.
[0010]
[Problems to be solved by the invention]
However, the above-described conventional MOSFET has a problem that the reliability life of the high-k gate insulating film is shortened.
[0011]
In view of the above, an object of the present invention is to realize a high-k gate insulating film having a long reliability life.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, the present inventor has studied the cause of shortening of the reliability life of the conventional high-k gate insulating film, and as a result, has obtained the following knowledge. That is, when a high-k gate insulating film is formed on a silicon substrate by using the above-described conventional method, SiO interface is formed on the silicon substrate interface. ₂ A silicate (a ternary compound of high-k material (metal oxide such as zirconium oxide) and silicon) is formed. In general, silicates have a lower dielectric constant than the original high-k material that does not contain silicon. Further, as a result of the crystallization of the high-k material constituting the gate insulating film being advanced by annealing (PDA (Post Deposition Anneal) for densifying the gate insulating film) after the deposition of the high-k gate insulating film, oxygen diffuses from the -k material through the grain boundaries to the silicon substrate, which causes SiO at the silicon substrate interface ₂ Will be formed. That is, the high-k gate insulating film is made of SiO having a low relative dielectric constant. ₂ Or SiO ₂ And a high-k layer having a high relative dielectric constant or a high-k layer having a silicate close to the composition of the high-k material. However, in such a laminated structure, when a voltage is applied through the gate electrode, electric field concentration occurs in the interface layer having a low dielectric constant, and as a result, dielectric breakdown is likely to occur, resulting in a high-k gate insulating film. It is considered that the reliability, which is an important characteristic of, deteriorates.
[0013]
Accordingly, the inventor of the present application has determined that the reliability lifetime of the high-k gate insulating film and the ratio of the interface layer thickness to the total thickness of the high-k gate insulating film are T1 / (T1 + T2) (where T1 is the interface layer thickness). The correlation with the physical thickness (T2 is the physical thickness of the high-k layer) was examined using simulation. The result is shown in FIG. The simulation was performed by applying a trap generation model (JHStathis, Technical Digest of International Electron Device and Material (1998), p167.) To a high-k gate insulating film. Specifically, for the high-k gate insulating film, the leakage current J _g Leakage current J immediately after stress application ₀ , Defect generation rate per injected charge P _g (= Current increase ratio ΔJ at dielectric breakdown) _g / J ₀ ), And critical defect density N when it leads to dielectric breakdown _bd , And based on these values, the dielectric breakdown lifetime T in the high-k gate insulating film is obtained. _bd (= N _bd / P _g ) In the simulation, the ratio T1 / (T1 + T2) is changed while adjusting the physical thicknesses T1 and T2 so that the EOT of the high-k gate insulating film is always kept at 1.5 nm. The reliability lifetime of the high-k gate insulating film under a stress of 1 V applied voltage (temperature is room temperature) was calculated. However, in the simulation, the relative dielectric constant ε1 of the interface layer is fixed to a constant value of 3.9, whereas the relative dielectric constant ε2 of the high-k layer is 8.0, 12.0, 18.0. And multiple values of 24.0. Here, the relationship EOT = T1 + (ε1 / ε2) × T2 holds.
[0014]
As shown in FIG. 1, when the ratio T1 / (T1 + T2), that is, the ratio of the interface layer thickness to the total thickness of the high-k gate insulating film is 0.2 or less, the reliability of the high-k gate insulating film Can be kept high. Further, as the ratio T1 / (T1 + T2) increases, the reliability of the high-k gate insulating film tends to deteriorate. Furthermore, considering that the logarithmic scale is used for the vertical axis in FIG. 1, setting the ratio T1 / (T1 + T2) to 0.2 or less dramatically improves the reliability of the high-k gate insulating film. It turns out that it has the effect to make it. Specifically, by setting the ratio T1 / (T1 + T2) to 0.2 or less, for example, the reliability life is increased by three orders of magnitude or more compared to the case where the ratio T1 / (T1 + T2) is about 0.5. can do.
[0015]
Further, as shown in FIG. 1, in a gate insulating film having a structure where the ratio T1 / (T1 + T2) is 0.0 to 0.2, the high-k layer has a relative dielectric constant ε2 of 8.0 to 12.2. As the value increases to 0, the length of the reliability life increases, and in the range of ε2 from 12.0 to 18.0, the length of the reliability life is almost saturated and shows the maximum value. On the other hand, when ε2 increases from 18.0 to 24.0, the length of the reliability life decreases. Incidentally, in general, the value of the relative dielectric constant ε2 in the high-k layer changes in the thickness direction. Therefore, the average value of the relative dielectric constant ε2 in the high-k layer is ε2 _av Ε2 _av Is preferably 12.0 or more and 18.0 or less. When a silicate film containing one metal, silicon and oxygen is used as the high-k layer, the composition of the high-k layer is M _X Si _Y Assuming O (where M represents one metal and X> 0 and Y> 0), 12.0 ≦ ε2 described above _av The condition of ≦ 18.0 is equivalent to the condition of 0.20 ≦ Y / (X + Y) ≦ 0.30. That is, from the viewpoint of the reliability of the high-k gate insulating film, 0.20 ≦ Y / (X + Y) ≦ 0.30 rather than using a complete metal oxide containing no silicon as the material of the high-k layer. Silicon-containing silicate M satisfying the relationship _X Si _Y It is preferable to use O. The reason is considered to be that the electric field concentration on the interface layer is reduced by reducing the difference in relative dielectric constant between the high-k layer and the interface layer. The interface layer is also M _X Si _Y In some cases, silicate represented by O may be included, but Y / (X + Y) in this silicate is 0.90 or more, and compositionally SiO 2 ₂ Is almost equivalent.
[0016]
Further, the inventor of the present application has determined the reliability lifetime of the high-k gate insulating film and the total thickness (T1 + T2) of the high-k gate insulating film having the interface layer thickness T1 (where T2 is the physicality of the high-k layer). The correlation with the ratio to the thickness was determined experimentally. The result is shown in FIG. The interface layer used in the experiment has a composition of SiO. ₂ SiON film (relative permittivity ε1 = 3.9) close to, and the high-k layer used in the experiment is Si formed by CVD (chemical vapor deposition) method. _Three N _Four It is a film (relative dielectric constant ε2 = 7.5). In the experiment, the ratio T1 / (T1 + T2) was changed while adjusting the physical thicknesses T1 and T2 so that the EOT of the high-k gate insulating film always kept 3.0 nm. The total amount of charge injected into the insulating film before breakdown occurs under a stress of applied voltage 3.5 V (temperature is 100 ° C.) (total breakdown charge Q _bd ) Was measured. Here, the total dielectric breakdown Q _bd Corresponds to the reliability lifetime of the high-k gate insulating film.
[0017]
As shown in FIG. 2, when the ratio T1 / (T1 + T2) is 0.2 or less, the reliability of the high-k gate insulating film can be maintained high. On the other hand, when the ratio exceeds 0.3, the reliability increases rapidly. It was experimentally proved to deteriorate. In addition, considering that the logarithmic scale is used on the vertical axis in FIG. 2, setting the ratio T1 / (T1 + T2) to 0.2 or less dramatically improves the reliability of the high-k gate insulating film. It turns out that it has the effect to make it.
[0018]
As described above, from the results shown in FIGS. 1 and 2, from the viewpoint of the reliability of the high-k gate insulating film, the ratio of the interface layer thickness T1 to the total thickness (T1 + T2) is set to 0.3 or less. It is essential that the ratio T1 / (T1 + T2) is 0.2 or less.
[0019]
The present invention has been made based on the above knowledge. Specifically, the semiconductor device according to the present invention is premised on a semiconductor device having a high dielectric constant insulating film formed on a semiconductor substrate. The dielectric constant insulating film has an interface layer formed at the interface with the semiconductor substrate, and a high dielectric constant layer formed on the interface layer and having a higher relative dielectric constant than the interface layer, and the thickness of the interface layer T1 and the thickness T2 of the high dielectric constant layer satisfy the relationship of T1 / (T1 + T2) ≦ 0.3.
[0020]
According to the semiconductor device of the present invention, when the ratio of the interface layer thickness T1 to the total thickness (T1 + T2) in the high dielectric constant insulating film is set to 0.3 or less, the voltage is applied to the high dielectric constant insulating film. Also, the electric field concentration on the interface layer can be suppressed. Therefore, a high-k gate insulating film having a long reliability life can be realized by using such a high dielectric constant insulating film. At this time, since the interface layer having a low relative dielectric constant is thin and the high dielectric constant layer having a high relative dielectric constant is thick, the EOT of the high-k gate insulating film can be reduced.
[0021]
In the semiconductor device of the present invention, T1 and T2 preferably satisfy the relationship of T1 / (T1 + T2) ≦ 0.2.
[0022]
In this way, the reliability of the high dielectric constant insulating film can be further improved.
[0023]
In the semiconductor device of the present invention, the relative dielectric constant ε1 of the interface layer is 3.9 or more and 7.0 or less, and the relative dielectric constant ε2 of the high dielectric layer is larger than 7.0. Average value ε2 of relative permittivity ε2 _av Is preferably 12.0 or more and 18.0 or less.
[0024]
In this way, since the difference in relative dielectric constant between the high dielectric constant layer and the interface layer is limited within a predetermined range, the electric field concentration on the interface layer during voltage application is further relaxed, and the high dielectric constant The reliability of the insulating film can be further improved.
[0025]
In the semiconductor device of the present invention, the relative dielectric constant ε1 of the interface layer is 3.9 or more and 7.0 or less, and the relative dielectric constant ε2 of the high dielectric layer is larger than 7.0. , Which consists of a silicate containing one metal, silicon and oxygen, and the composition of the high dielectric constant layer is M _X Si _Y When O (where M represents one metal and X> 0 and Y> 0), X and Y satisfy the relationship of 0.20 ≦ Y / (X + Y) ≦ 0.30. Is preferred.
[0026]
In this way, the relative dielectric constant difference between the high dielectric constant layer and the interface layer is reduced compared to the case where a complete metal oxide not containing silicon is used as the material of the high dielectric constant layer. Electric field concentration on the interface layer during voltage application is further relaxed, and as a result, the reliability of the high dielectric constant insulating film can be further improved.
[0027]
In the semiconductor device of the present invention, the high dielectric constant layer is preferably made of silicate containing hafnium or zirconium, silicon, and oxygen.
[0028]
In this way, a high-k gate insulating film having a long reliability life can be reliably realized.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings.
[0030]
3A to 3E are cross-sectional views showing respective steps of the semiconductor device manufacturing method according to the present embodiment.
[0031]
As shown in FIG. 3A, for example, an element isolation insulating film 12 is formed on a Si (100) substrate 11, thereby forming a device region R. _D Is specified.
[0032]
Next, after sequentially performing standard RCA cleaning and diluted HF cleaning on the Si substrate 11, for example, NH _Three A heat treatment at about 600 to 700 ° C. is performed on the Si substrate 11 in a gas. As a result, as shown in FIG. _D A silicon nitride film (Si _Three N _Four Film) 13 is formed.
[0033]
Next, as shown in FIG. 3C, for example, the CVD method is used to form Si. _Three N _Four HfO on the film 13 ₂ A film 14 is formed. Specifically, Hf t-butoxide (C ₁₆ H ₃₆ HfO _Four ) N inside ₂ Bubbling is performed by blowing a carrier gas such as. As a result, the liquid Hf source is made into a gaseous state, the source gas is introduced into the reaction furnace together with the carrier gas, and HfO is used by using RT-CVD (Rapid Thermal CVD) treatment at a temperature of about 500 ° C. ₂ A film 14 is formed. At this time, HfO ₂ In order to improve the growth rate or film quality of the film 14, the dry O ₂ Gas is introduced into the reactor. HfO formed in this way ₂ When the composition analysis was performed on the film 14, Hf, O, C, and H were contained in the Hf source. ₂ The film 14 contained trace amounts of C and H of about 1 to 2 atomic% or less. In the reactor, N ₂ Gas is also introduced, but at temperatures around 500 ° C, N ₂ Since the gas is very inert, N ₂ The contribution of gas is very small.
[0034]
Next, for example, N ₂ In gas, HfO ₂ The film 14 is subjected to PDA treatment at about 600 to 800 ° C. for about 30 seconds. As a result, oxidation of the Si substrate 11 and HfO ₂ Desorption of hydrogen from the film 14, HfO ₂ Densification and microcrystallization of the film 14, and Si substrate 11 or Si _Three N _Four Film 13 and HfO ₂ Reaction such as interdiffusion of Si and Hf with the film 14 occurs. As a result, HfO ₂ Si is deposited on the Si substrate 11 at the beginning of deposition of the film 14 (see FIG. 3C). _Three N _Four A film 13 is formed and Si _Three N _Four HfO on the film 13 ₂ The structure in which the film 14 is formed finally has an interface layer 15 having a low relative dielectric constant formed on the Si substrate 11 and a high relative dielectric constant on the interface layer 15 as shown in FIG. The structure changes to the structure in which the high-k layer 16 is formed. Here, the interface layer 15 is made of SiO. ₂ Or SiO ₂ The high-k layer 16 is made of silicate close to the composition of HfO. ₂ Or HfO ₂ It consists of a silicate close to the composition. Further, the interface layer 15 and the high-k layer 16 each contain a small amount of N.
[0035]
Next, as shown in FIG. 3E, a gate electrode 17 made of, for example, polysilicon is formed on the high-k gate insulating film having a laminated structure of the interface layer 15 and the high-k layer 16. Specifically, SiH _Four After forming a polysilicon film at a deposition temperature of about 540 ° C. using, for example, 5 × 10 5 with respect to the polysilicon film ¹⁵ The gate electrode 17 is formed by implanting P ions at a dose of cm −2 and then patterning the ion-implanted polysilicon film. Thereby, the nMOSFET structure is completed. The activation annealing for the impurities implanted into the gate electrode 17 is performed by dry N ₂ This was performed by RTP (Rapid Thermal Process) in gas at 900 ° C. for 30 seconds.
[0036]
The feature of this embodiment is, for example, HfO ₂ Before the film 14 is formed, Si is deposited on the Si substrate 11. _Three N _Four By forming the film 13, or for example HfO ₂ The ratio of the thickness of the interface layer 15 to the total thickness of the high-k gate insulating film is set to a predetermined value by setting the PDA processing temperature for the film 14 lower or by setting the PDA processing time shorter. It is to set within the range. Specifically, the thickness T1 of the interface layer 15 with respect to the total thickness of the high-k gate insulating film, that is, the total thickness (T1 + T2) of the thickness T1 of the interface layer 15 and the thickness T2 of the high-k layer 16 Is set to 0.3 or less, more preferably 0.2 or less. Thereby, in this embodiment, since electric field concentration on the interface layer 15 can be suppressed even when a gate voltage is applied, a high-k gate insulating film having a long reliability life can be realized. Further, CV (capacitance-voltage) measurement is performed using a LCR (inductance-capacitance-resistance) meter for a MOS capacitor having a gate insulating film in which the interface layer 15 and the high-k layer 16 are laminated, When the EOT of the gate insulating film was calculated by a simulation program in consideration of the depletion of the gate electrode or the quantization effect of the substrate based on the measurement result, a sufficiently small EOT was obtained. That is, in the present embodiment, since the interface layer 15 having a low relative dielectric constant is thin and the high-k layer 16 having a high relative dielectric constant is thick, the EOT of the high-k gate insulating film can be reduced.
[0037]
FIG. 4A shows the semiconductor device of this embodiment, that is, HfO formed using an Hf precursor. ₂ 3 shows a high-resolution cross-sectional TEM (transmission electron microscope) image of a MOSFET provided with a gate insulating film whose dielectric is a high-k material. As shown in FIG. 4A, the total thickness of the high-k gate insulating film in the semiconductor device of this embodiment (the sum of the thickness T1 of the interface layer 15 and the thickness T2 of the high-k layer 16 (T1 + T2 )) Is about 3.0 to 3.3 nm. Further, the thickness T1 of the interface layer 15 is about 0.4 to 0.5 nm. That is, the ratio T1 / (T1 + T2) of the thickness of the interface layer 15 to the total thickness of the high-k gate insulating film is about 0.12 to 0.17, and the relationship recommended in the present invention: T1 / (T1 + T2) ≦ 0.3 (more preferably T1 / (T1 + T2) ≦ 0.2) is sufficiently satisfied.
[0038]
FIG. 4B shows a semiconductor device as a comparative example, that is, HfO formed by the same method as in this embodiment. ₂ The high-resolution cross-sectional TEM image of the other MOSFET provided with the gate insulating film which uses a dielectric as a high-k material is shown. As shown in FIG. 4B, in the semiconductor device of the comparative example, the interface layer 25 and the high-layer are formed on the Si substrate 21 so as to correspond to the MOS capacitor structure of this embodiment shown in FIG. A gate electrode 27 made of Poly-Si is formed through a gate insulating film having a laminated structure with the k layer 26. In the semiconductor device of the comparative example, the total thickness of the high-k gate insulating film (the total of the thickness T1 ′ of the interface layer 25 and the thickness T2 ′ of the high-k layer 26 (T1 ′ + T2 ′)) Is about 3.0 to 3.3 nm. Further, the thickness T1 ′ of the interface layer 25 is about 1.0 nm. That is, the ratio T1 ′ / (T1 ′ + T2 ′) of the thickness of the interface layer 25 to the total thickness of the high-k gate insulating film is about 0.30 to 0.33, and is the relationship recommended in the present invention. Does not meet.
[0039]
The gate area is 5000 μm for each of the MOS capacitor structure of the present embodiment shown in FIG. 4A and the MOS capacitor structure of the comparative example shown in FIG. ² As a result, the reliability life of the gate insulating film under a stress (temperature is room temperature) under an applied voltage of 3.0 V (the gate electrode side is low potential) was calculated. As a result, the reliability lifetime of the gate insulating film of this embodiment in which the relative thickness of the interface layer is small is 1 × 10. ^Four The reliability life of the gate insulating film of the comparative example in which the relative thickness of the interface layer is large is about 1 × 10 seconds. ² It was about a second. That is, when the ratio T1 / (T1 + T2) of the interface layer thickness to the total thickness of the high-k gate insulating film is 0.2 or less, the reliability life of the high-k gate insulating film is dramatically improved. . This is presumably because if the low dielectric constant interface layer formed on the surface of the Si substrate can be made thin, it is possible to avoid the occurrence of reliability degradation due to the strong electric field strength concentrated on the interface layer.
[0040]
Incidentally, as shown in FIGS. 4A and 4B, in the high-resolution cross-sectional TEM image of the high-k gate insulating film, the image of the interface layer is clearly white compared to the image of the high-k layer. Here, the composition of the high-k gate insulating film is Hf _X Si _Y If O (where X> 0, Y> 0), Y / (X + Y) = 0.90 corresponds to the boundary between the interface layer and the high-k layer. Note that the composition of the high-k gate insulating film changes so that the Si composition gradually decreases from the Si substrate side, in other words, the value of Y / (X + Y) gradually decreases from 1.0. That is, the range satisfying the relationship of 0.90 ≦ Y / (X + Y) ≦ 1.0 is the interface layer, and the range satisfying the relationship of Y / (X + Y) <0.90 is the high-k layer. At this time, the relative dielectric constant ε1 of the interface layer is not less than 3.9 and not more than 7.0, and the relative dielectric constant ε2 of the high-k layer is larger than 7.0.
[0041]
In the present embodiment, Si on the Si substrate 11 _Three N _Four HfO through membrane 13 ₂ After forming the film 14, HfO ₂ PDA treatment was performed on the film 14, thereby forming a high-k gate insulating film having a stacked structure of the interface layer 15 and the high-k layer 16. Such a portion (near the substrate, near the electrode, the center of the film, etc.) may be included. PDA processing conditions are not particularly limited, but the PDA processing temperature is preferably about 800 ° C. or lower, and the PDA processing temperature is preferably about 30 seconds or lower.
[0042]
In the present embodiment, HfO is used by using Hf t-butoxide which is a liquid Hf source. ₂ A film 14 was formed, but HfO ₂ The formation method of the film | membrane 14 is not specifically limited. Specifically, for example, Hf nitrato (Hf (NO _Three ) _Four ) Is heated to a liquid state and a carrier gas such as Ar is blown into the liquid raw material to perform bubbling, and then the reaction of a CVD apparatus having a substrate heater and a cold wall with the vaporized raw material together with the carrier gas. Introduced into the furnace and then HfO using RT-CVD process at a temperature of about 200 ° C ₂ The film 14 may be formed. At this time, HfO ₂ In order to improve the growth rate or film quality of the film 14, the dry O ₂ Gas is introduced into the reactor. HfO formed in this way ₂ When composition analysis is performed on the film 14, Hf, O, and N are contained in the Hf source. ₂ The film 14 contains a trace amount of N of about 1 to 2 atomic% or less. Ar gas is also introduced into the reactor, but Ar gas is very inactive at a temperature of about 200 ° C., so the contribution of Ar gas is very small.
[0043]
In this embodiment, HfO is used as a material for the high-k gate insulating film (that is, the high-k layer 16 therein). ₂ Was used. However, instead of this, other metal oxides, specifically, Zr oxide having the same properties as Hf (ZrO ₂ ), TiO ₂ , Ta ₂ O _Five , La ₂ O _Three Or Al ₂ O _Three Also, when the thickness T1 of the interface layer 15 and the thickness T2 of the high-k layer 16 are T1 / (T1 + T2) ≦ 0.3 (more preferably T1 / (T1 + T2) ≦ 0.2). As long as the relationship (1) is satisfied, the dramatic improvement effect similar to that of the present embodiment occurs in the reliability lifetime of the high-k gate insulating film. In particular, the relative dielectric constant ε1 of the interface layer is 3.9 or more and 7.0 or less, and the relative dielectric constant ε2 of the high-k layer 16 is larger than 7.0. Average value of dielectric constant ε2 ε2 _av Is 12.0 or more and 18.0 or less, the following special effects can be obtained. That is, since the relative dielectric constant difference between the high-k layer 16 and the interface layer 15 is limited within a predetermined range, the electric field concentration on the interface layer 15 during voltage application is further relaxed, and the high-k layer The reliability of the gate insulating film can be further improved.
[0044]
In the present embodiment, the composition of the high-k gate insulating film (that is, the high-k layer 16 therein) is M. _X Si _Y A metal silicate represented by O (where M represents one metal and X> 0 and Y> 0) (may contain elements other than metal, silicon and oxygen), for example, Hf silicate (Hf _X Si _Y O ₂ ) Or Zr silicate (Zr _X Si _Y O ₂ ), Etc., as long as the relationship of ratio T1 / (T1 + T2) ≦ 0.3 (preferably the relationship of T1 / (T1 + T2) ≦ 0.2) is satisfied, the reliability lifetime of the high-k gate insulating film The same dramatic improvement effect as in the present embodiment occurs. In particular, the relative dielectric constant ε1 of the interface layer is 3.9 or more and 7.0 or less, the relative dielectric constant ε2 of the high-k layer 16 is larger than 7.0, and the high-k layer 16 is 0. Metal silicate M satisfying the relationship of 20 ≦ Y / (X + Y) ≦ 0.30 _X Si _Y When it is O, the following special effects are obtained. That is, the relative dielectric constant difference between the high-k layer 16 and the interface layer 15 is smaller than when a complete metal oxide not containing silicon is used. As a result, the reliability of the high-k gate insulating film can be further improved.
[0045]
By the way, HfO of this embodiment ₂ When, for example, an Hf silicate film is formed instead of the film 14, the following method can be used. That is, Hf t-butoxide (C ₁₆ H ₃₆ HfO _Four ) And Si source TDEAS (Tetrakis Diethyl Amino Silicon: Si [N (C ₂ H _Five ) ₂ ] _Four ) And N as the carrier gas ₂ After being introduced into the reaction furnace together with the gas, a Hf silicate film can be formed by performing a CVD process at a temperature of about 300 to 500 ° C. At this time, the composition of the Hf silicate film can be changed by adjusting the mixing ratio of the Hf source and the Si source or the temperature of the CVD process. Further, in order to improve the growth rate or film quality of the Hf silicate film, dry O ₂ Gas may be introduced into the reactor.
[0046]
In the present embodiment, the Si substrate 11 is used as the substrate, but instead of this, another semiconductor substrate such as a SiGe substrate or a SiC substrate may be used.
[0047]
In the present embodiment, a Poly-Si gate electrode is used as the gate electrode 17, but a metal gate electrode may be used instead. Specifically, a metal gate electrode having a laminated structure of a TiN film and an Al film or a single layer structure of a TaN film may be formed by using, for example, PVD (physical vapor deposition) by Ar sputtering.
[0048]
【The invention's effect】
According to the present invention, the ratio of the interface layer thickness T1 to the total thickness (T1 + T2) in the high-k gate insulating film is 0.3 or less, more preferably 0.2 or less. Therefore, the reliability life of the high-k gate insulating film can be improved.
[Brief description of the drawings]
FIG. 1 shows the reliability lifetime of a high-k gate insulating film and the total thickness of the high-k gate insulating film having an interface layer thickness T1 (T1 + T2) (where T2 is the physical thickness of the high-k layer) It is a figure which shows the result of having investigated the correlation with the ratio with respect to) using simulation.
FIG. 2 shows the reliability lifetime of the high-k gate insulating film and the total thickness of the high-k gate insulating film having the interface layer thickness T1 (T1 + T2) (where T2 is the physical thickness of the high-k layer) It is a figure which shows the result of having investigated the correlation with ratio to) by experiment.
FIGS. 3A to 3E are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIGS.
4A is a diagram showing a high-resolution cross-sectional TEM image of a semiconductor device according to an embodiment of the present invention, and FIG. 4B is a diagram showing a high-resolution cross-sectional TEM image of a semiconductor device according to a comparative example. is there.
FIG. 5 is a cross-sectional view of a conventional semiconductor device.
[Explanation of symbols]
11 Si substrate
12 Insulating film for element isolation
13 Si _Three N _Four film
14 HfO ₂ film
15 Interface layer
16 high-k layers
17 Gate electrode
21 Si substrate
25 Interface layer
26 high-k layer
27 Gate electrode
R _D Device area

Claims

A semiconductor device having a high dielectric constant insulating film formed on a semiconductor substrate,
The high dielectric constant insulating film is
An interface layer formed at the interface with the semiconductor substrate;
A high dielectric constant layer formed on the interface layer and having a relative dielectric constant higher than that of the interface layer;
The interface layer thickness T1 and the high dielectric constant layer thickness T2 are:
Meet the relationship of T1 / (T1 + T2) ≦ 0.3,
The relative dielectric constant ε1 of the interface layer is 3.9 or more and 7.0 or less, and the relative dielectric constant ε2 of the high dielectric layer is larger than 7.0.
The high dielectric constant layer is made of a silicate containing a first metal, silicon, and oxygen,
When the composition of the high dielectric constant layer is M _X Si _Y O (where M represents the first metal and X> 0, Y> 0),
X and Y are
A semiconductor device characterized by satisfying a relationship of 0.20 ≦ Y / (X + Y) ≦ 0.30 .

2. The semiconductor device according to claim 1, wherein a relative dielectric constant ε <b> 2 of the high dielectric constant layer is greater than 7.0 and 18.0 or less.

The semiconductor device according to claim 2, wherein a relative dielectric constant ε2 of the high dielectric constant layer is 12.0 or more and 18.0 or less.

The semiconductor device according to claim 1, wherein the first metal is Hf or Zr.

The semiconductor device according to claim 1, wherein the first metal is Ti, Ta, La, or Al.

T1 and T2 are
T1 / (T1 + T2) The semiconductor device according to any one of claims 1-5 characterized by satisfying the relation of ≦ 0.2.

The semiconductor device according to claim 1, wherein the interface layer contains nitrogen.

The semiconductor device according to claim 7, wherein the nitrogen concentration in the interface layer is 4/7 or less in terms of atomic ratio.

The semiconductor device according to claim 1, wherein the high dielectric constant layer contains carbon and hydrogen.

The semiconductor device according to claim 9, wherein the carbon and hydrogen concentrations in the high dielectric constant layer are 2 atomic% or less.

SiO of the high dielectric constant layer _{2 2} 11. The semiconductor device according to claim 1, wherein the converted film thickness is about 3.0 nm.

SiO of the high dielectric constant layer _{2 2} 11. The semiconductor device according to claim 1, wherein the converted film thickness is 3.0 nm or less.

SiO of the high dielectric constant layer _{2 2} The semiconductor device according to claim 12, wherein the converted film thickness is 1.5 nm or more and 3.0 nm or less.

SiO of the high dielectric constant layer _{2 2} 13. The semiconductor device according to claim 12, wherein the converted film thickness is about 1.5 nm.

SiO of the high dielectric constant layer _{2 2} 13. The semiconductor device according to claim 12, wherein the converted film thickness is less than 1.5 nm.

The semiconductor device according to claim 1, wherein the high dielectric constant insulating film has a thickness of 3.3 nm or less.

The semiconductor device according to claim 16, wherein a thickness of the high dielectric constant insulating film is not less than 3.0 nm and not more than 3.3 nm.

The semiconductor device according to claim 16, wherein a thickness of the high dielectric constant insulating film is 3.0 nm or less.

The semiconductor device according to claim 1, further comprising a gate electrode containing polysilicon on the high dielectric constant insulating film.

The semiconductor device according to claim 1, further comprising a metal gate electrode on the high dielectric constant insulating film.

21. The semiconductor device according to claim 20, wherein the metal gate electrode includes at least one of Ti, Al, or Ta.

21. The semiconductor device according to claim 20, wherein the metal gate electrode includes TiN.

21. The semiconductor device according to claim 20, wherein the metal gate electrode contains TaN.

The semiconductor device according to claim 1, wherein the semiconductor substrate is a Si substrate.

The semiconductor device according to claim 1, wherein the semiconductor substrate is a SiC substrate.

The semiconductor device according to claim 1, wherein the semiconductor substrate contains Ge.

27. The semiconductor device according to claim 26, wherein the semiconductor substrate is a SiGe substrate.

27. The semiconductor device according to claim 1, wherein the high dielectric constant layer has a crystallized portion and a crystal grain boundary.