JP4499374B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, an oxide film equivalent thickness (EOT: Equivalent Oxide Thickness) due to formation of a low dielectric constant oxide at an interface between a high dielectric constant insulating film and a semiconductor substrate. The present invention relates to a semiconductor device characterized by a configuration for suppressing an increase and a manufacturing method thereof.
[0002]
[Prior art]
In recent years, with the progress of miniaturization of MOSFETs accompanying the development of integrated circuit technology, high dielectric constants (High-k) such as HfO ₂ , ZrO ₂ , silicates or aluminates thereof, and Al ₂ O ₃ as gate insulating films. ) Attempts have been made to adopt a film (for example, see Non-Patent Documents 1 to 3).
[0003]
Here, an example of a conventional MOS type semiconductor device using a high dielectric constant gate insulating film will be described with reference to FIG.
FIG. 5 is a schematic cross-sectional view of a main part of a conventional MOS type semiconductor device using a high dielectric constant gate insulating film. First, a p-type well region 32 is formed in a predetermined region of an n-type silicon substrate 31. At the same time, the element isolation oxide film 33 is formed by selectively oxidizing the n-type silicon substrate 31, and then Hf (t-OC ₄ H ₉ ) ₄ , Al (t-C ₄ ) is used by metal organic vapor phase epitaxy. A gate insulating film 34 made of Hf ₈₀ Al ₂₀ O _{y is} formed in the element formation region in an oxidizing atmosphere in which H ₉ ) ₃ and O ₂ are flowed.
[0004]
Next, a gate electrode 35 made of polycrystalline silicon is formed, and n ⁺ type source / drain regions 36 are formed by implanting ions such as As using the gate electrode 35 as a mask, and then a low-temperature oxide film (LTO) is formed on the entire surface. ), And then, contact holes reaching the n ⁺ -type source / drain regions 36 are formed in the interlayer insulating film 37, and the contact holes are filled with W to form W plugs 38. The basic structure of the MOSFET is completed.
[0005]
Since the relative dielectric constant of Hf ₈₀ Al ₂₀ O _y constituting the gate insulating film 34 is about 27, for example, even when the gate insulating film 34 is deposited to 2 nm, the equivalent oxide thickness EOT is SiO _2. Since this is the equivalent film thickness when converted to a film, if the relative dielectric constant of SiO ₂ is about 3.9,
EOT≈2 × 3.9 / 27≈0.2888≈0.3 [nm]
It becomes.
[0006]
Therefore, by using such a high dielectric constant film, it is possible to configure a fine MOSFET having a gate insulating film having an equivalent oxide film thickness EOT that exceeds the limit of a normal film formation technique.
[0007]
[Non-Patent Document 1]
IEDM2001 Technical Digest, No. 20.3, pp. 459-462, 2001
[Non-Patent Document 2]
IEDM2002 Technical Digest, No. 34.1, pp. 849-852, 2002
[Non-Patent Document 3]
2002 Symposium on VLSI Technology Digest of Technical Paper, No. 15.1, 2002
[0008]
[Problems to be solved by the invention]
However, when the above-described high dielectric constant film (High-k film) is used as the gate insulating film, there is a problem that a SiO ₂ film having a low dielectric constant is formed at the interface with the silicon substrate. The situation will be described with reference to FIG.
[0009]
FIG. 6 is an explanatory view of a problem in a conventional MOS type semiconductor device using a high dielectric constant gate insulating film. The film thickness is about 1 nm at the interface between the p-type well region 32 and the gate insulating film 34. The SiO ₂ film 39 is formed.
[0010]
This is because the chemical oxide film remains on the surface of the p-type well region 32 immediately before the formation of the gate insulating film 34, and when the film is formed in an oxidizing atmosphere, further, the activation of the implanted ions is performed. It is considered that O ₂ and the surface of the p-type well region 32 react to form the SiO ₂ film 39 in the subsequent heat treatment step such as.
[0011]
The presence of such a SiO ₂ film 39 causes an increase in EOT and becomes an obstacle to miniaturization of the MOS transistor.
Incidentally, as described above, when the SiO ₂ film 39 is formed with a thickness of 1 nm, the EOT is as follows:
EOT = EOT _HfAlO + EOT _SiO2
≒ 2x3.9 / 27 + 1 ≒ 1.2888 ≒ 1.3 [nm]
It becomes.
[0012]
Therefore, an object of the present invention is to prevent the formation of a low dielectric constant oxide film at the interface between a high dielectric constant insulating film and a semiconductor substrate and suppress an increase in EOT.
[0013]
[Means for Solving the Problems]
FIG. 1 is an explanatory diagram of the principle configuration of the present invention. Here, means for solving the problems in the present invention will be described with reference to FIG.
In order to achieve the above object, according to the present invention, in the semiconductor device, as the gate insulating film 3, nitrogen and metal composed of any one of HfON, HfSiON, AlON, and AlSiON from the semiconductor substrate 1 side are used. The included first high dielectric constant film 4 and the first high dielectric constant film 4 have different compositions from Hf _x Al _1-x O _y N _z (where 0 ≦ x ≦ 1, y> 0, z ≧ 0) or _{Hf x Al 1-x Si w} O y N z ( where a 0 ≦ x ≦ 1, y> 0, z ≧ 0, w> 0) a second high dielectric constant film 5 consisting of either It has an insulated gate transistor using a two-layer insulating film in which only two layers are stacked.
[0014]
In this way, by providing the first high dielectric constant film 4 containing nitrogen and metal so as to be in contact with the element formation region 2, the formation of the SiO ₂ film can be prevented, and the nitrogen and metal can be removed. Since the included first high dielectric constant film 4 has a higher dielectric constant than the SiO ₂ film, it is possible to suppress an increase in EOT.
[0015]
In particular, since any one of HfON, HfSiON, AlON, and AlSiON is used as the first high dielectric constant film 4 containing nitrogen and metal, an increase in EOT can be reduced.
When the gate electrode 6 is made of other than polycrystalline silicon, ZrON or ZrSiON may be used.
[0016]
Further, as the second high dielectric constant film _{5, Hf x Al 1-x} O y N z ( where, 0 ≦ x ≦ 1, y > 0, z ≧ 0) or _{Hf x Al 1-x Si w} O A high dielectric constant film having a relative dielectric constant of 20 or more of _y N _z (where 0 ≦ x ≦ 1, y> 0, z ≧ 0, w> 0) is used.
[0017]
When manufacturing the above-described semiconductor device, after forming a metal nitride film made of any of HfN, HfSiN, AlN, and AlSiN on at least the exposed surface of the element formation region 2, the metal nitride film On top, Hf _x Al _1-x O _y N _z (where 0 ≦ x ≦ 1, y> 0, z ≧ 0) or Hf _x Al _1-x Si _w O _y N _z ( However, a high dielectric constant film of any one of 0 ≦ x ≦ 1, y> 0, z ≧ 0, and w> 0 may be formed.
[0018]
In this case, after the metal nitride film is formed, it is desirable to form the high dielectric constant film without exposing the semiconductor substrate 1 to the atmosphere, that is, in-situ, thereby undesired SiO ₂ film. The formation of a low dielectric constant film such as can be prevented.
[0019]
Further, it is desirable to heat-treat the metal nitride film in an oxidizing atmosphere after forming the metal nitride film and before forming the high dielectric constant film.
That is, since the metal nitride film is generally conductive, the metal nitride film is changed to a metal oxynitride film such as HfON by heat treatment in an oxidizing atmosphere, and has an insulating property.
[0020]
Alternatively, it is desirable to perform heat treatment in an oxidizing atmosphere and film formation of a high dielectric constant film without exposing the substrate 1 to the air after the metal nitride film is formed.
Also in this case, the high dielectric constant film can be formed after the metal nitride film is reliably insulated without forming an undesired low dielectric constant film such as a SiO ₂ film.
[0021]
When the gate electrode 6 is made of other than polycrystalline silicon, ZrN or ZrSiN may be used.
[0023]
Further, SiH ₂ [NH (t-C ₄ H ₉ )] ₂ (BTBASi: Bis TertiaryButylAminoSilane) or NH ₃ is used as the N source in at least one step of forming the metal nitride film or the high dielectric constant film. Is desirable.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Here, with reference to FIG. 2 thru | or FIG. 4, the manufacturing process of the insulated gate semiconductor device of embodiment of this invention is demonstrated.
2A. First, after forming a p-type well region 12 in a predetermined region of the n-type silicon substrate 11, a SiN film is formed on the surface of the n-type silicon substrate 11 via a pad oxide film 13, and this SiN The film is patterned into a shape corresponding to the element formation region to form the SiN film pattern 14.
[0025]
Next, referring to FIG. 2B, element isolation oxide film 15 is formed by performing thermal oxidation in an oxidizing atmosphere using SiN film pattern 14 as an oxidation resistant mask.
[0026]
Next, after removing the SiN film pattern 14, the pad oxide film 13 is removed to expose the surface of the element formation region by processing with dilute HF.
[0027]
Next, see FIG. 3D. Next, Hf [N (CH ₃ ) ₂ ] ₄ (Tetrakis dimethylamino hafnium) as an Hf source and NH ₃ as an N source are allowed to flow under a pressure of 65 Pa using metal organic vapor phase epitaxy. Thus, the HfN film 16 having a thickness of, for example, 1 nm is formed on the entire surface at 500 ° C.
[0028]
Next, referring to FIG. 3 (e), Hf (t-OC ₄ H ₉ ) ₄ (Tetra tertiary buty hafnium), Al source as an Hf source using metalorganic vapor phase epitaxy without exposing the substrate to the atmosphere. Al (t-C ₄ H ₉ ) ₃ (Tri tert butyl aluminum) and O ₂ are flown as Hf ₈₀ Al ₂₀ O _y with a thickness of, for example, 2 nm at 500 ° C. under a pressure of 65 Pa. A film 18 is formed.
In this film forming process, the conductive HfN film 16 is oxidized to form an insulating HfON film 17.
[0029]
Next, for example, by applying RTA (Rapid Thermal Anneal) for 30 seconds at 800 ° C., the gate insulating film 19 having a two-layer structure including the Hf ₈₀ Al ₂₀ O _y film 18 and the HfON film 17 is obtained.
[0030]
Next, after depositing a polycrystalline silicon film on the entire surface, the gate electrode 20 is formed by etching the polycrystalline silicon film together with the gate insulating film 19 so that the gate length becomes 350 nm, for example.
[0031]
Next, referring to FIG. 4G, As ions 21 are implanted by using the gate electrode 20 as a mask to form n ⁺ -type source / drain regions 22.
[0032]
Next, after an interlayer insulating film 23 made of a low temperature oxide film (LTO) film is deposited on the entire surface, contact holes 24 reaching the n ⁺ type source / drain regions 22 are formed in the interlayer insulating film 23. .
[0033]
Next, referring to FIG. 4I, an Al film is deposited on the entire surface to fill the contact hole 24, followed by patterning to form a metal wiring 25, thereby completing the basic configuration of the insulated gate semiconductor device.
[0034]
When COT measurement of this insulated gate type semiconductor device was performed and EOT was measured, EOT _tot = 0.8 nm.
In this case, the EOT of the 2 nm Hf ₈₀ Al ₂₀ O _y film 18, that is, EOT _HfAlO is about 0.3 nm, and the EOT of the 1 nm HfON film 17, ie, EOT _HfON, has a dielectric constant of HfON of about 8. Then
EOT _HfON = 1 × 3.9 / 8 = 0.4875≈0.5
And therefore
EOT _HfAlO + EOT _HfON ≒ 0.3 + 0.5 = 0.8 = EOT _tot
Thus, a result consistent with the fact that the HfON film 17 is formed at the interface was obtained.
[0035]
Thus, in the embodiment of the present invention, since the HfN film 16 having excellent oxidation resistance is provided under the Hf ₈₀ Al ₂₀ O _y film 18, the step of converting the HfN film 16 into the HfON film 17. However, since a low dielectric constant SiO ₂ film is not formed at the interface with the p-type well region 12, an increase in EOT can be suppressed, thereby increasing the dielectric constant of the interface layer. It is possible to realize a highly integrated semiconductor integrated circuit device composed of various insulated gate transistors.
[0036]
Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various modifications can be made.
For example, in the above embodiment, when the HfN film to be the base is formed, Hf [N (CH ₃ ) ₂ ] ₄ is used as the Hf source and NH ₃ is used as the N source. As a source, SiH ₂ [NH (t-C ₄ H ₉ )] ₂ may be used. In this case, since Si derived from the N source is slightly mixed, an HfSiN film is formed.
[0037]
In addition, the substrate is not limited to HfN or HfSiN as a base, and AlN or AlSiN may be used. In that case, Al (t-C ₄ H ₉ ) ₃ or Al (C ₂ H ₅ ) ₃ (Tri eftyluminum) may be used, and NH ₃ or SiH ₂ [NH (t-C ₄ H ₉ )] ₂ may be used as the N source.
[0038]
When the conductive material constituting the gate electrode is a material other than polycrystalline silicon, for example, a metal gate such as W, ZrN or ZrSiN may be used as a high dielectric constant film as a base.
[0039]
In the above embodiment, when forming the HfAlO _y film, Hf (t—OC ₄ H ₉ ) ₄ as the Hf source, Al (t—C ₄ H ₉ ) ₃ as the Al source, and Although O ₂ is used as the oxygen source, when Hf (t-OC ₄ H ₉ ) ₄ is used as the Hf source, Al (C ₂ H ₅ ) ₃ is used as the Al source, and as the oxygen source. O ₃ may be used.
[0040]
Further, Hf [N (CH ₃ ) ₂ ] ₄ may be used as the Hf source, in which case Al (t-C ₄ H ₉ ) ₃ as the Al source and O ₂ or O ₃ as the oxygen source. May be used.
[0041]
In addition, the composition ratio of Hf and Al is arbitrary, and when Al increases, the dielectric constant decreases. However, since thermal stability is improved and polycrystallization is difficult, leakage current through the grain boundary is less likely to flow. In addition, penetration of the dopant contained in the gate electrode can be prevented.
[0042]
The high dielectric constant film is not limited to _{Hf x Al 1-x O y} , those may be used _{Hf x Al 1-x O y} N z.
Thus, by including N, polycrystallization of the gate insulating film in the heat treatment step can be suppressed.
[0043]
In this case, for example, Hf [N (CH ₃ ) ₂ ] ₄ as the Hf source, Al (t-C ₄ H ₉ ) ₃ as the Al source, NH ₃ as the N source, and O ₂ or O as the oxygen source. ₃ may be used.
[0044]
Alternatively, Hf (t-OC ₄ H ₉ ) ₄ as the Hf source, Al (t-C ₄ H ₉ ) ₃ or Al (C ₂ H ₅ ) _{3 as the} Al source, and SiH ₂ [NH (t-C ₄ H ₉ )] ₂ , and O ₂ or O ₃ may be used as the oxygen source.
Also in this case, since Si derived from the N source is slightly mixed, an Hf _x Al _1-x Si _w O _y N _z film is obtained.
[0045]
In the above embodiment, the HfN film is oxidized in the process of forming the Hf _x Al _1-x O _y film to lose the conductivity. However, after the HfN film or the HfSiN film is formed, the in− It may be oxidized by heat treatment in situ in an oxidizing atmosphere.
[0046]
In the above embodiment, element isolation is performed using the LOCOS (selective oxidation) method. However, the present invention is not limited to the selective oxidation method, and other element isolation methods such as STI may be used. Is.
[0047]
In the above embodiment, a silicon substrate is used as the substrate. However, the substrate is not limited to a silicon substrate, and a SiGe substrate may be used, thereby enabling higher speed operation. An integrated semiconductor integrated circuit device can be realized.
[0048]
In the above-described embodiment, a single n-channel IGFET is shown, but it goes without saying that a CMOS may be configured in combination with a p-channel IGFET.
[0049]
In the above embodiment, an example in which a high dielectric constant film is used as a gate insulating film is shown. However, the high dielectric constant film of the two-layer structure of the present invention is not limited to a gate insulating film, The conductive region provided on the semiconductor substrate may be used as a dielectric film in the case of forming a capacitive element using one electrode.
[0050]
The detailed features of the present invention will now be described with reference to FIG. 1 again.
See FIG. 1 again. (Supplementary Note 1) As gate insulating film 3, from the semiconductor substrate 1 side, a first high dielectric constant film containing nitrogen and metal made of any one of HfON, HfSiON, AlON, and AlSiON. 4 and Hf _x Al _1-x O _y N _z (where 0 ≦ x ≦ 1, y> 0, z ≧ 0) or Hf _x Al ₁₋ Insulation using an insulating film in which a second high dielectric constant film 5 made of _x Si _w O _y N _z (where 0 ≦ x ≦ 1, y> 0, z ≧ 0, w> 0) is laminated. A semiconductor device including a gate transistor.
(Supplementary Note 2) After forming a metal nitride film made of any of HfN, HfSiN, AlN, and AlSiN on at least the exposed surface of the element formation region 2, the metal nitride film and the composition are formed on the metal nitride film. Hf _x Al _1-x O _y N _z (where 0 ≦ x ≦ 1, y> 0, z ≧ 0) or Hf _x Al _1-x Si _w O _y N _z (where 0 ≦ x ≦ 1) , Y> 0, z ≧ 0, w> 0). A method for manufacturing a semiconductor device, comprising the step of forming a high dielectric constant film.
(Supplementary note 3) The method for manufacturing a semiconductor device according to supplementary note 2, wherein the high dielectric constant film is formed without exposing the semiconductor substrate 1 to the atmosphere after the metal nitride film is formed.
(Supplementary note 4) The semiconductor device according to Supplementary note 2, wherein the metal nitride film is heat-treated in an oxidizing atmosphere after the metal nitride film is formed and before the high dielectric constant film is formed. Method. (Supplementary note 5) The semiconductor according to supplementary note 4, wherein after the formation of the metal nitride film, a heat treatment in an oxidizing atmosphere and the formation of the high dielectric constant film are performed without exposing the semiconductor substrate 1 to the atmosphere. Device manufacturing method.
(Supplementary Note 6) SiH ₂ [NH (t-C ₄ H ₉ )] ₂ is used as an N source in at least one step of forming the metal nitride film or the high dielectric constant film. The method for manufacturing a semiconductor device according to any one of appendices 2 to 5.
(Supplementary note 7) The semiconductor according to any one of supplementary notes 2 to 5, wherein NH ₃ is used as an N source in at least one step of forming the metal nitride film or the high dielectric constant film. Device manufacturing method.
[0051]
【The invention's effect】
According to the present invention, since the metal nitride film is formed before the high dielectric constant oxynitride film is formed, a low dielectric constant SiO ₂ film can be formed at the semiconductor substrate interface, so that EOT can be kept small. Thus, it is possible to form a gate insulating film, which greatly contributes to the realization of a highly integrated semiconductor integrated circuit device composed of a fine insulated gate transistor having excellent characteristics.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a basic configuration of the present invention.
FIG. 2 is an explanatory diagram of a manufacturing process until halfway through the insulated gate semiconductor device according to the embodiment of the present invention;
FIG. 3 is an explanatory diagram of the manufacturing process of the insulated gate semiconductor device according to the embodiment of the present invention until halfway through FIG. 2;
FIG. 4 is an explanatory diagram of the manufacturing process of the insulated gate semiconductor device according to the embodiment of the present invention after FIG. 3;
FIG. 5 is a schematic cross-sectional view of a conventional MOS type semiconductor device using a high dielectric constant gate film.
FIG. 6 is an explanatory diagram of a problem in a MOS semiconductor device using a conventional high dielectric constant gate film.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element formation area 3 Gate insulating film 4 First high dielectric constant film 5 Second high dielectric constant film 6 Gate electrode 11 n-type silicon substrate 12 p-type well region 13 pad oxide film 14 SiN film pattern 15 element Isolation oxide film 16 HfN film 17 HfON film 18 Hf ₈₀ Al ₂₀ O _y film 19 Gate insulating film 20 Gate electrode 21 As ion 22 n ⁺ source / drain region 23 Interlayer insulating film 24 Contact hole 25 Metal wiring 31 N-type silicon substrate 32 p-type well region 33 element isolation oxide film 34 gate insulating film 35 gate electrode 36 n ⁺ type source / drain region 37 interlayer insulating film 38 W plug 39 SiO ₂ film

Claims (3)

As the gate insulating film, from the semiconductor substrate side, a first high dielectric constant film containing nitrogen and metal made of any one of HfON, HfSiON, AlON, and AlSiON, and the first high dielectric constant film, Hf _x Al _1-x O _y N _z (where 0 ≦ x ≦ 1, y> 0, z ≧ 0) or Hf _x Al _1-x Si _w O _y N _z (where 0 ≦ x ≦ 1, y> 0, z ≧ 0, w> 0), and having an insulated gate transistor using a two-layer insulating film laminated only with a second high dielectric constant film. Semiconductor device. After forming a metal nitride film made of any of HfN, HfSiN, AlN, and AlSiN on at least the exposed surface of the element formation region, Hf _x Al having a composition different from that of the metal nitride film is formed on the metal nitride film _1-x O _y N _z (where 0 ≦ x ≦ 1, y> 0, z ≧ 0) or Hf _x Al _1-x Si _w O _y N _z (where 0 ≦ x ≦ 1, y> 0, A method of manufacturing a semiconductor device, comprising the step of forming a high dielectric constant film comprising any one of z ≧ 0 and w> 0).   3. The method of manufacturing a semiconductor device according to claim 2, wherein after the metal nitride film is formed, heat treatment in an oxidizing atmosphere and film formation of the high dielectric constant film are performed without exposing the substrate to the atmosphere.

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