WO2004073072A1

WO2004073072A1 - Mis semiconductor device and method for manufacturing mis semiconductor device

Info

Publication number: WO2004073072A1
Application number: PCT/JP2004/001408
Authority: WO
Inventors: Noriyuki Miyata; Manisha Kundu
Original assignee: National Institute Of Advanced Industrial Science And Technology
Priority date: 2003-02-17
Filing date: 2004-02-10
Publication date: 2004-08-26
Also published as: JPWO2004073072A1

Abstract

For preventing growth of a low dielectric constant film (a silicon oxide film) arranged between a substrate (1) and a high dielectric constant film (3) in a MOSFET wherein the high dielectric constant film is used as a gate insulating film, a heat treatment for modifying film properties of the high dielectric constant film (3) is conducted after forming the high dielectric constant film (3) and a diffusion barrier layer (4) on the substrate (1). A gate electrode material film is then deposited and a gate electrode (6) is formed by patterning this gate electrode material film. During this etching step, the lateral faces of the high dielectric constant film (3) are exposed to plasma and thus suffers injection of charges and other damages. For discharging the charges and restoring the damages, a heat treatment is conducted while covering the entire surface including the gate portion with a diffusion barrier layer (8). An impurity diffusion layer to be a source/drain region is then formed.

Description

^ Statement

TECHNICAL FIELD The present invention relates to a MIS type semiconductor device and a method of manufacturing the MIS type semiconductor device.

The present invention relates to a MIS type semiconductor device and a method of manufacturing the MIS type semiconductor device, and more particularly to an electrode Z used for a miniaturized MIS type semiconductor device. And technology for forming the Background art

S i0 ₂ has been widely used as MI S (Metal Insulator Semiconductor) type semiconductor device of the insulating film (gate insulating film) material. However, as semiconductor devices become finer and denser and the gate insulating film becomes thinner to 3 nm or less in accordance with the scaling law,

-Tunneling occurs directly between the gate electrode and the silicon substrate, increasing power consumption and reducing device reliability. Therefore, Ri by that the dielectric constant to form a high dielectric constant gate insulating film with a large metal oxide S i 0 ₂ yo Ri dielectric constant of 3.9, the equivalent oxide thickness EOT (equivalent Oxide A method of increasing the physical film thickness without increasing the thickness) is being studied. Materials that have been or are being considered for use as the material of the high dielectric constant insulating film include Hf 0 ₂ (relative permittivity £ Γ: 25) r Z r 02 (£ r: 25), L n _{_{2 0 3 (£ r: 8~}} 30) (L n: the run evening Neu _{_{de), Ta 2 0 3 (£}} r: 26), T i 0 2 (£ r: 80) , and the like (e.g., patent See references 1 and 2).

7A to 7D are cross-sectional views in the order of steps showing a conventional method for manufacturing a MIS transistor having a high dielectric constant gate insulating film. Consisting of S I_〇 ₂ very thin on the silicon substrate 1 to form a low dielectric constant interlayer 2 made of Hf 0 ₂ thereon high dielectric constant film 3 Sno Uz evening, vapor deposition, CVD (Chemical Vapor It is formed by using a deposition on factory method, ALD (atomic layer deposition) method (FIG. 7A). Next, heat treatment is performed in an inert atmosphere for the purpose of improving film quality such as reduction of defects in the high dielectric constant film 3. Then, polysilicon or the like is deposited on the high dielectric constant film 3 to form a gate electrode material film 6a (FIG. 7B). Next, by applying photolithography and RIE (reactive ion etching), the gate electrode material film 6a, the high dielectric constant film 3, and the low dielectric constant The intermediate layer 2 is patterned to form a gate portion having a gate electrode 6 on the gate insulating film 7 (FIG. 7C). At this time, when the side surface of the high dielectric constant film 3 is exposed to the plasma, defects are introduced or electric charges are accumulated in the high dielectric constant film. Since these defects and accumulated charges change the threshold voltage of the transistor, heat treatment is performed after the gate section to repair defects and release accumulated charges. Next, ion implantation is performed using the gate portion as a mask, and heat treatment for activating the implanted impurities is performed to form an impurity diffusion layer 9 serving as a source / drain region on both sides of the gate portion [7th D Figure].

[Patent Document 1] Japanese Unexamined Patent Application Publication No. 2000-2202

[Patent Document 2] Japanese Patent Application Laid-Open Publication No. 2000-334430

In the heat treatment after the formation of the high dielectric constant film 3 during the above-described manufacturing process, as shown in FIG. 8, the oxidizing species 5 such as O ₂ and H ₂₀ remaining in the processing atmosphere are high. The low dielectric constant intermediate layer 2 is grown by diffusing in the dielectric constant film 3 as indicated by the arrow and reaching the interface between the high dielectric constant film and the silicon substrate. The growth of this low-k layer hinders low EOT. In addition, since the concentration of oxidizing species remaining in the atmosphere of the heat treatment differs every time the heat treatment is performed, the dispersion of the formed low dielectric constant layer becomes large, and the dispersion of the characteristics among the wafers becomes large.

Further, in the heat treatment performed for the purpose of removing plasma damage and accumulated charge after processing the gate portion, the oxidized species remaining in the heat treatment atmosphere enter from the side wall of the gate portion, as shown in FIG. Thus, the thick low dielectric constant intermediate layer 2 is formed on the side wall side. The low dielectric constant intermediate layer formed on the side wall side is further grown by a subsequent heat treatment for activating the ion implantation.

An object of the present invention is to solve the above-mentioned problems of the prior art. First, in heat treatment performed for the purpose of improving the quality of a high dielectric constant film and recovering plasma damage, The goal is to provide high-quality products with uniform characteristics without preventing the growth of low-k films.Secondly, diffusion barrier layers formed on high-k films To prevent EOT from becoming thicker. In order to achieve the above object, according to the present invention, there is provided an MIS type semiconductor device in which a gate electrode is formed on a high dielectric constant gate insulating film. An MIS type semiconductor device, wherein a reaction layer which is a conductor layer formed by a reaction between an insulating film and a gate electrode is interposed between the gate electrode and the gate electrode. Is done.

In addition, according to the present invention, in order to achieve the above object,

(a) forming a high dielectric constant film on a semiconductor substrate,

(b) depositing a lower diffusion Baria layer to suppress the contamination of the high dielectric constant film on the oxide species into the high dielectric constant film _{_{(0 2, H 2 0)}} ,

(c) performing a heat treatment;

A method for manufacturing a MIS type semiconductor device, comprising:

(a) forming a high dielectric constant film on a semiconductor substrate,

(b) depositing a lower diffusion Roh ^ Ria layer to suppress the contamination of the high dielectric constant oxide species into the high dielectric constant film on a film _{_{(0 2, H 2 0)}} ,

(c) forming a gate electrode forming material film on the lower diffusion barrier layer; and (d) conducting heat treatment to react the lower diffusion barrier layer with the gate electrode forming material film to conduct. Forming a reactive layer,

A method for manufacturing a MIS type semiconductor device, comprising:

(a) forming a high dielectric constant film on a semiconductor substrate,

(b) forming a gate electrode forming material film on the high dielectric constant film;

(c) forming a gate portion by patterning the gate electrode forming material film and the high dielectric constant film into a gate electrode shape;

and (d) depositing at least suppressing upper diffusion Baria layer penetration of the gate portion and on oxidizing species on its side surface (0 ₂ヽH ₂ 0),

(e) performing a heat treatment;

A method for manufacturing a MIS type semiconductor device, comprising:

It is not necessary to perform the treatment alone, and the treatment may be performed by a heat treatment performed thereafter.

As described above, according to the present invention, the heat treatment for improving the film quality of the high dielectric constant film is performed after the lower diffusion barrier layer is formed on the high dielectric constant film. The low dielectric constant film grows undesirably because the electric conductivity film does not diffuse to reach the surface Will not be done. Further, according to the embodiment in which the lower diffusion barrier layer is made conductive by reacting with the gate electrode material, it is possible to suppress an increase in E〇T due to the formation of the diffusion noria layer. The present invention also provides a heat treatment for repairing damage introduced into the high-dielectric-constant film by processing the gate portion in a state where at least the gate portion is covered with the upper diffusion barrier layer after processing the gate portion. Since the heat treatment is performed, the side surface of the low dielectric constant intermediate layer does not increase by this heat treatment. BRIEF DESCRIPTION OF THE FIGURES

1A to 1F are cross-sectional views in the order of steps for explaining a first embodiment of the present invention.

2A to 2C are cross-sectional views in the order of steps for explaining a second embodiment of the present invention.

FIG. 3 is an observation value of the interface S i 0 ₂ by XPS for explaining the effect of the present invention.

FIG. 4 is a graph showing the relationship between the heat treatment time and the thickness of the interface SiO ₂ layer for explaining the effect of the present invention.

Figure 5 is a graph showing the relationship between the heat treatment time and the 0 ₂ pressure and incubation time.

FIG. 6 is a schematic diagram of a heat treatment apparatus according to an embodiment of the present invention.

7A to 7D are cross-sectional views in the order of steps showing a conventional method for manufacturing a MIS semiconductor device.

FIG. 8 is a cross-sectional view for explaining one problem of a conventional manufacturing method.

FIG. 9 is a cross-sectional view for explaining another problem of the conventional manufacturing method. BEST MODE FOR CARRYING OUT THE INVENTION

Next, embodiments of the present invention will be described in detail with reference to the drawings.

1A to 1F are sectional views showing a first embodiment of the present invention in the order of steps. A silicon substrate 1 having a suitable specific resistance, after partitioning an active region to form a dielectric isolation region by etc. STI (shallow trench isolation) method, by performing hand thermal oxidation vacuum 0 ₂ on the substrate surface forming a low dielectric intermediate layer 2 of S i 0 ₂ very thin (less than 2 atomic layers). This low dielectric constant intermediate layer 2 is not formed aggressively. It may be a natural oxide film that is inevitably formed when the dielectric film 3 is formed. On the low dielectric constant interlayer 2, ALD method, CVD method, Supadzu evening method, Rezaabure one Chillon method, Hf 〇 ₂ by using a vapor deposition _{_{method, Z r0 2, Ln0 3 (}} Ln: La, Ce, Nd, Gd , DY Ho), to form a Ta ₂ 〇 _{_{3, T i0 2, S rT}} i0 3, B a x S ri 0 the high dielectric constant film 3 is deposited one or more of the _three. Alternatively, the high-dielectric-constant metal oxide may be formed by oxidizing a metal in an oxidizing atmosphere while depositing a metal by a snow-burning method, a laser ablation method, an evaporation method, or the like. Good.

On the high dielectric constant film 3, using a method similar to the method for forming a high dielectric constant film 3, 0 _2, H0 ₂ of high resistance to permeation Al ₂ 〇 _{3, A1N, A1N0, S i0} 2 , Si ₃ N ₄ , Si NO, S i C, etc., to form a diffusion barrier layer 4 (FIG. 1A). The thickness of the diffusion barrier layer 4 is preferably at least 0.4 nm, more preferably at least 0.6 nm (or at least two atomic layers). If the film thickness is less than this, the function of suppressing oxygen permeation is reduced. However, the relative dielectric constant of the material forming the diffusion barrier layer 4 is not high, so it is desirable to keep it below 1.5 nm (or below 5 atomic layers) to keep EOT low. Next, heat treatment is performed for the purpose of densifying the high dielectric constant film 3 and removing defects. At this time, oxidizing species such as O ₂ and H ₂₀ may remain in the atmosphere, but oxidizing species 5 may enter the high dielectric constant film 3 due to the diffusion noria layer 4. As a result, the growth of the low dielectric constant intermediate layer 2 is suppressed (FIG. 1B). Desirable heat treatment temperature is 650-850 ° C. The heat treatment can be performed using a resistance heating furnace or a lamp arrayer, but may be performed continuously in a film forming chamber where the diffusion barrier layer 4 is formed.

Next, a gate electrode material film 6a is formed by depositing polysilicon, polycide, refractory metal silicide, refractory metal, and the like by a sputtering method, a CVD method, a vapor deposition method, etc. (FIG. 1C). Next, the gate electrode material film 6a, the diffusion barrier layer 4, the high dielectric constant film 3, and the low dielectric constant intermediate layer 2 other than the gate portion are etched and removed by applying photolithography and RIE. Then, a gate portion having a gate electrode 6 is formed on the gate insulating film 7 (FIG. 1D). In this etching step, the side surfaces of the high dielectric constant film 3 are exposed to plasma, so that charges are injected and damaged. In order to release the charges and repair the damage, a heat treatment is performed by covering the entire surface including the gate portion with the diffusion nori layer 8. The material, film forming method, film thickness, and the like of the diffusion barrier layer 8 are the same as those of the diffusion barrier layer 4. However, if the barrier layer is removed after heat treatment, It may be a conductive material. The heat treatment conditions are the same as those shown in FIG. 1B. Since the gate portion is covered with the diffusion barrier layer 8, the thickness of the side surface of the low dielectric constant intermediate layer does not increase even after the heat treatment is completed (FIG. 1E).

Next, ion implantation is performed using the gate portion as a mask, and a heat treatment is performed for generating active “I” of the implanted impurity to form an impurity diffusion layer 9 which is a source / drain region [FIG. 1F] c After removing the diffusion barrier layer 8 if necessary, depositing an interlayer insulating film and opening a contact hole, a metal wiring connected to the source / drain region is formed.

The heat treatment in the state shown in FIG. 1E may be omitted, and the heat treatment for activating the implanted impurities may also serve as the heat treatment for damage repair of the high dielectric constant film 3. Further, the diffusion barrier layer 8 may be removed before ion implantation for forming the source and drain regions.

In the first embodiment, the diffusion barrier layer 4 formed on the high dielectric constant film 3 is left without being removed. The dielectric constant of the diffusion Baria layer 4, since in general although higher than S i 0 ₂ lower than that of the high dielectric constant film, providing the insulating film leads to an increase in E 0 T. In the second embodiment, an increase in EOT is prevented by making the diffusion barrier layer 4 a conductor. FIG. 2A to FIG. 2C are cross-sectional views in the order of steps showing a second embodiment of the present invention. A low dielectric constant intermediate layer 2 and a high dielectric constant film 3 are formed on a silicon substrate 1 by a method similar to that of the first embodiment shown in FIG. The diffusion barrier layer 4 is formed using a material which is low and which becomes a conductive material by reacting with the gate electrode forming material. Then, heat treatment is performed to improve the film quality of the high dielectric constant film (FIG. 2A).

Next, a gate electrode material film 6a is formed on the diffusion barrier layer (FIG. 2B), and heat treatment is performed to cause the diffusion barrier layer 4 to react with the gate electrode material film 6a to form a conductive reaction layer 10. [Fig. 2C]. Thereafter, as in the first embodiment, the gate portion is processed to form a source / drain region, and a series of manufacturing steps is completed.

Examples of the combination of the diffusion barrier layer 4 and the gate electrode material film 6a include nitride or silicide and a high melting point metal such as aluminum nitride and titanium, silicon nitride and titanium, and silicon carbide and titanium. Example 1

As shown in 1 A _{^{diagram, O 2: 2 xl 0- 6}} T orr the ^{(2 6 6 x 1 0- 4} P a.) Atmosphere, by thermal oxidation of 650 C, 10 min, the 0. 3 nm thick S i 0 ₂ to form a low dielectric constant intermediate layer 2 on the silicon substrate 1, on which, a high dielectric constant film 3 the hf 0 ₂ film 2. thereby forming the 6 nm thick. HF0 ₂ film, and the H f in vacuo 0 ₂ atmosphere deposited by causing electron beams one beam evaporation. Depositing a metal A 1 in heating evaporation method thereon, to form A 1 ₂ 0 ₃ layer 1. 2 nm thick as a diffusion barrier layer 4 by thermal oxidation in a vacuum 〇 ₂ atmosphere.

Next, 0 ₂ pressure in an atmosphere of ^{lx 10 -5 To rr (1. 33x10-} 3 Pa), heat treatment was performed in 8 00 ° C, 3 min. In order to confirm the degree growth S i 0 ₂ layer at this time, also creates comparative sample having no A 1 ₂ 0 ₃ barrier layer was subjected to the same heat treatment. FIG. 3 shows the Si 2 p photoelectron spectrum of these examples and comparative examples by XPS (X-ray excitation photoelectron spectroscopy). Although A 1 ₂ 0 ₃ surface S i 0 if there is no barrier layer ₂ layer is grown, A 1 ₂ 0 ₃ is the case of forming a barrier layer very interfacial layer thin, and before heating ho Tondo There is no change. It can be seen that A 1 ₂ 〇 ₃ Baria layer is won suppress the growth of the low dielectric constant interlayer from this result.

Figure 4 is 0 ₂ atmosphere pressure ^{1 X 10- 5 T orr (1.} 33x10 "3 Pa), shows the change in time and the interface S i 0 ₂ having a thickness of performing heat treatment at 800 ° C are. If there is no a 1 ₂ 0 ₃ barriers layer interface S i 0 ₂ layers heating initial stage is growing. On the other hand, if there is burr § layer up to about 5 minutes increases the interfacial layer (This time is referred to as incubation in the present specification), after which slow growth and growth begin, which is determined by the diffusion of the oxidizing species in the barrier layer, It is thought to depend on the partial pressure of the species.

Figure 5 is a graph showing changes in Inkyube one Chillon against 0 ₂ pressure and heat treatment temperature. This result, 0 ₂ pressure does not exceed a fin-incubated over Chillon Knowing Netsusho physical condition, that is, to determine the optimum heat treatment time for the heat treatment temperature. FIG. 6 is a schematic diagram of a heat treatment apparatus configured to perform heat treatment for a desired time at a desired heat treatment temperature. In the heat treatment chamber 12, an infrared lamp 13 for irradiating the wafer 11 with infrared rays is arranged. Ar from the tank 18 into the heat treatment chamber 12, New ₂ of which inert gas is supplied, indoor gas is exhausted by the exhaust pump 17. Then, the partial pressure of the oxidizing species in the room is measured by a differential exhaust type mass spectrometer 14 which receives the room gas through the orifice 20 and, based on the measured value, the controller 19 determines the desired heating temperature. To determine the optimal heat treatment time for Control in real time. In the figure, 15 is a valve and 16 is an exhaust bonnet. C a ό o Example 2

As shown in FIG. 2, on a silicon substrate 1, in the same manner as in Example 1, 0. 3 nm low dielectric intermediate layer 2 having a thickness, 2. high dielectric consisting of 6 nm thickness H f 0 ₂ The rate film 3 was formed. Silicon is deposited thereon by a heat evaporation method and heat-treated in an ammonia atmosphere to form a 1.2 nm thick SiN layer to become a non-aluminum layer 4. For improvement, heat treatment was performed at 770 ° C for 3 minutes. Next, the gate electrode material film 6a was deposited to a thickness of 10011111 by an electron beam evaporation method. Then, heating was performed at 600 ° C. for 1 minute to form a conductive reaction layer 10.

When the EOT before and after the heat treatment for forming the conductive reaction layer 10 was measured using the CV (capacitance-voltage) method, the EOT was reduced from the initial 1.4 nm to 1.1 nm. Therefore, T i and S i N reacts T i N + T i S i is formed, the gate electrode is divide that was directly bonded to H f 0 _2.

The preferred embodiments and examples have been described above. However, the present invention is not limited to these, and can be appropriately changed without departing from the gist of the present invention. For example, the heat treatment for improving the film quality of the high-dielectric-constant film does not necessarily have to be performed alone, but may be performed by a heat treatment performed thereafter.

Claims

The scope of the claims

1. In a MIS type semiconductor device having a gate electrode formed on a high dielectric constant gate insulating film, an insulating film and a gate electrode are provided between the high dielectric constant gate insulating film and the gate electrode. A MIS type semiconductor device characterized in that a reaction layer, which is a conductor layer formed by reacting with a semiconductor, is interposed.

2. The MIS type semiconductor device according to claim 1, wherein the reaction layer contains a metal nitride or a metal silicide.

3. The MIS type semiconductor device according to claim 1, wherein the gate electrode is formed by Ti ヽ W or Ta.

4. (a) forming a high dielectric constant film on the semiconductor substrate;

(b) depositing the high dielectric constant oxide species into the high dielectric constant film on a film (0 _{_2,} H ₂ 0) lower diffusion Bruno Ria layer you suppress contamination,

(c) performing a heat treatment;

A method for manufacturing a MIS type semiconductor device, comprising:

5. The method for manufacturing a MIS semiconductor device according to claim 4, wherein the time for performing the heat treatment is set based on the concentration of the oxidizing species in the atmosphere and the heat treatment temperature. A method for manufacturing a MIS type semiconductor device.

6. The method for manufacturing a MIS type semiconductor device according to claim 4, wherein the time for performing the heat treatment is within a time for the oxidized species to pass through the high dielectric constant film and reach the surface of the semiconductor substrate. A method of manufacturing a MIS semiconductor device, wherein the method is set.

7. (a) forming a high dielectric constant film on the semiconductor substrate;

(b) depositing the high dielectric constant film on the oxide species into the high dielectric constant film (0 _{_2,} H ₂ 0) lower diffusion Baria layer you suppress contamination,

(c) forming a gate electrode forming material film on the lower diffusion barrier layer;

(d) performing a heat treatment to react the lower diffusion barrier layer with the gate electrode forming material film to form a conductive reaction layer;

A method for manufacturing a MIS type semiconductor device, comprising:

8. (a) forming a high dielectric constant film on the semiconductor substrate;

(b) depositing the high dielectric constant film on the oxide species into the high dielectric constant film (0 _{_2,} H ₂ 0) lower diffusion Bruno ^ Ria layer you suppress contamination, (c) performing a heat treatment to improve the film quality of the high dielectric constant film,

(d) forming a gate electrode forming material film on the lower diffusion barrier layer;

(e) performing a heat treatment to react the lower diffusion barrier layer and the gate electrode forming material film to form a conductive reaction layer;

A method for manufacturing a MIS type semiconductor device, comprising:

9. In the method for manufacturing a MIS type semiconductor device according to claim 7 or 8, wherein a combination of the material of the lower diffusion barrier layer and the material for forming the gate electrode includes a nitride or a silicide. A method for manufacturing an MIS type semiconductor device, wherein the method is a refractory metal.

10. The method for manufacturing a MIS type semiconductor device according to claim 7 or 8, wherein a combination of the material for the lower diffusion barrier layer and the material for forming the gate electrode includes aluminum nitride and titanium, A method for producing a MIS type semiconductor device, comprising silicon nitride and titanium or titanium nitride and titanium.

11. (a) forming a high dielectric constant film on the semiconductor substrate;

(d) depositing an upper diffusion barrier layer that suppresses intrusion of oxidizing species (0 ₂ , H ₂₀ ) at least on the gate portion and on side surfaces thereof;

(e) performing a late heat treatment;

A method for manufacturing a MIS type semiconductor device, comprising:

12. (a) forming a high dielectric constant film on the semiconductor substrate;

(b) depositing the high dielectric constant oxide species into the film (0 _{_2,} H ₂ 0) to suppress the lower diffusion barrier layer contamination,

(c) forming a gate electrode forming material film on the diffusion barrier layer;

(d) forming a gate portion by patterning the gate electrode forming material film, the diffusion barrier layer and the high dielectric constant film into a gate electrode shape,

(Theta) depositing at least the gate portion and on oxidizing species on its side surface (0 _{_2,} Η ₂ 0) suppressing layer diffusion Roh ^ Ria layer intrusion of

(f) performing a late heat treatment;

A method for manufacturing a MIS type semiconductor device, comprising:

13. (a) forming a high dielectric constant film on the semiconductor substrate;

(c) performing a heat treatment in the previous period;

(e) patterning the gate electrode forming material film, the lower diffusion barrier layer and the high dielectric constant film into a gate electrode shape to form a gate portion,

(f) depositing an upper diffusion barrier layer for suppressing intrusion of the oxidizing species (0 ₂ , H ₂₀ ) at least on the gate portion and on the side surface thereof;

(g) performing a late heat treatment;

A method for manufacturing a MIS type semiconductor device, comprising:

14. In the method for manufacturing a MIS semiconductor device according to claim 11, 12, or 13, after the step of forming the gate portion, or depositing the upper diffusion barrier layer After the step, a step of implanting impurity ions into the semiconductor substrate on both sides of the gate portion is added, and the latter heat treatment also serves as a heat treatment for activating the implanted impurities. Manufacturing method of MIS type semiconductor device.

15. The method for manufacturing a MIS type semiconductor device according to claim 4, 7, 8, 11, 12, or 13, wherein the lower diffusion barrier layer or the upper diffusion Aluminum oxide, aluminum nitride, aluminum oxynitride, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, with a barrier layer with a thickness of 2 atomic layers or more than 0.6 nm thick, 5 atomic layers or less than 1.5 nm thick A method for manufacturing a MIS type semiconductor device, which is any one of the above.