JP2005210060A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device comprising a high dielectric constant oxide insulating film which functions as a gate insulating film and has a reduced silicon oxide converted film thickness, a small hysteresis, and a small shift in a flat band voltage (ΔVfb). <P>SOLUTION: A semiconductor device comprises: a silicon substrate; a silicon oxide layer formed on the surface of the silicon substrate; a first oxide layer which is composed of a high dielectric constant film having a dielectric constant higher than that of a silicon oxide and is formed above the silicon oxide layer; a first nitride layer which is formed above the first oxide layer and made of nitride having oxygen intercepting capability; and a gate electrode formed above the first nitride layer. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

    The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a high dielectric constant oxide insulating film and a manufacturing method thereof.

  As a typical semiconductor element used in a semiconductor integrated circuit device, an insulated gate (IG) field effect transistor (FET) typified by a MOS transistor is widely used. In order to achieve high integration of semiconductor integrated circuit devices, IG-FETs have been miniaturized according to scaling rules. Miniaturization makes it possible to keep the performance of the miniaturized element normal and to improve the performance by reducing each dimension of the IG-FET, such as making the gate insulating film thinner, shortening the gate length, etc. .

  The thickness of the gate oxide film of the next generation MOS transistor is required to be reduced to 2 nm or less. This film thickness is the thickness at which the tunnel current starts to flow directly, and the gate leakage current increases and the power consumption increases. As long as silicon oxide is used as the gate insulating film, there is a limit to miniaturization. In order to suppress a tunnel current passing through the gate insulating film, it is desirable to use a thick gate insulating film.

  In order to increase the physical film thickness while keeping the equivalent silicon oxide equivalent film thickness (capacitance equivalent film thickness, CET) of the gate insulating film to 2 nm or less, a high dielectric constant insulating material having a dielectric constant higher than that of silicon oxide is used for the gate insulating film. Proposals to use have been made. The relative dielectric constant of silicon oxide is said to be about 3.5 to 4.5 (for example, 3.9) depending on the film forming method. Silicon nitride has a higher dielectric constant than silicon oxide, and the relative dielectric constant is said to be about 7-8 (for example, 7.5).

Japanese Patent Laid-Open No. 2001-274378 has a dielectric constant higher than that of silicon oxide as a gate insulating film, that is, barium titanate (strontium) (Ba (Sr) TiO ₃ ) (with a relative dielectric constant of 200 to 300); Titanium oxide (TiO ₂ ) (about 60); tantalum oxide (Ta ₂ O ₅ ), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ) (having a relative dielectric constant of about 25); It is proposed to use silicon nitride (7.5) (Si ₃ N ₄ ); alumina (Al ₂ O ₃ ) (with a relative dielectric constant of about 7.8). In addition, a structure in which a silicon oxide film is interposed between the high dielectric constant insulating material film and the silicon substrate is also proposed.

JP, 2001-274378, A When a new material with a high dielectric constant is adopted as a gate insulating film of IG-FET, a new problem will also arise. Zirconium oxide and hafnium oxide are easily crystallized by high-temperature treatment, and increase the leakage current due to electric conduction through crystal grain boundaries and defect levels.

  Japanese Patent Laid-Open No. 2001-77111 proposes that the addition of aluminum oxide to zirconium oxide or hafnium oxide inhibits the formation of a crystal structure and maintains an amorphous phase.

  Japanese Patent Laid-Open No. 2003-8011 proposes to increase the thermal stability of amorphous hafnium oxide by adding silicon oxide to hafnium oxide.

JP 2001-77111 A Japanese Patent Laid-Open No. 2003-8011 discloses that when a high dielectric constant material (High-k material) layer made of a metal oxide film is formed on a silicon substrate, silicon oxide is formed at the interface between the metal oxide film and the silicon substrate. It is pointed out that a physical layer is formed and the effective dielectric constant is lowered, and it is proposed to flow hydrogen instead of oxygen before forming a metal oxide film.

  Japanese Patent Laid-Open No. 2002-359370 discloses nitrogen atoms on both surfaces of a high dielectric constant gate insulating film in order to suppress impurity diffusion from the gate electrode to the silicon substrate and diffusion of metal elements and oxygen from the gate insulating film to the gate electrode or silicon substrate. It is proposed to form a layer.

JP 2003-23005 A JP 2002-359370 A

An object of the present invention is to provide a semiconductor device having a novel gate insulating film structure.
Another object of the present invention is to provide a semiconductor device that includes a high dielectric constant oxide insulating material having a dielectric constant higher than that of silicon oxide as a gate insulating film, and suppresses an increase in CET, hysteresis, and change in flat band voltage or threshold. It is to be.

  According to one aspect of the present invention, a first of a silicon substrate, a silicon oxide layer formed on the surface of the silicon substrate, and a high dielectric constant film having a higher dielectric constant than silicon oxide formed above the silicon oxide layer. A semiconductor having an oxide layer, a first nitride layer formed of a nitride having an oxygen shielding ability above the first oxide layer, and a gate electrode formed above the first nitride layer An apparatus is provided.

  When an insulating gate electrode is formed by depositing a high dielectric constant oxide film on the underlying silicon oxide layer by thermal CVD and stacking an oxidizable conductive material layer thereon, an oxygen shielding ability is formed under the gate electrode. It has been found that the formation of a nitride layer having can suppress the formation of a reaction layer, reduce the change in flat band voltage, and form a gate insulating film with little hysteresis.

  Hafnium oxide (hafnia) is an insulator that can exhibit a dielectric constant several to ten times higher than that of silicon oxide, and has a high possibility as a gate insulating film of an IG-FET. Thermal chemical vapor deposition (CVD) is known as a method by which an oxide insulating film having a high dielectric constant such as hafnium oxide can be formed with good film quality without adversely affecting the substrate.

  When an insulating gate electrode structure is formed by forming a silicon oxide layer on the surface of a silicon substrate and forming a hafnium oxide film and a polycrystalline silicon film thereon by thermal CVD, the flat band voltage changes. This makes it difficult to control the threshold voltage. In addition, the oxide film between the hafnium oxide film and the silicon substrate becomes thick and CET increases.

  The inventor considered that a reaction layer grows at the interface between the hafnium oxide film and the polycrystalline silicon layer and generates fixed charges. An attempt was made to suppress the reaction at the interface with the polycrystalline silicon layer by covering the surface of the hafnium oxide film with another film. First, an AlN film was tried as a reaction suppression film. In the following, description will be made along with experiments conducted by the present inventors.

As shown in FIG. 1A, the surface of the silicon substrate 1 was cleaned with H ₂ SO ₄ + H ₂ O ₂ (SPM). A natural oxide film 2 is formed on the surface of the silicon substrate 1 by being left in the air. Organic contamination adhering to the surface of the natural oxide film 2 is cleaned.

As shown in FIG. 1B, the silicon substrate was washed with pure water for 10 minutes. The residue of the H ₂ SO ₄ + H ₂ O ₂ wash is rinsed with pure water.
As shown in FIG. 1C, the silicon substrate 1 was immersed in a dilute HF aqueous solution for about 1 minute to remove the natural oxide film 2 on the silicon substrate surface.

As shown in FIG. 1D, the silicon substrate was washed with running pure water for 10 minutes. The remainder of the HF + H ₂ O oxide film removal step is rinsed with pure water.
As shown in FIG. 1E, the silicon substrate was cleaned by SC2 (HCl + H ₂ O ₂ + H ₂ O), and a chemical oxide film 3 made of SC 2 was formed on the silicon surface to a thickness of about 0.3 nm. A thin silicon oxide film 3 that is cleaner than the natural oxide film 2 is formed. By forming the silicon oxide film on the surface that is exposed to water and becomes water-repellent, the surface becomes hydrophilic and the generation of watermarks is prevented.

  As shown in FIG. 1F, the silicon substrate was washed with running pure water for 10 minutes. The remainder of the silicon oxide film formation step by SC2 is rinsed with pure water. Subsequently, the substrate surface was dried by thermal drying (nitrogen atmosphere). This process is common to all samples. Thereafter, the silicon substrate was carried into a CVD film forming apparatus. Before describing the next step of FIG. 1G, an embodiment of a CVD film forming apparatus will be described.

  FIG. 2A schematically shows a configuration of a thermal CVD film forming apparatus. A shower head 8 is disposed in the reaction chamber 6, and a susceptor 7 having a heater H is disposed below the shower head 8. The shower head 8 is provided with independent pipes 9A and 9B. A hafnium source gas bubbler 10a, an aluminum source gas bubbler 10b, a nitrogen gas supply pipe 10c, and an oxygen gas supply pipe 10d are connected to the pipe 9A via a mass flow controller MFC1.

The hafnium source gas bubbler 10a uses nitrogen gas as a bubbling gas and contains tetratertiarybutoxyhafnium (Hf (OtC ₄ H ₉ ) ₄ , TTBHf). Aluminum source gas bubbler 10b is a nitrogen gas and bubbling gas, housing the tri tert-butylaluminum _{(Al (t-C 4 H} 9) 3, TTBAl).

The mass flow controller MFC1 supplies Hf, Al organic source gas, nitrogen gas, and oxygen gas at a predetermined flow rate. This film forming gas is supplied onto the susceptor 7 from the pipe 9 </ b> A via the shower head 8. Another pipe 9B is also connected to the shower head 8, and is connected to an ammonia (NH ₃ ) pipe 10e and a nitrogen pipe 10f via a mass flow controller MFC2. When ammonia is mixed with the organic metal source gas, it may react, so that it can be supplied independently. The susceptor 7 is kept at a constant temperature, and the silicon wafer 1 placed thereon also has the same temperature as the susceptor 7.

As shown in FIG. 1G, a hafnium oxide (HfO ₂ ) film 4x having a thickness of 3 nm is formed on the chemical oxide film 3 of the silicon substrate 1 by thermal CVD at a total flow rate of 1100 sccm, and an aluminum nitride having a thickness of 1 nm is further formed thereon. A sample S1 in which a high dielectric constant insulating film having a laminated structure was formed by laminating an (AlN) film 4y was prepared.

As shown in FIG. 1H, a comparative sample S3 in which a single-layer HfO ₂ film 4s having a thickness of 4 nm was formed on the chemical oxide film 3 by thermal CVD at a total flow rate of 1100 sccm was also created.

FIG. 2B is a table showing the flow rate ratio of the deposition gas when depositing the high dielectric constant insulating layer of each sample. The source gas for forming the HfO ₂ film 4x or 4s on the silicon oxide film 3 is 500 sccm nitrogen gas containing Hf (OtC ₄ H ₉ ) ₄ bubbling, 100 sccm oxygen gas, The balance (500 sccm) of nitrogen gas. The total flow rate is 1100 sccm. 100 sccm of oxygen is a sufficient amount of oxygen to form a high-quality oxide film in which oxygen vacancies are prevented.

The source gas for forming the AlN film 4y on the HfO ₂ film 4x is 300 sccm of nitrogen gas containing (Al (t-C ₄ H ₉ ) ₃ ) and 100 sccm of NH ₃ gas. And the remainder (700 sccm) of nitrogen gas (total flow rate is 1100 sccm). The total flow rate is the same.

  After the high dielectric constant insulating layer 4y or 4s was formed, post-deposition annealing was performed in a nitrogen atmosphere at 800 ° C. for 30 seconds to densify the deposited film and desorb C mixed from the organic raw material. Thereafter, a polycrystalline silicon layer doped by low pressure CVD (LPCVD) using silane as a raw material was deposited to form a sample of a MOS diode structure. Instead of the polycrystalline silicon layer, a silicide layer, a metal layer containing Ti, W, Al, or a polycide may be laminated, and a structure having a low contact resistance with a contact plug in contact with the gate electrode is selected. it can.

3A and 3B show the configurations of these two types of samples. FIG. 3A shows a sample S1 according to the example. A silicon oxide layer 3 made of chemical oxide is formed on the surface of the silicon substrate 1, a stacked layer of an HfO ₂ layer 4x and an AlN layer 4y is formed thereon, and a silicon layer 5 is formed thereon. FIG. 3B shows a sample S3 according to the prior art. A single HfO ₂ layer 4s is formed instead of the laminated high dielectric constant insulating layers 4x and 4y.

FIG. 3C shows each film thickness obtained from transmission electron microscope (TEM) imaging of a sample cross section and a capacitance equivalent film thickness CET (silicon oxide equivalent film thickness) obtained from capacitance-voltage (CV) measurement. In the sample S1 according to the example, the thickness of the HfO ₂ film 4x is 3.2 nm, the thickness of the AlN film 4y is 0.8 nm (the high dielectric constant insulating films 4x and 4y as a whole is 4 nm), and the oxide film thereunder 3 has a thickness of 0.7 nm and CET of 1.9 nm. In the sample S3 according to the prior art, the thickness of the HfO ₂ film 4s is 3.8 nm, which is smaller than the high dielectric constant insulating film thickness 4.0 nm of the sample S1, but the thickness of the oxide film 3 is 1 nm and 0.3 nm. Thicker, CET is 2.2 nm and 0.3 nm thick.

  The total thickness of the insulating film is approximately equal to 4.7 nm for S1 and 4.8 nm for S3, but CET is 0.3 nm thinner for sample S1. It can be seen that the sample S1 can maintain the oxide film 3 in a thinner state, and the controllability by the gate voltage will be higher because the CET is thinner. Even if a gate electrode made of a material that can transmit and donate oxygen like the silicon layer 5 is in contact with the AlN film 4y, CET fluctuation is suppressed.

FIG. 3D shows a configuration of a sample S2 in which an HfN film 4z is formed instead of the AlN film 4y of the sample S1 in FIG. 3A. FIG. 3E shows a configuration of a sample S4 in which a single-layer HfN film 4t is formed on a silicon oxide film instead of the HfO ₂ film 4s of the sample S3 in FIG. 3B. Further, a sample S5 in which a single layer Hf _0.5 Al _0.5 O _y film was formed on the silicon oxide film was also prepared.

FIG. 4A is a graph showing the leakage current measured for samples S1 to S4. The measurement conditions are as follows.
For measurement, 4156C (Precision Semiconductor Parameter Analyzer) manufactured by Agilent Technology was used to sweep the gate voltage of the MOS diode.

Only the sample S4 in which the single-layer HfN film 4t is formed as the high dielectric constant film on the silicon oxide film 3 exhibits a large leakage current ranging from 10 ⁻³ to 10 ⁻¹ A / cm ² . The hafnium nitride film includes those that are not insulating. The leakage current of the other samples is 10 ⁻⁴ A / cm ² or less, but the leakage current is particularly low in the sample S3 in which the high dielectric constant film is an HfO ₂ single layer and the sample S1 in which the HfO ₂ / AlN layer is stacked. From another point of view, even if the HfN single layer has a large leakage current and cannot be used as a gate insulating film, it can be used as a gate insulating film if an HfO ₂ / HfN stack is used.

  FIG. 4B is a graph showing a shift amount ΔVfb from the ideal value expected from the physical properties of hysteresis and flat band voltage obtained from CV measurement for samples S1 to S5. The upper left direction is a small desirable region for both, and the lower right direction is a large undesirable region for both.

Sample S3 having a high dielectric constant film of HfO ₂ single layer has a small hysteresis of almost 0, but a large ΔVfb of about 0.33V. In the sample S4 having a high dielectric constant film of HfN, ΔVfb decreases to about 0.24V, but the hysteresis increases to about −0.1V or more. In sample S5 in which a single-layer Hf _0.5 Al _0.5 O _y film was formed as a high dielectric constant film, ΔVfb decreased to less than about 0.1 V, but the hysteresis increased to a value greater than −0.2 V. doing. The measured values of the samples S3 to S5 of these three types of single-layer high dielectric constant films are almost on the straight line p, indicating that there is a trade-off relationship between the shift amount ΔVfb of the flat band voltage and the hysteresis. It is.

In the sample S1 in which the high dielectric constant film is an HfO ₂ / AlN laminated layer, ΔVfb is as small as about 0.15V, and the hysteresis is also small as about −0.05V. A large improvement in the characteristics is realized by approaching the origin (0, 0) largely from the straight line p. The single layer HfO ₂ film has a large amount of fixed charge, but the fixed charge seems to decrease when the surface of the HfO ₂ film is covered with an AlN film. Sample S2 in which the high dielectric constant film is HfO ₂ / HfN stacked has a large ΔVfb of about 0.3 V or more, but the shift amount of the flat band voltage is about 0.05 V, which is slightly different from the straight line p indicating the conventional characteristics. It is on the (0,0) side. However, since HfN can be conductive, the fixed charge could naturally be reduced.

Aluminum nitride and hafnium nitride can form a mixture and can be an insulator. If an aluminum nitride-hafnium (AlHfN) film is formed on the hafnium oxide film, the characteristics on the line q will be obtained. By covering hafnium oxide with aluminum nitride-hafnium (Al _1-x Hf _x N, 0 ≦ x ≦ 1), it is possible to form a gate insulating film with improved characteristics of hysteresis and flat band voltage shift amount. Let's go.

  The same effect can be expected by adding silicon nitride to aluminum nitride. Note that even if a nitride film is formed, oxygen may be included when left in the air. Even in the case of such a film containing oxygen, a film that maintains characteristics as a nitride film such as the above-described reaction suppression is called a nitride film.

Hafnium oxide is a substance that easily crystallizes, and it is not easy to form a thin and dense film having a uniform thickness. When a gate insulating film is formed using only hafnium oxide on a silicon substrate, a crystalline insulating film with a lot of leakage is easily formed. Crystallization can be suppressed by mixing hafnium oxide (HfO ₂ ) with aluminum oxide (alumina) (AlO) or silicon oxide (SiO.) By adding aluminum oxide or silicon oxide to the hafnium oxide film in the above sample. However, the effect of improving the characteristic of the hysteresis-flat band voltage shift amount can be expected.

When crystallization is suppressed, the leakage current is reduced. Aluminum oxide and silicon oxide have a lower dielectric constant than hafnium oxide. In order to obtain a dielectric constant as high as possible, the amount of aluminum oxide or silicon oxide mixed with hafnium oxide is expressed as Hf _1-x Si _x O, Hf _1-x Al _x O (0 <x <0.3). ) Is preferable. For the purpose of suppressing crystallization, (0.1 <x <0.3) is preferable.

  Further, the diffusion of oxygen will be the largest cause of the reaction when the hafnium oxide film is used as the gate insulating film. Even if an oxide other than hafnium oxide is used as the high dielectric constant film, the same effect can be expected from the viewpoint of suppressing the diffusion of oxygen. That is, the high dielectric constant oxide layer may be any oxide layer or stack of Hf, Ti, Ta, Zr, Y, W, Al, and mixtures thereof. The relative dielectric constant of the high dielectric constant film is preferably greater than 10. Some nitrogen may be introduced into the oxide high dielectric constant layer. Such a thing is also called an oxide.

Although the case where a silicon oxide layer of chemical oxide is formed on a silicon substrate by SC2 cleaning as the base of the oxide high dielectric constant insulating layer has been described, the surface thereof may be nitrided. Such a thing is also called silicon oxide. Nitrogen may be introduced by other methods. A thin silicon oxide layer may be formed by a method other than SC2 cleaning. Not only wet processing but dry processing may be performed.
A nitride film may be inserted into the oxide film high dielectric constant layer. A silicon nitride film may be provided on the oxide high dielectric constant layer to block oxygen supplied from the gate electrode. At that time, the stress can be controlled by reducing the thickness of the silicon nitride film. An example using a silicon nitride film will be described later.

The substrate temperature at the time of CVD film formation is 400 ° C. to 600 ° C., and the HfAlO film can be grown well.
The source gas of Hf is not limited to (Hf (OtC ₄ H ₉ ) ₄ ). Hf [N (CH ₃ ) ₂ ] ₄ , Hf {N (C ₂ H ₅ ) ₂ } ₄ , Hf {N (CH ₃ ) (C ₂ H ₅ )} _4, etc. may be used. Al source gas is also not limited to _{Al (t-C 4 H 9} ) 3. Al (C ₂ H ₅ ) ₃ , Al (CH ₃ ) ₃ or the like may be used. The source gas is not limited to an organic metal, but will likely be high when an organic metal source is used. As the nitriding gas, other than NH ₃ , binary butylaminosilane (SiH ₂ [NHt—C ₄ H ₉ ] ₂ , BTBAS), triethylamine (N (C ₂ H ₅ ) ₃ , TEN) or the like may be used.

  FIG. 5A shows a configuration of a gate insulating film according to another embodiment. The structure in which the silicon oxide layer 3 made of chemical oxide is formed on the surface of the silicon substrate 1 is the same as that shown in FIG. 3A. In this embodiment, aluminum nitride layers 4y and hafnium oxide layers 4x are alternately stacked. In the figure, two hafnium oxide layers 4x are sandwiched by three aluminum nitride layers 4x. A silicon gate electrode 5 is formed on the uppermost aluminum nitride layer 4y. You may increase / decrease the number of lamination | stacking suitably. A nitride layer is disposed at least at a position in contact with the gate electrode 5 and the silicon oxide layer 3.

  FIG. 5B illustrates a configuration example of a semiconductor device having a CMOS structure. In the silicon substrate 11, an element isolation region 12 is formed by shallow trench isolation (STI) to define an active region. An n-type well 13n and a p-type well 13p are formed in the active region. An n-channel IG-FET 20n is formed in the p-type well 13p. A p-channel IG-FET 20p is formed in the n-type well 13n. A silicon oxide layer 3 made of chemical oxide is formed on the surface of the active region, and a high dielectric constant insulating laminate 4 in which a hafnium oxide film 4x is sandwiched between a pair of aluminum nitride films 4y is formed thereon by CVD. Polycrystalline silicon gate electrodes 5 n and 5 p are formed on the high dielectric constant insulating laminate 4. P and n after the reference symbol indicate the conductivity type. Sidewall spacers 17 are formed on the side walls of the gate electrode, and source / drain regions 18n and 18p having extensions 16n and 16p are formed on both sides of the gate electrode. A silicide layer 19 is formed on the surface of the gate electrode and source / drain regions. The p-channel IG-FET 20p has a configuration in which the conductivity type of each semiconductor region of the n-channel IG-FET 20n is inverted.

  A high dielectric constant insulating film including a stack of a hafnium oxide layer and an aluminum nitride layer has a CET of 2 nm or less, a small hysteresis, and a flat band voltage change ΔVfb is suppressed.

An interlayer insulating film 21 is formed so as to cover the gate electrode, and a multilayer wiring 24 is formed in the interlayer insulating film. Each wiring 24 is configured using a barrier metal layer 22 and a main wiring layer 23 such as copper.
When the aluminum nitride layer is disposed between the HfO ₂ film, which is a high dielectric constant insulating film in the gate insulating film, and the gate electrode of polycrystalline silicon, the increase in the thickness of the oxide film and the reaction of the high dielectric constant film are suppressed, It was found that the physical film thickness is large and the capacitance equivalent film thickness can be reduced. Silicon nitride is known to have a high oxygen shielding ability and is expected to exhibit the same effect as aluminum nitride. In addition, hafnium nitride can be a conductor, but hafnium nitride oxide can be an insulator, and has the potential as a gate insulating film with a high dielectric constant.

  FIG. 8A is a cross-sectional view schematically showing the configuration of the created sample S. FIG. An element isolation region for defining an active region was formed in the silicon substrate 11, and a p-type impurity and an n-type impurity were ion-implanted into the active region to form a p-type well 13p and an n-type well 13n. A silicon oxide film 3 having a thickness of about 0.7 nm was formed on the surface of the active region, and a high dielectric constant insulating layer 41 having six types of structures was formed thereon by metal organic chemical vapor deposition (MOCVD).

After the high dielectric constant insulating layer 41 is deposited, the high dielectric constant film is densified by heat treatment (annealing) at 600 ° C. to 1100 ° C., for example, 800 ° C. for 30 seconds in an N ₂ atmosphere, and carbon derived from organic matter is released. Thereafter, a thin silicon nitride layer 42 having a thickness of less than 1 nm was stacked as a dielectric film having an oxygen shielding function and a dielectric constant higher than that of silicon oxide.

  A polycrystalline silicon film 5 was deposited on the silicon nitride film 42 and patterned using a resist pattern to form an insulated gate electrode. An n-type impurity is ion-implanted into the p-type well 13p and a p-type impurity is ion-implanted into the n-type well 13n to form an n-type extension region 16n and a p-type extension region 16p. A silicon oxide layer was deposited and anisotropically etched to form sidewall spacers 17 on the gate electrode sidewalls. An n-type impurity is ion-implanted into the p-type well 13p and a p-type impurity is ion-implanted into the n-type well 13n to form an n-type source / drain region 18n and a p-type source / drain region 18p.

8B-8G show the design structures of six types of high dielectric constant insulating layers 41. FIG. FIG. 8B is a sample S6 in which the high-dielectric-constant insulating layer 41a is formed with a single-layer HfO ₂ film having a thickness of 4 nm. FIG. 8C is a sample S7 in which a high dielectric constant insulating film 41b is formed by stacking a 1 nm thick HfON film on a 3 nm thick HfO ₂ film. FIG. 8D is a sample S8 that is a reverse of FIG. 8C, and forms a high dielectric constant insulating film 41c by stacking a 3 nm thick HfO ₂ film on a 1 nm thick HfON film. FIG. 8E shows a sample s9 in which a high dielectric constant insulating film 41d is formed by sandwiching the top and bottom of a ₂ nm thick HfO ₂ film with a 1 nm thick HfON film. 8F and 8G are samples S10 and S11 in which the upper HfON film in FIGS. 8C and 8E is replaced with an AlON film to obtain high dielectric constant insulating layers 41e and 41f.

  Thus, after forming 6 types of samples S (S6 to S11) having a CMOS structure, the equivalent oxide thickness (EOT, effects other than capacitance) of the gate insulating film were measured. For the samples S6, S7, and S9, the relationship between the drain current Id and the gate voltage Vg before and after the heat treatment was measured. 4156C made by Agilent Technology was used for the measurement of current-voltage characteristics, and 4284A made by Agilent Technology was used for the measurement of capacity-voltage characteristics.

FIG. 8H is a table collectively showing measured EOT. Sample S6 in which the single-layer HfO ₂ film is covered with a SiN film has an EOT of 1.58 nm, suggesting that a thin SiN film exhibits oxygen shielding ability. The EOT of the sample S8 in which the HfON film is stacked on the HfO ₂ film is 1.33 nm, which is clearly reduced as compared with the EOT 1.58 nm of the sample S6. It is considered that the HfON film exhibits an oxygen shielding ability, diffuses from the polycrystalline silicon layer 5, shields oxygen that cannot be shielded by the thin SiN film, and prevents the reaction. The EOT of sample S8 in which the HfON film is disposed below the HfO ₂ film is 1.48 nm, which is thinner than the EOT of sample S6. It can be considered that oxygen diffuses also from the lower silicon oxide film 3, and the lower HfON film shields this oxygen. The EOT of sample S9 in which HfON films are arranged above and below the HfO ₂ film is 1.35 nm, which is thinner than the EOT of sample S8, supporting this idea. However, the dielectric constant of HfON is smaller than HfO ₂ , and the EOT can be relatively increased when the ratio of the HfON film is increased.

The EOTs of the samples S10 and S11 in which the HfON film is replaced with the AlON film are 1.36 nm and 1.36 nm, which are close to the EOTs 1.33 nm and 1.35 nm of the samples S7 and S9. The AlON film is considered to have the same oxygen shielding ability as the HfON film. A nitride insulating film such as an AlN film, a SiN film, a HfON film, or an AlON film is considered to have an effective oxygen shielding ability. It would be possible to form an HfON film or an AlON film on the HfO ₂ film and omit the SiN film. In the structure shown in FIG. 5A, the hafnium oxide layer 4x may be sandwiched between layers of hafnium oxynitride or aluminum oxynitride 4y. The number of hafnium oxide layers may be increased or decreased.

FIG. 9A shows the result of measuring the relationship between the drain current Id after the heat treatment and the gate voltage Vg for the samples S6, S7, and S9. The characteristic s7 of the sample S7 is shifted in the negative direction by the gate voltage from the characteristic s6 of the sample S6. The characteristic s9 of the sample S9 is further shifted negatively. If there is a negative fixed charge in sample S6, the fixed charge is reduced in samples S7 and S9. If the HfON film is disposed adjacent to the HfO ₂ film, the fixed charge can be reduced.

This phenomenon can be considered as follows. The deposited HfO ₂ film includes traps such as lattice defects and traps electrons. When N diffuses from the HfON film into the HfO ₂ film by the heat treatment, there is a function of eliminating traps such as lattice defects. If the trap disappears, the electrons that have been fixed charges can be extinguished. In the heat treatment described above, N diffused from one side is not distributed up to the entire thickness of the HfO ₂ film, and the effect is greater when the HfON film is arranged on both sides than when the HfON film is arranged on one side.

  FIG. 9B shows the result of simulation based on the above idea. As the characteristics of the samples S6, S7, and S9, characteristics s6, s7, and s9 showing the same tendency as in FIG. 9A were obtained. It seems that the validity of the above idea was supported.

  In the structure in which the nitride layer having an oxygen shielding ability is disposed on the surface of the high dielectric constant oxide layer, it is preferable that the oxygen shielding nitride film includes at least one of an AlN film and an SiN film. It is considered that the HfON film and the AlNO film can be used both as a high dielectric constant oxide layer and an oxygen shielding nitride layer.

  FIG. 6 shows a configuration example of a semiconductor integrated circuit device having a multilayer wiring structure. An element isolation region 102 by shallow trench isolation (STI) is formed on the silicon substrate 101. In order to form a MOS transistor in the active region surrounded by the element isolation region 102, a p-type well 103 and an n-type well 104 are formed.

  On the p-type well region 103, the high dielectric constant gate insulating film 105, the polycrystalline silicon gate electrode 106, and the side wall spacer 107 having the above-described configuration are formed. The extension-type n-type source / drain regions 108 are formed on both sides of the gate electrode 106. Is formed. In the n-type well region 104, a p-type source / drain region 109 is formed.

  A silicon nitride layer 111 is formed on the semiconductor substrate so as to cover the gate electrode, and a phosphosilicate glass (PSG, phosphorus-doped silicon oxide) layer 112 is formed thereon. A via conductor formed of the TiN barrier metal layer B11 and the tungsten layer V1 is formed through the PSG layer 112 and the silicon nitride layer 111.

  An organic insulating layer 113 and a silicon oxide layer 114 are stacked on the PSG layer 112. A wiring pattern formed of the barrier metal layer B1, the copper wiring layer W1, the auxiliary barrier metal layer B1x, and the auxiliary copper wiring layer W1x is embedded in this stack. In this way, the first wiring layer WL1 is formed.

  A stack of a silicon nitride layer 121, a silicon oxide layer 122, an organic insulating layer 123, and a silicon oxide layer 124 is formed on the first wiring layer WL1, and an interlayer insulating film for the second wiring WL2 is formed. The second wiring layer WL2 formed of the barrier metal layer B2, the copper wiring layer W2, the auxiliary barrier metal layer B2x, and the auxiliary copper wiring layer W2x is embedded in the second wiring interlayer insulating film.

  Similar to the interlayer insulating film for the second wiring WL2, the interlayer insulating films for the third wiring layer WL3 and the fourth wiring layer WL4 are silicon nitride layers 131 and 141, silicon oxide layers 132 and 142, organic insulating layers 133 and 143, A stack of silicon oxide layers 134 and 144 is formed.

  The damascene wiring structure of the third wiring layer WL3 and the fourth wiring layer WL4 is the same as that of the second wiring layer. A wiring pattern is formed by the barrier metal layer Bn, the copper wiring layer Wn, the auxiliary barrier metal layer Bnx, and the auxiliary copper wiring layer Wnx.

  The fifth wiring layer WL5 to the seventh wiring layer WL7 have different configurations from the second wiring layer WL2 to the fourth wiring layer WL4. The interlayer insulating film of the fifth wiring layer WL5 is formed by stacking a silicon nitride layer 151, a silicon oxide layer 152, a silicon nitride layer 153, and a silicon oxide layer 154. The configuration of the wiring pattern is the same as that of the second to fourth wirings WL4.

  Similarly to the fifth wiring layer WL5, an interlayer insulating film for the sixth wiring layer and the seventh wiring layer is formed of silicon nitride layers 161 and 171, silicon oxide layers 162 and 172, silicon nitride layers 163 and 173, and silicon oxide layers 164 and 174. Has been. The configuration of the wiring pattern is the same as that of the fifth wiring WL5.

  In the upper layer wiring, the pitch between the wirings becomes wider and the wiring density becomes lower. For this reason, in order to reduce the stray capacitance between wirings, the necessity of using a low dielectric constant insulating layer is reduced. Therefore, in the fifth to seventh wiring layers, the organic insulating layer is not used, and the reliability of the interlayer insulating layer is enhanced.

  The uppermost eighth wiring layer WL8 has a unique configuration. A lower insulating layer is formed by the silicon nitride layer 181 and the silicon oxide layer 182, and a via portion is formed by the barrier metal layer B81 and the tungsten layer V8.

  A wiring layer also serving as a pad is formed of the TiN layer B82, the aluminum layer W8, and the TiN layer B83 on the via portion. Cu can also be used in place of aluminum. A silicon oxide layer 183 and a silicon nitride layer 190 are formed so as to cover the uppermost wiring.

  In the configuration of FIG. 6, the auxiliary barrier metal layer is embedded in the wiring pattern in all of the first wiring layer WL1 to the seventh wiring layer WL7 to suppress the generation of voids. The structure of the interlayer insulating film is different between the lower wiring layer and the upper wiring layer except the uppermost layer.

  FIG. 7 shows another configuration example of a semiconductor integrated circuit device having a multilayer wiring structure. The structure of the MOS transistor structure and the source / drain lead conductive plug formed in the semiconductor substrate is the same as that shown in FIG.

  A stack of a SiC layer 116, an organic insulating layer 117, and a SiC layer 118 is formed on the PSG layer 112, and a first wiring layer WL1 is formed of a barrier metal layer B1 and a copper wiring layer W1. No auxiliary barrier metal layer is used.

  The second wiring layer WL2 to the fourth wiring layer WL4 have the same configuration as the first wiring layer WL1. Taking the fourth wiring layer WL4 as an example, the interlayer insulating film is formed of a SiC layer 141, an organic insulating layer 142, and a SiC layer 143. The dual damascene wiring is formed of a barrier metal layer B4 and a copper layer W4, and no auxiliary barrier metal layer is disposed.

  The fifth wiring layer WL5 to the eighth wiring layer WL8 have the same configuration. Taking the fifth wiring layer WL5 as an example, the interlayer insulating film is formed of an SiC layer 151, a silicon oxide carbide (SiOC) layer 152, an SiC layer 153, and a silicon oxide carbide layer 154. The dual damascene wiring is formed of a barrier metal layer B and a copper wiring layer W, and no auxiliary barrier metal layer is disposed.

  The ninth wiring layer WL9 includes a barrier metal layer B9, a copper wiring layer W9, an auxiliary barrier metal layer B9x, and an auxiliary insulating film formed on an interlayer insulating film formed of the SiC layer 191, the silicon oxide layer 192, the SiC layer 193, and the silicon oxide layer 194. A dual damascene wiring formed of the copper wiring layer W9x is embedded.

  The tenth wiring WL10 has a configuration similar to that of the ninth wiring WL9. The SiC layer 201, the silicon oxide layer 202, the SiC layer 203, and the silicon oxide layer 204 are formed, and the interlayer insulating film is formed of the barrier metal layer B10, the copper wiring layer W10, the auxiliary barrier metal layer B10x, and the auxiliary copper wiring layer W10x. Dual damascene wiring is embedded.

  The uppermost wiring layer WL11 is formed in FIG. 7 has the same configuration as the uppermost wiring. A SiC layer 211 and a silicon oxide layer 212 are laminated, and a via conductor formed of a TiN barrier metal layer B11 and a W wiring layer W11 is embedded therein. On the via conductor, a TiN layer B111, a main wiring layer W12 formed of aluminum or an aluminum alloy containing copper, and a bonding pad combined uppermost wiring layer formed of an upper barrier metal layer B112 of TiN are formed. A silicon oxide layer 213 and a silicon nitride layer 220 are formed to cover this wiring layer.

  In the configuration of FIG. 7, the laminated configuration of the interlayer insulating layer changes in three stages from the lower layer to the upper layer, and the substantial dielectric constant is lowered as the lower layer. The lower layer wiring has a high density, and it is preferable to reduce the dielectric constant of the interlayer insulating layer in order to reduce the accompanying capacitance of the wiring.

Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. For example, other metal oxides could be used.
It will be apparent to those skilled in the art that other various modifications, improvements, and combinations can be made.

The features of the present invention will be described below.
(Appendix 1) (1) A silicon substrate,
A silicon oxide layer formed on the surface of the silicon substrate;
A first oxide layer of a high dielectric constant film having a higher dielectric constant than silicon oxide formed above the silicon oxide layer;
A first nitride layer formed of a nitride having an oxygen shielding ability above the first oxide layer;
A gate electrode formed above the first nitride layer;
A semiconductor device.

(Supplementary note 2) (2) The semiconductor device according to supplementary note 1, wherein the first oxide layer includes an oxide of any one of Hf, Ti, Ta, Zr, Y, W, Al, and La.
(Supplementary note 3) (3) The semiconductor device according to supplementary note 1, wherein the first oxide layer includes a hafnium oxide layer, and the first nitride layer includes an aluminum nitride layer or a silicon nitride layer.

(Supplementary note 4) The semiconductor device according to supplementary note 3, wherein the first oxide layer includes any one of Al and Si.
(Appendix 5) (4) The semiconductor device according to Appendix 3 or 4, wherein the first oxide layer includes a hafnium oxynitride layer or an aluminum oxynitride layer on at least one of the upper and lower sides of the hafnium oxide layer.

(Appendix 6) (6) The semiconductor device according to any one of appendices 1 to 5, wherein the first oxide layer also includes a hafnium oxynitride layer or an aluminum oxynitride layer.
(Supplementary note 7) The semiconductor device according to any one of supplementary notes 3 to 5, wherein the first nitride layer includes Hf.

    (Supplementary note 8) The semiconductor device according to supplementary note 7, wherein the first nitride layer contains more Hf than Al.

(Supplementary note 9) The semiconductor device according to supplementary note 3 or 4, wherein the first nitride layer also includes Si.
(Supplementary note 10) The semiconductor device according to any one of supplementary notes 1 to 9, wherein the first nitride layer includes oxygen.

(Supplementary note 11) The semiconductor device according to any one of supplementary notes 1 to 10, wherein the first nitride layer includes a nitride layer containing aluminum and a nitride layer containing silicon.
(Supplementary note 12) (5) The semiconductor device according to any one of supplementary notes 1 to 4, 6 to 11, wherein the first nitride layer includes a hafnium oxynitride layer or an aluminum oxynitride layer. (Additional remark 13) The insulating lamination | stacking of the said high dielectric constant film | membrane includes the 2nd nitride layer arrange | positioned between the said 1st oxide layer and the said silicon oxide layer. Semiconductor device.

(Supplementary note 14) The semiconductor device according to supplementary note 13, wherein the second nitride layer includes any of Hf and Si.
(Additional remark 15) The said 2nd nitride layer is a semiconductor device of Additional remark 13 or 14 containing oxygen.

(Supplementary note 16) The semiconductor device according to supplementary note 1, wherein the gate electrode is made of an oxygen donating substance.
(Appendix 17) (7) Silicon substrate;
A silicon oxide layer formed on the surface of the silicon substrate;
A method of manufacturing a semiconductor device including a first oxide film having a higher dielectric constant film than silicon oxide,
(A) forming a high dielectric constant first oxide layer above the silicon oxide;
(B) forming a first nitride layer made of a nitride having an oxygen shielding ability above the first oxide layer;
(C) forming a gate electrode above the first nitride layer;
A method for manufacturing a semiconductor device comprising:

(Appendix 18) (8)
(D) forming the silicon oxide layer by hydrochloric acid-hydrogen peroxide treatment;
18. A method for manufacturing a semiconductor device according to appendix 17, wherein:

(Additional remark 19) The said 1st nitride layer is a manufacturing method of the semiconductor device of Additional remark 17 or 18 containing Hf.
(Additional remark 20) The manufacturing method of the semiconductor device of Additional remark 19 whose content of Al contained in a said 1st nitride layer is less than content of Hf.

(Supplementary note 21) The method for manufacturing a semiconductor device according to supplementary note 17, wherein the gate electrode is made of an oxygen donating substance.
(Appendix 22) (9)
The step (a) forms a hafnium oxide layer by metal organic vapor phase epitaxy;
(E) After the step (a), annealing at 600 ° C. to 1100 ° C.
22. A manufacturing method of a semiconductor device according to any one of appendices 17 to 21, including:

(Appendix 23) (10)
24. The method of manufacturing a semiconductor device according to appendix 22, wherein the step (a) or (b) includes a step of forming a hafnium oxynitride layer or an aluminum oxynitride layer.

It is sectional drawing for demonstrating the method of forming a high dielectric constant insulating film on a silicon substrate by chemical vapor deposition (CVD). It is the table | surface which shows the block diagram which shows the structure of a thermal CVD apparatus roughly, and experimental conditions collectively. It is a graph which shows the CV characteristic of the produced MOS structure. It is a graph which shows collectively flat band voltage variation | change_quantity (DELTA) Vfb and hysteresis. It is sectional drawing which shows the structure of the MOS transistor by an Example. It is sectional drawing which shows the structure of a semiconductor integrated circuit device. It is sectional drawing which shows the structure of a semiconductor integrated circuit device. It is sectional drawing and a table | surface which show the structure of a sample, and the measurement result of EOT. It is a graph which shows the measurement result of the characteristic of drain current versus gate voltage, and a simulation result.

Explanation of symbols

1 Silicon substrate 2 Natural oxide film 3 Chemical oxide film (silicon oxide film)
4 High dielectric constant insulating layer 4x Hafnium oxide layer 4y Aluminum nitride layer 4z Hafnium nitride layer 4s Hafnium oxide layer 4t Hafnium nitride layer 5 Gate electrode 6 Reaction chamber 7 Susceptor 8 Shower head 9 Piping 11 Silicon substrate 13 Well 16 Extension 17 Side wall 19 Silicide 41 High dielectric constant layer 42 Oxygen shielding layer

Claims (10)

A silicon substrate;
A silicon oxide layer formed on the surface of the silicon substrate;
A first oxide layer of a high dielectric constant film having a higher dielectric constant than silicon oxide formed above the silicon oxide layer;
A first nitride layer formed of a nitride having an oxygen shielding ability above the first oxide layer;
A gate electrode formed above the first nitride layer;
A semiconductor device. The semiconductor device according to claim 1, wherein the first oxide layer includes an oxide of any one of Hf, Ti, Ta, Zr, Y, W, Al, and La. The semiconductor device according to claim 1, wherein the first oxide layer includes a hafnium oxide layer, and the first nitride layer includes an aluminum nitride layer or a silicon nitride layer. 4. The semiconductor device according to claim 3, wherein the first oxide layer includes a hafnium oxynitride layer or an aluminum oxynitride layer on at least one of upper and lower sides of the hafnium oxide layer. The semiconductor device according to claim 1, wherein the first nitride layer also includes a hafnium oxynitride layer or an aluminum oxynitride layer. The semiconductor device according to claim 1, wherein the first oxide layer includes a hafnium oxynitride layer or an alternate stack of an aluminum oxynitride layer and a hafnium oxide layer. A silicon substrate;
A silicon oxide layer formed on the surface of the silicon substrate;
A method of manufacturing a semiconductor device including a first oxide film having a higher dielectric constant than silicon oxide,
(A) forming a high dielectric constant first oxide layer above the silicon oxide layer;
(B) forming a first nitride layer made of a nitride having an oxygen shielding ability above the first oxide layer;
(C) forming a gate electrode above the first nitride layer;
A method for manufacturing a semiconductor device comprising: further,
(D) forming the silicon oxide layer by hydrochloric acid-hydrogen peroxide treatment;
A method for manufacturing a semiconductor device according to claim 7. The step (a) forms a hafnium oxide layer by metal organic vapor phase epitaxy;
(E) After the step (a), annealing at 600 ° C. to 1100 ° C.
The manufacturing method of the semiconductor device of Claim 7 or 8 containing these.   The method for manufacturing a semiconductor device according to claim 9, wherein the step (a) or (b) includes a step of forming a hafnium oxynitride layer or an aluminum oxynitride layer.

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