466615 A7 B7 五、發明說明（ 相關中請案的奋g東者 本發明爲1997年9月22曰歸檔的美國專利申請案第 08/995,435鸹之延續，其來自^卯年12月23日歸檔的美國臨 時申請案第60/033,839號之申請專利範圍優先權將讓與J c Kizilyalli等人。上述參考申請案和臨時專利申請案所揭露 之事項在此將特別併入當成參考。 技術簌喼 本發明與用於積體電路的閘極堆疊結構及其製造方法有 關。 _發明背景 在光蝕刻和降低閘極氧化物厚度的推進下，使得縮小金 氧半導體的尺寸技術到達〇.25微米的地步。在電子系統中 使用以矽爲基礎的積體電路會随工業進入毫微米的整合境 界而持續。當尺寸降低時，電容密度需求增加。如在這方 面已完備的普通技術，MOS電晶體的閘極結構大約爲平行 板電容，具有閘極且由半導體形成電極。爲要增加電容値 ，必須要降低電容電極間的間隙或使用高介電係數的材料 。不幸地，傳統的介電質，例如極薄（小於3 5 nm)的二氧 化妙層對降低電容間電極間隙有妨礙。例如，接近二氧化 矽2.5 nm的隧道極限時，隧道電流超過可接受的値。當在 尺寸上薄介電質的問題消除時，藉由使用介電係數高於二 氧化矽的材料，可以達到想要的電容値。發明使用高介電 係數堆疊閘極結構的範例在上述〗c Kizilyalli的母申請專 利中。在Kizilyalli等人應用發明的實施例有—層二氧化矽 {請先閱讀背面之注意事項再填寫本頁} ----I I 1 I «Ill — — — — — ^ 經濟部智慧財產局員工消費合作社印製 d 6 66 1 5 A7 五、發明說明（2 ) (請先聞讀背面之注意事項再填寫本頁} 經濟部智慧財產局員工消費合作社印製 長出來並且全集在可氧化的基底上；一層高介電係數（高 k)的材料：和一沈積的二氧化矽分佈在高介電係數的材科 上。在眾多理由中，使用沈積的二氧化矽層是爲了當做高 k材料和多晶矽閘極電極間的「緩衝」層，其中多晶矽閘 極電極分佈在沈積的二氧化矽層上。例如當高^^層是五氧 化二鈕時，沈積的二氧化矽可尚當作由多晶矽閘極來的高 k層之緩衝，防止五氧化钽因多晶矽層而減少。這防止重 要的钽在層與在高k層中不想要的短路。電晶體使用母 應用的堆疊閘極介電質材料具有低密度的介面陷井特性， 改良的隧道電壓，可忽略的固定電荷（Qf)，改良的介面載 子移動性和其他傳統結構相比低效率的介電厚度。當母應 用的介電閘極堆疊通過增加電容密度幫助縮小化，還是有 更加降低特性大小的需求。如上所述，通常有降低介電質 厚度的需求來幫助元件縮小和整合。當降低傳統材料的介 電質厚度時，例如二氧化矽，會増加它的電容，二氧化矽 的厚度上有較低的極限會發生有害的電子效應。因相 要有種介電材料在特定二氧化矽的厚度上有相同的電容値 ’但是處理上有較低的複雜性以及不會因極薄的二氧化欢 層導致電子短路。更進一步’當避免傳統結構上使用極薄 的二氧化秒層的問題時’閘極介電質的結構需求爲何，以 及它的製造方法使得降低尺寸增加密度/縮小程度成爲可 能。 發明總結 本發明相關於閘極堆疊結構和它的製造方法，具有介電 -5- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 466615 A7 經濟部智慧財產局員工消費合作社印製 B7 五、發明說明（3 ) 材料分佈於基底和閘極電極間，其中介電材料層具有2.5 nm 或更小的等效電氣厚度，並至少包含一層非二氧化矽層。 這結構的製造方法是佈一層介電材料在基底上，再直接 佈一層導電層在介電材料上。 圖式之簡單説明 當與附圖一起讀時，本發明最好從下面的詳細説明中加 以瞭解。要強調的是依照半導體工業中通用的實施例，不 同的特性未必要調整尺寸》事實上爲了清楚討論，不同特 性的尺寸可以任意增加或降低。 圖1爲本發明實施範例的剖面圖。 圖2爲顯示形成氧化層範例的製程參數之表格。 發明之詳細説明 如下詳細討論及依照本發明如圖1所示的實施範例，可 氧化的基底101已經在其上分佈—層長好的氧化層，並具 長好的二氧化矽層在其下^長好的氧化層和在其下長好的 二氧化砍層it常顯*爲102。—層冑介電隸的材料顯示 如103，閉極電極顯示如104 β在實施範例中，基底1〇1可以 是單晶砍但不能爲任何可被氣化的一層，例如多晶梦或固 定長晶方向的矽。抑止漏電流的高！^介電材料1〇3可以是五 氧化二钽，閘極電極104例如像鎢的金屬。利用圖丨所示結 構的優點’堆疊層獅103的等效電氣厚度爲25nm或更 少。（本應用的目的即等效電氣厚度意味特定的介電質層 結構具：二氧化砂特定厚度的電容値。例如，單一"腿 厚的五氧化二鈕其等效電氣厚度與單— -----;------- . - I I I I---訂 - ---— II--竣 -請先閱讀背面之注意事項再填寫本頁) -6- 經濟部智慧財產局員工消費合作社印製 466615 A7 ____B7 五、發明說明（4 ) 矽層相等。）然而高k材料層具有3 〇 nm或更厚的尺寸，如 此在製私上有所助盈並且克服與極薄二氧化矽層相關的製 程和效能上之課題。當説明上述實施例時，本發明之閉極 結構大多爲位於基底和閘極電極間的介電材料層，其中介 电材料層具備等效電乳厚度爲2·5 nm或更小，並且至少包 含一層非二氧化矽層。 造成薄氧化閘極介電質層缺陷的主要因素爲成長感應的 微細孔和氧化層中内部的壓力。形成在二氧化矽層中的微 細孔網路爲擴散質點傳遞和漏電電流造成短路路徑。除此 之外，在二氧化矽層中的壓力通常會增加微細孔的大小和 密度。因此’在研發低缺陷密度的薄介電質上，不僅需要 降低初始的缺陷密度，更要使用壓力調適層降低在矽與二 氧化碎介面附近的區域壓力梯度。結果，在介電質中使用 介面是必要的，它是當作壓力緩衝和減少缺陷。在本發明 的實施範例中這一層可以爲二氧化矽層（在此參考到沒有 壓力的氧化層）藉由介面的氧化反應長在第一長好的氧化 層下。這氧化層可以在接近平衡條件的情況下成長，結果 陷在的地方可以被練出並且實際上爲平的，藉由新長成的 二氧化矽形成幾乎沒有壓力的矽與二氧化矽介面。 關於長在矽與二氧化矽介面上氧化層的詳細内容可以在 下面的參考内容中找到；美國專利4,851，37〇 ;美國專利申 請序號 08/995,435 ; 1998 年 6 月 i 曰給 Roy et al 的 AppUed466615 A7 B7 V. Description of the invention (related applicants) The present invention is a continuation of US Patent Application No. 08 / 995,435 filed on September 22, 1997, which was filed on December 23, ^ The priority of the patent scope of US Provisional Application No. 60 / 033,839 will be assigned to J. Kizilyalli et al. The matters disclosed in the above referenced applications and provisional patent applications are specifically incorporated herein by reference. The present invention relates to a gate stack structure for integrated circuits and a manufacturing method thereof. _ BACKGROUND OF THE INVENTION Under the advancement of photo-etching and reducing gate oxide thickness, the technology for reducing the size of gold-oxide semiconductors has reached 0.25 micron. The point. The use of silicon-based integrated circuits in electronic systems will continue as the industry enters the realm of nanometer integration. When the size is reduced, the demand for capacitor density increases. For example, MOS transistors, which are complete common technologies in this respect, The gate structure is approximately a parallel plate capacitor, which has a gate and an electrode formed by a semiconductor. In order to increase the capacitance 値, the gap between the capacitor electrodes must be reduced or a high Material of electrical coefficient. Unfortunately, traditional dielectrics, such as very thin (less than 35 nm), prevent the electrode gap between capacitors from being reduced. For example, near the 2.5 nm tunneling limit of silicon dioxide, The tunnel current exceeds acceptable 値. When the problem of thin dielectrics in size is eliminated, the desired capacitance 介 can be achieved by using a material with a higher dielectric constant than silicon dioxide. Invented using a high-dielectric stack Examples of the gate structure are in the above-mentioned parent patent of Kizilyalli. Examples of the inventions applied by Kizilyalli et al. Are: layer of silicon dioxide {Please read the precautions on the back before filling this page} ---- II 1 I «Ill — — — — — ^ Printed by the Consumers’ Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs d 6 66 1 5 A7 V. Invention Description (2) (Please read the notes on the back before filling this page} Intellectual Property of the Ministry of Economic Affairs The Bureau's Consumer Cooperative printed and grown on the oxidizable substrate; a layer of high dielectric constant (high k) material: and a deposited silicon dioxide distributed on the high dielectric constant material family. For many reasons The deposited silicon dioxide layer is used as a "buffer" layer between the high-k material and the polycrystalline silicon gate electrode, where the polycrystalline silicon gate electrode is distributed on the deposited silicon dioxide layer. For example, when the high- ^ layer is pentoxide At the second button, the deposited silicon dioxide can still serve as a buffer for the high-k layer from the polycrystalline silicon gate, preventing the reduction of tantalum pentoxide due to the polycrystalline silicon layer. This prevents the important tantalum from being unwanted in the layer and in the high-k layer. Short circuit of transistor. The stacked gate dielectric material used by the transistor has low density interface trap characteristics, improved tunnel voltage, negligible fixed charge (Qf), improved interface carrier mobility and other traditional structures. Compared to inefficient dielectric thickness. When the dielectric gate stack of the mother application helps to reduce the size by increasing the capacitance density, there is still a need to further reduce the characteristic size. As mentioned above, there is often a need to reduce the thickness of the dielectric to help shrink and integrate components. When the dielectric thickness of traditional materials is reduced, such as silicon dioxide, its capacitance will be increased. There is a lower limit on the thickness of silicon dioxide and harmful electronic effects will occur. There is a relative need for a dielectric material that has the same capacitance over a specific silicon dioxide thickness, but it has lower complexity in handling and does not cause electronic shorts due to the extremely thin dioxide layer. Furthermore, 'when avoiding the problem of using a very thin second oxide layer on a conventional structure', what is the structural requirement of the gate dielectric, and its manufacturing method makes it possible to reduce the size and increase the density / reduction degree. Summary of the Invention The present invention is related to a gate stack structure and a manufacturing method thereof, and has a dielectric-5- This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public love) 466615 A7 Staff Consumption of Intellectual Property Bureau of the Ministry of Economic Affairs Cooperative printed B7 V. Description of the invention (3) The material is distributed between the substrate and the gate electrode. The dielectric material layer has an equivalent electrical thickness of 2.5 nm or less, and includes at least one non-silicon dioxide layer. The manufacturing method of this structure is to lay a layer of dielectric material on the substrate, and then directly lay a conductive layer on the dielectric material. BRIEF DESCRIPTION OF THE DRAWINGS When read with the accompanying drawings, the present invention is best understood from the following detailed description. It is emphasized that, according to the embodiment commonly used in the semiconductor industry, different characteristics do not need to be adjusted in size. In fact, for the sake of clear discussion, the dimensions of different characteristics can be arbitrarily increased or decreased. FIG. 1 is a cross-sectional view of an example of the present invention. FIG. 2 is a table showing process parameters for an example of forming an oxide layer. Detailed description of the invention is discussed in detail below and according to the embodiment of the present invention shown in FIG. 1, an oxidizable substrate 101 has been distributed thereon—a well-formed oxide layer and a well-formed silicon dioxide layer underneath it. ^ It often shows that the well-formed oxide layer and the well-below dioxide cut layer * are 102. -The material of the layered dielectric is shown as 103, and the closed electrode is shown as 104 β. In the embodiment example, the substrate 101 can be a single crystal but cannot be any layer that can be vaporized, such as polycrystalline dream or fixed Silicon in the growth direction. Suppress high leakage current! The dielectric material 103 may be tantalum pentoxide, and the gate electrode 104 is, for example, a metal like tungsten. Taking advantage of the structure shown in Figure 丨 the equivalent electrical thickness of the stacked layer Lion 103 is 25 nm or less. (The purpose of this application is that the equivalent electrical thickness means that the specific dielectric layer structure has a capacitor with a specific thickness of sand dioxide. For example, a single " leg thick pentoxide button has an equivalent electrical thickness and a single-- ----; -------.-III I --- Order- ----- II--End-Please read the notes on the back before filling out this page) -6- Intellectual Property Bureau, Ministry of Economic Affairs Printed by the employee consumer cooperative 466615 A7 ____B7 V. Description of the invention (4) The silicon layers are equal. ) However, the high-k material layer has a size of 30 nm or more, which can help in manufacturing and overcome the process and performance issues associated with very thin silicon dioxide layers. When the above embodiments are described, most of the closed-electrode structures of the present invention are dielectric material layers located between the substrate and the gate electrode, wherein the dielectric material layer has an equivalent electrical emulsion thickness of 2.5 nm or less, and at least Contains a non-silicon dioxide layer. The main causes of defects in thin oxide gate dielectrics are growth-induced micropores and internal pressure in the oxide layer. The microporous network formed in the silicon dioxide layer causes short-circuit paths for diffusive particle transfer and leakage current. In addition, the pressure in the silicon dioxide layer usually increases the size and density of the micropores. Therefore, in developing thin dielectrics with low defect densities, it is necessary not only to reduce the initial defect density, but also to use a pressure-adapting layer to reduce the pressure gradient in the region near the interface between silicon and silica. As a result, it is necessary to use an interface in a dielectric, which acts as a buffer against pressure and reduces defects. In the embodiment of the present invention, this layer may be a silicon dioxide layer (here, an oxide layer having no pressure is referred to), and an interface oxidation reaction is grown under the first good oxide layer. This oxide layer can grow under near-equilibrium conditions. As a result, the trapped area can be trained and is actually flat. The newly grown silicon dioxide forms a silicon-silicon interface with almost no pressure. Details on the oxide layer grown on the interface between silicon and silicon dioxide can be found in the following references; US Patent 4,851,370; US Patent Application Serial No. 08 / 995,435; June 1998 to Roy et al. AppUed
Physics Letter第72册，編號u，題目爲堆疊的£ r ,金氧半 導體積體電路縮小十億倍整合技術的閘極介電質；以及 -7- 本紙張尺度適財關家標準（CNS)A4規格⑵Q χ挪公爱） .^1 n I I I! I . > I I 1 eJ I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 4 6 6 6 1 5 A7 ------- B7 五、發明說明（5 ) 1998年 1 1 月給 KizilyalH et al.的 IEEE Electron Letters 第 19册， 編號11，題目爲金氧半導體積體電路縮小十億倍整合技術 具堆疊Si〇2-Ta2〇5_Si〇2閘極介電質的M0S電晶體。上述標註 的專利和文章的這些發明在此併入當成參考。然而有趣且 値得注意的是那與縮小閘極介電質層降低等效電氣厚度的 看法致，本發明消除上述標註的專利、母應用和R〇y ei ai.與Kizilyalh的文章所討論沈積的氧化層。結果藉由選擇 非多晶矽的閘極材料，閘極電極可以直接分佈在高k材料 上（例如五氧化二麵）。 藉由前面分佈在高k材料上的沈積二氧化矽層，應用者 可以實際上得到一些好處，如上述的參考，等效電氣厚度 減少°另外’消除了介電質堆疊中二氧化矽層的上層，增 加了電容量。這是依照堆疊介電質層的電容結構相當於串 聯電容的事實。結果消除了沈積的氧化層増加電容，並且 使得分佈尺寸較厚的介電材料層成爲可能，因此處理極薄 層的危險和薄層二氧化矽的隧道問題可以避免。此外，藉 由直接在高k介電質上形成金屬閘極電極，可以消除沈積 的二氧化硬層之「緩衝層」。 回到圖1基底101爲單晶矽範例，具有相當薄的二氧化矽 層長在上面。這一層可以薄到3_8A的數量級，在65〇_85〇 C和低壓（小於i Torr)下加熱地成長s二氧化矽層爲介電質 堆4中的第一層並且當作矽基底的鈍化層來用。當加熱成 長的二氧化矽可以被快速熱氧化作用影響時，藉由低溫電 漿（LTP)氧化處理或UV臭氧處理執行的氧化步驟也在本發 -8- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --1,----；.------ 裝------ - —訂·----! — ··^ (請先閱讀背面之注意事項再填寫本頁) 466615 A7 B7 經濟部智慧財產局員工消費合作杜印製 五、發明說明（6 明的範圍中。紫外線波長輻射用來啓動臭氧，在這方面爲 已知的技術。電漿氧化可以用來製造長好的氧化層，在這 方面也是已知的普通技術。圖2爲一表格顯示低溫電漿和 UV臭氧處理的範例處理參數。最後有趣且値得注意的是當 基底爲可氧化的矽，可以使用其它的基底。這種基底包含 但不限於III- V族半導體和矽鍺半導體。 在二氧化梦層長出後’高介電係數材料1〇3沈積著。在 實施fe例中，103層爲五氧化二鈕它的沈積藉由有機金屬 化學氣象沈積（MOCVD)或其他在這方面普通的已知技術來 執行。 用來形成供壓力二氧化矽層的氧化/鍛鍊步驟是在65〇t 與大約0.9 Ton·下執行的，在氧化的環境（例如乂和〇2)結果 產生平面且無壓力矽和二氧化矽介面1〇5。這一層是從氧 化種子（在此情況下爲氧氣）的擴散傳遞形成的結果’厚度 爲3-5A的數量級。再一次在上述合作專利、專利申請案和 文章中含有關於無壓力氧化層的形成之更詳細内容。在氧 化/鍛鍊處理中，環境中的氧氣穿過高k層結果長在氧化層 的下方=藉由長出二氧化矽層與位於矽層ί〇1和高k介電層 1〇3間的無壓力氧化廣⑽之優,點，增加了高w電層的相位 轉換溫度。以i氧化」艇爲w ’晶體相位轉換溫度增加至 850-C的等級，·對大多數的避免五氧化4晶體化的處理Physics Letter Volume 72, numbered u, titled Stacked £ r, Metal Oxide Semiconductor Integrated Circuit Shrinks Billion Times Integrated Gate Dielectrics; and -7- This paper is a financially appropriate standard (CNS) A4 specifications ⑵ Q χ Norwegian public love). ^ 1 n III! I. ≫ II 1 eJ I (Please read the notes on the back before filling out this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives 4 6 6 6 1 5 A7 ------- B7 V. Description of the Invention (5) IEEE Electron Letters to KizilyalH et al., Volume 19, No. 11, November 1998, titled Gold Oxide Semiconductor Integrated Circuits Reduced by One Billion Times Integration The technology has a MOS transistor with stacked Si02-Ta205-5Si2 gate dielectric. The inventions of the above-identified patents and articles are incorporated herein by reference. However, it is interesting and noteworthy that it is related to the reduction of the gate dielectric layer to reduce the equivalent electrical thickness. The present invention eliminates the above-mentioned patents, parent applications, and Roy ei ai. Deposition discussed in the article with Kizilyalh Oxide layer. As a result, by selecting a non-polycrystalline silicon gate material, the gate electrode can be directly distributed on a high-k material (for example, two-sided pentoxide). By depositing the silicon dioxide layer on the high-k material previously, the user can actually get some benefits, such as the reference above, the equivalent electrical thickness is reduced ° and in addition, the silicon dioxide layer in the dielectric stack is eliminated. The upper layer increases the capacitance. This is based on the fact that the capacitance structure of the stacked dielectric layers is equivalent to a series capacitor. As a result, the added capacitance of the deposited oxide layer is eliminated, and it is possible to distribute a thicker layer of the dielectric material. Therefore, the danger of handling extremely thin layers and the tunneling problem of the thin silicon dioxide can be avoided. In addition, by forming a metal gate electrode directly on a high-k dielectric, the "buffer layer" of the hard dioxide layer deposited can be eliminated. Returning to FIG. 1, the substrate 101 is an example of single crystal silicon, and a relatively thin silicon dioxide layer is grown on it. This layer can be as thin as 3-8A, and it is heated to grow at 65-85 ° C and low pressure (less than i Torr). The silicon dioxide layer is the first layer in the dielectric stack 4 and serves as a passivation for the silicon substrate. Layer to use. When the thermally grown silicon dioxide can be affected by rapid thermal oxidation, the oxidation step performed by low-temperature plasma (LTP) oxidation treatment or UV-ozone treatment is also used in this paper. ) A4 specification (210 X 297 mm) --1, ----; .------ installed ----------order · ----! — · ^ (Please read first Note on the back, please fill out this page again) 466615 A7 B7 Consumer Cooperation of Intellectual Property Bureau of the Ministry of Economic Affairs Du printed 5. Invention Description (in the scope of 6). Ultraviolet wavelength radiation is used to activate ozone, which is a known technology in this respect Plasma oxidation can be used to make a good oxide layer, which is also a common technology known in this regard. Figure 2 is a table showing example processing parameters of low temperature plasma and UV ozone treatment. Finally, it is interesting and noteworthy that When the substrate is oxidizable silicon, other substrates can be used. Such substrates include but are not limited to III-V semiconductors and silicon germanium semiconductors. After the dream layer has grown, a high dielectric constant material 103 is deposited. In the embodiment, the 103 layer is a button of pentoxide. Metal Chemical Meteorological Deposition (MOCVD) or other commonly known techniques in this regard are performed. The oxidation / exercise steps used to form the supply pressure silicon dioxide layer are performed at 65 ° and approximately 0.9 Ton. The environment (such as 乂 and 〇2) results in a flat and pressure-free silicon and silicon dioxide interface 105. This layer is formed as a result of the diffusion transfer of oxidized seeds (in this case oxygen) 'thickness 3- On the order of 5A. Once again, the above-mentioned co-patent, patent application and article contain more detailed information on the formation of a pressure-free oxide layer. In the oxidation / exercise process, oxygen in the environment passes through the high-k layer and results in oxidation. Beneath the layer = By growing a silicon dioxide layer and the pressure-free oxidation between the silicon layer ΙΟ1 and the high-k dielectric layer 103, the advantages of the point are increased, and the phase transition temperature of the high-w layer is increased. "I-oxidation" boat is used to increase the crystal phase transition temperature to 850-C, and for most of the treatments to avoid crystallization of pentoxide-4
步驟高的恰好合適。另外一方面’如果想要更增加高W 電層晶體的相位轉換溫度，適當地佈植或加入些雜質。在 本實施範例巾，五氧化二起的高k層在適當的用量和能 -9- 本紙張尺度適用_國國家標準（CNS)A4規格（210 X 297公釐〉 --------.—, — 11! -----1--訂---------竣 (請先閱讀背面之ii意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 466615 A7 ______B7___ 五、發明說明（7 ) 下可以佈植氮’或加入適當濃度的鋁。這可以增加相位轉 換溫度到大約950°C，對源極/渠極作用鍛鍊步驟是高的给 好合適。 藉由在這方面已知的普通技術，使閘極電極1〇4分佈在 介電材料層上。閘極電極包含金屬，例如鎢或WxSiy。然而 本發明可以使用其他的金屬。這些包括，但不限於氮妙化 物（例如WSixNy、TaSixNy和MoSixNy);和金屬氮化物（例如 輕、飲和ί目的氮化物）。最後本發明預料多層的閘極電椏 材料之使用，例如WxSiy\WSixNy\WxSiy。在範例具體實施例 中，閘極電極爲一非多晶矽的材料。 在本應用中，介電材料層大多參考到具有等效電氣厚度 在2.5 nm或更低數量級且至少有一層非二氧化梦的閘極層 。在範例具體實施例中，介電材料層是長出的氧化層具有 典壓力的氧化層長在其下方，以及至少有—層高k介電材 料層在其上。這高k介電材料層具等效電氣厚度（再次相對 於二氧化矽）在〇.5至1〇11111的數量級。這轉換到五氧化二鈕 層的尺寸有大約3.0到6.0 nm的厚度。這是一個用來説明的 厚度範圍，五氧化二鈕層的厚度有可能爲15〇nm。注意五 氧化二钽爲高k材料的一範例是重要的，我們要清楚地明 白也可以用其他的材料。特別是二氧化錯、二氧化鈦和鈣 鈦材料可以用來影響本發明的高介電係數極薄閘極介電質 結構。最後，我們相信除了上述提到的材料或化合物外， 在這方面的普通技術範圍中其他材料、材料组合或這種材 料堆叠彳以用來形成介電質#料層達成想要的25A或更低 _ -10- 成張尺度適用中關家標举（CNS)A4規格（210 X 297公f )"-------- ----------I I I I ^ -------訂---！-線 f請先閱靖背面夂注意事項再填寫本頁> 466615 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（8 ) 的等效電氣厚度。然而在任何情況下，選擇的閘極材料不 應該對介電材料層的介電質性質有不利的影響。例如，如 上討論’多晶硬不應該直接分佈在許多上述討論的高k材 料上’因爲它增加高k材料層的漏電流，因此降低它的介 電質的性質。 本發明的高k介電材料堆疊預料使用在具高效能類比和 混合信號CMOS電路的積體電路上。具類比和混合信號 CMOS電路在一矽1C上的能力，從成本和製造的複雜性角度 看’比起在坤化鎵和SiGe爲基底的元件上具有重要的優勢 °此降低等效電氣厚度的能力使得縮小和整合上改良成爲 可能的。一組通常參考的縮小的規則用來當作導引，使用 那些技術中選擇的材料參數、結構和相對的物理尺寸。 MOS元件物理分析和縮小規則可由p〇iss〇n方程式和電流密 度方程式導出。因爲感謝這方面的普通技術，在M〇s元件 中閘極長度縮小時常要需要達到最小化。爲要完成降低閘 極長度’乳化厚度（Ιχ)必須降低到維持一特殊的比率^然 而如上討論，從處理觀點來看，極薄層的二氧化矽的製程 可能相當複雜。此外’當二氧化矽層太薄時，隧道、效應可 能成爲問題，通道控制參數可能被不利地影響。 如所説明，藉由消除沈積的二氧化矽層可以有許多優點 ;特別的優點是降低等效電氣厚度和能夠符合縮小規則的 參數縮小元件尺寸。藉由這些能力的優點來縮小氧化層的 等效電氣厚度，閘極的長度LG可以按比例地降低，藉由減 少LG，内部的跨導gm可以增加。如同在這方面已知的普通 -11 - 本紙張尺度適用中國囤家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝-----I--訂---------破 經濟部智慧財產局員工消費合作社印製 466615 A7 ___B7____ 五、發明說明（9 ) 技術，内部的跨導gm可以大約估爲 ί Λ ^ \ ε OX 'Vsar §Λτ)τ ⑴ 丹中sQX爲閘極介電材料層的介電係數，vsat是飽合速度。 結果藉由本發明的優點縮小間極長度導致增加元件的跨 導。此外，降低閘極長度的能力導致增加飽合速度和增加 截止頻率&，由下式 f \ ft VsarThe steps are just right. On the other hand, if you want to increase the phase transition temperature of the high W electric layer crystal, implant or add some impurities appropriately. In this example towel, the high-k layer from pentoxide is in the proper amount and energy. -9- This paper size applies _ National Standard (CNS) A4 specification (210 X 297 mm> ------- -.—, — 11! ----- 1--Order --------- End (Please read the notice on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 466615 A7 ______B7___ 5. Description of the invention (7) Nitrogen can be planted or an appropriate concentration of aluminum can be added. This can increase the phase transition temperature to about 950 ° C. It is good for the source / drain effect. The gate electrode 104 is distributed over the dielectric material layer by common techniques known in this regard. The gate electrode contains a metal such as tungsten or WxSiy. However, other metals can be used in the present invention. These include, But it is not limited to nitrogen compounds (such as WSixNy, TaSixNy, and MoSixNy); and metal nitrides (such as light, drinking, and high-order nitrides). Finally, the present invention anticipates the use of multilayer gate electrode materials, such as WxSiy \ WSixNy \ WxSiy. In the exemplary embodiment, the gate electrode is a non-polycrystalline silicon material. In this application, the dielectric material layer mostly refers to a gate layer having an equivalent electrical thickness of the order of 2.5 nm or less and at least one layer of non-dioxide dream. In the exemplary embodiment, the dielectric material layer is grown out The oxide layer with a typical pressure is grown below it, and there is at least one layer of high-k dielectric material on it. This high-k dielectric material layer has an equivalent electrical thickness (again relative to silicon dioxide) at On the order of 0.5 to 1011111. This translates to the size of the pentoxide layer having a thickness of about 3.0 to 6.0 nm. This is a range of thicknesses used to illustrate that the thickness of the pentoxide layer may be 15 〇nm. It is important to note that tantalum pentoxide is an example of a high-k material, we must clearly understand that other materials can also be used. In particular, titanium dioxide, titanium dioxide and perovskite materials can be used to affect the high Dielectric constant thin gate dielectric structure. Finally, we believe that in addition to the materials or compounds mentioned above, other materials, combinations of materials, or stacks of such materials are used in the general technical scope in this regard. Chengdielectric #material layer achieves the desired 25A or lower_ -10- The scale is applicable to the Zhongguanjia Standard (CNS) A4 specification (210 X 297 male f) " --------- -------- IIII ^ ------- Order ---!-Line f Please read the note on the back of Jing and fill in this page before printing.> 466615 Printed by the Employees ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 5. The equivalent electrical thickness of the invention description (8). However, in any case, the selected gate material should not adversely affect the dielectric properties of the dielectric material layer. For example, as discussed above, 'polycrystalline hardness should not be directly distributed on many of the high-k materials discussed above' because it increases the leakage current of the high-k material layer and therefore reduces its dielectric properties. The high-k dielectric material stack of the present invention is expected to be used in integrated circuits with high-performance analog and mixed-signal CMOS circuits. With the ability of analog and mixed-signal CMOS circuits on a silicon 1C, from the perspective of cost and manufacturing complexity, it has important advantages over components based on gallium and SiGe. This reduces the equivalent electrical thickness. Capabilities make it possible to reduce and integrate improvements. A commonly referenced set of reduced rules is used as a guide, using the material parameters, structure, and relative physical dimensions selected in those techniques. MOS device physical analysis and reduction rules can be derived from the poisson equation and the current density equation. Thanks to the common technology in this area, gate length reduction in Mos devices often needs to be minimized. To accomplish the reduction of the gate length, the emulsification thickness (Ix) must be reduced to maintain a specific ratio. However, as discussed above, from a processing point of view, the fabrication of very thin layers of silicon dioxide can be quite complicated. In addition, when the silicon dioxide layer is too thin, tunneling, effects may become a problem, and channel control parameters may be adversely affected. As illustrated, there are many advantages by eliminating the deposited silicon dioxide layer; a particular advantage is that the equivalent electrical thickness is reduced and the size of the component can be reduced by parameters that meet the reduction rules. By virtue of the advantages of these capabilities to reduce the equivalent electrical thickness of the oxide layer, the gate length LG can be proportionally reduced, and by reducing LG, the internal transconductance gm can be increased. Ordinary as known in this area -11-This paper size is applicable to China Store Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling out this page) Loading ----- I--Order --------- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 466615 A7 ___B7____ V. Description of Invention (9) Technology, the internal transconductance gm can be estimated as ί Λ ^ \ ε OX 'Vsar §Λτ) τ ⑴ sQX in Dan is the dielectric constant of the gate dielectric material layer, and vsat is the saturation velocity. As a result, reducing the interelectrode length by virtue of the present invention results in an increase in the transconductance of the element. In addition, the ability to reduce the gate length results in increased saturation speed and increased cut-off frequency & by f \ ft Vsar
Jt{2LJ (2) 其中ft爲截止頻率。 最後，顯示出降低的\、增加的Vsat和增加的“；有效的 ft既有增加了且在一範圍的負載電容Cl—下幾乎爲一常數。 本發明使得t〇x可以在20A的數量級，下面的；^可以在〇18微 米或更小的數量級，元件具有數量級爲3〇 GHz以及更高的 截止頻率；相當合適於類比和混合信號的CM〇s電路。 本發明廣泛應用到不同的積體電路，包含但不限於邏輯 、DRAM、FLASH與類比和混合信號CM〇s電路。當高介電 係數的五氧化二钽層壓抑漏電流時，高品質的矽與二氧化 矽介面導致非常低的介面陷阱密度^最後鎢金屬消除與多 晶秒間極電極的耗損問I本發明結果在改良閘極介電質 的可靠性，降低閘極漏電流，低的臨限電壓，改進子臨限 特性和低電壓雙閘極的應用性β 本發明已詳細説明過，我們清楚對本發明以及上述内容 的變動和修改都會明顯的成爲這方面的普通技術，這些修 改產生此陳述之改良特性的極薄的問極介電質結構爲此技 術的延伸，這些更改是在本發明的範圍内。 ；_ - 12- 本紙張尺度適用中國國家標準（CNS)A4規格（210 297公釐） C請先閱讀背面之注意事項再填寫本頁) ，裝--------訂---- 峻Jt {2LJ (2) where ft is the cutoff frequency. Finally, it is shown that the lowered, increased Vsat, and increased; effective ft has been increased and is almost a constant under a range of load capacitance Cl. The present invention allows t0x to be on the order of 20A, The following; ^ can be on the order of 018 microns or less, the component has a cutoff frequency on the order of 30 GHz and higher; quite suitable for analog and mixed-signal CMOS circuits. The invention is widely applied to different products Body circuits, including but not limited to logic, DRAM, FLASH and analog and mixed-signal CMOS circuits. When high dielectric constant tantalum pentoxide laminates suppress leakage current, high-quality silicon and silicon dioxide interfaces result in very low The density of the interface trap ^ Finally, the elimination of tungsten metal and the loss of the polycrystalline inter-electrode electrode The results of the present invention improve the reliability of the gate dielectric, reduce gate leakage current, low threshold voltage, and improve sub-threshold characteristics And low-voltage dual-gate applicability β The present invention has been described in detail. We clearly understand that changes and modifications to the present invention and the above content will obviously become common techniques in this regard. These modifications The extremely thin interlayer dielectric structure that produces the improved characteristics of this statement is an extension of this technology, and these changes are within the scope of the present invention; _-12- This paper size applies the Chinese National Standard (CNS) A4 specification (210 297 mm) C Please read the notes on the back before filling this page)