TW201532241A - Integrated circuit device and method for manufacturing the same - Google Patents

Abstract

A method of forming an integrated circuit device includes forming dummy gates over a semiconductor substrate, depositing a first dielectric layer over the dummy gates, chemical mechanical polishing to recede the first dielectric layer to the height of the dummy gates, etching to recess the first dielectric layer below the height of the gates, depositing one or more additional dielectric layers over the first dielectric layer, and chemical mechanical polishing to recede the one or more additional dielectric layers to the height of the gates. The method provides integrated circuit devices having metal gate electrodes and an inter-level dielectric at the gate level that includes a capping layer. The capping layer resists etching and preserves the gate height through a replacement gate process.

Description

Compound structure for gate interlayer dielectric layer

The present invention relates to an integrated circuit device, and more particularly to an integrated circuit device having a high dielectric constant dielectric layer and a metal gate formed by a gate post process.

In order to increase device density, the subject of research over the years has been to reduce the critical size (CD) of integrated circuit devices. The above findings replace the conventional gate structure with a high-k dielectric layer and a metal gate. The high-k dielectric layer has a higher capacitance than the yttria layer of the same thickness. A metal gate with a suitable work function avoids charge carrier consumption near the high-k dielectric layer and the gate interface. Gates for p-type and n-type transistors require different materials to provide an appropriate work function.

The process used to form the source and drain regions is not conducive to the metal suitable for the gate. In a particular embodiment, repairing the tempering process of source and drain implant damage may alter the work function of the metal gate. The above problems have led to a variety of new process technologies, such as replacement gate (or post gate) processes. In the replacement gate process, a gate stack is formed first with polysilicon instead of metal. After the source and drain regions are formed, the polysilicon is then removed to form trenches, and the desired gate metal is filled into the trenches.

1 is a flow chart of a process in an embodiment of the present invention.

2 to 11 are schematic views showing the formation of an integrated circuit device in accordance with the process of Fig. 1 in another embodiment of the present invention.

12 to 13 are schematic views showing a device for forming an integrated circuit in the process of Fig. 1 in still another embodiment of the present invention.

In the prior art, removing the dummy gate process may cause an unexpected height reduction of the gate, which may adversely affect device performance. The method for solving the above problem is that the interlayer dielectric layer (ILD0) having the same height as the gate is a composite of two or more layers, which is higher in resistance to the etching process for removing the dummy gate than the upper layer. The composite ILD0 maintains a good gate height during the gate replacement process and allows the metal gate integrated circuit device to have a relatively predictable and consistent height.

1 is a flow chart of a process 100 in an embodiment of the invention. 2 through 11 are schematic views of another embodiment in which the circuit device 10A is formed by the process 100. 12 through 13 are schematic views of a circuit device 10B formed by a process 100 in yet another embodiment.

The process 100 proceeds to step 111 to provide the substrate 19. The substrate 19 has a suitable isolation region 11. A series of steps 112 are then performed to form a separate transistor on the substrate 19. Step 112 includes steps 115, 117, and 119. Step 115 forms a dummy gate stack, step 117 patterns the dummy gate stack to form a dummy gate, and step 119 forms source/drain regions 23. These steps can be adjusted generally without departing from the scope of the invention. These steps form the structure shown in Fig. 2.

Substrate 19 can be any suitable substrate that includes a semiconductor body. Suitable substrates include, but are not limited to, germanium, germanium on insulator (SOI), germanium, tantalum carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or germanium. The isolation region 11 is typically a shallow trench isolation (STI) region, but may also be a local oxide germanium (LOCOS) or other suitable process isolation region. Substrate 19 can be doped via any suitable means. In most embodiments, substrate 19 has a PMOS region 9 and an NMOS region 13 after doping.

As shown in FIG. 2, the dummy gate 41 includes a high-k dielectric layer 15 and a dummy gate 47. The high-k dielectric layer 15 comprises one or more layers of high dielectric constant material. In most embodiments, the conductivity of the high-k dielectric layer 15 is at least five times greater than the conductivity of yttrium oxide. The high-k dielectric layer may be a ruthenium-based material such as ruthenium oxide, ruthenium oxide, ruthenium oxynitride, ruthenium oxide, ruthenium iridium oxide, yttrium zirconium oxide, or yttria-oxidized aluminum alloy. Other high-k dielectric layers may include, but are not limited to, zirconia, yttria, alumina, yttria, yttria, yttrium titanium oxide, or combinations thereof. In most embodiments, the high-k dielectric layer 15 has a thickness between 5 Å and 50 Å.

The dummy gate 47 may optionally include additional layers (not shown). For example, the interfacial layer can naturally produce the result of oxidation between the high-k dielectric layer 15 and the substrate 19. A cap layer may also be formed between the high-k dielectric layer 15 and the dummy gate 47 to protect the high-k dielectric layer 15 during the process of removing the dummy gate 47 (step 149).

The dummy gate 47 is formed of a sacrificial layer, and its composition may be any composition suitable for its function. In most embodiments, the dummy gate 47 is polysilicon. The thickness of the dummy gate 47 is approximately the initial height 54A. In a typical embodiment, the initial height 54A is between 800 Å and 1500 Å.

Step 411 forms source/drain regions 23 including forming one or more sidewall spacers adjacent to dummy gates 47. Most of the embodiments include at least an oxide-based sidewall spacer 27 and a nitride-based sidewall spacer 31, as shown in FIG. Step 117 patterns the dummy gate stack layer to form the dummy gate stack 41, and typically forms the native oxide layer 43 as shown in FIG. The oxide-based sidewall spacers 27 and the nitride-based sidewall spacers 31 control the dopant distribution when the source/drain regions 23 are formed. In most embodiments, the source/drain regions 23 are germanides. The oxide-based sidewall spacers 27 and the nitride-based sidewall spacers 31 can also be used to control the deuteration process. As shown in Fig. 2, the nitride-based sidewall spacer 31 forms the cap layer 52 on the dummy gate 47.

In most embodiments, the oxide-based sidewall spacers 27 are formed of a dielectric material that is the same as the ruthenium oxide. For example, the oxide-based sidewall spacers 27 can be one or more layers of materials (such as hafnium oxide and tantalum carbonium oxide). In most embodiments, the nitride-based sidewall spacers 31 are one or more layers of material (such as tantalum nitride or other dielectric materials that are similar in etching properties to tantalum nitride). In a typical embodiment, the cap layer 52 comprised of nitride-based sidewall spacers 31 has a thickness between 30 Å and 200 Å.

The process 100 then proceeds to step 123 to deposit a yttria-based interlayer dielectric layer 35 as shown in FIG. A yttria-based interlayer dielectric layer 35 is filled in and overflows into the space 50 between the dummy gate stacks 41. In most embodiments, the yttria-based interlayer dielectric layer 35 is yttrium oxide. In a typical embodiment, the yttria-based interlayer dielectric layer 35 is deposited to a thickness between 2000 Å and 5000 Å. The method of forming the yttrium oxide-based interlayer dielectric layer 35 in step 123 may be any suitable process, and a process having excellent gap filling characteristics is generally selected. In some embodiments The deposition method of the interlayer dielectric layer 35 mainly composed of cerium oxide is a fluid oxide precursor. In some embodiments, the deposition method of the yttria-based interlayer dielectric layer 35 is a high density plasma (HDP) process. In some embodiments, the deposition method of the yttria-based interlayer dielectric layer 35 is a high aspect ratio (HARP) process such as a sub-atmospheric pressure CVD process using ozone with tetraethoxy decane (TEOS).

Step 127 is a chemical mechanical polishing process that planarizes the yttrium oxide-based interlayer dielectric layer 35 and reduces it to the dummy gate cap layer 52, as shown in FIG. The CMP process of step 127 can be selected to selectively remove the yttria-based interlayer dielectric layer 35 rather than the cap layer 52.

Step 131 is an etching process to recess the yttria-based interlayer dielectric layer 35 to be lower than the initial height 54A of the dummy gate stack 41, as shown in FIG. In a typical embodiment, step 131 etches the yttrium oxide-based interlayer dielectric layer 35 until it is recessed to be 150 Å to 500 Å lower than the initial height 54A of the dummy gate stack 41. In a typical embodiment, the yttria-based interlayer dielectric layer 35 retained in the above steps has a height 48 between 300 Å and 1350 Å. The etching process of step 131 may be wet etching or dry etching, and the interlayer dielectric layer 35 mainly composed of yttrium oxide may be selectively removed instead of the nitride-based sidewall spacer 31.

Step 135 etches away all or a portion of the exposed nitride-based sidewall spacers 31 as shown in FIG. Step 135 can be performed as appropriate. If step 135 is performed, the resulting structure will be slightly different. In summary, Fig. 12 forms the device 10B. Other processes performed on device 10B are similar to those performed on device 10A in Figures 6 through 11, as described in the following. Step 135 etch back the nitride-based sidewall spacers 31 to widen the space 50 between the dummy gate stacks 41 to improve subsequent gap fill. In most of the examples In step 135, the nitride-based sidewall spacer 31 is recessed to the height of the yttrium oxide-based interlayer dielectric layer 35. Step 135 can be dry etching to selectively remove the tantalum nitride-based dielectric layer instead of the hafnium oxide-based dielectric layer and polysilicon.

Step 141 deposits an interlayer dielectric cap layer 51 as shown in FIG. The interlayer dielectric cap layer 51 can comprise one or more layers of any suitable composition. The proper composition of the interlayer dielectric cap layer 51 is more resistant to etching of the dummy gate 47 in subsequent processes (e.g., step 149) than the composition of the interlayer dielectric layer 35 dominated by yttrium oxide. The resistivity and the dielectric constant are generally difficult to achieve, so that the dielectric constant of the interlayer dielectric cap layer 51 of most of the embodiments is larger than the dielectric constant of the interlayer dielectric layer 35 mainly composed of yttrium oxide. In a typical embodiment, the composition of the interlayer dielectric cap layer 51 is a compound of ruthenium or iridium oxide with one or more of the following: carbon, nitrogen, and boron. In a general embodiment, the composition of the interlayer dielectric cap layer 51 is tantalum nitride, tantalum nitride, tantalum boride, tantalum carbonitride, tantalum carbide, niobium oxynitride, niobium oxynitride, or a combination thereof. In some embodiments, the interlayer dielectric cap layer 51 has a thickness between 500 Å and 1000 Å. The interlayer dielectric cap layer 51 can be deposited by any suitable process, such as atomic layer deposition (ALD), plasma enhanced CVD (PE-CVD), or high plasma density CVD (HPD-CVD).

In some embodiments, the interlayer dielectric cap layer 51 comprises two or more layers. Taking FIG. 7 as an example, the interlayer dielectric cap layer 51 includes a first layer 51A and a second layer 51B. In most embodiments, the first layer 51A is formed by ALD to provide good gap fill. The second layer 51B can be deposited by a lower cost process such as PE-CVD or HPD-CVD. In some embodiments, the first layer 51A and the second layer 51B of the interlayer dielectric cap layer 51 each have a thickness of between 250 Å and 500 Å.

Process 100 then proceeds to step 145 where a CMP process is performed to expose dummy gate 47, as shown in FIG. The CMP process of step 145 selectively removes the material of the interlayer dielectric cap layer 51 instead of the dummy gate 47. In the general embodiment, the CMP process of step 145 reduces the initial height 54A of the dummy gate stack 41 to a height 54B. In some embodiments, the initial height 54A of the dummy gate stack is reduced by 100 Å to 300 Å. In certain embodiments, step 145 reduces the initial height 54A of the dummy gate stack to a height 54B between 600 Å and 1300 Å, which is the appropriate gate height for many inventions. In some embodiments, step 145 reduces the initial height of the dummy gate stack by 5% to 25%.

The CMP process of step 145 is thinned rather than completely removing the interlayer dielectric cap layer 51. When the interlayer dielectric cap layer 51 is the multilayer structure shown in FIG. 7, the CMP process will completely remove the second layer 51B of the upper layer, but retain at least a portion of the first layer 51A of the lower layer. In a typical embodiment, the portion of the interlayer dielectric cap layer 51 remaining between 70 Å and 300 Å is sufficient to provide the desired corrosion resistance, but does not excessively increase the dielectric constant of the overall interlayer dielectric layer 7. . In other words, the interlayer dielectric cap layer 51 after the CMP process of step 145 generally occupies 5% to 45% of the overall thickness of the interlayer dielectric layer 7.

Step 100 then proceeds to step 149 to remove the dummy gate 47 as shown in FIG. The dummy gate 47 can be removed by any suitable process. In most embodiments, the step of removing the dummy gate 47 in step 149 is a dry etching process, and the etching process conditions selectively remove the material of the dummy gate 47 instead of the interlayer dielectric cap layer 51. In most embodiments, the etch selectivity of this step is greater than the etch selectivity between the dummy gate 47 and the yttria-based interlayer dielectric layer 35. In some embodiments, the process of step 149 has a much higher etch selectivity for polysilicon than nitridation. Hey. The general process of step 149 is plasma etching using a mixture of fluoroform, hydrogen bromide, and oxygen. Other process conditions include pressure (between 10mT and 20mT), power supply (between 500W and 1000W), and power supply bias (between 10W and 30W).

Step 153 deposits metal to replace the removed dummy gate stack 47, as shown in FIG. In certain embodiments, the metal 53 comprises a multilayer structure of a different composition. In some embodiments, the metal 53 in the PMOS region 9 is different from the metal 53 in the NMOS region 13. The bottom layer of the metal 53 may be a work function metal including, but not limited to, titanium, titanium nitride, tantalum nitride, tantalum, tantalum carbide, tantalum nitride, tungsten, tungsten nitride, molybdenum nitride, and molybdenum oxynitride. Or multilayer structure. The additional metal layer may comprise one or more intermediate layers or top layers, which may be of any suitable metal, including but not limited to germanium, palladium, platinum, cobalt, nickel, cerium, zirconium, titanium, hafnium, aluminum, conductive carbonization as described above. The above-mentioned conductive oxide or the above alloy. The method of forming these metal layers can be any suitable process or a combination thereof. Physical vapor deposition (PVD) is a general process. The formation process of other metal layers may be electroplating, electroless plating, ALD, or CVD.

The process 100 then proceeds to step 157 to remove the additional metal 53 on the interlayer dielectric cap layer 51 by CMP to form the metal gate 55 on the substrate 19, as shown in FIG. Figure 13 shows the results of device 10B using step 135 as appropriate to etch back the tantalum nitride layer. The CMP process condition of step 157 removes the metal 53 instead of the interlayer dielectric cap layer 51. In most embodiments, the selectivity of this CMP step is higher than the selectivity of CMP for metal 53 and yttrium oxide-based interlayer dielectric layer 35. In summary, the interlayer dielectric cap layer 51 can effectively maintain the height 54B of the metal gate during the CMP process of step 157.

As shown in FIGS. 11 and 13, in the final structure formed in step 157, the interlayer dielectric layer 7 includes an interlayer dielectric layer 35 mainly composed of yttrium oxide and an interlayer dielectric cap layer 51. The interlayer dielectric layer 7 fills the width 56 of the space 50 between the metal gates 55. In most embodiments, the yttrium oxide-based interlayer dielectric layer 35 is the main constituent of the interlayer dielectric layer 7, and determines most of the electrical properties of the interlayer dielectric layer 7. When the thickness 58 of the yttrium oxide-based interlayer dielectric layer 35 is at least half of the height 54B of the gate, the thickness thereof is substantially smaller than the height of the metal gate 55. On the other hand, the upper surface 60 of the interlayer dielectric cap layer 51 and the upper surface 62 of the metal gate are approximately coplanar.

The cross-sectional area of the interlayer dielectric layer 7 and its sub-layers (such as the yttria-based interlayer dielectric layer 35 and the interlayer dielectric cap layer 51) increases as the height increases. The above-described structure is formed by the shape of the oxide-based sidewall spacer 27 and the nitride-based sidewall spacer 31, and the interlayer dielectric layer 7 is formed later than the sidewall spacer. Taking the device 10B as an example, the nitride-based sidewall spacers 31 are raised to the same level as the yttrium oxide-based interlayer dielectric layer 35, that is, the two are approximately coplanar.

The integrated circuit device provided by the present invention comprises: a plurality of transistors on a semiconductor body, the transistor having a plurality of separate metal gates, and the metal gate having a height; the first dielectric structure including one or more The electrical layer traverses a spatial width between adjacent metal gates, the first dielectric structure having a thickness wherein the thickness is substantially the same as the height of at least half of the metal gates, but substantially less than the height of the metal gates. The second dielectric structure includes one or more dielectric layers and is formed on the first dielectric structure, and the top of the second dielectric structure is near the top of the metal gate. The top of the first dielectric structure is different from the composition of the bottom of the second dielectric structure. The second dielectric structure acts as a cap layer and helps control the gate height during the process.

The integrated circuit device provided by the present invention comprises a semiconductor body; an interlayer dielectric layer formed on the semiconductor body and at the same height as the gate; and a metal gate having a gate height. The interlayer dielectric layer has two dielectric layers of different compositions. The upper dielectric layer in the interlayer dielectric layer is coplanar with the top of the metal gate. The upper dielectric layer in the interlayer dielectric layer is more resistant to the etching process than the lower dielectric layer in the interlayer dielectric layer, and the etching process includes fluoroform, hydrogen bromide, and oxygen etching gas, which is suitable for Remove the dummy gate of the polysilicon.

The invention provides a method for forming an integrated circuit device, comprising: providing a semiconductor substrate; forming a dummy gate on the semiconductor substrate; depositing a first dielectric layer on the dummy gate; performing chemical mechanical polishing to reduce the first dielectric layer a height to the dummy gate; etching the first dielectric layer to recess it to a height lower than the gate; depositing one or more additional dielectric layers on the first dielectric layer; and performing chemical mechanical polishing to The or the additional dielectric layers are reduced to the height of the gate.

The components and structures of the present invention have been shown and/or illustrated in conjunction with the above-described embodiments and examples. A particular component or structure or component or structure is used to describe an embodiment or example, and all components or structures may be combined with other components or structures, as known to those of ordinary skill in the art. .

Claims (20)

An integrated circuit device comprising: a semiconductor body; a plurality of transistors on the semiconductor body, the transistors having a plurality of separate metal gates, and the metal gates having a height; a first dielectric structure Having one or more dielectric layers and traversing a width of a space between adjacent metal gates, the first dielectric structure having a thickness, wherein the thickness and at least half of the metal gates The height is substantially the same, but is substantially smaller than the height of the metal gates; and a second dielectric structure includes one or more dielectric layers formed on the first dielectric structure, and the second dielectric The top of the structure is near the top of the metal gate; wherein the top of the first dielectric structure is different from the composition of the bottom of the second dielectric structure. The integrated circuit device of claim 1, wherein the second dielectric structure is more resistant to a plasma etch than the first dielectric structure is resistant to the plasma etch, the plasma The etching is suitable for removing the polysilicon dummy gate, and the etching gas used for the plasma etching includes fluoroform, hydrogen bromide, and oxygen. The integrated circuit device of claim 1, wherein: the first dielectric structure comprises ruthenium oxide; and the second dielectric structure is tantalum nitride, tantalum carbide, niobium oxynitride, tantalum nitride carbon , lanthanum boride, lanthanum boride, niobium oxynitride, or a mixture thereof. The integrated circuit device of claim 1, wherein a cross-sectional area of the first dielectric structure and the second dielectric structure increases with height. The integrated circuit of claim 1, further comprising a plurality of sidewall spacers formed adjacent to the metal gate, and a height of the sidewall spacers and a height of the first dielectric structure Same on the same. The integrated circuit device of claim 1, wherein the first dielectric structure has a thickness of between 600 Å and 1300 Å, and the second dielectric structure has a thickness of between 70 Å and 300 Å. The integrated circuit device of claim 6, wherein the first dielectric structure and the second dielectric structure are each a single layer structure. An integrated circuit device comprising: a semiconductor body; an interlayer dielectric layer formed on the semiconductor body and having a height equal to a gate; a metal gate having the gate height; wherein the interlayer dielectric layer Two dielectric layers having different compositions; the upper dielectric layer of the interlayer dielectric layer is coplanar with the top of the metal gate; and the upper dielectric layer of the interlayer dielectric layer is etched The process resistance is higher than the lower dielectric layer in the interlayer dielectric layer, and the etching process includes fluoroform, hydrogen bromide, and an etching gas with oxygen, which is suitable for removing the dummy gate of the polysilicon. The integrated circuit device of claim 8, wherein: the lower dielectric layer of the interlayer dielectric layer is yttrium oxide; and the upper dielectric layer of the interlayer dielectric layer is ruthenium or oxidized. a compound of at least one of carbon, nitrogen, and boron. The integrated circuit device of claim 8, wherein an upper dielectric layer in the interlayer dielectric layer is slightly larger than a lower dielectric layer in the interlayer dielectric layer. The integrated circuit device of claim 8, wherein the thickness of the upper dielectric layer in the interlayer dielectric layer is about 5% to 40% of the height of the metal gate. The integrated circuit device of claim 11, wherein the thickness of the lower dielectric layer in the interlayer dielectric layer is about 60% to 95% of the height of the metal gate. The integrated circuit device of claim 8, wherein a lower dielectric layer of the interlayer dielectric layer has a dielectric constant lower than a dielectric layer of the upper dielectric layer of the interlayer dielectric layer. constant. A method for forming an integrated circuit device includes: providing a semiconductor substrate; forming a dummy gate on the semiconductor substrate; depositing a first dielectric layer on the dummy gate; performing chemical mechanical polishing to make the first Reducing a dielectric layer to a height of the dummy gate; etching the first dielectric layer to recess it to a height lower than a gate; depositing one or more additional dielectric layers on the first dielectric layer And performing a chemical mechanical polishing to reduce the or the additional dielectric layer to the height of the gate. The method of forming an integrated circuit device according to claim 14, wherein the step of depositing the or the additional dielectric layer comprises depositing at least two External dielectric layer. The method of forming an integrated circuit device according to claim 15, wherein the deposition step of one additional dielectric layer is atomic layer deposition, and the deposition step of another additional dielectric layer is another process. The method for forming an integrated circuit device according to claim 14, further comprising: forming sidewall spacers on sidewalls of the dummy gate; and etching the first dielectric layer to recess it below After the height of the gate, and prior to depositing the or the additional dielectric layers, the sidewall spacers are etched to recess them. The method for forming an integrated circuit device according to claim 17, wherein the height of the sidewall spacers after recessing is equal to the height of the recessed first dielectric layer. The method for forming an integrated circuit device according to claim 14, further comprising: etching and removing the dummy gate; wherein the or the additional dielectric layer is an etching process for removing the dummy gate The resistance is higher than the resistance of the first dielectric layer to the etching process for removing the dummy gate. The method for forming an integrated circuit device according to claim 14, wherein the first dielectric layer is a ruthenium oxide-based material, and the additional dielectric layer is tantalum or tantalum oxide and carbon, a compound of at least one of nitrogen and boron.