CN113113309B - Method for forming semiconductor structure - Google Patents
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- CN113113309B CN113113309B CN202010032652.9A CN202010032652A CN113113309B CN 113113309 B CN113113309 B CN 113113309B CN 202010032652 A CN202010032652 A CN 202010032652A CN 113113309 B CN113113309 B CN 113113309B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A method of forming a semiconductor structure, comprising: providing a substrate, and forming a pseudo gate structure on the substrate; forming an interlayer dielectric layer on the substrate, wherein the top of the interlayer dielectric layer is flush with or lower than the top surface of the dummy gate structure; forming a first covering layer on the surface of the pseudo gate structure; forming protective layers on the surface of the interlayer dielectric layer and the surface of the first covering layer; forming a second covering layer on the surface of the protective layer; carrying out planarization treatment on the second covering layer, the protective layer and the first covering layer until the surface of the pseudo gate structure is exposed; removing the pseudo gate structure to form an opening; and filling metal in the opening to form a metal gate. The forming method provided by the embodiment of the invention enables the forming height of the metal grid to be more easily controlled.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a semiconductor structure.
Background
MOS transistors are one of the most important components in modern integrated circuits. The basic structure of the MOS transistor includes: a semiconductor substrate; the semiconductor device comprises a grid structure positioned on the surface of a semiconductor substrate, a source region positioned in the semiconductor substrate on one side of the grid structure and a drain region positioned in the semiconductor substrate on the other side of the grid structure. The working principle of the MOS transistor is as follows: the switching signal is generated by applying a voltage to the gate structure to regulate current through the bottom channel of the gate structure.
With the development of semiconductor technology, the conventional planar MOS transistor has a weak ability to control channel current, resulting in a serious leakage current. Fin field effect transistors (Fin FETs) are emerging multi-gate devices, which generally include a Fin protruding from the surface of a semiconductor substrate, a gate structure covering a portion of the top surface and sidewall surfaces of the Fin, a source region in the Fin on one side of the gate structure, and a drain region in the Fin on the other side of the gate structure.
No matter the semiconductor device is a planar MOS transistor or a fin field effect transistor, the height control of the gate structure is poor.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure, which can effectively control the forming height of a metal gate.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, and forming a pseudo gate structure on the substrate; forming an interlayer dielectric layer on the substrate, wherein the top of the interlayer dielectric layer is flush with or lower than the top surface of the dummy gate structure; forming a first covering layer on the surface of the pseudo gate structure; forming protective layers on the surface of the interlayer dielectric layer and the surface of the first covering layer; forming a second covering layer on the surface of the protective layer; carrying out planarization treatment on the second covering layer, the protective layer and the first covering layer until the surface of the pseudo gate structure is exposed; removing the pseudo gate structure to form an opening; and filling metal in the opening to form a metal gate.
Optionally, the method for forming the interlayer dielectric layer includes: forming a dielectric material layer on the substrate, wherein the top of the dielectric material layer is higher than the top surface of the dummy gate structure; carrying out chemical mechanical grinding on the medium material layer to form an interlayer medium layer; and etching back the interlayer dielectric layer until the top of the interlayer dielectric layer is flush with or lower than the top surface of the dummy gate structure.
Optionally, the method for etching back the interlayer dielectric layer includes a Certas etching process or wet etching.
Optionally, the Certas etching process includes remote etching and in-situ annealing after the remote etching, where process parameters of the remote etching include: the etching atmosphere comprises NH 3 And HF 5 NH of said 3 The flow rate of the gas is 5-100 sccm, soHF as described 5 The flow rate of the gas is 5-100 sccm, and the etching temperature is 20-80 ℃; the annealing temperature of the in-situ annealing is 100-250 ℃.
Optionally, the wet etching process parameters include: adopting hydrofluoric acid solution as corrosive liquid, wherein the volume ratio of hydrofluoric acid to water is 50:1 to 1000:1.
optionally, the method further includes: before the interlayer dielectric layer is formed, forming an etching stop layer on the pseudo gate structure; and etching the etching stop layer after the interlayer dielectric layer is formed until the top of the etching stop layer is flush with the top of the interlayer dielectric layer.
Optionally, the method for etching the etching stop layer is dry etching, and the process parameters of the dry etching include: the etching atmosphere comprises CH 3 F and O 2 Said CH 3 The flow rate of the F gas is 10-500 sccm, and the O gas is 2 The flow rate of the gas is 10-500 sccm, the etching pressure is 2-100 mTorr, and the etching power is 100-2000 watts.
Optionally, the range of the height difference between the top of the interlayer dielectric layer and the top surface of the dummy gate structure is less than or equal to
Optionally, the material of the protective layer is amorphous silicon doped with boron ions.
Optionally, the doping concentration of the boron ions is 1E12 atoms/cm 3-1E19 atoms/cm3.
Optionally, the method for forming the protective layer includes a furnace tube reduction method or a chemical vapor deposition method.
Optionally, the material of the interlayer dielectric layer includes one or more of silicon oxide, borosilicate glass, borophosphosilicate glass, and tetraethoxysilane.
Optionally, the material of the first cover layer includes silicon oxide, borosilicate glass, borophosphosilicate glass, or tetraethoxysilane; the material of the second covering layer comprises silicon oxide, borosilicate glass, borophosphosilicate glass or tetraethoxysilane.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
when the metal grid is formed by removing the pseudo grid structure, the height of the metal grid is limited by the height of the interlayer dielectric layer, so that the forming height of the metal grid can be effectively controlled; on the other hand, the metal gate can be formed with high uniformity.
Furthermore, after the interlayer dielectric layer is formed, the etching stop layer is etched until the top of the etching stop layer is flush with the top of the interlayer dielectric layer, compared with the technology of grinding the interlayer dielectric layer, the etching stop layer and the pseudo gate structure together to the same height, the interlayer dielectric layer and the etching stop layer are respectively enabled to reach the preset height, in the etching process, the height of the etching stop layer is controlled more easily, and the heights of the etching stop layers on the two sides of the pseudo gate structure are kept consistent.
Drawings
FIGS. 1-3 are schematic views illustrating a semiconductor structure formation process according to an embodiment;
fig. 4 to 12 are schematic structural diagrams corresponding to steps in a semiconductor structure forming process according to an embodiment of the invention.
Detailed Description
As can be seen from the background, the control of the height of the metal gate is not stable in the current process of forming a semiconductor structure.
Fig. 1 to 3 are schematic structural diagrams illustrating a semiconductor structure forming process according to an embodiment.
Referring to fig. 1, a semiconductor substrate 10 is provided, wherein a dummy gate structure 20 is formed on the semiconductor substrate 10; forming an etching stop layer 30 covering the dummy gate structure 20 on the semiconductor substrate 10; and forming a dielectric layer 40 on the surface of the etching stop layer 30.
Referring to fig. 2, the dielectric layer 40 and the etch stop layer 30 are chemically and mechanically polished, and the surfaces of the dielectric layer 40 and the etch stop layer 30 are flush with the surface of the dummy gate structure 20 by using the surface of the dummy gate structure 20 as a stop layer.
Referring to fig. 3, the dummy gate structure 20 is removed to form an opening (not shown), a metal layer (not shown) is filled in the opening, the metal layer is chemically and mechanically polished, and the dielectric layer 40 is used as a stop layer to form a metal gate 50.
The inventor finds that, in the method for forming the semiconductor structure, when the surface of the pseudo gate structure is used as the stop layer and the dielectric layer and the etching stop layer are chemically and mechanically polished, the polishing selection ratio among the dielectric layer, the etching stop layer and the pseudo gate structure is difficult to control, the dielectric layer and the etching stop layer are easily over-polished during polishing, the polished surface is also uneven, and when the pseudo gate structure is subsequently removed to form the metal gate, the height control of the metal gate is not facilitated, and the height uniformity of the metal gate is also influenced.
In order to solve the above problems, the inventor provides a method for forming a semiconductor structure, in which an interlayer dielectric layer is formed on a substrate, the top of the interlayer dielectric layer is flush with or lower than the top surface of a dummy gate structure, the height of the interlayer dielectric layer is fixed in the subsequent process of forming a metal gate, and the height of the interlayer dielectric layer is taken as a reference when the dummy gate structure is removed to form the metal gate, so that the formation height of the metal gate can be better controlled.
In order to make the aforementioned objects, features and advantages of the present invention more comprehensible, embodiments accompanying figures are described in detail below.
Fig. 4 is a schematic structural diagram corresponding to steps in the process of forming the semiconductor structure shown in fig. 12 according to an embodiment of the invention.
Referring to fig. 4, a substrate 100 is provided, and a dummy gate structure 110 is formed on the substrate 100.
The substrate 100 provides a process platform for the subsequent formation of semiconductor structures.
In this embodiment, the substrate 100 is used to form a finfet, and thus, discrete fins (not shown) are also formed on the substrate 100. In other embodiments, the substrate is used to form a planar transistor, and accordingly, the substrate is a planar substrate.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium, and may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The dummy gate structure 110 is a single-layer structure or a stacked structure. The dummy gate structure 110 includes a dummy gate layer 111; or the dummy gate structure 110 includes a dummy gate oxide layer and a dummy gate layer on the dummy gate oxide layer. In this embodiment, the dummy gate structure 110 is a stacked structure, and the dummy gate structure 110 includes a dummy oxide layer (not shown) and a dummy gate layer 111 on the dummy oxide layer.
In this embodiment, the dummy oxide layer is made of silicon oxide, the dummy gate layer 111 is made of polysilicon, and the dummy gate structure 110 is removed to form a metal gate.
Specifically, the step of forming the dummy gate structure 110 includes: forming a dummy oxide layer on the substrate 100, wherein the dummy oxide layer crosses the fin portion and covers the top surface and the sidewall surface of the fin portion; forming a dummy gate film on the dummy oxide layer; forming a hard mask layer 120 on the surface of the pseudo gate film, wherein the hard mask layer 120 defines a pattern of the pseudo gate structure 110 to be formed; and patterning the pseudo gate film by taking the hard mask layer 120 as a mask to form the pseudo gate structure 110.
In this embodiment, after the dummy gate structure 110 is formed, the hard mask layer 120 located at the top of the dummy gate structure 110 may be retained, the hard mask layer 120 is made of silicon nitride, and the hard mask layer 120 is used to protect the top of the dummy gate structure 110 in a subsequent process. In other embodiments, the material of the hard mask layer may also be silicon oxynitride, silicon carbide, or boron nitride.
After the dummy gate structure 110 is formed, an interlayer dielectric layer is formed on the substrate 100, and the top of the interlayer dielectric layer is flush with the top surface of the dummy gate structure 110 or lower than the top surface of the dummy gate structure 110.
Referring to fig. 4, it should be noted that before the formation of the interlayer dielectric layer, a sidewall 112 is further formed on the sidewall of the dummy gate structure 110, and the top of the sidewall 112 is flush with the top surface of the hard mask layer 120.
In this embodiment, the material of the sidewall 112 is a low-K dielectric material (the low-K dielectric material refers to a dielectric material having a relative dielectric constant greater than or equal to 2.5 and less than 3.9), and the material of the sidewall 112 is SiCON. In other embodiments, the material of the sidewall spacers 112 may also be other materials such as silicon nitride.
In this embodiment, after the side wall 112 is formed, an etching stop layer 113 is further formed on the side wall of the side wall 112, and the top of the etching stop layer 113 is flush with the top surface of the hard mask layer 120.
In this embodiment, the material of the etch stop layer 113 is silicon nitride. In other embodiments, the material of the etch stop layer 113 may also be silicon oxynitride, silicon carbide, or boron nitride.
After the etching stop layer 113 is formed, an interlayer dielectric layer is formed on the surface of the etching stop layer 113 and the substrate 100.
Specifically, the step of forming the interlayer dielectric layer includes:
referring to fig. 4, a dielectric material layer 200 is formed on the substrate 100, and the top of the dielectric material layer 200 is higher than the top surface of the dummy gate structure 110.
In this embodiment, the top of the dielectric material layer 200 is higher than the top surface of the hard mask layer 120.
In this embodiment, the dielectric material layer 200 is made of silicon oxide. In other embodiments, the material of the dielectric material layer may also be one or more of borosilicate glass, borophosphosilicate glass, and tetraethoxysilane.
In this embodiment, the method for forming the dielectric material layer 200 is a chemical vapor deposition method. In other embodiments, the dielectric material layer 200 may be formed by an atomic layer deposition method.
Referring to fig. 5, the dielectric material layer 200 is chemically and mechanically polished, and the surface of the hard mask layer 120 is used as a stop layer, so that the top of the dielectric material layer 200 is flush with the top surface of the hard mask layer 120, and an interlayer dielectric layer 210 is formed.
Referring to fig. 6, the interlayer dielectric layer 210 is etched back until the top of the interlayer dielectric layer 210 is flush with the top surface of the dummy gate structure 110, or lower than the top surface of the dummy gate structure 110.
In this embodiment, the top of the interlayer dielectric layer 210 is lower than the top surface of the dummy gate structure 110.
In this embodiment, the interlayer dielectric layer 210 is etched back by a Certas etching process (chemical etching with gas based on atomic layer etching). The Certas etching process comprises remote etching and in-situ annealing after the remote etching, wherein the process parameters of the remote etching comprise: the etching atmosphere comprises NH 3 And HF 5 NH of said 3 The flow rate of the gas is 5-100 sccm, and the HF is 5 The flow rate of the gas is 5-100 sccm, and the etching temperature is 20-80 ℃; the annealing temperature of the in-situ annealing is 100-250 ℃.
The interlayer dielectric layer 210 is etched back by adopting a Certas etching process, so that on one hand, the difference between the patterns formed by etching is small; on the other hand, the Certas etching makes the silicon oxide have a high selectivity to silicon, and avoids damaging the dummy gate layer 111 when etching the interlayer dielectric layer 210.
In other embodiments, the interlayer dielectric layer 210 may also be etched back by using a wet etching process, where the process parameters of the wet etching process include: adopting hydrofluoric acid solution as corrosive liquid, wherein the volume ratio of hydrofluoric acid to water is 50:1 to 1000:1.
in this embodiment, the height difference between the top of the interlayer dielectric layer 210 and the top surface of the dummy gate structure 110 is less than or equal to
In this embodiment, when the interlayer dielectric layer 210 is formed, the interlayer dielectric layer 210 is etched back, so that the top of the interlayer dielectric layer 210 is lower than the top of the dummy gate structure 110, compared with chemical mechanical polishing, the height of the interlayer dielectric layer 210 can be better controlled, the surface of the formed interlayer dielectric layer is smoother, the dummy gate structure 110 is subsequently removed, when a metal gate is formed, the height of the interlayer dielectric layer 210 is taken as a reference, the formation height of the metal gate can be effectively controlled, and the heights between the metal gates are uniform.
Continuing to refer to fig. 6, the etch stop layer 113 is etched until the top of the etch stop layer 113 is flush with the top of the interlayer dielectric layer 210.
In this embodiment, the method for etching the etching stop layer 113 is dry etching, and the process parameters of the dry etching include: the etching atmosphere comprises CH 3 F and O 2 Said CH 3 The flow rate of the F gas is 10-500 sccm, and the O gas is 2 The flow rate of the gas is 10-500 sccm, the etching pressure is 2-100 mTorr, and the etching power is 100-2000 watts.
In this embodiment, the material of the etching stop layer 113 is the same as that of the hard mask layer 120, and when the etching stop layer 113 is etched, the hard mask layer 120 is etched and removed, so that the process steps are reduced, and the process flow is simplified.
In this embodiment, when the etching stop layer 113 is etched, the sidewall layer 112 is etched at the same time until the top of the sidewall layer 112 is flush with the top of the interlayer dielectric layer 210.
In this embodiment, the interlayer dielectric layer 210 is etched to a desired height, and then the etch stop layer 113 and the sidewall layer 112 are etched with reference to the height of the interlayer dielectric layer 210 until the top of the etch stop layer 113 is flush with the top of the interlayer dielectric layer 210, and the top of the sidewall layer 112 is flush with the top of the interlayer dielectric layer 210. Compared with the method of directly carrying out chemical mechanical polishing on the interlayer dielectric layer and the etching stop layer to enable the heights of the interlayer dielectric layer and the etching stop layer to be consistent, the heights of the interlayer dielectric layer 210, the etching stop layer 113 and the side wall layer 112 can be conveniently and effectively controlled without considering the polishing selection ratio among several materials, and therefore the forming height of the metal grid electrode is more stable.
Referring to fig. 7, a first capping layer 300 is formed on the surface of the dummy gate structure 110.
In this embodiment, the first capping layer 300 covers the top surface and the exposed sidewall surface of the dummy gate structure 110.
In this embodiment, the material of the first capping layer 300 is silicon oxide; in other embodiments, the material of the first cover layer 300 may also be one or more of borosilicate glass, borophosphosilicate glass, and tetraethoxysilane.
In this embodiment, the first capping layer 300 is formed by a chemical vapor deposition method; in other embodiments, the first capping layer 300 may also be formed by using an atomic layer deposition method.
The thickness of the first capping layer 300 ranges from 1nm to 5nm.
In this embodiment, the first capping layer 300 is used to isolate the dummy gate layer 111 from a protection layer to be formed later.
Referring to fig. 8, a protective layer 400 is formed on the surface of the interlayer dielectric layer 210 and the surface of the first capping layer 300.
In this embodiment, the material of the protection layer 400 is amorphous silicon doped with boron ions, and the doping concentration of the boron ions is 1E12 atoms/cm 3 ～1E19 atoms/cm 3 。
In this embodiment, the method of forming the protection layer 400 is a furnace tube growth method; in other embodiments, the protection layer 400 may also be formed by a chemical vapor deposition method.
The thickness of the protective layer 400 is 5nm to 20nm. If the thickness of the formed protective layer is too small, the protective effect on the interlayer dielectric layer can be weakened; if the thickness of the formed protective layer is too large, the gap between the adjacent dummy gate structures can be completely filled, and the subsequent planarization process is not facilitated due to the uneven surface of the protective layer.
In this embodiment, since the protection layer 400 is doped with boron ions and has an etching selection ratio with the polysilicon material of the dummy gate structure 110, the protection layer 400 can protect the interlayer dielectric layer 210 when the dummy gate structure 110 is subsequently removed, so as to prevent the interlayer dielectric layer 210 from being damaged, so that the interlayer dielectric layer 210 is kept in a stable state, thereby improving the performance of the semiconductor structure.
Referring to fig. 9, a second capping layer 500 is formed on the surface of the protection layer 400.
In this embodiment, the second capping layer 500 is made of silicon oxide; in other embodiments, the material of the second cover layer 500 may also be one or more of borosilicate glass, borophosphosilicate glass, and tetraethoxysilane.
In this embodiment, the second capping layer 500 is formed by a chemical vapor deposition method; in other embodiments, the second capping layer 500 may also be formed by using an atomic layer deposition method.
In this embodiment, the second cover layer 500 is used to fill up the unevenness of the surface of the protection layer 400 after the protection layer 400 is formed, so as to perform the subsequent planarization process.
Referring to fig. 10, the second capping layer 500, the protection layer 400, and the first capping layer 300 are planarized until the surface of the dummy gate structure 110 is exposed.
In this embodiment, the planarization process is a chemical mechanical polishing process, and the chemical mechanical polishing process is a conventional process, which is not described herein again.
Referring to fig. 11, the dummy gate structure 110 is removed, and an opening 600 is formed.
In this embodiment, the dummy gate layer 111 in the dummy gate structure 110 is specifically removed.
In this embodiment, the method for removing the dummy gate layer 111 is a dry etching process; in other embodiments, a wet etching process may be further used to remove the dummy gate layer 111.
With continued reference to fig. 11, after removing the dummy gate layer 111, the dummy oxide layer is removed, and the remaining first and second capping layers 300 and 500 are removed.
In this embodiment, the method for removing the dummy oxide layer, the first capping layer 300, and the second capping layer 500 is a dry etching process; in other embodiments, a wet etching process may be further used to remove the dummy oxide layer, the first capping layer 300, and the second capping layer 500.
In this embodiment, the protection layer 400 plays a role in protecting the interlayer dielectric layer 210 when removing the dummy gate layer 111, and removing the dummy oxide layer, the first cover layer 300, and the second cover layer 500.
Referring to fig. 12, after the opening 600 is formed, the opening is filled with metal to form a metal gate 610.
The forming process of the metal gate 610 is as follows: filling the opening with a metal layer (not shown) covering the surface of the protection layer 400; and chemically and mechanically grinding the metal layer until the top of the metal layer is flush with the surface of the top of the interlayer dielectric layer 210 to form a metal gate 610.
When the metal gate 610 is formed, the height of the interlayer dielectric layer 210 is used as a reference, the metal layer is directly ground until the height of the metal layer is flush with the height of the interlayer dielectric layer 210, the grinding selection ratio among the interlayer dielectric layer, the etching stop layer, the side wall layer and the metal layer does not need to be considered, and the height of the formed metal gate is easier to control.
The material of the metal gate 610 is one or more of aluminum, copper, tungsten, cobalt, and platinum.
In this embodiment, before the metal gate 610 is formed, a diffusion barrier layer (not shown) is further formed on the bottom and the sidewall of the opening 600. The diffusion barrier layer is used for preventing metal ions in the metal gate 610 from diffusing into the interlayer dielectric layer 210, and the stability of the device is affected. The diffusion impervious layer is made of TiN or TaN.
According to the forming method of the semiconductor structure, provided by the embodiment of the invention, when the interlayer dielectric layer is formed, the height of the interlayer dielectric layer is fixed, the interlayer dielectric layer is prevented from being damaged in the subsequent forming process, the stability of the height of the interlayer dielectric layer is ensured, and when the metal gate is formed by removing the pseudo gate structure subsequently, the height of the metal gate is limited by taking the height of the interlayer dielectric layer as a reference, so that the forming height of the metal gate is easier to control.
Furthermore, after the interlayer dielectric layer is formed, the etching stop layer and the side wall layer are respectively etched until the tops of the etching stop layer and the side wall layer are flush with the top of the interlayer dielectric layer by taking the height of the interlayer dielectric layer as a reference, the grinding ratio among the interlayer dielectric layer, the etching stop layer, the side wall layer and the pseudo gate structure does not need to be considered, the heights of the etching stop layer and the side wall layer are more easily controlled by respectively etching, and the improvement of the height uniformity of the formed metal gate is facilitated.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (13)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, and forming a pseudo gate structure on the substrate;
forming an interlayer dielectric layer on the substrate, wherein the top of the interlayer dielectric layer is lower than the top surface of the dummy gate structure;
forming a first covering layer on the surface of the pseudo gate structure;
forming protective layers on the surface of the interlayer dielectric layer and the surface of the first covering layer;
forming a second covering layer on the surface of the protective layer;
carrying out planarization treatment on the second covering layer, the protective layer and the first covering layer until the surface of the pseudo gate structure is exposed;
removing the pseudo gate structure to form an opening;
filling the opening with a metal layer, wherein the metal layer covers the surface of the protective layer;
and chemically and mechanically grinding the metal layer until the top of the metal layer is flush with the surface of the top of the interlayer dielectric layer to form the metal gate.
2. The method of forming a semiconductor structure of claim 1, wherein forming the interlevel dielectric layer comprises:
forming a dielectric material layer on the substrate, wherein the top of the dielectric material layer is higher than the top surface of the dummy gate structure;
carrying out chemical mechanical grinding on the medium material layer to form an interlayer medium layer;
and etching back the interlayer dielectric layer until the top of the interlayer dielectric layer is lower than the top surface of the pseudo gate structure.
3. The method of claim 2, wherein the etching back the interlevel dielectric layer comprises a Certas etch process or a wet etch.
4. The method of claim 3, wherein the Certas etching process comprises a remote etching and an in-situ annealing after the remote etching, wherein the process parameters of the remote etching comprise: the etching atmosphere comprises NH 3 And HF 5 NH of said 3 The flow rate of the gas is 5 to 100sccm, and the HF is 5 The flow rate of the gas is 5 to 100sccm, and the etching temperature is 20 to 80 ℃; the annealing temperature of the in-situ annealing is 100 to 250 ℃.
5. The method of forming a semiconductor structure according to claim 3, wherein the process parameters of the wet etching comprise: adopting hydrofluoric acid solution as corrosive liquid, wherein the volume ratio of hydrofluoric acid to water is 50:1 to 1000:1.
6. the method of forming a semiconductor structure of claim 1, further comprising:
before the interlayer dielectric layer is formed, forming an etching stop layer on the pseudo gate structure;
and etching the etching stop layer after the interlayer dielectric layer is formed until the top of the etching stop layer is flush with the top of the interlayer dielectric layer.
7. The method for forming a semiconductor structure according to claim 6, wherein the etching stop layer is etched by a dry etching method, and the dry etching process parameters include: the etching atmosphere comprises CH 3 F and O 2 Said CH 3 The flow rate of the gas F is 10 to 500sccm, and the gas O is 2 The flow rate of the gas is 10 to 500sccm, the etching pressure is 2 to 100 millitorr, and the etching power is 100 to 2000 watts.
8. The method of forming a semiconductor structure of claim 1, wherein a difference in height between a top of the interlayer dielectric layer and a top surface of the dummy gate structure ranges from less than or equal to 200A.
9. The method of claim 1, wherein the material of the protective layer is amorphous silicon doped with boron ions.
10. The method of claim 9, wherein said boron ions are doped to a concentration of 1E12 atoms/cm 3 ~1E19 atoms/cm 3 。
11. The method of claim 9, wherein the step of forming the passivation layer comprises furnace growth or chemical vapor deposition.
12. The method of claim 1, wherein the interlayer dielectric layer comprises one or more of silicon oxide, borosilicate glass, borophosphosilicate glass, and tetraethoxysilane.
13. The method of forming a semiconductor structure of claim 1, wherein a material of the first capping layer comprises silicon oxide or borosilicate glass or borophosphosilicate glass or tetraethoxysilane; the material of the second covering layer comprises silicon oxide, borosilicate glass, borophosphosilicate glass or tetraethoxysilane.
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