CN113113356B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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CN113113356B
CN113113356B CN202010026831.1A CN202010026831A CN113113356B CN 113113356 B CN113113356 B CN 113113356B CN 202010026831 A CN202010026831 A CN 202010026831A CN 113113356 B CN113113356 B CN 113113356B
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CN113113356A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Tianjin Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Tianjin Corp
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: etching the fourth doped material layer, the second semiconductor material layer, the third doped material layer, the buffer material layer, the second doped material layer and the first semiconductor material layer to form a fourth doped layer, a second semiconductor column, a third doped layer, a buffer layer, a second doped layer and a first semiconductor column respectively; forming a first gate structure on a sidewall of the first semiconductor column, the third doped layer and the second doped layer having different conductivity types of doping ions; after the first gate structure is formed, a second gate structure is formed on the sidewall of the second semiconductor pillar. According to the embodiment of the invention, the buffer layer enables the third doped layer and the second doped layer not to be in direct contact, so that doped ions in the second doped layer are not easy to diffuse into the third doped layer, and doped ions in the third doped layer are not easy to diffuse into the second doped layer, thereby optimizing the performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration, and the development trend of semiconductor process nodes following moore's law is continuously decreasing. Transistors are currently being widely used as the most basic semiconductor devices, and therefore, as the element density and integration level of the semiconductor devices are improved, the channel length of the transistors has to be continuously shortened in order to accommodate the reduction of process nodes.
The reduction of the transistor channel length has the benefits of increasing the die density of the chip, increasing the switching speed, and the like. However, as the channel length is shortened, the distance between the source and the drain of the transistor is shortened, the control capability of the gate to the channel is reduced, so that the subthreshold leakage (subthreshold leakage) phenomenon, that is, short-channel effects (SCE) is more likely to occur, and the channel leakage current of the transistor is increased.
Accordingly, to better accommodate the demand for device scaling, semiconductor processes are increasingly beginning to transition from planar transistors to three-dimensional transistors with higher power, such as Gate-all-around (GAA) transistors. In the fully-enclosed gate transistor, the gate encloses the region where the channel is located from the periphery, and compared with a planar transistor, the gate of the fully-enclosed gate transistor has stronger control capability on the channel and can better inhibit the short channel effect. The fully-surrounding Gate transistors include a Lateral Gate-all-around (lga) transistor and a vertical Gate-all-around (VGAA) transistor, wherein the channel of VGAA extends in a direction perpendicular to the substrate surface, which is advantageous for improving the area utilization efficiency of the semiconductor structure, and thus for achieving further feature size reduction.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and optimizes the electrical performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate, a first doped material layer positioned on the substrate, a first semiconductor material layer positioned on the first doped material layer, and a second doped material layer positioned on the first semiconductor material layer, and the first doped material layer and the second doped material layer are provided with first type doping ions; forming a buffer material layer on the substrate; forming a third doped material layer, a second semiconductor material layer and a fourth doped material layer on the buffer material layer in sequence, wherein second type doped ions are arranged in the third doped material layer and the fourth doped material layer, and the second type doped ions are different from the first type doped ions in conductivity type; etching the fourth doped material layer, the second semiconductor material layer, the third doped material layer, the buffer material layer, the second doped material layer and the first semiconductor material layer to form a fourth doped layer, a second semiconductor column, a third doped layer, a buffer layer, a second doped layer and a first semiconductor column respectively; forming a first gate structure on a sidewall of the first semiconductor column; and after the first gate structure is formed, forming a second gate structure on the side wall of the second semiconductor column.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate; a first doped material layer on the substrate; a first semiconductor pillar on the first doped material layer; the second doped layer is positioned on the first semiconductor column, and first type doped ions are arranged in the first doped material layer and the second doped layer; a buffer layer located on the second doped layer; a third doped layer located on the buffer layer; a second semiconductor pillar located on the third doped layer; a fourth doped layer located on the second semiconductor column, wherein second type doped ions are arranged in the third doped layer and the fourth doped layer, and the second type doped ions are different from the first type doped ions in conductivity type; a first gate structure located on a sidewall of the first semiconductor column; and the second grid structure is positioned on the side wall of the second semiconductor column.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming a semiconductor structure provided by the embodiment of the invention, a first gate structure is formed on the side wall of the first semiconductor column, and the first semiconductor column, the first doping material layer, the second doping layer and the first gate structure form a first transistor; and forming a second grid structure on the side wall of the second semiconductor column, wherein the fourth doped layer, the second semiconductor column, the third doped layer and the second grid structure form a second transistor. The conductivity types of doping ions of the third doping layer and the second doping layer are different, the buffer layer enables the third doping layer and the second doping layer not to be in direct contact, the buffer layer enables the doping ions in the second doping layer not to be easily diffused into the third doping layer, the doping ions in the third doping layer not to be easily diffused into the second doping layer, and the buffer layer reduces the probability of junction leakage current between the first transistor and the second transistor; and because the conductivity types of the doping ions of the first transistor and the second transistor are different, the buffer layer has a certain thickness, the distance between the second doping layer and the third doping layer is increased, the capacitive coupling effect of the second doping layer and the third doping layer is reduced, the junction capacitance between the first transistor and the second transistor is smaller, in sum, the probability of leakage current between the first transistor and the second transistor is reduced by the buffer layer, the junction capacitance between the first transistor and the second transistor is reduced, and the performance of the semiconductor structure is optimized.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
fig. 2 to 13 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As can be seen from the background art, the semiconductor structure formed at present still has the problem of poor performance. The reason for the poor performance of the semiconductor structure is analyzed by combining a forming method of the semiconductor structure.
Fig. 1 is a schematic structural diagram of a semiconductor structure.
As shown in fig. 1, the semiconductor structure includes: a substrate 1; a first full-surrounding Gate (GAA) transistor on the substrate 1; a second fully-enclosed gate transistor on the first fully-enclosed gate transistor, the first fully-enclosed gate transistor comprising: a first doped layer material layer 2; a first semiconductor pillar 3 located on the first doped layer material layer 2; and a second doped layer 4 located on the first semiconductor pillar 3, wherein the first doped layer material layer 2 and the second doped layer 4 have first type doped ions therein. The second fully-enclosed gate transistor includes: a third doped layer 5; a second semiconductor pillar 7 located on the third doped layer 5; a fourth doped layer 6 located on the second semiconductor pillar 7, wherein the third doped layer 5 and the fourth doped layer 6 have second type doped ions therein, and the second type doped ions have different conductivity types from the first type doped ions; a first gate structure 8 located on a sidewall of the first semiconductor pillar 3; and a second gate structure 9 on a sidewall of the second semiconductor pillar 7.
The semiconductor structure comprises a first fully-enclosed gate transistor and a second fully-enclosed gate transistor which are stacked, wherein a second doping layer 4 of the first fully-enclosed gate transistor is directly contacted with a third doping layer 5 of the second fully-enclosed gate transistor, and junction leakage current is easy to occur between the first fully-enclosed gate transistor and the second fully-enclosed gate transistor because the conductivity types of doping ions in the second doping layer 4 and the third doping layer 5 are different, so that the electrical performance of the semiconductor structure is poor; and because the conductivity types of the doping ions of the first transistor and the second transistor are different, the capacitive coupling effect of the second doping layer and the third doping layer is stronger when the semiconductor structure works, so that the electrical performance of the semiconductor structure is poorer.
In order to solve the technical problem, in the method for forming a semiconductor structure provided by the embodiment of the invention, a first gate structure is formed on a sidewall of the first semiconductor column, and the first semiconductor column, the first doped material layer, the second doped layer and the first gate structure form a first transistor; and forming a second grid structure on the side wall of the second semiconductor column, wherein the fourth doped layer, the second semiconductor column, the third doped layer and the second grid structure form a second transistor. The conductivity types of doping ions of the third doping layer and the second doping layer are different, the buffer layer enables the third doping layer and the second doping layer not to be in direct contact, the buffer layer enables the doping ions in the second doping layer not to be easily diffused into the third doping layer, the doping ions in the third doping layer not to be easily diffused into the second doping layer, and the buffer layer reduces the probability of junction leakage current between the first transistor and the second transistor; and because the conductivity types of the doping ions of the first transistor and the second transistor are different, the buffer layer has a certain thickness, the distance between the second doping layer and the third doping layer is increased, the capacitive coupling effect of the second doping layer and the third doping layer is reduced, the junction capacitance between the first transistor and the second transistor is smaller, in sum, the probability of leakage current between the first transistor and the second transistor is reduced by the buffer layer, the junction capacitance between the first transistor and the second transistor is reduced, and the performance of the semiconductor structure is optimized.
In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, a detailed description of specific embodiments of the present invention is provided below with reference to the accompanying drawings.
Fig. 2 to 13 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 2, a base is provided, the base including a substrate 100, a first doped material layer 101 on the substrate 100, a first semiconductor material layer 102 on the first doped material layer 101, a second doped material layer 103 on the first semiconductor material layer 102, the first doped material layer 101 and the second doped material layer 103 having first type dopant ions therein.
The substrate 100 provides a process platform for the subsequent formation of semiconductor structures.
In this embodiment, the material of the substrate 100 comprises silicon. In other embodiments, the material of the substrate may also include one or more of germanium, silicon carbide, gallium arsenide, and indium gallium.
The first doped material layer 101 serves as the drain of the first transistor. In other embodiments, the first doped material layer serves as a source of the semiconductor structure.
In this embodiment, the semiconductor structure is a PMOS transistor, the first type of doped ions are P-type ions, and specifically, the material of the first doped material layer 101 is silicon germanium doped with P-type ions. This embodiment is achieved by doping P-type ions in silicon germanium. Specifically, the P-type ions include B, ga or In.
In other embodiments, the semiconductor structure is an NMOS transistor, the first type of dopant ions are N-type ions, and specifically, the material of the first doped material layer is silicon carbide or silicon phosphide doped with N-type ions, respectively. Specifically, the N-type ions include P, as or Sb.
The first semiconductor material layer 102 provides for the subsequent formation of a first semiconductor pillar.
In this embodiment, when the PMOS transistor is operated, the carriers are holes, and accordingly, the material of the first semiconductor material layer 102 includes SiGe or Si. SiGe or Si is a material of a channel region of the PMOS transistor, so that the mobility of carriers in a channel is higher when the semiconductor structure works, and the electrical property of the semiconductor structure is improved.
The second doped layer material layer 103 provides for the subsequent formation of a second doped layer.
In this embodiment, the semiconductor structure is a PMOS transistor, the first type doped ions are N type ions, and specifically, the material of the second doped layer material layer 103 is silicon germanium doped with P type ions. This embodiment is achieved by doping P-type ions in silicon germanium. Specifically, the P-type ions include B, ga or In.
In other embodiments, the semiconductor structure is an NMOS transistor, the first type of doping ions are N-type ions, and specifically, the material of the second doped layer material layer is silicon carbide or silicon phosphide doped with N-type ions, respectively. By doping N-type ions in silicon carbide or silicon phosphide. Specifically, the N-type ions include P, as or Sb.
Referring to fig. 3, a buffer material layer 104 is formed on a substrate.
The buffer material layer 104 provides for the subsequent formation of a buffer layer. And forming a third doped material layer, a second semiconductor material layer and a fourth doped material layer on the buffer material layer, wherein the third doped material layer and the fourth doped material layer are provided with second type doped ions, and the second type doped ions are different from the first type doped ions in conductivity type. The buffer material layer 104 makes the second buffer material layer 103 and the third doped material layer not directly contact, and the buffer material layer 104 makes the doped ions in the second doped material layer 103 not easily diffuse into the third doped material layer, and the doped ions in the third doped material layer not easily diffuse into the second doped material layer 103; the probability of junction leakage current between the second doped material layer 103 and the third doped material layer is made smaller, which is beneficial to optimizing the performance of the semiconductor structure. The buffer material layer has a certain thickness, so that the distance between the second doped material layer 103 and the third doped material layer is increased, the capacitive coupling effect of the second doped material layer 103 and the third doped material layer is reduced, and the performance of the semiconductor structure is optimized.
In this embodiment, the buffer material layer 104 is a semiconductor layer doped with impurity ions.
The buffer material layer 104 is a semiconductor layer, so that the first transistor and the second transistor formed later can be electrically connected when the semiconductor structure is in operation. The impurity ions can plug the lattice gaps of the material in the buffer material layer 104, so that the doping ions of the second doping material layer 103 are not easy to diffuse into the third doping material layer, and the doping ions of the third doping material layer are not easy to diffuse into the second doping material layer.
In this embodiment, the material of the buffer material layer 104 includes Si or SiGe having C. In other embodiments, si or SiGe with N.
C can plug the lattice gaps of the material in the buffer material layer 104, impeding the passage of ions, and C can form covalent bonds with Si or SiGe in the buffer material layer 104, which have a stable spatial electric field, and also impede the movement of ions. In summary, C can prevent dopant ions in the second doping material layer 103 and the third doping material layer from diffusing along the crystal lattice.
In other embodiments, N can plug the lattice gaps of the material in the buffer material layer, impeding ion penetration, and N can form covalent bonds with Si or SiGe in the buffer material layer, the covalent bonds having a stable spatial electric field, and also impeding ion movement. In summary, N can prevent dopant ions in the second doped material layer and the third doped material layer from diffusing along the crystal lattice.
It should be noted that the buffer material layer 104 is not too thick or too thin. If the buffer material layer 104 is too thick, correspondingly, the interval between the second doped material layer 103 and the third doped material layer is too large, and when the semiconductor structure works, carriers are blocked by the buffer material layer 104 too much, which is not beneficial to improving the migration rate of carriers. If the buffer material layer 104 is too thin, the doped ions of the second doped material layer 103 are easy to diffuse into the third doped material layer through the buffer material layer 104, so that the doped ions of the third doped material layer are easy to diffuse into the second doped material layer 103 through the buffer material layer 104, and the probability of junction leakage current between the second doped material layer 103 and the third doped material layer is high, which is not beneficial to optimizing the performance of the semiconductor structure; in addition, if the buffer material layer 104 is too thin, the distance between the second doped material layer 103 and the third doped material layer is not easy to be significantly increased, and the capacitive coupling effect between the corresponding second doped material layer 103 and the third doped material layer is relatively strong, which is not beneficial to optimizing the performance of the semiconductor structure. In this embodiment, the thickness of the buffer material layer 104 is 2 nm to 8 nm.
In this embodiment, a selective epitaxial growth process (selective epitaxy growth, SEG) is used to form an epitaxial layer on a substrate, and during the process of forming the epitaxial layer, the epitaxial layer is ion doped in situ to form the buffer material layer 104.
In this embodiment, the epitaxial layer obtained by the selective epitaxial growth method has high film purity and few defects, and the buffer material layer 104 has a high formation quality, so that the electrical performance of the semiconductor structure is advantageously optimized.
In the step of in-situ ion doping of the epitaxial layer, the doping amount of impurity ions in the epitaxial layer should not be too large or too small. If the doping amount of the impurity ions in the epitaxial layer is too large, lattice mismatch of the buffer material layer 104 is easily caused, the lattice of the buffer material layer 104 is deformed, so that the doping ions of the second doped material layer 103 are easily diffused into the third doped material layer through the buffer material layer 104, and the doping ions of the third doped material layer are easily diffused into the second doped material layer 103 through the buffer material layer 104, so that the probability of junction leakage current between the second doped material layer 103 and the third doped material layer is high, which is not beneficial to optimizing the performance of the semiconductor structure. If the doping amount of the impurity ions in the epitaxial layer is too small, the impurity ions are not easy to plug the lattice gaps of the epitaxial layer material, which is easy to cause that the buffer material layer 104 cannot well block the impurity ions in the second doped material layer 103 from diffusing to the third doped material layer, and cannot well block the impurity ions in the third doped material layer from diffusing to the second doped material layer 103, which results in higher probability of junction leakage current between the second doped material layer 103 and the third doped material layer, and is easy to cause that the capacitive coupling effect between the second doped material layer 103 and the third doped material layer is stronger, which is unfavorable for optimizing the performance of the semiconductor structure. In this embodiment, in the step of in-situ ion doping the epitaxial layer, the doping amount of the impurity ions in the epitaxial layer is 8.0E14 atoms per square centimeter to 5.0E15 atoms per square centimeter.
In other embodiments, the buffer material layer may also be formed using an atomic layer deposition process or a chemical vapor deposition process.
Referring to fig. 4, a third doping material layer 105, a second semiconductor material layer 106, and a fourth doping material layer 107 are sequentially formed on the buffer material layer 104, the third doping material layer 105 and the fourth doping material layer 107 have second type doping ions therein, and the second type doping ions have a different conductivity type from the first type doping ions.
The third doped material layer 105 provides for the subsequent formation of a third doped layer.
In this embodiment, the semiconductor structure is an NMOS transistor, the second type of doped ions are N-type ions, and specifically, the material of the third doped material layer 105 is silicon carbide or silicon phosphide doped with N-type ions, respectively. By doping N-type ions in silicon carbide or silicon phosphide. Specifically, the N-type ions include P, as or Sb.
In other embodiments, the semiconductor structure is a PMOS transistor, the second type of dopant ions are P-type ions, and specifically, the material of the third doped material layer is silicon germanium doped with P-type ions. This embodiment is achieved by doping P-type ions in silicon germanium. Specifically, the P-type ions include B, ga or In.
The second semiconductor material layer 106 provides for the subsequent formation of second semiconductor pillars.
In this embodiment, when the NMOS transistor is in operation, the carriers are electrons, and correspondingly, the material of the second semiconductor material layer 106 includes InGaAs or GaAs, where InGaAs or GaAs is the material of the channel region of the NMOS transistor, and when the semiconductor structure is in operation, the mobility of carriers in the channel can be higher, which is beneficial to improving the electrical performance of the semiconductor structure.
The fourth doped material layer 107 provides for the subsequent formation of a fourth doped layer.
In this embodiment, the semiconductor structure is an NMOS transistor, the second type of doped ions are N-type ions, and specifically, the material of the fourth doped layer material layer 107 is silicon carbide or silicon phosphide doped with N-type ions, respectively. By doping N-type ions in silicon carbide or silicon phosphide. Specifically, the N-type ions include P, as or Sb.
In other embodiments, the semiconductor structure is a PMOS transistor, the second type of dopant ions are P-type ions, and specifically, the material of the fourth doped layer material layer is silicon germanium doped with P-type ions. This embodiment is achieved by doping P-type ions in silicon germanium. Specifically, the P-type ions include B, ga or In.
Referring to fig. 5, the fourth doping material layer 107, the second semiconductor material layer 106, the third doping material layer 105, the buffer material layer 104, the second doping material layer 103, and the first semiconductor material layer 102 are etched, forming a fourth doping layer 108, a second semiconductor pillar 109, a third doping layer 110, a buffer layer 111, a second doping layer 112, and a first semiconductor pillar 113, respectively.
The first semiconductor column 113, the first doped material layer 101, the second doped layer 112 and the subsequently formed first gate structure form a first transistor; the fourth doped layer 108, the second semiconductor pillar 109, the third doped layer 110 and a subsequently formed second gate structure constitute a second transistor. The conductivity types of doping ions of the third doped layer 110 and the second doped layer 112 are different, the buffer layer 111 enables the third doped layer 110 and the second doped layer 112 not to be in direct contact, the buffer layer 111 enables the doping ions in the second doped layer 112 not to be easily diffused into the third doped layer 110, the doping ions in the third doped layer 110 not to be easily diffused into the second doped layer 112, and the buffer layer 111 reduces the probability of junction leakage current between the first transistor and the second transistor; and because the conductivity types of the doped ions of the first transistor and the second transistor are different, the buffer layer 111 has a certain thickness, the distance between the second doped layer 112 and the third doped layer 110 is increased, the capacitive coupling effect of the second doped layer 112 and the third doped layer 110 is reduced, the junction capacitance between the first transistor and the second transistor is smaller, in sum, the probability of leakage current between the first transistor and the second transistor is reduced by the buffer layer 111, the junction capacitance between the first transistor and the second transistor is reduced, and the performance of the semiconductor structure is optimized.
The first semiconductor pillar 113 serves as a channel for the first transistor when the semiconductor structure is in operation.
In this embodiment, the first doped material layer 101 serves as the drain of the first transistor. In other embodiments, the first doped material layer may also serve as a source of the semiconductor structure.
In this embodiment, the second doped layer 112 serves as the source of the first transistor. In other embodiments, the second doped layer may also function as a drain for the semiconductor structure.
In this embodiment, the third doped layer 110 serves as the source of the second transistor. In other embodiments, the third doped layer may also function as a drain for the semiconductor structure.
The fourth doped layer 108 serves as the drain of the second transistor when the semiconductor structure is in operation. In other embodiments, the fourth doped layer serves as a source of the semiconductor structure.
In this embodiment, the second doped layer 112 and the third doped layer 110 are both sources. When the semiconductor structure works, the second doped layer 112 and the third doped layer 110 load the same voltage, so that the circuit structure of the semiconductor structure is simpler, and the function of the semiconductor structure is easier to realize.
In this embodiment, the fourth doped layer 108, the second semiconductor pillar 109, the third doped layer 110, the buffer layer 111, the second doped layer 112, and the first semiconductor pillar 113 are formed as a stacked structure.
In this embodiment, the fourth doped material layer 107, the second semiconductor material layer 106, the third doped material layer 105, the buffer material layer 104, the second doped material layer 103 and the first semiconductor material layer 102 are etched by a dry etching process to form a stacked structure. The dry etching process has anisotropic etching characteristics and better etching profile control, and is beneficial to better shape quality of the side walls of the formed fourth doped layer 108, the second semiconductor column 109, the third doped layer 110, the buffer layer 111, the second doped layer 112 and the first semiconductor column 113. And by changing the etching gas, the fourth doped material layer 107, the second semiconductor material layer 106, the third doped material layer 105, the buffer material layer 104, the second doped material layer 103 and the first semiconductor material layer 102 can be etched in the same etching apparatus, thereby simplifying the process steps.
It should be noted that, in the dry etching process, the first semiconductor material layer 102 and the first doped material layer 101 have a larger etching selectivity, and the top of the first doped material layer 101 can be used as an etching stop position, so as to avoid damage to the first doped material layer 101 and the substrate 100.
Before etching, a mask layer (not shown) is formed on the fourth doped material layer 107, and in the step of forming the stacked structure, the mask layer is used as an etching mask.
In this embodiment, the material of the mask layer 101 includes silicon nitride. In other embodiments, the material of the mask layer may further include: one or more of silicon oxynitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
It should be further noted that the method for forming a semiconductor structure further includes: an isolation layer 114 is formed on the first doped material layer 101 exposed by the first semiconductor pillar 113 (as shown in fig. 5), and the isolation layer 114 covers a portion of the sidewalls of the first semiconductor pillar 113.
The isolation layer 114 is used to electrically isolate the subsequently formed first gate structure from the first doped material layer 101, optimizing the electrical performance of the semiconductor structure.
In this embodiment, the material of the isolation layer 114 is an insulating material. Specifically, the material of the isolation layer 104 includes one or more of silicon oxide, silicon nitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the isolation layer 114 is silicon oxide.
Referring to fig. 6 to 8, a first gate structure 118 is formed on sidewalls of the first semiconductor pillar 113.
The first gate structure 118 and the first doped material layer 102, the first semiconductor pillar 113, and the second doped layer 112 serve as a first transistor.
Specifically, the step of forming the first gate structure 118 includes:
as shown in fig. 6, a first gate dielectric material layer 115 conformally covering the stacked structure and a first gate material layer 116 located on a surface of the first gate dielectric material layer 115 are formed, and the first gate dielectric material layer 115 extends to cover a part of the first doped material layer 101.
In this embodiment, the materials of the first gate dielectric material layer 115 include: hfO (HfO) 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO and Al 2 O 3 One or more of the following.
In this embodiment, the first gate material layer 116 includes a first work function material layer 1161 and a first gate electrode material layer 1162 located on a surface of the first work function material layer 1161.
The material of the first work function material layer 1161 includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide. The material of the first gate electrode material layer 1162 is magnesium-tungsten alloy. In other embodiments, the material of the first gate electrode material layer may also be W, al, cu, ag, au, pt, ni or Ti.
The forming steps of the first gate dielectric material layer 115 and the first gate material layer 116 include: forming a first gate dielectric material film (not shown) conformally covering the stack structures and the spacers 114 between the stack structures and a first gate material film (not shown) on the first gate dielectric material film; forming a first shielding layer covering a part of the region of the first gate material film; the first gate dielectric material film and the first gate material film are etched with the first blocking layer as a mask, the remaining first gate dielectric material film is used as the first gate dielectric material layer 115, and the remaining first gate material film is used as the first gate material layer 116.
In this embodiment, an atomic layer deposition process (Atomic layer deposition, ALD) is used to form a first gate dielectric material film. In other embodiments, a chemical vapor deposition process (ChemicalVapor Deposition, CVD) may also be used to form the first gate dielectric material film.
In this embodiment, an atomic layer deposition process is used to form the first gate material film. In other embodiments, the first gate material film may also be formed using a chemical vapor deposition process.
As shown in fig. 7, a first isolation structure 117 is formed to cover a portion of the sidewall of the first gate material layer 116, and a top surface of the first isolation structure 117 is lower than a top surface of the first semiconductor pillar 113.
The first isolation structure 117 provides for subsequent removal of the first gate dielectric material layer 115 and the first gate material layer 116 above the first isolation structure 117 to form a first gate structure.
The first isolation structure 117 is used to achieve electrical isolation between adjacent devices, and the material of the first isolation structure 117 is an insulating material. In this embodiment, the material of the first isolation structure 117 is silicon oxide. In other embodiments, the material of the first isolation structure may be another insulating material such as silicon nitride or silicon oxynitride.
As shown in fig. 8, the first gate dielectric material layer 115 and the first gate material layer 116 above the first isolation structure 117 are removed, and the remaining first gate dielectric material layer 115 and the remaining first gate material layer 116 serve as a first gate structure 118.
The first gate structure 118 is used to control the turning on and off of the channel of the first transistor during operation of the semiconductor structure.
The forming step of the first gate structure 118 includes: removing the first gate material layer 116 above the first isolation structures 117 using a dry etching process; after the first gate material layer 116 above the first isolation structure 117 is removed, a dry etching process is used to remove the first gate dielectric material layer 115 above the first isolation structure 117.
Specifically, the remaining first gate dielectric material layer 115 is used as the first gate dielectric layer 1181, the remaining first work function material layer 1161 is used as the first work function layer 1182, the remaining first gate electrode material layer 1162 is used as the first gate electrode layer 1183, and the first gate dielectric layer 1181, the first work function layer 1182 and the first gate electrode layer 1183 are used together as the first gate structure 118.
The dry etching process is adopted to remove the first gate dielectric material layer 115 and the first gate material layer 116 which are higher than the first isolation structure 117, so that the situation that the top of the formed first gate structure 118 is recessed (dishing) is avoided, the appearance quality of the first gate structure 118 is improved, and the control capability of the first gate structure on a channel is improved when the semiconductor structure works.
In the process of forming the first gate structure 118, the first gate dielectric material layer 115 higher than the first isolation structure 117 is removed to prepare for forming a second gate dielectric layer on the surface of the second semiconductor pillar 109.
Referring to fig. 9 to 11, after the first gate structure 118 is formed, a second gate structure 121 (shown in fig. 11) is formed on the sidewall of the second semiconductor pillar 109.
The second gate structure 120, the third doping 110, the second semiconductor pillar 109, and the fourth doped layer 108 act as a second transistor.
Specifically, the step of forming the second gate structure 121 includes:
as shown in fig. 10, a second gate dielectric material layer 119 conformally covering the second semiconductor pillars 109 and the fourth doped layer 108 and a second gate material layer 120 located on the surface of the second gate dielectric material layer 119 are formed.
In this embodiment, the materials of the second gate dielectric material layer 119 include: hfO (HfO) 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO and Al 2 O 3 One or more of the following.
In this embodiment, the second gate material layer 120 includes a second work function material layer 1201 and a second gate electrode material layer 1202 located on a surface of the second work function material layer 1201.
The material of the second work function material layer 1201 includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide.
The material of the second gate electrode material layer 1202 is magnesium-tungsten alloy. In other embodiments, the material of the second gate electrode material layer may also be W, al, cu, ag, au, pt, ni or Ti.
The forming step of the second gate dielectric material layer 119 and the second gate material layer 120 includes: forming a second gate dielectric material film (not shown) conformally covering the second semiconductor pillars 109 and the fourth doped layer 108 and a second gate material film (not shown) on the second gate dielectric material film; forming a second shielding layer covering a part of the region of the second gate material film; the second gate dielectric material film and the second gate material film are etched with the second blocking layer as a mask, the remaining second gate dielectric material film is used as the second gate dielectric material layer 119, and the remaining second gate material film is used as the second gate material layer 120.
In this embodiment, an atomic layer deposition process is used to form the second gate dielectric material film. In other embodiments, the second gate dielectric material film may also be formed using a chemical vapor deposition process.
In this embodiment, an atomic layer deposition process is used to form the second gate material film. In other embodiments, the second gate material film may also be formed using a chemical vapor deposition process.
As shown in fig. 11, a second isolation structure 122 is formed on a portion of the sidewall of the second gate material layer 120, and a top surface of the second isolation structure 122 is lower than a top surface of the second semiconductor pillar 109.
The second isolation structure 122 provides for subsequent removal of the second gate dielectric material layer 119 and the second gate material layer 120 above the second isolation structure 122. The second isolation structure 122 is also used to achieve electrical isolation between adjacent devices, and the material of the second isolation structure 122 is an insulating material. In this embodiment, the material of the second isolation structure 122 is silicon oxide, and in other embodiments, the material of the second isolation structure may be another insulating material such as silicon nitride or silicon oxynitride.
As shown in fig. 12, the second gate dielectric material layer 119 and the second gate material layer 120 higher than the second isolation structure 122 are removed, and the remaining second gate dielectric material layer 119 and second gate material layer 120 serve as a second gate structure 121.
The second gate structure 121 is used to control the opening and closing of the channel during operation of the semiconductor structure. The forming step of the second gate structure 121 includes: removing the second gate material layer 120 higher than the second isolation structure 122 using a dry etching process; after removing the second gate material layer 120 above the second isolation structure 122, a dry etching process is used to remove the second gate dielectric material layer 119 above the second isolation structure 122.
Specifically, the remaining second gate dielectric material layer 119 serves as a second gate dielectric layer 1211, the remaining second work function material layer 1201 serves as a second work function layer 1212, the remaining second gate electrode material layer 1202 serves as a second gate electrode layer 1213, and the second gate dielectric layer 1211, the second work function layer 1212, and the second gate electrode layer 1213 collectively serve as the second gate structure 121.
The dry etching process is adopted to remove the second gate dielectric material layer 119 and the second gate material layer 120 which are higher than the second isolation structure 122, so that the situation that the top of the formed second gate structure 121 is recessed (dishing) is avoided, the appearance quality of the second gate structure 121 is improved, and the control capability of the second gate structure 121 on the second semiconductor column 109 is improved when the semiconductor structure works.
Note that, as shown in fig. 9, the method for forming a semiconductor structure further includes: after forming the first gate structure 118 and before forming the second gate dielectric material layer 119, a third isolation structure 123 is formed on the first isolation structure 117, where the third isolation structure 123 covers the sidewalls of the second doped layer 112, the buffer layer 111 and the third doped layer 110, and covers a portion of the sidewalls of the second semiconductor pillar 109.
The third isolation structure 123 provides a process platform for the subsequent formation of the second gate structure.
The third isolation structure 123 is used to achieve electrical isolation between adjacent devices, and the material of the third isolation structure 123 is an insulating material. In this embodiment, the material of the third isolation structure 123 is silicon oxide, and in other embodiments, the material of the third isolation structure may be another insulating material such as silicon nitride or silicon oxynitride.
In the step of forming the second gate dielectric material layer 119, the second gate dielectric material layer 119 covers the second semiconductor pillar 109 and the fourth doped layer 108 higher than the third isolation structure 123, and the second gate dielectric material layer 119 further extends to cover the third isolation structure 123 in a partial region.
The second gate dielectric material layer 119 also extends over a portion of the region of the third isolation structure 123 in preparation for subsequent formation of a contact plug for connection to the second gate structure 121.
In the direction perpendicular to the sidewalls of the second semiconductor pillars 109, the second gate dielectric layer 1211 in the second transistor is generally larger than the first gate dielectric layer 1181. When the semiconductor structure is in operation, the carriers of the first transistor are holes, and the carriers of the second transistor are electrons, so that hot carrier effects are likely to occur in the second transistor, the reliability of the second transistor is poor, and accordingly, in the direction perpendicular to the sidewall of the second semiconductor pillar 109, the size of the second gate dielectric layer 1211 in the second transistor is generally larger than the size of the first gate dielectric layer 1181.
It should be noted that, in the direction perpendicular to the sidewall of the second semiconductor pillar 109, the size of the second gate dielectric layer 1211 is not much larger than that of the first gate dielectric layer 1181, and is not much larger than that of the first gate dielectric layer 1181. If the size of the second gate dielectric layer 1211 is too small compared with the size of the first gate dielectric layer 1181 in the direction perpendicular to the sidewall of the second semiconductor pillar 109, the second transistor is prone to generate hot carrier effect, so that the second gate structure 121 is prone to be damaged, and the electrical performance and reliability of the semiconductor structure are poor. If the second gate dielectric layer 1211 is too much larger than the first gate dielectric layer 1181 in the direction perpendicular to the sidewall of the second semiconductor pillar 109, the second gate structure 121 has poor control over the channel in the second semiconductor pillar 109 during operation of the semiconductor structure. In this embodiment, the second gate dielectric layer 1211 has a larger size than the first gate dielectric layer 1181 in a direction perpendicular to the sidewall of the second semiconductor column 109
Figure BDA0002362765820000141
To->
Figure BDA0002362765820000142
In the present embodiment, the second gate dielectric layer 1211 has a dimension larger than that of the first gate dielectric layer 1 in a direction perpendicular to the sidewall of the second semiconductor column 109181 is large in size
Figure BDA0002362765820000143
To->
Figure BDA0002362765820000144
Correspondingly, the size of the second gate dielectric material layer 119 is larger than the size of the first gate dielectric material layer 115>
Figure BDA0002362765820000145
To->
Figure BDA0002362765820000146
Referring to fig. 13, the method of forming a semiconductor structure further includes: forming a dielectric layer 124 covering the second isolation structure 122 and the fourth doped layer 108; after forming the dielectric layer 124, forming a first contact plug 125 penetrating the dielectric layer 124, the second isolation structure 122, the third isolation structure 123 and the first isolation structure 117 and connected to the first doped material layer 101; after forming the dielectric layer 124, a second contact plug 126 penetrating the dielectric layer 124 and connected to the fourth doped layer 108 is formed; after forming the dielectric layer 124, forming a third contact plug 127 penetrating the dielectric layer 124 and the second isolation structure 122 and connected to the second gate mechanism 121; a dielectric layer 124, a second isolation structure 122, a third isolation structure 123, and a fourth contact plug 128 connected to the first gate structure 121 are formed.
The first contact plug 125, the second contact plug 126, the third contact plug 127 and the fourth contact plug 128 are used for achieving electrical connection between the semiconductor structure and the semiconductor structure in addition to electrical connection within the semiconductor structure.
The materials of the first contact plug 125, the second contact plug 126, the third contact plug 127, and the fourth contact plug 128 include W, al, cu, ag or Au, etc.
The material of the dielectric layer 124 is an insulating material. The material of the dielectric layer 124 includes silicon oxide.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 13, a schematic structure diagram of an embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate 100; a first doped material layer 101 on the substrate 100; a first semiconductor pillar 113 on the first doped material layer 101; a second doped layer 112 on the first semiconductor pillar 113, the first doped material layer 101 and the second doped layer 112 having first type doping ions therein; a buffer layer 111 on the second doped layer 112; a third doped layer 110 on the buffer layer 111; a second semiconductor pillar 109 located on the third doped layer 110; a fourth doped layer 108 on the second semiconductor column 109, the third doped layer 110 and the fourth doped layer 108 having second type doping ions therein, the second type doping ions having a conductivity type different from that of the first type doping ions; a first gate structure 118 on a sidewall of the first semiconductor pillar 113; the second gate structure 121 is located on the sidewall of the second semiconductor pillar 109.
The first semiconductor pillar 113, the first doped material layer 101, the second doped layer 112, and the first gate structure 118 constitute a first transistor; a second gate structure 121 is formed on the sidewall of the second semiconductor pillar 109, and the fourth doped layer 108, the second semiconductor pillar 109, the third doped layer 110, and the second gate structure 121 constitute a second transistor. The conductivity types of doping ions of the third doped layer 110 and the second doped layer 112 are different, the buffer layer 111 enables the third doped layer 110 and the second doped layer 112 not to be in direct contact, the buffer layer 111 enables the doping ions in the second doped layer 112 not to be easily diffused into the third doped layer 110, the doping ions in the third doped layer 110 not to be easily diffused into the second doped layer 112, and the buffer layer 111 reduces the probability of junction leakage current between the first transistor and the second transistor; and because the conductivity types of the doped ions of the first transistor and the second transistor are different, the buffer layer 111 has a certain thickness, the distance between the second doped layer 112 and the third doped layer 110 is increased, the capacitive coupling effect of the second doped layer 112 and the third doped layer 110 is reduced, the junction capacitance between the first transistor and the second transistor is smaller, in sum, the probability of leakage current between the first transistor and the second transistor is reduced by the buffer layer 111, the junction capacitance between the first transistor and the second transistor is reduced, and the performance of the semiconductor structure is optimized.
The substrate 100 provides a process platform for the subsequent formation of semiconductor structures. In this embodiment, the material of the substrate 100 comprises silicon. In other embodiments, the material of the substrate may also include one or more of germanium, silicon carbide, gallium arsenide, and indium gallium.
The first doped material layer 101 serves as the drain of the first transistor. In other embodiments, the first doped material layer serves as a source of the semiconductor structure.
In this embodiment, the semiconductor structure is a PMOS transistor, the first type of doped ions are P-type ions, and specifically, the material of the first doped material layer 101 is silicon germanium doped with P-type ions. This embodiment is achieved by doping P-type ions in silicon germanium. Specifically, the P-type ions include B, ga or In.
In other embodiments, the semiconductor structure is an NMOS transistor, the first type of dopant ions are N-type ions, and specifically, the material of the first doped material layer is silicon carbide or silicon phosphide doped with N-type ions, respectively. By doping N-type ions in silicon carbide or silicon phosphide. Specifically, the N-type ions include P, as or Sb.
The first semiconductor pillars 113 act as channels during operation of the semiconductor structure.
In this embodiment, when the PMOS transistor is operated, the carriers are holes, and accordingly, the material of the first semiconductor pillar 113 includes SiGe or Si. SiGe or Si is a material of a channel region of the PMOS transistor, so that the mobility of carriers in a channel is higher when the semiconductor structure works, and the electrical property of the semiconductor structure is improved.
The second doped layer 112 serves as the source of the first transistor. In other embodiments, the second doped layer may also serve as the drain of the first transistor.
In this embodiment, the semiconductor structure is a PMOS transistor, the first type doped ions are N type ions, and specifically, the material of the second doped layer 112 is silicon germanium doped with P type ions. This embodiment is achieved by doping P-type ions in silicon germanium. Specifically, the P-type ions include B, ga or In.
In other embodiments, the semiconductor structure is an NMOS transistor, the first type of doping ions are N-type ions, and specifically, the material of the second doped layer 112 is silicon carbide or silicon phosphide doped with N-type ions, respectively. By doping N-type ions in silicon carbide or silicon phosphide. Specifically, the N-type ions include P, as or Sb.
The buffer layer 111 is a semiconductor layer doped with impurity ions. The buffer layer 111 is a semiconductor layer so that the first transistor and the second transistor can be electrically connected when the semiconductor structure is in operation.
The impurity ions can plug the lattice gap of the material in the buffer layer 111, so that the impurity ions of the second doped layer 112 are not easily diffused into the third doped layer 110, so that the impurity ions of the third doped layer 110 are not easily diffused into the second doped layer 112.
In this embodiment, the material of the buffer layer 111 includes Si or SiGe having C. In other embodiments, si or SiGe with N.
C can plug the lattice gap of the material in the buffer layer 111, blocking the ion penetration, and C can form covalent bonds with Si or SiGe in the buffer layer 111, which have a stable spatial electric field, and can also block the ion movement. In summary, the C-doped Si or SiGe can prevent impurity ions in the second doped layer 112 and the third doped layer 110 from diffusing along the lattice.
In other embodiments, N can plug the lattice gap of the material in the buffer layer, blocking the ion from passing through, and N can form a covalent bond with Si in the buffer layer, the covalent bond having a stable spatial electric field, and also blocking the ion motion. In summary, N-doped Si or SiGe can prevent impurity ions in the second doped layer and the third doped layer from diffusing along the lattice.
It should be noted that the buffer layer 111 should not be too thick or too thin. If the buffer layer 111 is too thick, the interval between the second doped layer 112 and the third doped layer 110 is too large, and when the semiconductor structure works, carriers are blocked by the buffer layer 111 too much, which is not beneficial to improving the migration rate of carriers. If the buffer layer 111 is too thin, the dopant ions of the second doped layer 112 are easy to diffuse into the third doped layer 110, so that the dopant ions of the third doped layer 110 are easy to diffuse into the second doped layer 112, and the probability of junction leakage current between the second doped layer 112 and the third doped layer 110 is high, which is not beneficial to optimizing the performance of the semiconductor structure; in addition, if the buffer layer 111 is too thin, the distance between the second doped layer 112 and the third doped layer 110 is not easy to be significantly increased, and the capacitive coupling effect between the second doped layer 112 and the third doped layer 110 is relatively strong, which is not beneficial to optimizing the performance of the semiconductor structure. In this embodiment, the thickness of the buffer layer 111 is 2 nm to 8 nm.
The impurity ion doping concentration in the buffer layer 111 should not be too high or too low. If the doping concentration of the impurity ions in the buffer layer 111 is too large, lattice mismatch of the buffer layer 111 is easily caused, the lattice of the buffer layer 111 is deformed, so that the doped ions of the second doped layer 112 are easily diffused into the third doped layer 110 through the buffer layer 111, so that the doped ions of the third doped layer 110 are easily diffused into the second doped layer 112 through the buffer layer 111, and the probability of junction leakage current between the second doped layer 112 and the third doped layer 110 is relatively high, which is unfavorable for optimizing the performance of the semiconductor structure. If the doping concentration of the impurity ions in the buffer layer 111 is too small, the impurity ions are not easy to plug the lattice gap of the material of the buffer layer 111, which is easy to cause that the buffer layer 111 cannot well block the impurity ions in the second doped layer 112 from diffusing into the third doped layer 110, and cannot well block the impurity ions in the third doped layer 110 from diffusing into the second doped layer 112, so that the probability of junction leakage current between the second doped layer 112 and the third doped layer 110 is larger, and the capacitive coupling effect between the second doped layer 112 and the third doped layer 110 is easy to be stronger, which is unfavorable for optimizing the performance of the semiconductor structure. In this embodiment, the doping concentration of the impurity ions in the buffer layer 111 is 8.0E19 atoms per cubic centimeter to 5.0E20 atoms per cubic centimeter.
The third doped layer 110 serves as the source of the second transistor. In other embodiments, the third doped layer may also serve as the drain of the second transistor.
In this embodiment, the semiconductor structure is an NMOS transistor, the second type of doped ions are N-type ions, and specifically, the material of the third doped layer 110 is silicon carbide or silicon phosphide doped with N-type ions, respectively. By doping N-type ions in silicon carbide or silicon phosphide. Specifically, the N-type ions include P, as or Sb.
In other embodiments, the semiconductor structure is a PMOS transistor, the second type of dopant ions are P-type ions, and specifically, the material of the third doped layer is silicon germanium doped with P-type ions. This embodiment is achieved by doping P-type ions in silicon germanium. Specifically, the P-type ions include B, ga or In.
The second semiconductor pillar 109 serves as a channel for the second transistor during operation of the semiconductor structure. The material of the second semiconductor pillars 109 comprises InGaAs or GaAs.
The fourth doped layer 108 serves as the drain of the second transistor. In other embodiments, the fourth doped layer may also serve as the source of the second transistor.
In this embodiment, the semiconductor structure is an NMOS transistor, the second type of doped ions are N-type ions, and specifically, the material of the fourth doped layer 108 is silicon carbide or silicon phosphide doped with N-type ions, respectively. By doping N-type ions in silicon carbide or silicon phosphide. Specifically, the N-type ions include P, as or Sb.
In other embodiments, the semiconductor structure is a PMOS transistor, the second type of doped ions are P-type ions, and specifically, the material of the fourth doped layer 108 is silicon germanium doped with P-type ions. This embodiment is achieved by doping P-type ions in silicon germanium. Specifically, the P-type ions include B, ga or In.
In this embodiment, the second doped layer 112 and the third doped layer 110 are both sources. When the semiconductor structure works, the second doped layer 112 and the third doped layer 110 load the same voltage, so that the circuit structure of the semiconductor structure is simpler, and the function of the semiconductor structure is easier to realize.
The first gate structure 118 controls the opening and closing of the channel in the first semiconductor pillar 113 during operation of the semiconductor structure. The first gate structure 118 includes a first gate dielectric layer 1181, a first work function layer 1182 disposed on the surface of the first gate dielectric layer 1181, and a first gate electrode layer 1183 disposed on the surface of the first work function layer 1182. The second gate structure 121 also extends the first doped material layer 101 covering a partial region. In this embodiment, the material of the first gate dielectric layer 1181 includes HfO 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO and Al 2 O 3 One or more of the following. The material of the first work function layer 1182 includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide. The material of the first gate electrode layer 1183 is magnesium-tungsten alloy. In other embodiments, the material of the first gate electrode layer may also be W, al, cu, ag, au, pt, ni or Ti.
The semiconductor structure further includes: the first isolation structure 117 is located on the first doped material layer 101 and covers the sidewall of the first gate structure 118, and the top surface of the first isolation structure 117 is lower than the top surface of the first semiconductor pillar 113. The first isolation structures 117 serve to electrically isolate adjacent devices.
The first isolation structure 117 is used to achieve electrical isolation between adjacent devices, and the material of the first isolation structure 117 is an insulating material. In this embodiment, the material of the first isolation structure 117 is silicon oxide, and in other embodiments, the material of the first isolation structure may be another insulating material such as silicon nitride or silicon oxynitride.
The semiconductor structure further includes: and a third isolation structure 123. The third isolation structure 123 provides support for the second gate structure 121.
The material of the third isolation structure 123 is an insulating material. In this embodiment, the material of the third isolation structure 123 is silicon oxide, and in other embodiments, the material of the third isolation structure may be another insulating material such as silicon nitride or silicon oxynitride.
The second gate structure 121 controls the opening and closing of the channel in the second semiconductor column 109 during operation of the semiconductor structure. In this embodiment, the second gate structure 121 includes a second gate dielectric layer 1211, a second work function layer 1212, and a second gate electrode layer 1213. The second gate structure 121 also extends the third doped layer 123 covering a partial region. In this embodiment, the materials of the second gate dielectric layer 1211 include: hfO (HfO) 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO, hfZrO and Al 2 O 3 One or more of the following. The material of the second work function layer 1212 includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide. The material of the second gate electrode layer 1213 is magnesium-tungsten alloy. In other embodiments, the material of the second gate electrode layer may also be W, al, cu, ag, au, pt, ni or Ti.
In the direction perpendicular to the sidewalls of the second semiconductor pillars 109, the second gate dielectric layer 1211 in the second transistor is generally larger than the first gate dielectric layer 1181. When the semiconductor structure is in operation, the carriers of the first transistor are holes, and the carriers of the second transistor are electrons, so that hot carrier effects are likely to occur in the second transistor, the reliability of the second transistor is poor, and accordingly, in the direction perpendicular to the sidewall of the second semiconductor pillar 109, the size of the second gate dielectric layer 1211 in the second transistor is generally larger than the size of the first gate dielectric layer 1181.
It should be noted that, in the direction perpendicular to the sidewall of the second semiconductor pillar 109, the size of the second gate dielectric layer 1211 is not much larger than that of the first gate dielectric layer 1181, and is not much larger than that of the first gate dielectric layer 1181. If the size of the second gate dielectric layer 1211 is too small compared with the size of the first gate dielectric layer 1181 in the direction perpendicular to the sidewall of the second semiconductor pillar 109, hot carrier effect is easily generated in the second transistor, so that the second gate structure 121 is easily damaged, resulting in poor electrical performance and reliability of the semiconductor structure. If the second gate dielectric layer 1211 is too much larger than the first gate dielectric layer 1181 in the direction perpendicular to the sidewall of the second semiconductor pillar 109, the second gate structure 121 has poor control over the channel in the second semiconductor pillar 109 during operation of the semiconductor structure. In this embodiment, the second gate dielectric layer 1211 is thicker than the first gate dielectric layer 1181 in a direction perpendicular to the sidewall of the second semiconductor column 109
Figure BDA0002362765820000201
To->
Figure BDA0002362765820000202
The semiconductor structure further includes: the second isolation structure 122 is located on a part of the sidewall of the second gate structure 121, and the top surface of the second isolation structure 122 is lower than the top surface of the second semiconductor pillar 109.
The second isolation structure 122 is used to achieve electrical isolation between adjacent devices, and the material of the second isolation structure 122 is an insulating material. In this embodiment, the material of the second isolation structure 122 is silicon oxide, and in other embodiments, the material of the second isolation structure may be another insulating material such as silicon nitride or silicon oxynitride.
The semiconductor structure may be formed by the forming method of the foregoing embodiment, or may be formed by other forming methods. For a specific description of the semiconductor structure of the present embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a substrate, a first doped material layer positioned on the substrate, a first semiconductor material layer positioned on the first doped material layer, and a second doped material layer positioned on the first semiconductor material layer, and the first doped material layer and the second doped material layer are provided with first type doping ions;
forming a buffer material layer on the substrate;
forming a third doped material layer, a second semiconductor material layer and a fourth doped material layer on the buffer material layer in sequence, wherein second type doped ions are arranged in the third doped material layer and the fourth doped material layer, and the second type doped ions are different from the first type doped ions in conductivity type;
Etching the fourth doped material layer, the second semiconductor material layer, the third doped material layer, the buffer material layer, the second doped material layer and the first semiconductor material layer by taking the top of the first doped material layer as an etching stop position to form a fourth doped layer, a second semiconductor column, a third doped layer, a buffer layer, a second doped layer and a first semiconductor column respectively;
forming a first gate structure on a sidewall of the first semiconductor column;
forming a second gate structure on the side wall of the second semiconductor column after forming the first gate structure;
after the first grid electrode structure is formed and before the second grid electrode structure is formed, a third isolation structure is formed on the first grid electrode structure, and covers the side wall of the second doping layer, the side wall of the buffer layer and the side wall of the third doping layer and covers part of the side wall of the second semiconductor column.
2. The method of forming a semiconductor structure according to claim 1, wherein the buffer layer is a semiconductor layer doped with impurity ions.
3. The method of forming a semiconductor structure according to claim 1 or 2, wherein the material of the buffer layer includes Si or SiGe having C or Si or SiGe having N.
4. The method of forming a semiconductor structure of claim 1, wherein the buffer layer has a thickness of 2 nm to 8 nm.
5. The method of forming a semiconductor structure of claim 1, wherein the step of forming the buffer material layer comprises: and forming an epitaxial layer on the substrate by adopting a selective epitaxial growth process, and carrying out in-situ ion doping on the epitaxial layer in the process of forming the epitaxial layer to form a buffer material layer.
6. The method of forming a semiconductor structure of claim 5, wherein in the step of in-situ ion doping the epitaxial layer, a dopant amount of impurity ions in the epitaxial layer is 8.0E14 atoms per square centimeter to 5.0E15 atoms per square centimeter.
7. The method of claim 1, wherein the buffer material layer is formed using an atomic layer deposition process or a chemical vapor deposition process.
8. The method of claim 1, wherein In the step of providing a substrate, the first type dopant ions are P-type ions, the P-type ions comprising B, ga or In; the material of the first semiconductor material layer comprises SiGe or Si; in the step of providing the fourth doped material layer and the third doped material layer, the second type doped ions are N type ions, and the N type ions comprise P, as or Sb; the material of the second semiconductor material layer comprises InGaAs or GaAs;
Or alternatively, the process may be performed,
in the step of providing a substrate, the first type doped ions are N type ions, and the N type ions comprise P, as or Sb; the material of the first semiconductor material layer comprises InGaAs or GaAs; in the step of providing the fourth doped material layer and the third doped material layer, the second type doped ions are P-type ions, and the P-type ions comprise B, ga or In; the material of the second semiconductor material layer comprises SiGe or Si.
9. The method of forming a semiconductor structure according to claim 1, wherein the fourth doped layer, the second semiconductor pillar, the third doped layer, the buffer layer, the second doped layer, and the first semiconductor pillar are formed as a stacked structure;
the step of forming the first gate structure includes: forming a first gate dielectric material layer conformally covering the laminated structure and a first gate material layer positioned on the surface of the first gate dielectric material layer, wherein the first gate dielectric material layer extends to cover the first doping material layer of a partial area;
forming a first isolation structure covering a part of the side wall of the first gate material layer, wherein the top surface of the first isolation structure is lower than the top surface of the first semiconductor column;
And removing the first gate dielectric material layer and the first gate material layer which are higher than the first isolation structure, and taking the rest of the first gate dielectric material layer and the first gate material layer as the first gate structure.
10. The method of forming a semiconductor structure of claim 9, wherein the step of forming a second gate structure comprises: forming a second gate dielectric material layer which conformally covers the second semiconductor column and the fourth doped layer and a second gate material layer positioned on the surface of the second gate dielectric material layer;
forming a second isolation structure on a part of the side wall of the second gate material layer, wherein the top surface of the second isolation structure is lower than the top surface of the second semiconductor column;
and removing the second gate dielectric material layer and the second gate material layer which are higher than the second isolation structure, and taking the remaining second gate dielectric material layer and second gate material layer as a second gate structure.
11. The method of forming a semiconductor structure of claim 10, wherein in the step of forming the second gate structure, a dimension of the second gate dielectric material layer is 2 a to 5 a greater than a dimension of the first gate dielectric material layer in a direction perpendicular to the second semiconductor pillar sidewall.
12. The method of forming a semiconductor structure of claim 10, wherein the material of the first gate dielectric material layer comprises: one or more of HfO2, zrO2, hfSiO, hfSiON, hfTaO, hfTiO, hfZrO, and Al2O 3;
the second gate dielectric material layer comprises the following materials: hfO (HfO) 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO and Al 2 O 3 One or more of the following.
13. A semiconductor structure, comprising:
a substrate;
a first doped material layer on the substrate;
the first semiconductor column is positioned on the first doped material layer, and part of the first doped material layer is exposed out of the first semiconductor column; the second doped layer is positioned on the first semiconductor column, and first type doped ions are arranged in the first doped material layer and the second doped layer;
a buffer layer located on the second doped layer;
a third doped layer located on the buffer layer; a second semiconductor pillar located on the third doped layer; a fourth doped layer located on the second semiconductor column, wherein second type doped ions are arranged in the third doped layer and the fourth doped layer, and the second type doped ions are different from the first type doped ions in conductivity type;
A first gate structure located on a sidewall of the first semiconductor column; a second gate structure on a sidewall of the second semiconductor pillar;
and the third isolation structure is positioned above the first grid structure, covers the side wall of the second doping layer, the side wall of the buffer layer and the side wall of the third doping layer, and covers part of the side wall of the second semiconductor column.
14. The semiconductor structure of claim 13, wherein the buffer layer is a semiconductor layer doped with impurity ions.
15. The semiconductor structure of claim 13, wherein the material of the buffer layer comprises Si or SiGe with C or Si or SiGe with N.
16. The semiconductor structure of claim 13, wherein the buffer layer has a thickness of 2 nm to 8 nm.
17. The semiconductor structure of claim 13, wherein a doping concentration of impurity ions in the buffer layer is 8.0E19 atoms per cubic centimeter to 5.0E20 atoms per cubic centimeter.
18. The semiconductor structure of claim 13, wherein the first type dopant ions are P-type ions comprising B, ga or In; the material of the first semiconductor column comprises SiGe or Si; the second type doped ions are N type ions, and the N type ions comprise P, as or Sb; the material of the second semiconductor column comprises InGaAs or GaAs;
Or the first type doped ions are N type ions, wherein the N type ions comprise P, as or Sb; the material of the first semiconductor column comprises InGaAs or GaAs; the second type doped ions are P-type ions, and the P-type ions comprise B, ga or In; the material of the second semiconductor column comprises SiGe or Si.
19. The semiconductor structure of claim 13, wherein the semiconductor structure further comprises: the first isolation structure is positioned on the first doped material layer and covers the side wall of the first grid structure, and the top surface of the first isolation structure is lower than the top surface of the first semiconductor column.
20. The semiconductor structure of claim 13, wherein the semiconductor structure further comprises: and the second isolation structure is positioned on part of the side wall of the second grid structure, and the top surface of the second isolation structure is lower than the top surface of the second semiconductor column.
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