CN110164968A - Semiconductor devices and forming method thereof - Google Patents
Semiconductor devices and forming method thereof Download PDFInfo
- Publication number
- CN110164968A CN110164968A CN201810141390.2A CN201810141390A CN110164968A CN 110164968 A CN110164968 A CN 110164968A CN 201810141390 A CN201810141390 A CN 201810141390A CN 110164968 A CN110164968 A CN 110164968A
- Authority
- CN
- China
- Prior art keywords
- groove
- layer
- source
- plug portion
- portion serve
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 238000000034 method Methods 0.000 title claims abstract description 52
- 238000002955 isolation Methods 0.000 claims abstract description 69
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 230000000873 masking effect Effects 0.000 claims description 39
- 239000000463 material Substances 0.000 claims description 36
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 3
- 238000009271 trench method Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 264
- 230000003071 parasitic effect Effects 0.000 description 29
- 229910052751 metal Inorganic materials 0.000 description 17
- 239000002184 metal Substances 0.000 description 17
- 238000000137 annealing Methods 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 239000011241 protective layer Substances 0.000 description 13
- 230000004888 barrier function Effects 0.000 description 10
- 150000002500 ions Chemical class 0.000 description 10
- 238000005530 etching Methods 0.000 description 8
- 239000007789 gas Substances 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 238000005224 laser annealing Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 2
- -1 phosphonium ion Chemical class 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A kind of semiconductor devices and forming method thereof, wherein semiconductor devices includes: substrate；Positioned at intrabasement isolation structure；Gate structure in substrate, and the gate structure extends on isolation structure；Positioned at the intrabasement source and drain doping layer in gate structure two sides；It is located at the conductive structure of gate structure two sides, the conductive structure extends on isolation structure from source and drain doping layer, the conductive structure includes: the first plug portion serve for covering source and drain doping layer and the second plug portion serve for covering isolation structure, the side wall of first plug portion serve has first distance to neighboring gate structures side wall, the side wall of second plug portion serve has second distance to neighboring gate structures side wall, the first distance is less than second distance, and the width of the first plug portion serve is greater than the width of the second plug portion serve.The performance of the semiconductor devices is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of semiconductor devices and forming method thereof.
Background technique
MOS (Metal-oxide-semicondutor) transistor is one of most important element in modern integrated circuits.MOS is brilliant
The basic structure of body pipe includes: semiconductor substrate；Positioned at the gate structure of semiconductor substrate surface, the gate structure includes:
Gate electrode layer positioned at the gate dielectric layer of semiconductor substrate surface and positioned at gate dielectric layer surface；Positioned at gate structure two sides
Source and drain doping layer in semiconductor substrate.
With the development of semiconductor technology, the MOS transistor of traditional plane formula becomes the control ability of channel current
It is weak, cause serious leakage current.Fin formula field effect transistor (Fin FET) is a kind of emerging multi-gate device, it is generally comprised
The fin of semiconductor substrate surface, the top surface of fin described in covering part and the gate structure of side wall are protruded from, grid are located at
Source and drain doping layer in the fin of pole structure two sides.
However, the performance for the semiconductor devices that fin formula field effect transistor is constituted in the prior art is still to be improved.
Summary of the invention
The technical problem to be solved by the present invention is to provide a kind of semiconductor devices and forming method thereof, to improve semiconductor device
The performance of part.
In order to solve the above technical problems, the present invention provides a kind of semiconductor devices, comprising: substrate；Positioned at it is intrabasement every
From structure；Gate structure in substrate, and the gate structure extends on isolation structure；Positioned at gate structure two sides
Intrabasement source and drain doping layer；It is located at the conductive structure of gate structure two sides, the conductive structure prolongs from source and drain doping layer
It extends on isolation structure, the conductive structure includes: the first plug portion serve and covering isolation structure for covering source and drain doping layer
The side wall of second plug portion serve, first plug portion serve has first distance, second plug portion serve to neighboring gate structures side wall
Side wall to neighboring gate structures side wall have second distance, the first distance be less than second distance, the first plug portion serve
Width is greater than the width of the second plug portion serve.
Optionally, the width of first plug portion serve is 17nm~62nm.
Optionally, the width of second plug portion serve is 15nm~50nm.
Optionally, the difference of the width of the width and the second plug portion serve of first plug portion serve is 2nm~12nm.Optionally,
The first distance is 20nm~100nm.
Optionally, the second distance is 22nm~112nm.
Optionally, the difference of the second distance and first distance is 2nm~12nm.
The present invention also provides a kind of forming methods of semiconductor devices, comprising: provides substrate, the substrate has isolation
Structure；It is to form gate structure in substrate, the gate structure extends on isolation structure；Substrate in gate structure two sides
Interior formation source and drain doping layer；Conductive structure is formed in gate structure two sides, the conductive structure is across source and drain doping layer and extension
To isolation structure, the conductive structure covers source and drain doping layer atop part surface and partial sidewall surface and isolation junction
Structure part of the surface, the conductor structure include: cover source and drain doping layer the first plug portion serve and cover isolation structure second
The side wall of plug portion serve, first plug portion serve has first distance, the side of first plug portion serve to neighboring gate structures side wall
Wall has second distance to neighboring gate structures side wall, and the first distance is less than second distance, and from gate structure side
Source and drain doping layer to the direction of the source and drain doping layer of the other side on, the size of the first plug portion serve is greater than the ruler of the second plug portion serve
It is very little.
Optionally, the difference of the width of the width and the second plug portion serve of first plug portion serve is 2nm~12nm.
Optionally, it is formed before conductive structure, is formed and be situated between on the isolation structure, gate structure and source and drain doping layer
Matter layer, the dielectric layer cover grid structural top surface；The conductive structure is located in the dielectric layer.
Optionally, the forming method of the conductive structure includes: to be developed across source in the dielectric layer of gate structure two sides
The groove of doped layer is leaked, the groove extending direction is parallel with gate structure extending direction, and the groove exposes source and drain doping
The part of the surface on layer atop part surface and partial sidewall surface and isolation structure, the groove include first groove area and
Second groove area, the first groove area expose source and drain doping floor atop part surface and partial sidewall surface, and described second
Trench area exposes the part of the surface of isolation structure, and second groove side wall is relative to first groove side walls collapse；In first groove
The first plug portion serve of interior formation, forms the second plug portion serve in second groove.
Optionally, the forming method of the groove includes: that the first Patterned masking layer is formed on dielectric layer, and described first
Patterned masking layer exposes the location and shape of groove, using first Patterned masking layer as exposure mask, etches the medium
Layer, exposes the part of the surface of source and drain doping layer part of the surface and isolation structure, is formed in the dielectric layer of gate structure two sides
Along gate structure extending direction across the groove of source and drain doping layer.
Optionally, the forming method of the groove includes: that initial trench is formed in dielectric layer, and the initial trench is sudden and violent
The part for exposing source and drain doping layer atop part surface and partial sidewall surface is initial first groove, and the initial trench is sudden and violent
The part for exposing isolation structure part of the surface is second groove, and initial first groove is adjacent with second groove, initial first groove
Side wall is flushed with second groove side wall；After forming initial trench, initial first groove is handled, so that initial first ditch
Groove sidewall is opened up with respect to the side wall of second groove along perpendicular to gate structure extending direction and perpendicular to the width in substrate surface direction
Width, to form the groove.
Optionally, the forming method of the initial trench includes: the second graphical mask layer on dielectric layer, with described
Second graphical mask layer is exposure mask, etches the dielectric layer, exposes the portion of source and drain doping layer part of the surface and isolation structure
Divide surface, is formed along gate structure extending direction in the dielectric layer of gate structure two sides across the initial ditch of source and drain doping layer
Slot, it is initial first ditch that the initial trench, which exposes source and drain doping layer atop part surface and the part on partial sidewall surface,
Slot, the part that the groove exposes isolation structure part of the surface is second groove, initial first groove and second groove phase
Neighbour, initial first groove side wall are flushed with second groove side wall.
Optionally, the forming method of the groove includes: the formation third Patterned masking layer on dielectric layer, and described the
Three Patterned masking layers etch the medium using the third Patterned masking layer as exposure mask due to the position for going out first groove
Layer forms first groove until exposing the part of the surface of source and drain doping layer part of the surface and isolation structure；Form the first ditch
After slot, the 4th Patterned masking layer, the 4th Patterned masking layer are formed on first groove, third Patterned masking layer
The dielectric layer is etched using the 4th Patterned masking layer as exposure mask due to the position of second groove out, until exposing
The part of the surface of isolation structure forms second groove, to form the groove.
Optionally, the first plug portion serve is formed in first groove, and the method packet of the second plug portion serve is formed in second groove
It includes: forming plug material layer in first groove and second groove；After forming plug material layer, the plug material is planarized
Layer, exposes dielectric layer surface, forms the first plug portion serve in first groove, form the second plug portion serve in second groove.
Optionally, the first distance is 20nm~100nm.
Optionally, the second distance is 22nm~112nm.
Optionally, the difference of the second distance and first distance is 2nm~12nm.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
In semiconductor devices provided by the invention, the first plug portion serve and covering isolation structure of source and drain doping layer are covered
The second plug portion serve, the second plug portion serve apart from neighboring gate structures distance farther out, the between the second plug portion serve and gate structure
Two parasitic capacitances are smaller.The size of first plug portion serve is larger, and the first plug portion serve and the contact area of source and drain doping layer are larger, the
One plug portion serve and the contact resistance of source and drain doping layer are smaller.The parasitic capacitance of semiconductor devices is by the first parasitic capacitance and second
Parasitic capacitance composition, by control the first plug portion serve and the second plug portion serve size, can obtain lesser parasitic capacitance and compared with
Small contact resistance, to improve the performance of device.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of semiconductor devices forming process；
Fig. 2 to Figure 12 is the structural schematic diagram of semiconductor devices forming process in one embodiment of the invention.
Specific embodiment
As described in background, the performance for the semiconductor devices that the prior art is formed is poor.
Fig. 1 is a kind of structural schematic diagram of semiconductor devices forming process.
With reference to Fig. 1, substrate 100 is provided, the substrate 100 has fin 110 and isolation structure, isolation structure covering part
Divide 110 side wall of fin；Gate structure 120, source and drain doping layer and dielectric layer are formed, gate structure 110 is located in substrate 100 horizontal
Across the fin 110, source and drain doping layer is located in the fin 110 of 120 two sides of gate structure, and dielectric layer is located at source and drain doping layer
On gate structure 120；In the dielectric layer of 120 two sides of gate structure formed from source and drain doping layer extend to isolation structure and
Expose the through-hole of part source and drain doping layer surface and isolation structure part of the surface；Plug 130 is formed in the through-hole.
It is isolated between the gate structure and plug by dielectric layer, forms parasitic capacitance, the parasitic electricity therebetween
Appearance consists of two parts, and parasitic capacitance between plug and gate structure above source and drain doping layer and is located at isolation junction
The parasitic capacitance between plug and gate structure above structure.Resistance between the source and drain doping layer and plug is to contact electricity
Resistance.
The plug has along fin extending direction and perpendicular to the width in substrate surface direction, and the plug is located at source
Leakage doping layer surface and the equivalent width positioned at isolation structure surface.The width of plug on source and drain doping layer is bigger, source
The contact resistance leaked between doped layer and plug is smaller, and the distance between plug and gate structure are closer, plug and gate structure
Between parasitic capacitance it is bigger.It therefore, is the contact resistance and parasitic capacitance of balance semiconductor device, the width of plug is certain,
Contact resistance at this time between source and drain doping layer and plug is larger, and the parasitic capacitance between plug and gate structure is also larger, and half
Conductor performance is bad.
The present invention by be located at the area source and drain Can Ceng on plug size and isolation structure on plug size not
With design, to reduce the parasitic capacitance and dead resistance of semiconductor devices.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention is described in detail.
Fig. 2 to Figure 12 is the structural schematic diagram of semiconductor devices forming process in one embodiment of the invention.
With reference to Fig. 2, substrate is provided.
It is that example is illustrated by fin formula field effect transistor of the semiconductor devices, in other realities in the present embodiment
It applies in example, semiconductor devices is the MOS transistor of plane formula.
In the present embodiment, the substrate includes semiconductor substrate 200 and the fin 210 in semiconductor substrate 200.
In other embodiments, when semiconductor devices is the MOS transistor of plane formula, substrate is the semiconductor substrate of plane formula.
In the present embodiment, also there is isolation structure 201 in the semiconductor substrate 200, isolation structure 201 covers fin
210 partial sidewall, the top surface of the isolation structure 201 are lower than the top surface of fin 210.The isolation structure 201
Material include silica.
With continued reference to Fig. 2, forms gate structure 220, source and drain doping layer 250 and dielectric layer, gate structure 220 and be located at base
On bottom, source and drain doping layer 250 is located in the substrate of 220 two sides of gate structure, and dielectric layer is located at source and drain doping layer 250 and grid
In structure 220, there is source and drain ion in the source and drain doping layer 250.
In the present embodiment, the gate structure 220 includes the boundary layer in substrate, and the grid on boundary layer are situated between
Matter layer and the gate electrode layer on gate dielectric layer.The material of the boundary layer is silica, and the material of gate dielectric layer is high K
(K is greater than 3.9) dielectric material, the material of the gate electrode layer are metal, such as tungsten.In other embodiments, gate structure 220
It further include the grid protection layer positioned at 220 bodies top of gate structure.
In the present embodiment, gate structure 220 is across the atop part surface and part side of fin 210 and covering fin 210
Wall surface.The gate dielectric layer is located at the part of the surface of isolation structure 201, covers the atop part surface and part of fin 210
Sidewall surfaces.
In the present embodiment, the substrate further includes positioned at the first side wall 221 of 220 side wall of gate structure and positioned at first
Second side wall 222 of 221 side wall of side wall.
The dielectric layer includes underlying dielectric layer 240 and top layer dielectric layer 241, underlying dielectric layer 240 be located in substrate and
220 side wall of gate structure is covered, top layer dielectric layer 241 is located in underlying dielectric layer 240 and gate structure 220.
Specifically, dummy gate structure 220 is formed on the substrate；The first side is sequentially formed in the side wall of dummy gate structure 220
Wall 221 and the second side wall 222；Source and drain doping layer is formed in the substrate of 222 two sides of dummy gate structure 220 and the second side wall
250；After forming source and drain doping layer 250, initial protective layers, the initial protective layers are formed on source and drain doping layer 250 and substrate
Cover the side wall of the second side wall 222 and the top surface of top surface and dummy gate structure 220；After forming protective layer, in source
The protective layer of leakage doped layer 250 and substrate surface forms initial underlying dielectric layer；After forming initial underlying dielectric layer, put down
The smoothization initial underlying dielectric layer is until exposing 220 top surface of dummy gate structure, forming underlying dielectric layer 240 and protecting
Sheath 230, the underlying dielectric layer 240 cover the side wall of the second side wall 222 and expose the second side wall 22 top surface and
The top surface of dummy gate structure 220；After forming underlying dielectric layer 240, dummy gate structure 220 is removed, in underlying dielectric layer
Grid opening is formed in 240；Gate structure 220 is formed in grid opening；In gate structure 220, underlying dielectric layer 240, the first side
Top layer dielectric layer 241 is formed on wall 221 and the second side wall 222.
The material of the underlying dielectric layer 240 and top layer dielectric layer 241 is silica.
The protective layer 230 protects source and drain doping layer when being subsequently formed second groove.
The material of the protective layer 230 is different from the material of dielectric layer.The material of the protective layer includes: silicon nitride, nitrogen
Silica, silicon oxide carbide, carbonitride of silicium or carbon silicon oxynitride.
In the present embodiment, the material of the protective layer 230 is silicon nitride.The material of dielectric layer is silica, silicon nitride phase
There is good etching selection ratio for silica, in subsequent etching dielectric layer, while capable of guaranteeing silicon,
It is less to the etching of silicon nitride, it can be well protected source and drain doping layer.
The source and drain doping layer 250 is located in the substrate of 220 two sides of gate structure, specifically, 250, source and drain doping layer
In the fin 210 of 220 two sides of gate structure.
The source and drain doping layer 250 has source and drain ion.
When the type of the semiconductor devices is N-type, the conduction type of source and drain ion is N-type, such as phosphonium ion；Work as institute
When the type for stating semiconductor devices is p-type, the conduction type of source and drain ion is p-type, such as boron ion.
In the present embodiment, source and drain doping layer 250 is formed using epitaxial growth technology.Correspondingly, working as the semiconductor devices
Type when being N-type, the material of source and drain doping layer 250 is the silicon with source and drain ion；When the type of the semiconductor devices is
When p-type, the material of source and drain doping layer 250 is the germanium silicon with source and drain ion.In other embodiments, source and drain doping layer 250 is adopted
It is formed with ion implantation technology.
Be developed across the groove of source and drain doping layer in the dielectric layer of gate structure two sides, the groove extending direction with
Gate structure extending direction is consistent, the groove expose source and drain doping layer atop part surface and partial sidewall surface and
The part of the surface of isolation structure.
The forming method of the groove please refers to Fig. 3 to Fig. 6.
With reference to Fig. 3, the first Patterned masking layer 231 is formed on dielectric layer, first Patterned masking layer 231 is sudden and violent
Expose the location and shape of the subsequent groove 260 needed to form.
In the present embodiment, formed the first Patterned masking layer 231 the step of include: that first is formed on dielectric layer
Mask layer (not shown)；After forming the first mask layer, processing is exposed to first mask layer, the exposure template is
Graphical template, the graphical template expose the location and shape of the subsequent groove needed to form, to first exposure mask
Layer carries out development treatment, exposes the location and shape of the subsequent groove needed to form, forms the first Patterned masking layer 231.
The material of first Patterned masking layer 231 includes photoresist.
In one embodiment, the material of first Patterned masking layer 231 is silicon nitride.Form first figure
The step of changing mask layer 231 includes: formation original mask layer (not shown) on dielectric layer；After forming original mask layer, first
Patterned layer is formed on beginning mask layer, the patterned layer exposes the location and shape of the subsequent groove needed to form, with institute
Stating patterned layer is exposure mask, etches the original mask layer, forms the first Patterned masking layer 231.The material of described image layer
Material includes photoresist.
After first Patterned masking layer 231 determines that the shape and size for the groove being subsequently formed, the groove are interior
Extended meeting forms conductive structure, the i.e. shape and size that the first Patterned masking layer 231 determines subsequent conductive structure.
With reference to Fig. 4 and Fig. 5, Fig. 5 be the semiconductor devices top view, Fig. 4 be Fig. 5 tangentially the direction A-A1 cut
Face figure is exposure mask with first Patterned masking layer 231, etches the medium after forming the first Patterned masking layer 231
Layer, exposes the part of the surface of source and drain doping layer 250 part of the surface and isolation structure 201, Jie in 220 two sides of gate structure
Groove 260 is formed in matter layer.
260 extending direction of groove is consistent with 220 extending direction of gate structure, and the groove 260 exposes source and drain and mixes
The part of the surface of 250 atop part surface of diamicton and partial sidewall surface and isolation structure 201.
It is first that the groove 260, which exposes 250 atop part surface of source and drain doping layer and the part on partial sidewall surface,
Trench area 261, the part that the groove 260 exposes isolation structure part of the surface is second groove area 262, first groove area
261 is adjacent with second groove area 262, and 262 side wall of second groove area is relative to 261 side walls collapse of first groove area.
Source and drain doping of the first groove area 261 from the source and drain doping floor 250 of 220 side of gate structure to the other side
Width on the direction of layer 250 is the first width, source and drain doping floor of the second groove area 262 from 220 side of gate structure
Width on 250 to the direction of the source and drain doping layer 250 of the other side is the second width, and the second width is less than the first width.
It is subsequently formed the first plug portion serve 301 in the first groove area 261, is subsequently formed second in second groove area 262
Plug portion serve 302.The position and width in first groove area 261 and second groove area 262 determine the first plug portion serve being subsequently formed
301 and second plug portion serve 302 position and width.
The distance at 260 centre distance gate structure of groove, 220 center is fixed, the second groove on isolation structure 201
262 narrower width of area, the second plug portion serve 302 being subsequently formed apart from gate structure 220 farther out, the second plug portion serve 302 and grid
The second parasitic capacitance between structure 220 is smaller, while 261 wider width of first groove area on source and drain doping floor 250, after
Continuous the first plug portion serve 301 formed and the contact area of source and drain doping layer 250 are larger, and contact resistance is smaller.Semiconductor devices
Parasitic capacitance is made of the first parasitic capacitance and the second parasitic capacitance, passes through the first plug portion serve 301 of control and the second plug portion serve
302 size can obtain small parasitic capacitance and small contact resistance, to improve the performance of semiconductor devices.
Specifically, being formed, the dielectric layer is etched in the method for the groove 260 is 220 two sides of etching grid structure
Dielectric layer forms groove 260 in the dielectric layer of 220 two sides of gate structure.
The technique of the dielectric layer of 220 two sides of etching grid structure includes anisotropy dry carving technology.
In the present embodiment, using the parameter packet of the dielectric layer of 220 two sides of anisotropy dry carving technology etching grid structure
Include: the gas of use includes CF4Gas, CH3F gas and O2, CF4The flow of gas is 5sccm~100sccm, CH3F gas
Flow is 8sccm~50sccm, O2Flow be 10sccm~100sccm, chamber pressure be 10mtorr~2000mtorr,
Radio-frequency power is 50W~300W, and voltage is 30V~100V, and the time is 4 seconds~50 seconds.
In other embodiments, the forming method of the groove 260 can also be formed for exposure mask twice.
In one embodiment, the forming method of the groove 260 includes: that initial trench is formed in dielectric layer, described first
It is initial first groove that beginning groove, which exposes 250 atop part surface of source and drain doping layer and the part on partial sidewall surface, described
The part that initial trench exposes 201 part of the surface of isolation structure is second groove area 262, initial first groove and the second ditch
Slot area 262 is adjacent, and initial first groove side wall is flushed with 262 side wall of second groove area；After forming initial trench, to initial the
One groove is handled so that initial first groove side wall with respect to second groove area 262 side wall from 220 side of gate structure
Source and drain doping layer 250 to the direction of the source and drain doping layer 250 of the other side on width widen, formed first groove area 261,
To form the groove 260.
The forming method of the initial trench includes: the second graphical mask layer on dielectric layer, with the second graph
Change mask layer is exposure mask, etches the dielectric layer, exposes the part table of 250 part of the surface of source and drain doping layer and isolation structure
Face is formed along 220 ontology of gate structure, 220 structure extending direction in the dielectric layer of 220 two sides of gate structure across source and drain doping
The initial trench of layer 250, the initial trench expose 250 atop part surface of source and drain doping layer and partial sidewall surface
Part is initial first groove, and the part that the groove exposes 201 part of the surface of isolation structure is second groove area 262, just
Beginning first groove is adjacent with second groove area 262, and initial first groove side wall is flushed with 262 side wall of second groove area.
Graphics shape in the second graphical mask layer is rectangle.
In another embodiment, the forming method of the groove 260 includes: the formation third pattern mask on dielectric layer
Layer, the third Patterned masking layer are to cover with the third Patterned masking layer due to the position for going out first groove area 261
Film etches the dielectric layer, until exposing the part of the surface of source and drain doping layer part of the surface and isolation structure, forms first
Trench area 261；After forming first groove area 261, the 4th figure is formed in first groove area 261 and third Patterned masking layer
Shape mask layer, the 4th Patterned masking layer are with the 4th Patterned masking layer due to the position for going out second groove
Exposure mask etches the dielectric layer, until exposing the part of the surface of isolation structure 201, forms second groove area 262, thus
Form the groove 260.
With reference to Fig. 6, after forming groove 260, the first Patterned masking layer 231 is removed.
The technique for removing the first Patterned masking layer 231 includes cineration technics.
In the present embodiment, the formation process of the groove 260 further include: after the first Patterned masking layer 231 of removal, carve
The protective layer 230 on 250 surface of source and drain doping floor that etching off is exposed except first groove area 261, exposes source and drain doping layer 250
Surface.In other embodiments, 250 surface of source and drain doping layer does not form protective layer 230, does not need removal protective layer 230.
It removes and removes protective layer 230 again after the first Patterned masking layer 231 and can be avoided cineration technics to source and drain doping layer
250 influence.
The technique of the protective layer 230 on 250 surface of source and drain doping floor that etching removal first groove area 261 exposes is each
To the dry etch process of the same sex, the technological parameter includes: that the gas of use includes CF4Gas, CH2F2Gas and O2, CF4Gas
The flow of body is 30sccm~200sccm, CH2F2The flow of gas is 8sccm~50sccm, O2Flow be 2sccm~
30sccm, chamber pressure be 10mtorr~2000mtorr, radio-frequency power be 100W~1000W, DC current be 30V~
500V, time are 4 seconds~50 seconds.
With reference to Fig. 7, after forming groove 260, metal layer 270 is formed in 260 bottom surface of groove and sidewall surfaces.
The material of the metal layer 270 includes Ti, Co or Ni.
The metal layer 270 is also located on dielectric layer.
The technique for forming metal layer 270 is depositing operation, such as sputtering technology.
The metal layer 270 and source and drain doping layer 250 are made annealing treatment after forming metal layer 270 with reference to Fig. 8,
Metal silicide layer 280 is formed on 250 surface of source and drain doping floor that first groove area 261 exposes.
In the present embodiment, when being made annealing treatment, the atom of metal layer 270 diffuses to source and drain doping layer 250 and and source and drain
250 material of doped layer reacts to form metal silicide layer 280.
The effect of the annealing further include: the second ion in activation source and drain doped layer 250.
In the present embodiment, due in the surfacing of source and drain doping layer 250 doped with source and drain ion, metal silication
Doped with source and drain ion in nitride layer 280, the resistance of metal silicide layer 280 is reduced.
The annealing includes laser annealing or spike annealing.
The annealing includes: laser annealing and spike annealing heating using the benefit of laser annealing or spike annealing
Process is very fast, avoids temperature-rise period that the ion of the doped region of semiconductor devices is caused to have biggish diffusion, improves doped region
The stability in domain.
In the present embodiment, before carrying out subsequent annealing, barrier layer also is formed on 270 surface of metal layer and (is not schemed
Show).The material on the barrier layer includes titanium nitride or tantalum nitride.The technique for forming the barrier layer is depositing operation, is such as sputtered
Technique.
In the present embodiment, barrier layer is formed before annealing, during being made annealing treatment, barrier layer energy
Enough guard metal layer 270, stop annealing to cause to aoxidize to metal layer 270.
In one embodiment, at a temperature of annealing in order to prevent, the material on barrier layer recrystallizes and leads to barrier layer
The poor problem of stability, the temperature of selective annealing processing is at 900 degrees Celsius or less.
In other embodiments, barrier layer is formed after anneal.
In other embodiments, barrier layer is not formed.
With reference to Fig. 9, after being made annealing treatment, conductive structure is formed in groove 260 (referring to Fig. 8) and on dielectric layer
Material layer 290.
In the present embodiment, conductive structure material layer 290 is located at barrier layer surface.
The material of the conductive structure material layer 290 is metal, such as tungsten.
The technique for forming conductive structure material layer 290 is depositing operation, as chemical vapor deposition process, physical vapor are heavy
Product technique or atom layer deposition process.
Please refer to Figure 10 to Figure 12, Figure 10 is the top view of the device, and Figure 11 is that Figure 10 tangentially cut by the direction A-A1
Face figure, Figure 12 are the sectional view in the tangentially direction A2-A3 Figure 10.It planarizes the conductive structure material layer 290 and exposes medium
Layer top surface, forms conductive structure 300.
300 extending direction of conductive structure is consistent with 220 extending direction of gate structure, and the conductive structure 300 covers
The part of the surface of 250 atop part surface of source and drain doping layer and partial sidewall surface and isolation structure 201；The conductive knot
It is the first plug portion serve 301 that structure 300, which covers 250 atop part surface of source and drain doping layer and the part on partial sidewall surface, described to lead
The part that electric structure 300 covers 201 surface of isolation structure is the second plug portion serve 302, the first plug portion serve 301 and the second plug portion serve
302 is adjacent, and 302 side wall of the second plug portion serve is relative to 301 side walls collapse of the first plug portion serve.
In the present embodiment, conductive structure material layer 290 and metal layer 270 are planarized, until exposing table at the top of dielectric layer
Face makes the conductive structure material layer 290 in first groove area 261 form the first plug portion serve 301, makes in second groove area 262
Conductive structure material layer 290 forms the second plug portion serve 302.
The distance of the side wall of first plug portion serve 301 to 220 side wall of neighboring gate structures is first distance, described the
The distance of the side wall of two plug portion serves 302 to 220 side wall of neighboring gate structures is second distance, and the first distance is less than second
Distance.
The side wall of first plug portion serve 301 has first distance L3, L3 20nm to 220 side wall of neighboring gate structures
~100nm
The side wall of second plug portion serve 302 has second distance L4, L4 22nm to 220 side wall of neighboring gate structures
~112nm.
The difference of the first distance L3 and second distance L4 is 2nm~12nm.
The distance between conductive structure 300 and gate structure 220 influence the size of parasitic capacitance between the two, and second inserts
Apart from neighboring gate structures 220 apart from farther out, second between the second plug portion serve 302 and gate structure 220 is parasitic for piston part 302
Capacitor is smaller；First plug portion serve 301 is closer apart from neighboring gate structures 220, and first between gate structure 220 is posted
Raw capacitor is larger；The parasitic capacitance of semiconductor devices is made of the first parasitic capacitance and the second parasitic capacitance, passes through control first
The size of plug portion serve 301 and the second plug portion serve 302, enables to semiconductor devices to obtain lesser parasitic capacitance, to improve
The performance of semiconductor devices.
The difference of the first distance L3 and second distance L4 are by the first plug portion serve 301 and the second plug portion serve 302 from grid knot
Width difference on the source and drain doping layer of 220 side of structure to the direction of the source and drain doping layer of the other side determines.
Source and drain doping layer of first plug portion serve 301 from the source and drain doping layer of 220 side of gate structure to the other side
The of same size of width on direction and first groove area 261 be the first width L1, L1 is 17nm~62nm.
Source and drain doping layer of second plug portion serve 302 from the source and drain doping layer of 220 side of gate structure to the other side
The of same size of width on direction and second groove area 262 be the second width L2, L2 is 15nm~50nm.
Second width is less than the first width, from the source and drain doping layer of 220 side of gate structure to the source and drain doping of the other side
Width of the width of second plug portion serve less than the first plug portion serve on the direction of layer.
The difference of first width and the second width is 2nm~12nm.
When the difference of first width and the second width is greater than 12nm, the dead resistance of the second plug portion serve 292 is excessive, is unfavorable for
When the difference of the performance of device, the first width and the second width is less than 2nm, between the second plug portion serve 292 and gate structure 220
Parasitic capacitance improvement is unobvious, and device performance does not significantly improve.
The distance at 300 centre distance gate structure of conductive structure, 220 center is fixed, and second on isolation structure inserts
302 narrower width of piston part, farther out apart from gate structure 220, second between the second plug portion serve 302 and gate structure 220 are parasitic
Capacitor is smaller, while 301 wider width of the first plug portion serve on source and drain doping layer 250, the first plug portion serve 301 and source and drain doping
The contact area of layer 250 is larger, and contact resistance is smaller.The parasitic capacitance of semiconductor devices is posted by the first parasitic capacitance and second
Raw capacitor composition can obtain lesser parasitic capacitance by controlling the size of the first plug portion serve 301 and the second plug portion serve 302
With lesser contact resistance, to improve the performance of device.
Correspondingly, the present embodiment also provides a kind of structure of semiconductor devices, Figure 10 is please referred to Figure 12, comprising: is provided
Substrate；Positioned at intrabasement isolation structure 201；Gate structure 220 in substrate, and the gate structure 220 extends to
On isolation structure 201；Positioned at the intrabasement source and drain doping layer 250 in 220 two sides of gate structure；It is located at 220 liang of gate structure
The conductive structure 300 of side, the conductive structure 300 extend on isolation structure 201 from source and drain doping layer 250, the conductive knot
Structure 300 includes: the first plug portion serve 301 for covering source and drain doping layer 250 and the second plug portion serve for covering isolation structure 201
302, the side wall of first plug portion serve 301 has first distance, second plug portion serve to 220 side wall of neighboring gate structures
302 side wall has second distance to 220 side wall of neighboring gate structures, and the first distance is less than second distance, and from grid
On the source and drain doping layer 250 of 220 side of pole structure to the direction of the source and drain doping layer 250 of the other side, the first plug portion serve 301
Size is greater than the size of the second plug portion serve 302.
Source and drain doping layer of first plug portion serve 301 in the source and drain doping layer from 220 side of gate structure to the other side
Direction on width be mutually all the first width L1, L1 with first groove be 17nm~62nm.
Source and drain doping layer of second plug portion serve 302 in the source and drain doping layer from 220 side of gate structure to the other side
Direction on width be mutually all the second width L2, L2 with second groove be 15nm~50nm.
Second width is less than the first width, and the second plug portion serve is in the source and drain doping layer from 220 side of gate structure to another
Width on the direction of the source and drain doping layer of side is less than the first plug portion serve.
The difference of first width L1 and the second width L2 are 2nm~12nm.
The first distance L3 is 20nm~100nm.
The second distance L4 is 22nm~112nm.
The difference of the second distance L4 and first distance L3 is 2nm~12nm.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from
It in the spirit and scope of the present invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim
Subject to limited range.
Claims (19)
1. a kind of semiconductor devices characterized by comprising
Substrate；
Positioned at intrabasement isolation structure；
Gate structure in substrate, and the gate structure extends on isolation structure；
Positioned at the intrabasement source and drain doping layer in gate structure two sides；
It is located at the conductive structure of gate structure two sides, the conductive structure extends on isolation structure from source and drain doping layer,
The conductive structure includes:
It covers the first plug portion serve of source and drain doping layer and covers the second plug portion serve of isolation structure, the side of first plug portion serve
Wall has a first distance to neighboring gate structures side wall, and the side wall of second plug portion serve to neighboring gate structures side wall is with the
Two distances, the first distance are less than second distance, and the width of the first plug portion serve is greater than the width of the second plug portion serve.
2. semiconductor devices as described in claim 1, which is characterized in that the width of first plug portion serve be 17nm~
62nm。
3. semiconductor devices as claimed in claim 2, which is characterized in that the width of second plug portion serve be 15nm~
50nm。
4. semiconductor devices as claimed in claim 4, which is characterized in that the width and the second plug portion serve of first plug portion serve
Width difference be 2nm~12nm.
5. semiconductor devices as described in claim 1, which is characterized in that the first distance is 20nm~100nm.
6. semiconductor devices as claimed in claim 5, which is characterized in that the second distance is 22nm~112nm.
7. semiconductor devices as claimed in claim 6, which is characterized in that the difference of the second distance and first distance is 2nm
~12nm.
8. a kind of forming method of semiconductor devices characterized by comprising
Substrate is provided, the substrate has isolation structure；
It is to form gate structure in substrate, the gate structure extends on isolation structure；
Source and drain doping layer is formed in the substrate of gate structure two sides；
Conductive structure is formed in gate structure two sides, the conductive structure is across source and drain doping layer and extends on isolation structure,
The conductive structure covering source and drain doping layer atop part surface and partial sidewall surface and isolation structure part of the surface, it is described
Conductor structure includes:
It covers the first plug portion serve of source and drain doping layer and covers the second plug portion serve of isolation structure, the side of first plug portion serve
Wall has a first distance to neighboring gate structures side wall, and the side wall of first plug portion serve to neighboring gate structures side wall is with the
Two distances, the first distance are less than second distance, and in the source and drain of the source and drain doping layer from gate structure side to the other side
On the direction of doped layer, the size of the first plug portion serve is greater than the size of the second plug portion serve.
9. the forming method of semiconductor devices as claimed in claim 8, which is characterized in that the width of first plug portion serve with
The difference of the width of second plug portion serve is 2nm~12nm.
10. the forming method of semiconductor devices as claimed in claim 8, which is characterized in that formed before conductive structure, in institute
It states and forms dielectric layer on isolation structure, gate structure and source and drain doping layer, the dielectric layer covers grid structural top surface；Institute
Conductive structure is stated to be located in the dielectric layer.
11. the forming method of semiconductor devices as claimed in claim 10, which is characterized in that the formation side of the conductive structure
Method includes: the groove that source and drain doping layer is developed across in the dielectric layer of gate structure two sides, the groove extending direction and grid
Pole structure extending direction is parallel, and the groove exposes source and drain doping layer atop part surface and partial sidewall surface and isolation
The part of the surface of structure, the groove include first groove area and second groove area, and the first groove area exposes source and drain and mixes
Diamicton atop part surface and partial sidewall surface, the second groove area expose the part of the surface of isolation structure, the second ditch
Groove sidewall is relative to first groove side walls collapse；The first plug portion serve is formed in first groove, and second is formed in second groove
Plug portion serve.
12. the forming method of semiconductor devices as claimed in claim 11, which is characterized in that the forming method packet of the groove
It including: forming the first Patterned masking layer on dielectric layer, first Patterned masking layer exposes the location and shape of groove, with
First Patterned masking layer is exposure mask, etches the dielectric layer, exposes source and drain doping layer part of the surface and isolation structure
Part of the surface, in the dielectric layer of gate structure two sides formed along gate structure extending direction across the ditch of source and drain doping layer
Slot.
13. the forming method of semiconductor devices as claimed in claim 11, which is characterized in that the forming method packet of the groove
It includes: forming initial trench in dielectric layer, the initial trench exposes source and drain doping layer atop part surface and partial sidewall
The part on surface is initial first groove, and the part that the initial trench exposes isolation structure part of the surface is second groove,
Initial first groove is adjacent with second groove, and initial first groove side wall is flushed with second groove side wall；After forming initial trench,
Initial first groove is handled, so that initially first groove side wall is with respect to the side wall of second groove along perpendicular to gate structure
It extending direction and is widened perpendicular to the width in substrate surface direction, forms first groove.
14. the forming method of semiconductor devices as claimed in claim 13, which is characterized in that the formation side of the initial trench
Method includes: the second graphical mask layer on dielectric layer, using the second graphical mask layer as exposure mask, etches the medium
Layer, exposes the part of the surface of source and drain doping layer part of the surface and isolation structure, is formed in the dielectric layer of gate structure two sides
Along gate structure extending direction across the initial trench of source and drain doping layer, the initial trench exposes source and drain doping layer part top
The part on portion surface and partial sidewall surface is initial first groove, and the groove exposes the part of isolation structure part of the surface
For second groove, initial first groove is adjacent with second groove, and initial first groove side wall is flushed with second groove side wall.
15. the forming method of semiconductor devices as claimed in claim 11, which is characterized in that the forming method packet of the groove
It including: forming third Patterned masking layer on dielectric layer, the third Patterned masking layer schedules the position of first groove, with
The third Patterned masking layer is exposure mask, etches the dielectric layer, until exposing source and drain doping layer part of the surface and isolation
The part of the surface of structure forms first groove；After forming first groove, formed on first groove, third Patterned masking layer
4th Patterned masking layer, the 4th Patterned masking layer are graphically covered due to the position for going out second groove with the described 4th
Film layer is exposure mask, etches the dielectric layer, until exposing the part of the surface of isolation structure, forms second groove.
16. the forming method of semiconductor devices as claimed in claim 11, which is characterized in that form first in first groove
Plug portion serve, the method that the second plug portion serve is formed in second groove include: the formation plug material in first groove and second groove
The bed of material；After forming plug material layer, the plug material layer is planarized, dielectric layer surface is exposed, is formed in first groove
First plug portion serve forms the second plug portion serve in second groove.
17. the forming method of semiconductor devices as claimed in claim 8, which is characterized in that the first distance be 20nm~
100nm。
18. the forming method of semiconductor devices as claimed in claim 17, which is characterized in that the second distance be 22nm~
112nm。
19. the forming method of semiconductor devices as claimed in claim 18, which is characterized in that the second distance and first away from
From difference be 2nm~12nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810141390.2A CN110164968B (en) | 2018-02-11 | 2018-02-11 | Semiconductor device and method of forming the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810141390.2A CN110164968B (en) | 2018-02-11 | 2018-02-11 | Semiconductor device and method of forming the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110164968A true CN110164968A (en) | 2019-08-23 |
| CN110164968B CN110164968B (en) | 2022-08-26 |
Family
ID=67635042
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810141390.2A Active CN110164968B (en) | 2018-02-11 | 2018-02-11 | Semiconductor device and method of forming the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110164968B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113540019A (en) * | 2020-04-20 | 2021-10-22 | 中芯国际集成电路制造(上海)有限公司 | Variable capacitor and method for forming variable capacitor |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07240501A (en) * | 1994-02-28 | 1995-09-12 | Nec Corp | Semiconductor integrated circuit device |
| CN104037226A (en) * | 2013-03-08 | 2014-09-10 | 台湾积体电路制造股份有限公司 | Finfet With An Asymmetric Source/drain Structure And Method Of Making Same |
| US20150243747A1 (en) * | 2014-02-21 | 2015-08-27 | Samsung Electronics Co., Ltd. | Integrated circuit devices including contacts and methods of forming the same |
| CN104979201A (en) * | 2014-04-03 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| US20160027727A1 (en) * | 2014-07-25 | 2016-01-28 | SK Hynix Inc. | Semiconductor device with air gaps and method for fabricating the same |
| US20160372467A1 (en) * | 2015-06-22 | 2016-12-22 | Samsung Electronics Co., Ltd. | Semiconductor device |
| CN107068761A (en) * | 2016-02-10 | 2017-08-18 | 台湾积体电路制造股份有限公司 | Semiconductor element and its manufacture method |
-
2018
- 2018-02-11 CN CN201810141390.2A patent/CN110164968B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07240501A (en) * | 1994-02-28 | 1995-09-12 | Nec Corp | Semiconductor integrated circuit device |
| CN104037226A (en) * | 2013-03-08 | 2014-09-10 | 台湾积体电路制造股份有限公司 | Finfet With An Asymmetric Source/drain Structure And Method Of Making Same |
| US20150243747A1 (en) * | 2014-02-21 | 2015-08-27 | Samsung Electronics Co., Ltd. | Integrated circuit devices including contacts and methods of forming the same |
| CN104979201A (en) * | 2014-04-03 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| US20160027727A1 (en) * | 2014-07-25 | 2016-01-28 | SK Hynix Inc. | Semiconductor device with air gaps and method for fabricating the same |
| US20160372467A1 (en) * | 2015-06-22 | 2016-12-22 | Samsung Electronics Co., Ltd. | Semiconductor device |
| CN107068761A (en) * | 2016-02-10 | 2017-08-18 | 台湾积体电路制造股份有限公司 | Semiconductor element and its manufacture method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113540019A (en) * | 2020-04-20 | 2021-10-22 | 中芯国际集成电路制造(上海)有限公司 | Variable capacitor and method for forming variable capacitor |
| CN113540019B (en) * | 2020-04-20 | 2023-07-21 | 中芯国际集成电路制造(上海)有限公司 | Variable capacitor and method for forming variable capacitor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110164968B (en) | 2022-08-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106684144B (en) | The manufacturing method of semiconductor structure | |
| CN108231588A (en) | Transistor and forming method thereof | |
| CN110416081A (en) | The selectivity of the regions and source/drain of NFET/PFET is recessed | |
| CN106158617A (en) | Semiconductor devices and manufacture method thereof | |
| CN108807378A (en) | Fin field effect pipe and forming method thereof | |
| CN109427664A (en) | Semiconductor structure and forming method thereof | |
| CN109994547A (en) | Semiconductor devices and forming method thereof | |
| CN105448730B (en) | Semiconductor structure and forming method thereof | |
| CN109979986B (en) | Semiconductor device and method of forming the same | |
| CN107039335B (en) | The forming method of semiconductor structure | |
| CN106158638B (en) | Fin formula field effect transistor and forming method thereof | |
| CN106158637B (en) | Fin formula field effect transistor and forming method thereof | |
| CN106558608A (en) | Semiconductor device and forming method thereof | |
| CN107346730B (en) | Improve the method for performance of semiconductor device | |
| CN109872953A (en) | Semiconductor devices and forming method thereof | |
| CN110164968A (en) | Semiconductor devices and forming method thereof | |
| CN107785265A (en) | The forming method of semiconductor devices | |
| CN107369621A (en) | Fin formula field effect transistor and forming method thereof | |
| CN109285808A (en) | Semiconductor devices and forming method thereof | |
| CN108630549A (en) | Semiconductor devices and forming method thereof | |
| CN106328530B (en) | Fin formula field effect transistor and forming method thereof | |
| CN107591327B (en) | Method for forming fin field effect transistor | |
| CN109659233A (en) | Semiconductor devices and forming method thereof | |
| CN106328706B (en) | The forming method of fin formula field effect transistor | |
| CN105097522B (en) | Semiconductor devices and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |