CN107785265A - The forming method of semiconductor devices - Google Patents
The forming method of semiconductor devices Download PDFInfo
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- CN107785265A CN107785265A CN201610744155.5A CN201610744155A CN107785265A CN 107785265 A CN107785265 A CN 107785265A CN 201610744155 A CN201610744155 A CN 201610744155A CN 107785265 A CN107785265 A CN 107785265A
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- 238000000034 method Methods 0.000 title claims abstract description 108
- 239000004065 semiconductor Substances 0.000 title claims abstract description 72
- 239000010410 layer Substances 0.000 claims abstract description 398
- 239000003989 dielectric material Substances 0.000 claims abstract description 78
- 238000002955 isolation Methods 0.000 claims abstract description 70
- 239000002243 precursor Substances 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000007772 electrode material Substances 0.000 claims abstract description 27
- 239000011229 interlayer Substances 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims description 37
- 230000008569 process Effects 0.000 claims description 30
- 230000003647 oxidation Effects 0.000 claims description 17
- 238000007254 oxidation reaction Methods 0.000 claims description 17
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 238000005137 deposition process Methods 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims 1
- 230000006866 deterioration Effects 0.000 abstract description 10
- 238000005530 etching Methods 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 4
- 229910021419 crystalline silicon Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910021486 amorphous silicon dioxide Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013039 cover film Substances 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
A kind of forming method of semiconductor devices, including：Semiconductor substrate is provided, there is fin and isolation structure in the Semiconductor substrate, the isolation structure covers fin partial sidewall；Surface with fin on the isolation structure forms precursor layer；The precursor layer is aoxidized, forms pseudo- gate dielectric material layer；Pseudo- layer of gate electrode material is formed on pseudo- gate dielectric material layer；Graphical pseudo- layer of gate electrode material and pseudo- gate dielectric material layer, form pseudo- gate dielectric layer and the pseudo- gate electrode layer on pseudo- gate dielectric layer, the pseudo- gate dielectric layer is located at the surface of isolation structure, the top surface and sidewall surfaces of covering part fin；The interlayer dielectric layer for the side wall for covering pseudo- gate dielectric layer and pseudo- gate electrode layer is formed on isolation structure and fin；Remove pseudo- gate electrode layer and pseudo- gate dielectric layer.The forming method of the semiconductor devices can reduce the extent of deterioration to isolation structure.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of forming method of semiconductor devices.
Background technology
MOS (Metal-oxide-semicondutor) transistor, is one of most important element in modern integrated circuits, and MOS is brilliant
The basic structure of body pipe includes：Semiconductor substrate；Positioned at the grid structure of semiconductor substrate surface, the grid structure includes：
Gate dielectric layer positioned at semiconductor substrate surface and the gate electrode layer positioned at gate dielectric layer surface；Positioned at grid structure both sides half
Source and drain doping area in conductor substrate.
With the development of semiconductor technology, the MOS transistor of traditional plane formula dies down to the control ability of channel current,
Cause serious leakage current.Fin formula field effect transistor (Fin FET) is a kind of emerging multi-gate device, and it generally comprises protrusion
In the fin of semiconductor substrate surface, the top surface of fin described in covering part and the grid structure of side wall, positioned at grid knot
Source and drain doping area in the fin of structure both sides.
However, the performance for the semiconductor devices that fin formula field effect transistor is formed has much room for improvement in the prior art.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of forming method of semiconductor devices, to reduce the loss to isolation structure
Degree.
To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, including：Semiconductor lining is provided
Bottom, has fin and isolation structure in the Semiconductor substrate, and the isolation structure covers fin partial sidewall；In the isolation
Surface in structure with fin forms precursor layer；The precursor layer is aoxidized, forms pseudo- gate dielectric material layer；In pseudo- gate dielectric material
Pseudo- layer of gate electrode material is formed on layer；Graphical pseudo- layer of gate electrode material and pseudo- gate dielectric material layer, formed pseudo- gate dielectric layer and
Pseudo- gate electrode layer on pseudo- gate dielectric layer, the pseudo- gate dielectric layer are located at the surface of isolation structure, covering part fin
Top surface and sidewall surfaces；The layer for the side wall for covering pseudo- gate dielectric layer and pseudo- gate electrode layer is formed on isolation structure and fin
Between dielectric layer；Remove pseudo- gate electrode layer and pseudo- gate dielectric layer.
Optionally, formed the technique of the precursor layer for atom layer deposition process, plasma activated chemical vapour deposition technique,
Low-pressure chemical vapor deposition process or sub-atmospheric pressure chemical vapor deposition method.
Optionally, the material of the precursor layer is non-crystalline silicon.
Optionally, the technique for forming the precursor layer is low-pressure chemical vapor deposition process, and parameter includes：The gas of use
Including SiH4, SiH4Flow be 30sccm~300sccm, temperature is 260 degrees Celsius~520 degrees Celsius, pressure 0.03torr
~1torr.
Optionally, temperature that the precursor layer uses is aoxidized as 850 degrees Celsius~1050 degrees Celsius, and the time is 5 seconds~500
Second.
Optionally, the technique for aoxidizing the precursor layer is dry oxidation technique or wet process oxidation technology.
Optionally, the thickness of the pseudo- gate dielectric material layer is 15 angstroms~80 angstroms.
Optionally, the method for removing pseudo- gate electrode layer and pseudo- gate dielectric layer is：Remove pseudo- gate electrode layer；Remove pseudo- gate electrode
After layer, pseudo- gate dielectric layer is removed.
Optionally, before interlayer dielectric layer is formed, in addition to：In the pseudo- gate dielectric layer and pseudo- gate electrode layer both sides
Source and drain doping area is formed in fin.
Optionally, pseudo- gate electrode layer and pseudo- gate dielectric layer are removed, forms opening；The forming method of the semiconductor devices is also
Including：Gate dielectric layer and the metal gate electrode on gate dielectric layer positioned at opening sidewalls and bottom are formed in said opening
Layer.
Optionally, the Semiconductor substrate includes core space and marginal zone；The fin, isolation structure and precursor layer are located at
In the Semiconductor substrate of core space and marginal zone；After forming pseudo- gate dielectric material layer, pseudo- gate dielectric material layer be located at core space and
In the Semiconductor substrate of marginal zone.
Optionally, in addition to：Remove the pseudo- gate dielectric material layer of marginal zone；Remove the pseudo- gate dielectric material layer of marginal zone
Afterwards, the fin portion surface in oxide edge area, added gate layer of dielectric material is formed；The pseudo- layer of gate electrode material is also located at added gate Jie
On the material bed of material；While pseudo- layer of gate electrode material and the pseudo- gate dielectric material layer of graphical core space, graphical marginal zone
Pseudo- layer of gate electrode material and added gate layer of dielectric material, forming pseudo- gate dielectric layer and while pseudo- gate electrode layer, formed attached
Add gate dielectric layer and the additional gate electrode layer on additional gate dielectric layer, the pseudo- gate dielectric layer is located at the isolation junction of core space
The surface of structure, the top surface and sidewall surfaces for covering core region fin, the additional gate dielectric layer covering marginal zone portion
Divide the top surface and sidewall surfaces of fin；The interlayer dielectric layer also covers the side of additional gate dielectric layer and additional gate electrode layer
Wall；Removing the method for pseudo- gate electrode layer and pseudo- gate dielectric layer includes：After removing pseudo- gate electrode layer, pseudo- gate dielectric layer is removed；Going
Additional gate electrode layer is removed while except the pseudo- gate electrode layer.
Optionally, the technique of the fin portion surface in oxide edge area is dry oxidation technique or wet process oxidation technology.
Compared with prior art, technical scheme has advantages below：
The forming method of semiconductor devices provided by the invention, the surface with fin on the isolation structure form forerunner
Layer, forms pseudo- gate dielectric material layer by aoxidizing the precursor layer.Hence in so that the consistency of pseudo- gate dielectric material layer is higher,
Accordingly, the consistency of the pseudo- gate dielectric layer of formation is higher.Because the consistency of pseudo- gate dielectric layer is higher, thus can avoid with
Too fast etch rate removes pseudo- gate dielectric layer so that the process that etching removes pseudo- gate dielectric layer is easily controlled.Therefore exist
During removing pseudo- gate dielectric layer, the over etching degree reduction to pseudo- gate dielectric layer is enabled to, so as to reduce to isolation
The etching extent of deterioration of structure.
Further, since the consistency of pseudo- gate dielectric layer is higher, thus ensure during pseudo- gate dielectric layer is removed to every
In the case of relatively low from the etching extent of deterioration of structure, thicker pseudo- gate dielectric layer is not necessarily formed.Accordingly, not necessarily form thicker
Pseudo- gate dielectric material layer.Hence in so that process costs reduce.
Brief description of the drawings
Fig. 1 to Figure 10 is the structural representation of semiconductor devices forming process in one embodiment of the invention；
Figure 11 to Figure 22 is the structural representation of semiconductor devices forming process in another embodiment of the present invention.
Embodiment
As described in background, the performance for the semiconductor devices that prior art is formed has much room for improvement.
A kind of forming method of semiconductor devices includes：Semiconductor substrate is provided, there is fin in the Semiconductor substrate
With the isolation structure of covering fin partial sidewall；Using plasma chemical vapor deposition method is in isolation structure and the table of fin
Face forms pseudo- gate dielectric material layer；Pseudo- layer of gate electrode material is formed on pseudo- gate dielectric material layer；Graphical pseudo- gate material
Layer and pseudo- gate dielectric material layer, form pseudo- gate dielectric layer and the pseudo- gate electrode layer on pseudo- gate dielectric layer, the pseudo- gate medium
The top surface and sidewall surfaces of layer covering part fin；Formed in Semiconductor substrate and fin and cover pseudo- gate dielectric layer and puppet
The interlayer dielectric layer of the side wall of gate electrode layer；After forming interlayer dielectric layer, pseudo- gate electrode layer and pseudo- gate dielectric layer are removed.
The fin is formed by etch semiconductor substrates.Influenceed by etching technics, cause the top of fin wide
Degree is less than bottom width.
The material of pseudo- gate dielectric layer is silica, and the material of isolation structure is silica.
In the above method, because pseudo- gate dielectric material layer using plasma chemical vapor deposition method is formed, therefore lead
Cause the consistency of pseudo- gate dielectric material layer poor.Accordingly, the consistency of the pseudo- gate dielectric layer of formation is poor.Certain thickness
, can be by pseudo- gate medium because the consistency of pseudo- gate dielectric layer is poor, therefore in the short period of time in the case of pseudo- gate dielectric layer
Layer removes.Because the time for removing pseudo- gate dielectric layer is shorter, therefore etching whard to control removes the process of pseudo- gate dielectric layer,
More serious over etching is easily caused, causes the extent of deterioration to isolation structure larger.
Because the extent of deterioration of isolation structure is larger, therefore cause the height for the fin that isolation structure exposes larger.By
It is less than bottom width in the top width of fin, therefore the fin height exposed is bigger, what corresponding isolation structure exposed
The peak width of fin bottom is bigger.The region is caused to be not easy to be depleted, short-channel effect is serious.
Need to reduce the extent of deterioration to isolation structure for this.
On this basis, the present invention provides a kind of forming method of semiconductor devices, including：Semiconductor substrate, institute are provided
Stating has fin and isolation structure in Semiconductor substrate, the isolation structure covers fin partial sidewall；In the isolation structure
Upper and fin surface forms precursor layer；The precursor layer is aoxidized, forms pseudo- gate dielectric material layer；On pseudo- gate dielectric material layer
Form pseudo- layer of gate electrode material；Graphical pseudo- layer of gate electrode material and pseudo- gate dielectric material layer, form pseudo- gate dielectric layer and are located at
Pseudo- gate electrode layer on pseudo- gate dielectric layer, the pseudo- gate dielectric layer are located at the surface of isolation structure, the top of covering part fin
Surface and sidewall surfaces；The interlayer that the side wall for covering pseudo- gate dielectric layer and pseudo- gate electrode layer is formed on isolation structure and fin is situated between
Matter layer；Remove pseudo- gate electrode layer and pseudo- gate dielectric layer.
Because pseudo- gate dielectric material layer is formed by aoxidizing the precursor layer, hence in so that the cause of pseudo- gate dielectric material layer
Density is higher, and accordingly, the consistency of the pseudo- gate dielectric layer of formation is higher.Because the consistency of pseudo- gate dielectric layer is higher, therefore
It can avoid removing pseudo- gate dielectric layer with too fast etch rate so that the process that etching removes pseudo- gate dielectric layer is easily controlled
System.Therefore during pseudo- gate dielectric layer is removed, the over etching degree reduction to pseudo- gate dielectric layer is enabled to, so as to reduce
To the etching extent of deterioration of isolation structure.Further, since the consistency of pseudo- gate dielectric layer is higher, therefore removing pseudo- gate medium
In the case that guarantee is relatively low to the etching extent of deterioration of isolation structure during layer, thicker pseudo- gate dielectric layer is not necessarily formed.
Accordingly, thicker pseudo- gate dielectric material layer is not necessarily formed.Hence in so that process costs reduce.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 1 to Figure 10 is the structural representation of semiconductor devices forming process in one embodiment of the invention.
With reference to figure 1, there is provided Semiconductor substrate 100, there is fin 110 and covering fin 110 in the Semiconductor substrate 100
The isolation structure 120 of partial sidewall.
The Semiconductor substrate 100 provides technique platform to be subsequently formed semiconductor devices.
In the present embodiment, the material of the Semiconductor substrate 100 is monocrystalline silicon.The Semiconductor substrate 100 can also be
Polysilicon or non-crystalline silicon.The material of the Semiconductor substrate 100 can also be the semi-conducting materials such as germanium, SiGe, GaAs.
In the present embodiment, the fin 110 is formed by the graphical Semiconductor substrate 100.In other embodiments
In, Ke Yishi：Fin material layer is formed on the semiconductor substrate, then the graphical fin material layer, so as to be formed
Fin.
The material of the isolation structure 120 is silica, silicon oxynitride or silicon oxide carbide.
The isolation structure 120 covers the partial sidewall of fin 110, and the surface of isolation structure 120 is less than the top of fin 110
Portion surface.
Formed isolation structure 120 method be：Form the isolation structure material of covering Semiconductor substrate 100 and fin 110
Layer；Remove the isolation structure material layer higher than the top surface of fin 110；Afterwards, isolation structure material layer is etched back to, forms isolation
Structure 120.
In the present embodiment, the technique for forming isolation structure material layer is fluid chemistry gas-phase deposition.In other implementations
In example, forming the technique of isolation structure material layer can select as plasma activated chemical vapour deposition technique, low pressure chemical phase
Depositing operation or sub-atmospheric pressure chemical vapor deposition method.
With reference to figure 2, the surface with fin 110 on the isolation structure 120 forms precursor layer 130.
The technique for forming precursor layer 130 is depositing operation, such as atom layer deposition process, plasma activated chemical vapour deposition work
Skill, low-pressure chemical vapor deposition process or sub-atmospheric pressure chemical vapor deposition method.
In the present embodiment, the material of the precursor layer 130 is non-crystalline silicon, and the technique for forming precursor layer 130 is low pressure chemical
Gas-phase deposition, specific parameter include：The gas of use includes SiH4, SiH4Flow be 30sccm~300sccm, temperature
Spend for 260 degrees Celsius~520 degrees Celsius, pressure is 0.03torr~1torr.
Precursor layer 130 is formed using the parameter of above-mentioned low-pressure chemical vapor deposition process so that sedimentation rate is relatively low, so as to
So that the consistency of precursor layer 130 is higher.
In another embodiment, precursor layer is formed using using ald.Due to using atom layer deposition process
Form precursor layer so that the conformal effect on surface of the precursor layer on isolation structure with fin is good so that the thickness of precursor layer is equal
One property is higher.And atom layer deposition process is deposited on the thickness of atomic weight pole so that the consistency of the precursor layer of formation
It is higher.
With reference to figure 3, the precursor layer 130 (with reference to figure 2) is aoxidized, forms pseudo- gate dielectric material layer 140.
The pseudo- gate dielectric material layer 140 is formed by oxidation precursor layer 130.The pseudo- gate dielectric material layer 140 is located at
On isolation structure 120 and fin 110 surface.
In the present embodiment, the material of the pseudo- gate dielectric material layer 140 is silica.
The technique for aoxidizing the precursor layer 130 is dry oxidation technique or wet process oxidation technology.
Due to pseudo- gate dielectric material layer 140 by aoxidize the precursor layer 130 and formed, hence in so that pseudo- gate dielectric material
The consistency of layer 140 is higher.
In the present embodiment, the material of precursor layer 130 is non-crystalline silicon, aoxidizes the temperature that the precursor layer 130 uses and is taken the photograph for 850
Family name degree~1050 degree Celsius, time are 5 seconds~500 seconds.
Aoxidize the temperature that the precursor layer 130 uses is for 850 degrees Celsius~1050 degrees Celsius of meaning：If described in oxidation
The temperature that precursor layer 130 uses is more than 1050 degrees Celsius, causes oxidation rate too fast, it is more difficult to control process；If oxidation institute
The temperature for stating the use of precursor layer 130 is less than 850 degrees Celsius, and in oxidizing process, the uniformity of degree of oxidation is by gas flow
In having a great influence for the difference that different zones are distributed, and the pseudo- gate dielectric material layer 140 formed is second-rate, and process efficiency
It is relatively low.
Further, since the consistency of pseudo- gate dielectric material layer 140 is higher, therefore in the process for subsequently removing pseudo- gate dielectric layer
In the case that middle guarantee is relatively low to the etching extent of deterioration of isolation structure 120, thicker pseudo- gate dielectric layer is not necessarily formed.Accordingly
, thicker pseudo- gate dielectric material layer 140 is not necessarily formed, hence in so that process costs reduce.In the present embodiment, the pseudo- grid are situated between
The thickness of the material bed of material 140 is 15 angstroms~80 angstroms, such as 15 angstroms, 20 angstroms, 30 angstroms, 50 angstroms or 80 angstroms.
Further, since pseudo- gate dielectric material layer 140 need not aoxidize fin 110 and be formed, therefore avoid forming pseudo- grid Jie
Fin 110 is lost during the material bed of material 140, avoids the width of fin 110 too small.If the width of fin 110 is too small, can lead
Cause the resistance of fin 110 excessive, so as to which driving current can be caused too small.In the present embodiment, due to avoiding the width mistake of fin 110
It is small, therefore it is avoided that driving current is too small.
With reference to figure 4, pseudo- layer of gate electrode material 150 is formed on pseudo- gate dielectric material layer 140.
The material of the pseudo- layer of gate electrode material 150 is polysilicon.
The technique for forming the pseudo- layer of gate electrode material 150 is depositing operation, as plasma activated chemical vapour deposition technique,
Sub-atmospheric pressure chemical vapor deposition method or low-pressure chemical vapor deposition process.
With reference to being the schematic diagram that is obtained along line of cut A-A1 in Fig. 5 with reference to figure 5 and Fig. 6, Fig. 6, graphical pseudo- gate electrode
Material layer 150 (with reference to figure 4) and pseudo- gate dielectric material layer 140 (with reference to figure 4), form pseudo- gate dielectric layer 141 and be situated between positioned at pseudo- grid
Pseudo- gate electrode layer 151 on matter layer 141, the pseudo- gate dielectric layer 141 are located at the surface of isolation structure 120, covering part fin
110 top surface and sidewall surfaces.
Graphical pseudo- layer of gate electrode material 150 and the method for pseudo- gate dielectric material layer 140 are：In pseudo- layer of gate electrode material
Patterned mask layer is formed on 150, the patterned mask layer defines pseudo- gate electrode layer 151 to be formed and pseudo- grid are situated between
The position of matter layer 141；Using the patterned mask layer as mask, pseudo- layer of gate electrode material 150 and pseudo- gate dielectric material are etched
Layer 140, so as to form pseudo- gate electrode layer 151 and pseudo- gate dielectric layer 141.
Wherein, the corresponding pseudo- gate dielectric material layer 140 of pseudo- gate dielectric layer 141, the corresponding pseudo- gate material of pseudo- gate electrode layer 151
Layer 150.
Because the consistency of pseudo- gate dielectric material layer 140 is higher, thus formed pseudo- gate dielectric layer 141 consistency compared with
It is high.
With reference to being the schematic diagram that is obtained along line of cut A-A1 in Fig. 7 with reference to figure 7 and Fig. 8, Fig. 8, in the pseudo- gate medium
Source and drain doping area (not shown) is formed in floor 141 and the fin 110 of the both sides of pseudo- gate electrode layer 151；After forming source and drain doping area,
The interlayer dielectric layer for the side wall for covering pseudo- gate dielectric layer 141 and pseudo- gate electrode layer 151 is formed on isolation structure 120 and fin 110
160。
The material of the interlayer dielectric layer 160 is silica, silicon oxynitride or silicon oxide carbide.
In the present embodiment, also side wall (not shown) is formd in the side wall of pseudo- gate dielectric layer 141 and pseudo- gate electrode layer 151；
Source and drain doping area is formed in pseudo- gate dielectric layer 141, pseudo- gate electrode layer 151 and the fin 110 of side wall both sides；Form source and drain doping
Qu Hou, forms interlayer dielectric layer 160, and the interlayer dielectric layer 160 covers the side wall of side wall.In other embodiments, may be used not
Form side wall.
Forming the method for interlayer dielectric layer 160 includes：Formed in Semiconductor substrate 100 and fin 110 and cover pseudo- grid Jie
The interlevel dielectric material layer of matter layer 141, pseudo- gate electrode layer 151 and side wall, the whole surface of the interlevel dielectric material layer are higher than
The top surface of pseudo- gate electrode layer 151；The interlevel dielectric material layer higher than the pseudo- top surface of gate electrode layer 151 is removed, so as to shape
Into interlayer dielectric layer 160.
With reference to being along the schematic diagram of line of cut A-A1 acquisitions in Fig. 9 with reference to figure 9 and Figure 10, Figure 10, pseudo- gate electrode is removed
Layer 151 and pseudo- gate dielectric layer 141, form opening 161.
Remove the technique of pseudo- gate electrode layer 151 and pseudo- gate dielectric layer 141 for dry etch process, wet-etching technology or
The combination of dry etch process or wet-etching technology.
The method for removing pseudo- gate electrode layer 151 and pseudo- gate dielectric layer 141 is：Remove pseudo- gate electrode layer 151；Remove pseudo- grid electricity
After pole layer 151, pseudo- gate dielectric layer 141 is removed.
Because the consistency of pseudo- gate dielectric layer 141 is higher, therefore can avoid removing pseudo- grid Jie with too fast etch rate
Matter layer 141 so that the process that etching removes pseudo- gate dielectric layer 141 is easily controlled.Therefore pseudo- gate dielectric layer 141 is being removed
During, the over etching degree reduction to pseudo- gate dielectric layer 141 is enabled to, so as to reduce the loss to isolation structure 120
Degree.
Then, the gate dielectric layer (not shown) positioned at the side wall of opening 161 and bottom is formed in the opening 161 and is located at
Metal gate electrode layer (not shown) on gate dielectric layer.
The material of the gate dielectric layer is high K (K is more than 3.9) dielectric material.
Because the extent of deterioration of isolation structure 120 is smaller, thus the height of fin 110 that exposes of isolation structure 120 compared with
It is small.When the top width of fin 110 is less than the bottom width of fin 110, the fin 110 that is exposed due to isolation structure 120
Height it is smaller, therefore the peak width of the bottom of fin 110 that isolation structure exposes is smaller.Isolation structure 120 is avoided to expose
The region of the bottom of fin 110 gone out can not be depleted, and reduce short-channel effect.
Figure 11 to Figure 22 is the structural representation of semiconductor devices forming process in another embodiment of the present invention.
With reference to figure 11, there is provided Semiconductor substrate 200, the Semiconductor substrate 200 include core space I and marginal zone II, core
There is fin 210 in heart district I and the Semiconductor substrate of marginal zone II 200 and cover the isolation structure of the partial sidewall of fin 210
220。
The material of the Semiconductor substrate 200 is with reference to the foregoing embodiments.
The Semiconductor substrate 200 includes core space I and marginal zone II, and marginal zone II is located at the periphery of core space I.Core
Area I is used to form core devices, and marginal zone II is used to form peripheral logical circuit.
The material and forming method of the fin 210 are with reference to the foregoing embodiments；The material of the isolation structure 220 and formation
Method is with reference to the foregoing embodiments.
With reference to figure 12, the surface with fin 210 on the isolation structure 220 forms precursor layer 230.
On the isolation structure 220 of core space I and the surface of fin 210 of core space I and the isolation structure of marginal zone II
The surface of fin 210 of on 220 and marginal zone II has been respectively formed precursor layer 230.
The material and forming method of precursor layer 230 are with reference to the material and forming method for forming precursor layer 130.
With reference to figure 13, the precursor layer 230 (with reference to figure 12) is aoxidized, forms pseudo- gate dielectric material layer 240.
The technique for aoxidizing the technique of the precursor layer 230 middle amorphous silicon dioxide layer 130 with reference to the foregoing embodiments.
The thickness of pseudo- gate dielectric material layer 240 is 15 angstroms~80 angstroms, such as 15 angstroms, 20 angstroms, 30 angstroms, 50 angstroms or 80 angstroms.
After forming pseudo- gate dielectric material layer 240, pseudo- gate dielectric material layer 240 is located at partly leading for core space I and marginal zone II
On body substrate 200.
With reference to figure 14, the pseudo- gate dielectric material layer 240 of removal marginal zone II.
Removing the method for the pseudo- gate dielectric material layer 240 of marginal zone II includes：Mask layer is formed, the mask layer covers core
The pseudo- gate dielectric material layer 240 of heart district I and the pseudo- gate dielectric material layer 240 for exposing marginal zone II；Using the mask layer to cover
Film, etching remove the pseudo- gate dielectric material layer 240 of marginal zone II；Then the mask layer is removed.
The pseudo- gate dielectric material layer 240 of marginal zone II is removed, so as to remain the pseudo- gate dielectric material layer 240 of core space I.
With reference to figure 15, after the pseudo- gate dielectric material layer 240 for removing marginal zone II, the surface of fin 210 in oxide edge area II,
Form added gate layer of dielectric material 250.
The technique on the surface of fin 210 in oxide edge area II is dry oxidation technique or wet process oxidation technology.
With reference to figure 16, on the pseudo- gate dielectric material layer 240 of core space I, on the isolation structure 220 of marginal zone II and attached
Add and pseudo- layer of gate electrode material 260 is formed on gate dielectric material layer 250.
Form the technique of the pseudo- layer of gate electrode material 260 middle work for forming pseudo- layer of gate electrode material 150 with reference to the foregoing embodiments
Skill.
With reference to being the signal that is obtained along line of cut A2-A3 in Figure 17 and line of cut A4-A5 with reference to figure 17 and Figure 18, Figure 18
Figure, in the pseudo- layer of gate electrode material 260 (with reference to figure 16) and pseudo- gate dielectric material layer 240 of graphical core space I (with reference to figure 16)
While, the pseudo- layer of gate electrode material 260 and added gate layer of dielectric material 250 of graphical marginal zone II, forming pseudo- gate medium
While layer 241 and pseudo- gate electrode layer 262 on pseudo- gate dielectric layer 241, additional gate dielectric layer 251 is formed and positioned at additional
Additional gate electrode layer 262 on gate dielectric layer 251, the pseudo- gate dielectric layer 241 are located at the table of the isolation structure 220 of core space I
Face, the top surface and sidewall surfaces for covering the part fin 210 of core space I, the additional gate dielectric layer 251 cover marginal zone II
The top surface and sidewall surfaces of part fin 210.
Additional gate electrode floor 262 is also located at the surface of the portions of isolation structure 220 in part edge area II.
Wherein, the corresponding pseudo- gate dielectric material layer 240 of pseudo- gate dielectric layer 241, the corresponding additional gate medium of gate dielectric layer 251 is added
Material layer 250, the corresponding pseudo- layer of gate electrode material 260 of pseudo- gate electrode layer 261 and additional gate dielectric layer 251.
With reference to being the signal that is obtained along line of cut A2-A3 in Figure 19 and line of cut A4-A5 with reference to figure 19 and Figure 20, Figure 20
Figure, source and drain doping area (not shown) is formed in the fin 210 of the pseudo- gate dielectric layer 241 and the both sides of pseudo- gate electrode layer 261；
Additional source and drain doped region is formed in additional gate dielectric layer 251 and the fin 210 of the both sides of additional gate electrode layer 262；Source and drain is formed to mix
Behind miscellaneous area and additional source and drain doped region, interlayer dielectric layer 270, interlayer dielectric layer are formed on isolation structure 220 and fin 210
The side wall and additional gate dielectric layer 251 and additional gate electrode layer of the pseudo- gate dielectric layer 241 of 270 coverings and pseudo- gate electrode layer 261
262 side wall.
Material and forming method of the material and forming method of the interlayer dielectric layer 270 with reference to interlayer dielectric layer 160.
With reference to being the signal that is obtained along line of cut A2-A3 in Figure 21 and line of cut A4-A5 with reference to figure 21 and Figure 22, Figure 22
Figure, removes pseudo- gate electrode layer 261, additional gate electrode layer 262 and pseudo- gate dielectric layer 241, opening 271 is formed in core space I, on side
Edge area II forms additional opening 272.
The method for removing pseudo- gate electrode layer 261, pseudo- gate dielectric layer 241 and additional gate electrode layer 262 is：Remove pseudo- gate electrode
Additional gate electrode layer 262 is removed while layer 261；After removing pseudo- gate electrode layer 261 and additional gate electrode layer 262, pseudo- grid are removed
Dielectric layer 241.
Then, formed in the side wall of opening 271 and bottom and be located at the gate dielectric layer of opening sidewalls and bottom and positioned at grid Jie
Metal gate electrode layer on matter layer；The additional metal gate electrode formed in additional opening 272 on additional gate dielectric layer 251
Layer.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (13)
- A kind of 1. forming method of semiconductor devices, it is characterised in that including：Semiconductor substrate is provided, there is fin and isolation structure, the isolation structure covering fin portion in the Semiconductor substrate Divide side wall；Surface with fin on the isolation structure forms precursor layer；The precursor layer is aoxidized, forms pseudo- gate dielectric material layer；Pseudo- layer of gate electrode material is formed on pseudo- gate dielectric material layer；Graphical pseudo- layer of gate electrode material and pseudo- gate dielectric material layer, form pseudo- gate dielectric layer and the puppet on pseudo- gate dielectric layer Gate electrode layer, the pseudo- gate dielectric layer are located at the surface of isolation structure, the top surface and sidewall surfaces of covering part fin；The interlayer dielectric layer for the side wall for covering pseudo- gate dielectric layer and pseudo- gate electrode layer is formed on isolation structure and fin；Remove pseudo- gate electrode layer and pseudo- gate dielectric layer.
- 2. the forming method of semiconductor devices according to claim 1, it is characterised in that the technique for forming the precursor layer For atom layer deposition process, plasma activated chemical vapour deposition technique, low-pressure chemical vapor deposition process or sub-atmospheric pressure chemistry Gas-phase deposition.
- 3. the forming method of semiconductor devices according to claim 1, it is characterised in that the material of the precursor layer is non- Crystal silicon.
- 4. the forming method of semiconductor devices according to claim 3, it is characterised in that the technique for forming the precursor layer For low-pressure chemical vapor deposition process, parameter includes：The gas of use includes SiH4, SiH4Flow for 30sccm~ 300sccm, temperature are 260 degrees Celsius~520 degrees Celsius, and pressure is 0.03torr~1torr.
- 5. the forming method of semiconductor devices according to claim 3, it is characterised in that aoxidize what the precursor layer used Temperature is 850 degrees Celsius~1050 degrees Celsius, and the time is 5 seconds~500 seconds.
- 6. the forming method of semiconductor devices according to claim 1, it is characterised in that the technique for aoxidizing the precursor layer For dry oxidation technique or wet process oxidation technology.
- 7. the forming method of semiconductor devices according to claim 1, it is characterised in that the pseudo- gate dielectric material layer Thickness is 15 angstroms~80 angstroms.
- 8. the forming method of semiconductor devices according to claim 1, it is characterised in that remove pseudo- gate electrode layer and pseudo- grid The method of dielectric layer is：Remove pseudo- gate electrode layer；After removing pseudo- gate electrode layer, pseudo- gate dielectric layer is removed.
- 9. the forming method of semiconductor devices according to claim 1, it is characterised in that formed interlayer dielectric layer it Before, in addition to：Source and drain doping area is formed in the fin of the pseudo- gate dielectric layer and pseudo- gate electrode layer both sides.
- 10. the forming method of semiconductor devices according to claim 1, it is characterised in that remove pseudo- gate electrode layer and puppet Gate dielectric layer, form opening；The forming method of the semiconductor devices also includes：The gate medium positioned at opening sidewalls and bottom is formed in said opening Layer and the metal gate electrode layer on gate dielectric layer.
- 11. the forming method of semiconductor devices according to claim 1, it is characterised in that the Semiconductor substrate includes Core space and marginal zone；The fin, isolation structure and precursor layer are located in the Semiconductor substrate of core space and marginal zone；Formed After pseudo- gate dielectric material layer, pseudo- gate dielectric material layer is located in the Semiconductor substrate of core space and marginal zone.
- 12. the forming method of semiconductor devices according to claim 11, it is characterised in that also include：Remove the pseudo- gate dielectric material layer of marginal zone；After the pseudo- gate dielectric material layer for removing marginal zone, the fin portion surface in oxide edge area, added gate layer of dielectric material is formed；The pseudo- layer of gate electrode material is also located in added gate layer of dielectric material；While pseudo- layer of gate electrode material and the pseudo- gate dielectric material layer of graphical core space, the pseudo- grid electricity of graphical marginal zone Pole material layer and added gate layer of dielectric material, while pseudo- gate dielectric layer and pseudo- gate electrode layer is formed, form additional gate medium Layer and the additional gate electrode layer on additional gate dielectric layer, the pseudo- gate dielectric layer are located at the table of the isolation structure of core space Face, the top surface and sidewall surfaces for covering core region fin, the additional gate dielectric layer covering marginal zone part fin Top surface and sidewall surfaces；The interlayer dielectric layer also covers the side wall of additional gate dielectric layer and additional gate electrode layer；Removing the method for pseudo- gate electrode layer and pseudo- gate dielectric layer includes：After removing pseudo- gate electrode layer, pseudo- gate dielectric layer is removed；Additional gate electrode layer is removed while the pseudo- gate electrode layer is removed.
- 13. the forming method of semiconductor devices according to claim 12, it is characterised in that the fin table in oxide edge area The technique in face is dry oxidation technique or wet process oxidation technology.
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| CN110828543A (en) * | 2018-08-14 | 2020-02-21 | 中芯国际集成电路制造（天津）有限公司 | Method for forming semiconductor device |
| CN111863609A (en) * | 2019-04-30 | 2020-10-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN113140459A (en) * | 2020-01-19 | 2021-07-20 | 中芯国际集成电路制造（天津）有限公司 | Method for forming semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110828543A (en) * | 2018-08-14 | 2020-02-21 | 中芯国际集成电路制造（天津）有限公司 | Method for forming semiconductor device |
| CN110828543B (en) * | 2018-08-14 | 2023-08-22 | 中芯国际集成电路制造（天津）有限公司 | Method for forming semiconductor device |
| CN111863609A (en) * | 2019-04-30 | 2020-10-30 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111863609B (en) * | 2019-04-30 | 2023-03-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN113140459A (en) * | 2020-01-19 | 2021-07-20 | 中芯国际集成电路制造（天津）有限公司 | Method for forming semiconductor device |
| CN113140459B (en) * | 2020-01-19 | 2022-09-20 | 中芯国际集成电路制造（天津）有限公司 | Method for forming semiconductor device |
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